adapter.h revision 309447
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/10/sys/dev/cxgbe/adapter.h 309447 2016-12-02 22:53:33Z jhb $ 28 * 29 */ 30 31#ifndef __T4_ADAPTER_H__ 32#define __T4_ADAPTER_H__ 33 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/types.h> 38#include <sys/malloc.h> 39#include <dev/pci/pcivar.h> 40#include <dev/pci/pcireg.h> 41#include <machine/bus.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44#include <net/ethernet.h> 45#include <net/if.h> 46#include <net/if_media.h> 47#include <netinet/in.h> 48#include <netinet/tcp_lro.h> 49 50#include "offload.h" 51#include "t4_ioctl.h" 52#include "common/t4_msg.h" 53#include "firmware/t4fw_interface.h" 54 55#define KTR_CXGBE KTR_SPARE3 56MALLOC_DECLARE(M_CXGBE); 57#define CXGBE_UNIMPLEMENTED(s) \ 58 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 59 60#if defined(__i386__) || defined(__amd64__) 61static __inline void 62prefetch(void *x) 63{ 64 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 65} 66#else 67#define prefetch(x) 68#endif 69 70#ifndef SYSCTL_ADD_UQUAD 71#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 72#define sysctl_handle_64 sysctl_handle_quad 73#define CTLTYPE_U64 CTLTYPE_QUAD 74#endif 75 76#if (__FreeBSD_version >= 900030) || \ 77 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 78#define SBUF_DRAIN 1 79#endif 80 81#ifdef __amd64__ 82/* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 83static __inline uint64_t 84t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 85 bus_size_t offset) 86{ 87 KASSERT(tag == X86_BUS_SPACE_MEM, 88 ("%s: can only handle mem space", __func__)); 89 90 return (*(volatile uint64_t *)(handle + offset)); 91} 92 93static __inline void 94t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 95 bus_size_t offset, uint64_t value) 96{ 97 KASSERT(tag == X86_BUS_SPACE_MEM, 98 ("%s: can only handle mem space", __func__)); 99 100 *(volatile uint64_t *)(bsh + offset) = value; 101} 102#else 103static __inline uint64_t 104t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 105 bus_size_t offset) 106{ 107 return (uint64_t)bus_space_read_4(tag, handle, offset) + 108 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 109} 110 111static __inline void 112t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 113 bus_size_t offset, uint64_t value) 114{ 115 bus_space_write_4(tag, bsh, offset, value); 116 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 117} 118#endif 119 120struct adapter; 121typedef struct adapter adapter_t; 122 123enum { 124 /* 125 * All ingress queues use this entry size. Note that the firmware event 126 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 127 * be at least 64. 128 */ 129 IQ_ESIZE = 64, 130 131 /* Default queue sizes for all kinds of ingress queues */ 132 FW_IQ_QSIZE = 256, 133 RX_IQ_QSIZE = 1024, 134 135 /* All egress queues use this entry size */ 136 EQ_ESIZE = 64, 137 138 /* Default queue sizes for all kinds of egress queues */ 139 CTRL_EQ_QSIZE = 128, 140 TX_EQ_QSIZE = 1024, 141 142#if MJUMPAGESIZE != MCLBYTES 143 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 144#else 145 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 146#endif 147 CL_METADATA_SIZE = CACHE_LINE_SIZE, 148 149 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 150 TX_SGL_SEGS = 39, 151 TX_SGL_SEGS_TSO = 38, 152 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 153}; 154 155enum { 156 /* adapter intr_type */ 157 INTR_INTX = (1 << 0), 158 INTR_MSI = (1 << 1), 159 INTR_MSIX = (1 << 2) 160}; 161 162enum { 163 XGMAC_MTU = (1 << 0), 164 XGMAC_PROMISC = (1 << 1), 165 XGMAC_ALLMULTI = (1 << 2), 166 XGMAC_VLANEX = (1 << 3), 167 XGMAC_UCADDR = (1 << 4), 168 XGMAC_MCADDRS = (1 << 5), 169 170 XGMAC_ALL = 0xffff 171}; 172 173enum { 174 /* flags understood by begin_synchronized_op */ 175 HOLD_LOCK = (1 << 0), 176 SLEEP_OK = (1 << 1), 177 INTR_OK = (1 << 2), 178 179 /* flags understood by end_synchronized_op */ 180 LOCK_HELD = HOLD_LOCK, 181}; 182 183enum { 184 /* adapter flags */ 185 FULL_INIT_DONE = (1 << 0), 186 FW_OK = (1 << 1), 187 /* INTR_DIRECT = (1 << 2), No longer used. */ 188 MASTER_PF = (1 << 3), 189 ADAP_SYSCTL_CTX = (1 << 4), 190 /* TOM_INIT_DONE= (1 << 5), No longer used */ 191 BUF_PACKING_OK = (1 << 6), 192 IS_VF = (1 << 7), 193 194 CXGBE_BUSY = (1 << 9), 195 196 /* port flags */ 197 HAS_TRACEQ = (1 << 3), 198 199 /* VI flags */ 200 DOOMED = (1 << 0), 201 VI_INIT_DONE = (1 << 1), 202 VI_SYSCTL_CTX = (1 << 2), 203 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 204 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 205 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 206 207 /* adapter debug_flags */ 208 DF_DUMP_MBOX = (1 << 0), 209}; 210 211#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 212#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 213#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 214#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 215#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 216 217struct vi_info { 218 device_t dev; 219 struct port_info *pi; 220 221 struct ifnet *ifp; 222 struct ifmedia media; 223 224 unsigned long flags; 225 int if_flags; 226 227 uint16_t *rss, *nm_rss; 228 uint16_t viid; 229 int16_t xact_addr_filt;/* index of exact MAC address filter */ 230 uint16_t rss_size; /* size of VI's RSS table slice */ 231 uint16_t rss_base; /* start of VI's RSS table slice */ 232 233 eventhandler_tag vlan_c; 234 235 int nintr; 236 int first_intr; 237 238 /* These need to be int as they are used in sysctl */ 239 int ntxq; /* # of tx queues */ 240 int first_txq; /* index of first tx queue */ 241 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 242 int nrxq; /* # of rx queues */ 243 int first_rxq; /* index of first rx queue */ 244 int nofldtxq; /* # of offload tx queues */ 245 int first_ofld_txq; /* index of first offload tx queue */ 246 int nofldrxq; /* # of offload rx queues */ 247 int first_ofld_rxq; /* index of first offload rx queue */ 248 int nnmtxq; 249 int first_nm_txq; 250 int nnmrxq; 251 int first_nm_rxq; 252 int tmr_idx; 253 int pktc_idx; 254 int qsize_rxq; 255 int qsize_txq; 256 257 struct timeval last_refreshed; 258 struct fw_vi_stats_vf stats; 259 260 struct callout tick; 261 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 262 263 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 264}; 265 266enum { 267 /* tx_sched_class flags */ 268 TX_SC_OK = (1 << 0), /* Set up in hardware, active. */ 269}; 270 271struct tx_sched_class { 272 int refcount; 273 int flags; 274 struct t4_sched_class_params params; 275}; 276 277struct port_info { 278 device_t dev; 279 struct adapter *adapter; 280 281 struct vi_info *vi; 282 int nvi; 283 int up_vis; 284 int uld_vis; 285 286 struct tx_sched_class *tc; /* traffic classes for this channel */ 287 288 struct mtx pi_lock; 289 char lockname[16]; 290 unsigned long flags; 291 292 uint8_t lport; /* associated offload logical port */ 293 int8_t mdio_addr; 294 uint8_t port_type; 295 uint8_t mod_type; 296 uint8_t port_id; 297 uint8_t tx_chan; 298 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 299 300 int linkdnrc; 301 struct link_config link_cfg; 302 303 struct timeval last_refreshed; 304 struct port_stats stats; 305 u_int tx_parse_error; 306 307 struct callout tick; 308}; 309 310#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 311 312/* Where the cluster came from, how it has been carved up. */ 313struct cluster_layout { 314 int8_t zidx; 315 int8_t hwidx; 316 uint16_t region1; /* mbufs laid out within this region */ 317 /* region2 is the DMA region */ 318 uint16_t region3; /* cluster_metadata within this region */ 319}; 320 321struct cluster_metadata { 322 u_int refcount; 323 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 324}; 325 326struct fl_sdesc { 327 caddr_t cl; 328 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 329 struct cluster_layout cll; 330}; 331 332struct tx_desc { 333 __be64 flit[8]; 334}; 335 336struct tx_sdesc { 337 struct mbuf *m; /* m_nextpkt linked chain of frames */ 338 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 339}; 340 341 342#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 343struct iq_desc { 344 struct rss_header rss; 345 uint8_t cpl[IQ_PAD]; 346 struct rsp_ctrl rsp; 347}; 348#undef IQ_PAD 349CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 350 351enum { 352 /* iq flags */ 353 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 354 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 355 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 356 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 357 358 /* iq state */ 359 IQS_DISABLED = 0, 360 IQS_BUSY = 1, 361 IQS_IDLE = 2, 362 363 /* netmap related flags */ 364 NM_OFF = 0, 365 NM_ON = 1, 366 NM_BUSY = 2, 367}; 368 369struct sge_iq; 370struct rss_header; 371typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 372 struct mbuf *); 373typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 374typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 375 376/* 377 * Ingress Queue: T4 is producer, driver is consumer. 378 */ 379struct sge_iq { 380 uint32_t flags; 381 volatile int state; 382 struct adapter *adapter; 383 cpl_handler_t set_tcb_rpl; 384 cpl_handler_t l2t_write_rpl; 385 struct iq_desc *desc; /* KVA of descriptor ring */ 386 int8_t intr_pktc_idx; /* packet count threshold index */ 387 uint8_t gen; /* generation bit */ 388 uint8_t intr_params; /* interrupt holdoff parameters */ 389 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 390 uint16_t qsize; /* size (# of entries) of the queue */ 391 uint16_t sidx; /* index of the entry with the status page */ 392 uint16_t cidx; /* consumer index */ 393 uint16_t cntxt_id; /* SGE context id for the iq */ 394 uint16_t abs_id; /* absolute SGE id for the iq */ 395 396 STAILQ_ENTRY(sge_iq) link; 397 398 bus_dma_tag_t desc_tag; 399 bus_dmamap_t desc_map; 400 bus_addr_t ba; /* bus address of descriptor ring */ 401}; 402 403enum { 404 EQ_CTRL = 1, 405 EQ_ETH = 2, 406 EQ_OFLD = 3, 407 408 /* eq flags */ 409 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 410 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 411 EQ_ENABLED = (1 << 3), /* open for business */ 412}; 413 414/* Listed in order of preference. Update t4_sysctls too if you change these */ 415enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 416 417/* 418 * Egress Queue: driver is producer, T4 is consumer. 419 * 420 * Note: A free list is an egress queue (driver produces the buffers and T4 421 * consumes them) but it's special enough to have its own struct (see sge_fl). 422 */ 423struct sge_eq { 424 unsigned int flags; /* MUST be first */ 425 unsigned int cntxt_id; /* SGE context id for the eq */ 426 unsigned int abs_id; /* absolute SGE id for the eq */ 427 struct mtx eq_lock; 428 429 struct tx_desc *desc; /* KVA of descriptor ring */ 430 uint16_t doorbells; 431 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 432 u_int udb_qid; /* relative qid within the doorbell page */ 433 uint16_t sidx; /* index of the entry with the status page */ 434 uint16_t cidx; /* consumer idx (desc idx) */ 435 uint16_t pidx; /* producer idx (desc idx) */ 436 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 437 uint16_t dbidx; /* pidx of the most recent doorbell */ 438 uint16_t iqid; /* iq that gets egr_update for the eq */ 439 uint8_t tx_chan; /* tx channel used by the eq */ 440 volatile u_int equiq; /* EQUIQ outstanding */ 441 442 bus_dma_tag_t desc_tag; 443 bus_dmamap_t desc_map; 444 bus_addr_t ba; /* bus address of descriptor ring */ 445 char lockname[16]; 446}; 447 448struct sw_zone_info { 449 uma_zone_t zone; /* zone that this cluster comes from */ 450 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 451 int type; /* EXT_xxx type of the cluster */ 452 int8_t head_hwidx; 453 int8_t tail_hwidx; 454}; 455 456struct hw_buf_info { 457 int8_t zidx; /* backpointer to zone; -ve means unused */ 458 int8_t next; /* next hwidx for this zone; -1 means no more */ 459 int size; 460}; 461 462enum { 463 NUM_MEMWIN = 3, 464 465 MEMWIN0_APERTURE = 2048, 466 MEMWIN0_BASE = 0x1b800, 467 468 MEMWIN1_APERTURE = 32768, 469 MEMWIN1_BASE = 0x28000, 470 471 MEMWIN2_APERTURE_T4 = 65536, 472 MEMWIN2_BASE_T4 = 0x30000, 473 474 MEMWIN2_APERTURE_T5 = 128 * 1024, 475 MEMWIN2_BASE_T5 = 0x60000, 476}; 477 478struct memwin { 479 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 480 uint32_t mw_base; /* constant after setup_memwin */ 481 uint32_t mw_aperture; /* ditto */ 482 uint32_t mw_curpos; /* protected by mw_lock */ 483}; 484 485enum { 486 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 487 FL_DOOMED = (1 << 1), /* about to be destroyed */ 488 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 489 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 490}; 491 492#define FL_RUNNING_LOW(fl) \ 493 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 494#define FL_NOT_RUNNING_LOW(fl) \ 495 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 496 497struct sge_fl { 498 struct mtx fl_lock; 499 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 500 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 501 struct cluster_layout cll_def; /* default refill zone, layout */ 502 uint16_t lowat; /* # of buffers <= this means fl needs help */ 503 int flags; 504 uint16_t buf_boundary; 505 506 /* The 16b idx all deal with hw descriptors */ 507 uint16_t dbidx; /* hw pidx after last doorbell */ 508 uint16_t sidx; /* index of status page */ 509 volatile uint16_t hw_cidx; 510 511 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 512 uint32_t cidx; /* consumer index */ 513 uint32_t pidx; /* producer index */ 514 515 uint32_t dbval; 516 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 517 volatile uint32_t *udb; 518 519 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 520 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 521 uint64_t cl_allocated; /* # of clusters allocated */ 522 uint64_t cl_recycled; /* # of clusters recycled */ 523 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 524 525 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 526 struct mbuf *m0; 527 struct mbuf **pnext; 528 u_int remaining; 529 530 uint16_t qsize; /* # of hw descriptors (status page included) */ 531 uint16_t cntxt_id; /* SGE context id for the freelist */ 532 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 533 bus_dma_tag_t desc_tag; 534 bus_dmamap_t desc_map; 535 char lockname[16]; 536 bus_addr_t ba; /* bus address of descriptor ring */ 537 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 538}; 539 540struct mp_ring; 541 542/* txq: SGE egress queue + what's needed for Ethernet NIC */ 543struct sge_txq { 544 struct sge_eq eq; /* MUST be first */ 545 546 struct ifnet *ifp; /* the interface this txq belongs to */ 547 struct mp_ring *r; /* tx software ring */ 548 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 549 struct sglist *gl; 550 __be32 cpl_ctrl0; /* for convenience */ 551 int tc_idx; /* traffic class */ 552 553 struct task tx_reclaim_task; 554 /* stats for common events first */ 555 556 uint64_t txcsum; /* # of times hardware assisted with checksum */ 557 uint64_t tso_wrs; /* # of TSO work requests */ 558 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 559 uint64_t imm_wrs; /* # of work requests with immediate data */ 560 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 561 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 562 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 563 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 564 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 565 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 566 567 /* stats for not-that-common events */ 568} __aligned(CACHE_LINE_SIZE); 569 570/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 571struct sge_rxq { 572 struct sge_iq iq; /* MUST be first */ 573 struct sge_fl fl; /* MUST follow iq */ 574 575 struct ifnet *ifp; /* the interface this rxq belongs to */ 576#if defined(INET) || defined(INET6) 577 struct lro_ctrl lro; /* LRO state */ 578#endif 579 580 /* stats for common events first */ 581 582 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 583 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 584 585 /* stats for not-that-common events */ 586 587} __aligned(CACHE_LINE_SIZE); 588 589static inline struct sge_rxq * 590iq_to_rxq(struct sge_iq *iq) 591{ 592 593 return (__containerof(iq, struct sge_rxq, iq)); 594} 595 596 597/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 598struct sge_ofld_rxq { 599 struct sge_iq iq; /* MUST be first */ 600 struct sge_fl fl; /* MUST follow iq */ 601} __aligned(CACHE_LINE_SIZE); 602 603static inline struct sge_ofld_rxq * 604iq_to_ofld_rxq(struct sge_iq *iq) 605{ 606 607 return (__containerof(iq, struct sge_ofld_rxq, iq)); 608} 609 610struct wrqe { 611 STAILQ_ENTRY(wrqe) link; 612 struct sge_wrq *wrq; 613 int wr_len; 614 char wr[] __aligned(16); 615}; 616 617struct wrq_cookie { 618 TAILQ_ENTRY(wrq_cookie) link; 619 int ndesc; 620 int pidx; 621}; 622 623/* 624 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 625 * and offload tx queues are of this type. 626 */ 627struct sge_wrq { 628 struct sge_eq eq; /* MUST be first */ 629 630 struct adapter *adapter; 631 struct task wrq_tx_task; 632 633 /* Tx desc reserved but WR not "committed" yet. */ 634 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 635 636 /* List of WRs ready to go out as soon as descriptors are available. */ 637 STAILQ_HEAD(, wrqe) wr_list; 638 u_int nwr_pending; 639 u_int ndesc_needed; 640 641 /* stats for common events first */ 642 643 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 644 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 645 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 646 647 /* stats for not-that-common events */ 648 649 /* 650 * Scratch space for work requests that wrap around after reaching the 651 * status page, and some infomation about the last WR that used it. 652 */ 653 uint16_t ss_pidx; 654 uint16_t ss_len; 655 uint8_t ss[SGE_MAX_WR_LEN]; 656 657} __aligned(CACHE_LINE_SIZE); 658 659 660struct sge_nm_rxq { 661 struct vi_info *vi; 662 663 struct iq_desc *iq_desc; 664 uint16_t iq_abs_id; 665 uint16_t iq_cntxt_id; 666 uint16_t iq_cidx; 667 uint16_t iq_sidx; 668 uint8_t iq_gen; 669 670 __be64 *fl_desc; 671 uint16_t fl_cntxt_id; 672 uint32_t fl_cidx; 673 uint32_t fl_pidx; 674 uint32_t fl_sidx; 675 uint32_t fl_db_val; 676 u_int fl_hwidx:4; 677 678 u_int nid; /* netmap ring # for this queue */ 679 680 /* infrequently used items after this */ 681 682 bus_dma_tag_t iq_desc_tag; 683 bus_dmamap_t iq_desc_map; 684 bus_addr_t iq_ba; 685 int intr_idx; 686 687 bus_dma_tag_t fl_desc_tag; 688 bus_dmamap_t fl_desc_map; 689 bus_addr_t fl_ba; 690} __aligned(CACHE_LINE_SIZE); 691 692struct sge_nm_txq { 693 struct tx_desc *desc; 694 uint16_t cidx; 695 uint16_t pidx; 696 uint16_t sidx; 697 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 698 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 699 uint16_t dbidx; /* pidx of the most recent doorbell */ 700 uint16_t doorbells; 701 volatile uint32_t *udb; 702 u_int udb_qid; 703 u_int cntxt_id; 704 __be32 cpl_ctrl0; /* for convenience */ 705 u_int nid; /* netmap ring # for this queue */ 706 707 /* infrequently used items after this */ 708 709 bus_dma_tag_t desc_tag; 710 bus_dmamap_t desc_map; 711 bus_addr_t ba; 712 int iqidx; 713} __aligned(CACHE_LINE_SIZE); 714 715struct sge { 716 int nrxq; /* total # of Ethernet rx queues */ 717 int ntxq; /* total # of Ethernet tx tx queues */ 718 int nofldrxq; /* total # of TOE rx queues */ 719 int nofldtxq; /* total # of TOE tx queues */ 720 int nnmrxq; /* total # of netmap rx queues */ 721 int nnmtxq; /* total # of netmap tx queues */ 722 int niq; /* total # of ingress queues */ 723 int neq; /* total # of egress queues */ 724 725 struct sge_iq fwq; /* Firmware event queue */ 726 struct sge_wrq mgmtq; /* Management queue (control queue) */ 727 struct sge_wrq *ctrlq; /* Control queues */ 728 struct sge_txq *txq; /* NIC tx queues */ 729 struct sge_rxq *rxq; /* NIC rx queues */ 730 struct sge_wrq *ofld_txq; /* TOE tx queues */ 731 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 732 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 733 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 734 735 uint16_t iq_start; /* first cntxt_id */ 736 uint16_t iq_base; /* first abs_id */ 737 int eq_start; /* first cntxt_id */ 738 int eq_base; /* first abs_id */ 739 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 740 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 741 742 int8_t safe_hwidx1; /* may not have room for metadata */ 743 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 744 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 745 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 746}; 747 748struct adapter { 749 SLIST_ENTRY(adapter) link; 750 device_t dev; 751 struct cdev *cdev; 752 753 /* PCIe register resources */ 754 int regs_rid; 755 struct resource *regs_res; 756 int msix_rid; 757 struct resource *msix_res; 758 bus_space_handle_t bh; 759 bus_space_tag_t bt; 760 bus_size_t mmio_len; 761 int udbs_rid; 762 struct resource *udbs_res; 763 volatile uint8_t *udbs_base; 764 765 unsigned int pf; 766 unsigned int mbox; 767 unsigned int vpd_busy; 768 unsigned int vpd_flag; 769 770 /* Interrupt information */ 771 int intr_type; 772 int intr_count; 773 struct irq { 774 struct resource *res; 775 int rid; 776 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 777 void *tag; 778 struct sge_rxq *rxq; 779 struct sge_nm_rxq *nm_rxq; 780 } __aligned(CACHE_LINE_SIZE) *irq; 781 int sge_gts_reg; 782 int sge_kdoorbell_reg; 783 784 bus_dma_tag_t dmat; /* Parent DMA tag */ 785 786 struct sge sge; 787 int lro_timeout; 788 int sc_do_rxcopy; 789 790 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 791 struct port_info *port[MAX_NPORTS]; 792 uint8_t chan_map[MAX_NCHAN]; 793 794 void *tom_softc; /* (struct tom_data *) */ 795 struct tom_tunables tt; 796 void *iwarp_softc; /* (struct c4iw_dev *) */ 797 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 798 struct l2t_data *l2t; /* L2 table */ 799 struct tid_info tids; 800 801 uint16_t doorbells; 802 int offload_map; /* ports with IFCAP_TOE enabled */ 803 int active_ulds; /* ULDs activated on this adapter */ 804 int flags; 805 int debug_flags; 806 807 char ifp_lockname[16]; 808 struct mtx ifp_lock; 809 struct ifnet *ifp; /* tracer ifp */ 810 struct ifmedia media; 811 int traceq; /* iq used by all tracers, -1 if none */ 812 int tracer_valid; /* bitmap of valid tracers */ 813 int tracer_enabled; /* bitmap of enabled tracers */ 814 815 char fw_version[16]; 816 char tp_version[16]; 817 char exprom_version[16]; 818 char cfg_file[32]; 819 u_int cfcsum; 820 struct adapter_params params; 821 const struct chip_params *chip_params; 822 struct t4_virt_res vres; 823 824 uint16_t nbmcaps; 825 uint16_t linkcaps; 826 uint16_t switchcaps; 827 uint16_t niccaps; 828 uint16_t toecaps; 829 uint16_t rdmacaps; 830 uint16_t tlscaps; 831 uint16_t iscsicaps; 832 uint16_t fcoecaps; 833 834 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 835 836 struct mtx sc_lock; 837 char lockname[16]; 838 839 /* Starving free lists */ 840 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 841 TAILQ_HEAD(, sge_fl) sfl; 842 struct callout sfl_callout; 843 844 struct mtx reg_lock; /* for indirect register access */ 845 846 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 847 848 const char *last_op; 849 const void *last_op_thr; 850 int last_op_flags; 851}; 852 853#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 854#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 855#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 856#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 857 858#define ASSERT_SYNCHRONIZED_OP(sc) \ 859 KASSERT(IS_BUSY(sc) && \ 860 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 861 ("%s: operation not synchronized.", __func__)) 862 863#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 864#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 865#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 866#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 867 868#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 869#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 870#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 871#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 872#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 873 874#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 875#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 876#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 877#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 878 879#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 880#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 881#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 882#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 883#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 884 885#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 886#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 887#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 888#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 889#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 890 891#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 892 do { \ 893 if (sc->debug_flags & DF_DUMP_MBOX) { \ 894 log(LOG_NOTICE, \ 895 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 896 "%016llx %016llx %016llx %016llx\n", \ 897 device_get_nameunit(sc->dev), mbox, \ 898 (unsigned long long)t4_read_reg64(sc, data_reg), \ 899 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 900 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 901 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 902 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 903 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 904 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 905 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 906 } \ 907 } while (0) 908 909#define for_each_txq(vi, iter, q) \ 910 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 911 iter < vi->ntxq; ++iter, ++q) 912#define for_each_rxq(vi, iter, q) \ 913 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 914 iter < vi->nrxq; ++iter, ++q) 915#define for_each_ofld_txq(vi, iter, q) \ 916 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 917 iter < vi->nofldtxq; ++iter, ++q) 918#define for_each_ofld_rxq(vi, iter, q) \ 919 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 920 iter < vi->nofldrxq; ++iter, ++q) 921#define for_each_nm_txq(vi, iter, q) \ 922 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 923 iter < vi->nnmtxq; ++iter, ++q) 924#define for_each_nm_rxq(vi, iter, q) \ 925 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 926 iter < vi->nnmrxq; ++iter, ++q) 927#define for_each_vi(_pi, _iter, _vi) \ 928 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 929 ++(_iter), ++(_vi)) 930 931#define IDXINCR(idx, incr, wrap) do { \ 932 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 933} while (0) 934#define IDXDIFF(head, tail, wrap) \ 935 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 936 937/* One for errors, one for firmware events */ 938#define T4_EXTRA_INTR 2 939 940/* One for firmware events */ 941#define T4VF_EXTRA_INTR 1 942 943static inline uint32_t 944t4_read_reg(struct adapter *sc, uint32_t reg) 945{ 946 947 return bus_space_read_4(sc->bt, sc->bh, reg); 948} 949 950static inline void 951t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 952{ 953 954 bus_space_write_4(sc->bt, sc->bh, reg, val); 955} 956 957static inline uint64_t 958t4_read_reg64(struct adapter *sc, uint32_t reg) 959{ 960 961 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 962} 963 964static inline void 965t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 966{ 967 968 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 969} 970 971static inline void 972t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 973{ 974 975 *val = pci_read_config(sc->dev, reg, 1); 976} 977 978static inline void 979t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 980{ 981 982 pci_write_config(sc->dev, reg, val, 1); 983} 984 985static inline void 986t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 987{ 988 989 *val = pci_read_config(sc->dev, reg, 2); 990} 991 992static inline void 993t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 994{ 995 996 pci_write_config(sc->dev, reg, val, 2); 997} 998 999static inline void 1000t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1001{ 1002 1003 *val = pci_read_config(sc->dev, reg, 4); 1004} 1005 1006static inline void 1007t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1008{ 1009 1010 pci_write_config(sc->dev, reg, val, 4); 1011} 1012 1013static inline struct port_info * 1014adap2pinfo(struct adapter *sc, int idx) 1015{ 1016 1017 return (sc->port[idx]); 1018} 1019 1020static inline void 1021t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 1022{ 1023 1024 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN); 1025} 1026 1027static inline bool 1028is_10G_port(const struct port_info *pi) 1029{ 1030 1031 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1032} 1033 1034static inline bool 1035is_40G_port(const struct port_info *pi) 1036{ 1037 1038 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1039} 1040 1041static inline int 1042port_top_speed(const struct port_info *pi) 1043{ 1044 1045 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1046 return (100); 1047 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1048 return (40); 1049 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1050 return (10); 1051 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1052 return (1); 1053 1054 return (0); 1055} 1056 1057static inline int 1058tx_resume_threshold(struct sge_eq *eq) 1059{ 1060 1061 /* not quite the same as qsize / 4, but this will do. */ 1062 return (eq->sidx / 4); 1063} 1064 1065static inline int 1066t4_use_ldst(struct adapter *sc) 1067{ 1068 1069#ifdef notyet 1070 return (sc->flags & FW_OK || !sc->use_bd); 1071#else 1072 return (0); 1073#endif 1074} 1075 1076/* t4_main.c */ 1077extern int t4_ntxq10g; 1078extern int t4_nrxq10g; 1079extern int t4_ntxq1g; 1080extern int t4_nrxq1g; 1081extern int t4_intr_types; 1082extern int t4_tmr_idx_10g; 1083extern int t4_pktc_idx_10g; 1084extern int t4_tmr_idx_1g; 1085extern int t4_pktc_idx_1g; 1086extern unsigned int t4_qsize_rxq; 1087extern unsigned int t4_qsize_txq; 1088extern device_method_t cxgbe_methods[]; 1089 1090int t4_os_find_pci_capability(struct adapter *, int); 1091int t4_os_pci_save_state(struct adapter *); 1092int t4_os_pci_restore_state(struct adapter *); 1093void t4_os_portmod_changed(const struct adapter *, int); 1094void t4_os_link_changed(struct adapter *, int, int, int); 1095void t4_iterate(void (*)(struct adapter *, void *), void *); 1096void t4_add_adapter(struct adapter *); 1097int t4_detach_common(device_t); 1098int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1099int t4_map_bars_0_and_4(struct adapter *); 1100int t4_map_bar_2(struct adapter *); 1101int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1102int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1103int t4_setup_intr_handlers(struct adapter *); 1104void t4_sysctls(struct adapter *); 1105int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1106void doom_vi(struct adapter *, struct vi_info *); 1107void end_synchronized_op(struct adapter *, int); 1108int update_mac_settings(struct ifnet *, int); 1109int adapter_full_init(struct adapter *); 1110int adapter_full_uninit(struct adapter *); 1111uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1112int vi_full_init(struct vi_info *); 1113int vi_full_uninit(struct vi_info *); 1114void vi_sysctls(struct vi_info *); 1115void vi_tick(void *); 1116 1117#ifdef DEV_NETMAP 1118/* t4_netmap.c */ 1119void cxgbe_nm_attach(struct vi_info *); 1120void cxgbe_nm_detach(struct vi_info *); 1121void t4_nm_intr(void *); 1122#endif 1123 1124/* t4_sge.c */ 1125void t4_sge_modload(void); 1126void t4_sge_modunload(void); 1127uint64_t t4_sge_extfree_refs(void); 1128void t4_tweak_chip_settings(struct adapter *); 1129int t4_read_chip_settings(struct adapter *); 1130int t4_create_dma_tag(struct adapter *); 1131void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1132 struct sysctl_oid_list *); 1133int t4_destroy_dma_tag(struct adapter *); 1134int t4_setup_adapter_queues(struct adapter *); 1135int t4_teardown_adapter_queues(struct adapter *); 1136int t4_setup_vi_queues(struct vi_info *); 1137int t4_teardown_vi_queues(struct vi_info *); 1138void t4_intr_all(void *); 1139void t4_intr(void *); 1140void t4_vi_intr(void *); 1141void t4_intr_err(void *); 1142void t4_intr_evt(void *); 1143void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1144void t4_update_fl_bufsize(struct ifnet *); 1145int parse_pkt(struct adapter *, struct mbuf **); 1146void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1147void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1148int tnl_cong(struct port_info *, int); 1149int t4_register_an_handler(an_handler_t); 1150int t4_register_fw_msg_handler(int, fw_msg_handler_t); 1151int t4_register_cpl_handler(int, cpl_handler_t); 1152 1153/* t4_tracer.c */ 1154struct t4_tracer; 1155void t4_tracer_modload(void); 1156void t4_tracer_modunload(void); 1157void t4_tracer_port_detach(struct adapter *); 1158int t4_get_tracer(struct adapter *, struct t4_tracer *); 1159int t4_set_tracer(struct adapter *, struct t4_tracer *); 1160int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1161int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1162 1163static inline struct wrqe * 1164alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1165{ 1166 int len = offsetof(struct wrqe, wr) + wr_len; 1167 struct wrqe *wr; 1168 1169 wr = malloc(len, M_CXGBE, M_NOWAIT); 1170 if (__predict_false(wr == NULL)) 1171 return (NULL); 1172 wr->wr_len = wr_len; 1173 wr->wrq = wrq; 1174 return (wr); 1175} 1176 1177static inline void * 1178wrtod(struct wrqe *wr) 1179{ 1180 return (&wr->wr[0]); 1181} 1182 1183static inline void 1184free_wrqe(struct wrqe *wr) 1185{ 1186 free(wr, M_CXGBE); 1187} 1188 1189static inline void 1190t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1191{ 1192 struct sge_wrq *wrq = wr->wrq; 1193 1194 TXQ_LOCK(wrq); 1195 t4_wrq_tx_locked(sc, wrq, wr); 1196 TXQ_UNLOCK(wrq); 1197} 1198 1199#endif 1200