adapter.h revision 308304
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/10/sys/dev/cxgbe/adapter.h 308304 2016-11-04 18:45:06Z jhb $ 28 * 29 */ 30 31#ifndef __T4_ADAPTER_H__ 32#define __T4_ADAPTER_H__ 33 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/types.h> 38#include <sys/malloc.h> 39#include <dev/pci/pcivar.h> 40#include <dev/pci/pcireg.h> 41#include <machine/bus.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44#include <net/ethernet.h> 45#include <net/if.h> 46#include <net/if_media.h> 47#include <netinet/in.h> 48#include <netinet/tcp_lro.h> 49 50#include "offload.h" 51#include "common/t4_msg.h" 52#include "firmware/t4fw_interface.h" 53 54#define KTR_CXGBE KTR_SPARE3 55MALLOC_DECLARE(M_CXGBE); 56#define CXGBE_UNIMPLEMENTED(s) \ 57 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 58 59#if defined(__i386__) || defined(__amd64__) 60static __inline void 61prefetch(void *x) 62{ 63 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 64} 65#else 66#define prefetch(x) 67#endif 68 69#ifndef SYSCTL_ADD_UQUAD 70#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 71#define sysctl_handle_64 sysctl_handle_quad 72#define CTLTYPE_U64 CTLTYPE_QUAD 73#endif 74 75#if (__FreeBSD_version >= 900030) || \ 76 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 77#define SBUF_DRAIN 1 78#endif 79 80#ifdef __amd64__ 81/* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 82static __inline uint64_t 83t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 84 bus_size_t offset) 85{ 86 KASSERT(tag == X86_BUS_SPACE_MEM, 87 ("%s: can only handle mem space", __func__)); 88 89 return (*(volatile uint64_t *)(handle + offset)); 90} 91 92static __inline void 93t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 94 bus_size_t offset, uint64_t value) 95{ 96 KASSERT(tag == X86_BUS_SPACE_MEM, 97 ("%s: can only handle mem space", __func__)); 98 99 *(volatile uint64_t *)(bsh + offset) = value; 100} 101#else 102static __inline uint64_t 103t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 104 bus_size_t offset) 105{ 106 return (uint64_t)bus_space_read_4(tag, handle, offset) + 107 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 108} 109 110static __inline void 111t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 112 bus_size_t offset, uint64_t value) 113{ 114 bus_space_write_4(tag, bsh, offset, value); 115 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 116} 117#endif 118 119struct adapter; 120typedef struct adapter adapter_t; 121 122enum { 123 /* 124 * All ingress queues use this entry size. Note that the firmware event 125 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 126 * be at least 64. 127 */ 128 IQ_ESIZE = 64, 129 130 /* Default queue sizes for all kinds of ingress queues */ 131 FW_IQ_QSIZE = 256, 132 RX_IQ_QSIZE = 1024, 133 134 /* All egress queues use this entry size */ 135 EQ_ESIZE = 64, 136 137 /* Default queue sizes for all kinds of egress queues */ 138 CTRL_EQ_QSIZE = 128, 139 TX_EQ_QSIZE = 1024, 140 141#if MJUMPAGESIZE != MCLBYTES 142 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 143#else 144 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 145#endif 146 CL_METADATA_SIZE = CACHE_LINE_SIZE, 147 148 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 149 TX_SGL_SEGS = 39, 150 TX_SGL_SEGS_TSO = 38, 151 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 152}; 153 154enum { 155 /* adapter intr_type */ 156 INTR_INTX = (1 << 0), 157 INTR_MSI = (1 << 1), 158 INTR_MSIX = (1 << 2) 159}; 160 161enum { 162 XGMAC_MTU = (1 << 0), 163 XGMAC_PROMISC = (1 << 1), 164 XGMAC_ALLMULTI = (1 << 2), 165 XGMAC_VLANEX = (1 << 3), 166 XGMAC_UCADDR = (1 << 4), 167 XGMAC_MCADDRS = (1 << 5), 168 169 XGMAC_ALL = 0xffff 170}; 171 172enum { 173 /* flags understood by begin_synchronized_op */ 174 HOLD_LOCK = (1 << 0), 175 SLEEP_OK = (1 << 1), 176 INTR_OK = (1 << 2), 177 178 /* flags understood by end_synchronized_op */ 179 LOCK_HELD = HOLD_LOCK, 180}; 181 182enum { 183 /* adapter flags */ 184 FULL_INIT_DONE = (1 << 0), 185 FW_OK = (1 << 1), 186 /* INTR_DIRECT = (1 << 2), No longer used. */ 187 MASTER_PF = (1 << 3), 188 ADAP_SYSCTL_CTX = (1 << 4), 189 /* TOM_INIT_DONE= (1 << 5), No longer used */ 190 BUF_PACKING_OK = (1 << 6), 191 192 CXGBE_BUSY = (1 << 9), 193 194 /* port flags */ 195 HAS_TRACEQ = (1 << 3), 196 197 /* VI flags */ 198 DOOMED = (1 << 0), 199 VI_INIT_DONE = (1 << 1), 200 VI_SYSCTL_CTX = (1 << 2), 201 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 202 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 203 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 204 205 /* adapter debug_flags */ 206 DF_DUMP_MBOX = (1 << 0), 207}; 208 209#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 210#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 211#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 212#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 213#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 214 215struct vi_info { 216 device_t dev; 217 struct port_info *pi; 218 219 struct ifnet *ifp; 220 struct ifmedia media; 221 222 unsigned long flags; 223 int if_flags; 224 225 uint16_t *rss, *nm_rss; 226 uint16_t viid; 227 int16_t xact_addr_filt;/* index of exact MAC address filter */ 228 uint16_t rss_size; /* size of VI's RSS table slice */ 229 uint16_t rss_base; /* start of VI's RSS table slice */ 230 231 eventhandler_tag vlan_c; 232 233 int nintr; 234 int first_intr; 235 236 /* These need to be int as they are used in sysctl */ 237 int ntxq; /* # of tx queues */ 238 int first_txq; /* index of first tx queue */ 239 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 240 int nrxq; /* # of rx queues */ 241 int first_rxq; /* index of first rx queue */ 242 int nofldtxq; /* # of offload tx queues */ 243 int first_ofld_txq; /* index of first offload tx queue */ 244 int nofldrxq; /* # of offload rx queues */ 245 int first_ofld_rxq; /* index of first offload rx queue */ 246 int nnmtxq; 247 int first_nm_txq; 248 int nnmrxq; 249 int first_nm_rxq; 250 int tmr_idx; 251 int pktc_idx; 252 int qsize_rxq; 253 int qsize_txq; 254 255 struct timeval last_refreshed; 256 struct fw_vi_stats_vf stats; 257 258 struct callout tick; 259 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 260 261 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 262}; 263 264struct port_info { 265 device_t dev; 266 struct adapter *adapter; 267 268 struct vi_info *vi; 269 int nvi; 270 int up_vis; 271 int uld_vis; 272 273 struct mtx pi_lock; 274 char lockname[16]; 275 unsigned long flags; 276 277 uint8_t lport; /* associated offload logical port */ 278 int8_t mdio_addr; 279 uint8_t port_type; 280 uint8_t mod_type; 281 uint8_t port_id; 282 uint8_t tx_chan; 283 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 284 285 int linkdnrc; 286 struct link_config link_cfg; 287 288 struct timeval last_refreshed; 289 struct port_stats stats; 290 u_int tx_parse_error; 291 292 struct callout tick; 293}; 294 295#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 296 297/* Where the cluster came from, how it has been carved up. */ 298struct cluster_layout { 299 int8_t zidx; 300 int8_t hwidx; 301 uint16_t region1; /* mbufs laid out within this region */ 302 /* region2 is the DMA region */ 303 uint16_t region3; /* cluster_metadata within this region */ 304}; 305 306struct cluster_metadata { 307 u_int refcount; 308 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 309}; 310 311struct fl_sdesc { 312 caddr_t cl; 313 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 314 struct cluster_layout cll; 315}; 316 317struct tx_desc { 318 __be64 flit[8]; 319}; 320 321struct tx_sdesc { 322 struct mbuf *m; /* m_nextpkt linked chain of frames */ 323 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 324}; 325 326 327#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 328struct iq_desc { 329 struct rss_header rss; 330 uint8_t cpl[IQ_PAD]; 331 struct rsp_ctrl rsp; 332}; 333#undef IQ_PAD 334CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 335 336enum { 337 /* iq flags */ 338 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 339 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 340 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 341 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 342 343 /* iq state */ 344 IQS_DISABLED = 0, 345 IQS_BUSY = 1, 346 IQS_IDLE = 2, 347 348 /* netmap related flags */ 349 NM_OFF = 0, 350 NM_ON = 1, 351 NM_BUSY = 2, 352}; 353 354/* 355 * Ingress Queue: T4 is producer, driver is consumer. 356 */ 357struct sge_iq { 358 uint32_t flags; 359 volatile int state; 360 struct adapter *adapter; 361 struct iq_desc *desc; /* KVA of descriptor ring */ 362 int8_t intr_pktc_idx; /* packet count threshold index */ 363 uint8_t gen; /* generation bit */ 364 uint8_t intr_params; /* interrupt holdoff parameters */ 365 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 366 uint16_t qsize; /* size (# of entries) of the queue */ 367 uint16_t sidx; /* index of the entry with the status page */ 368 uint16_t cidx; /* consumer index */ 369 uint16_t cntxt_id; /* SGE context id for the iq */ 370 uint16_t abs_id; /* absolute SGE id for the iq */ 371 372 STAILQ_ENTRY(sge_iq) link; 373 374 bus_dma_tag_t desc_tag; 375 bus_dmamap_t desc_map; 376 bus_addr_t ba; /* bus address of descriptor ring */ 377}; 378 379enum { 380 EQ_CTRL = 1, 381 EQ_ETH = 2, 382 EQ_OFLD = 3, 383 384 /* eq flags */ 385 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 386 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 387 EQ_ENABLED = (1 << 3), /* open for business */ 388}; 389 390/* Listed in order of preference. Update t4_sysctls too if you change these */ 391enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 392 393/* 394 * Egress Queue: driver is producer, T4 is consumer. 395 * 396 * Note: A free list is an egress queue (driver produces the buffers and T4 397 * consumes them) but it's special enough to have its own struct (see sge_fl). 398 */ 399struct sge_eq { 400 unsigned int flags; /* MUST be first */ 401 unsigned int cntxt_id; /* SGE context id for the eq */ 402 struct mtx eq_lock; 403 404 struct tx_desc *desc; /* KVA of descriptor ring */ 405 uint16_t doorbells; 406 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 407 u_int udb_qid; /* relative qid within the doorbell page */ 408 uint16_t sidx; /* index of the entry with the status page */ 409 uint16_t cidx; /* consumer idx (desc idx) */ 410 uint16_t pidx; /* producer idx (desc idx) */ 411 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 412 uint16_t dbidx; /* pidx of the most recent doorbell */ 413 uint16_t iqid; /* iq that gets egr_update for the eq */ 414 uint8_t tx_chan; /* tx channel used by the eq */ 415 volatile u_int equiq; /* EQUIQ outstanding */ 416 417 bus_dma_tag_t desc_tag; 418 bus_dmamap_t desc_map; 419 bus_addr_t ba; /* bus address of descriptor ring */ 420 char lockname[16]; 421}; 422 423struct sw_zone_info { 424 uma_zone_t zone; /* zone that this cluster comes from */ 425 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 426 int type; /* EXT_xxx type of the cluster */ 427 int8_t head_hwidx; 428 int8_t tail_hwidx; 429}; 430 431struct hw_buf_info { 432 int8_t zidx; /* backpointer to zone; -ve means unused */ 433 int8_t next; /* next hwidx for this zone; -1 means no more */ 434 int size; 435}; 436 437enum { 438 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 439 FL_DOOMED = (1 << 1), /* about to be destroyed */ 440 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 441 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 442}; 443 444#define FL_RUNNING_LOW(fl) \ 445 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 446#define FL_NOT_RUNNING_LOW(fl) \ 447 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 448 449struct sge_fl { 450 struct mtx fl_lock; 451 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 452 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 453 struct cluster_layout cll_def; /* default refill zone, layout */ 454 uint16_t lowat; /* # of buffers <= this means fl needs help */ 455 int flags; 456 uint16_t buf_boundary; 457 458 /* The 16b idx all deal with hw descriptors */ 459 uint16_t dbidx; /* hw pidx after last doorbell */ 460 uint16_t sidx; /* index of status page */ 461 volatile uint16_t hw_cidx; 462 463 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 464 uint32_t cidx; /* consumer index */ 465 uint32_t pidx; /* producer index */ 466 467 uint32_t dbval; 468 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 469 volatile uint32_t *udb; 470 471 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 472 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 473 uint64_t cl_allocated; /* # of clusters allocated */ 474 uint64_t cl_recycled; /* # of clusters recycled */ 475 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 476 477 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 478 struct mbuf *m0; 479 struct mbuf **pnext; 480 u_int remaining; 481 482 uint16_t qsize; /* # of hw descriptors (status page included) */ 483 uint16_t cntxt_id; /* SGE context id for the freelist */ 484 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 485 bus_dma_tag_t desc_tag; 486 bus_dmamap_t desc_map; 487 char lockname[16]; 488 bus_addr_t ba; /* bus address of descriptor ring */ 489 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 490}; 491 492struct mp_ring; 493 494/* txq: SGE egress queue + what's needed for Ethernet NIC */ 495struct sge_txq { 496 struct sge_eq eq; /* MUST be first */ 497 498 struct ifnet *ifp; /* the interface this txq belongs to */ 499 struct mp_ring *r; /* tx software ring */ 500 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 501 struct sglist *gl; 502 __be32 cpl_ctrl0; /* for convenience */ 503 504 struct task tx_reclaim_task; 505 /* stats for common events first */ 506 507 uint64_t txcsum; /* # of times hardware assisted with checksum */ 508 uint64_t tso_wrs; /* # of TSO work requests */ 509 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 510 uint64_t imm_wrs; /* # of work requests with immediate data */ 511 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 512 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 513 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 514 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 515 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 516 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 517 518 /* stats for not-that-common events */ 519} __aligned(CACHE_LINE_SIZE); 520 521/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 522struct sge_rxq { 523 struct sge_iq iq; /* MUST be first */ 524 struct sge_fl fl; /* MUST follow iq */ 525 526 struct ifnet *ifp; /* the interface this rxq belongs to */ 527#if defined(INET) || defined(INET6) 528 struct lro_ctrl lro; /* LRO state */ 529#endif 530 531 /* stats for common events first */ 532 533 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 534 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 535 536 /* stats for not-that-common events */ 537 538} __aligned(CACHE_LINE_SIZE); 539 540static inline struct sge_rxq * 541iq_to_rxq(struct sge_iq *iq) 542{ 543 544 return (__containerof(iq, struct sge_rxq, iq)); 545} 546 547 548/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 549struct sge_ofld_rxq { 550 struct sge_iq iq; /* MUST be first */ 551 struct sge_fl fl; /* MUST follow iq */ 552} __aligned(CACHE_LINE_SIZE); 553 554static inline struct sge_ofld_rxq * 555iq_to_ofld_rxq(struct sge_iq *iq) 556{ 557 558 return (__containerof(iq, struct sge_ofld_rxq, iq)); 559} 560 561struct wrqe { 562 STAILQ_ENTRY(wrqe) link; 563 struct sge_wrq *wrq; 564 int wr_len; 565 char wr[] __aligned(16); 566}; 567 568struct wrq_cookie { 569 TAILQ_ENTRY(wrq_cookie) link; 570 int ndesc; 571 int pidx; 572}; 573 574/* 575 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 576 * and offload tx queues are of this type. 577 */ 578struct sge_wrq { 579 struct sge_eq eq; /* MUST be first */ 580 581 struct adapter *adapter; 582 struct task wrq_tx_task; 583 584 /* Tx desc reserved but WR not "committed" yet. */ 585 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 586 587 /* List of WRs ready to go out as soon as descriptors are available. */ 588 STAILQ_HEAD(, wrqe) wr_list; 589 u_int nwr_pending; 590 u_int ndesc_needed; 591 592 /* stats for common events first */ 593 594 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 595 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 596 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 597 598 /* stats for not-that-common events */ 599 600 /* 601 * Scratch space for work requests that wrap around after reaching the 602 * status page, and some infomation about the last WR that used it. 603 */ 604 uint16_t ss_pidx; 605 uint16_t ss_len; 606 uint8_t ss[SGE_MAX_WR_LEN]; 607 608} __aligned(CACHE_LINE_SIZE); 609 610 611struct sge_nm_rxq { 612 struct vi_info *vi; 613 614 struct iq_desc *iq_desc; 615 uint16_t iq_abs_id; 616 uint16_t iq_cntxt_id; 617 uint16_t iq_cidx; 618 uint16_t iq_sidx; 619 uint8_t iq_gen; 620 621 __be64 *fl_desc; 622 uint16_t fl_cntxt_id; 623 uint32_t fl_cidx; 624 uint32_t fl_pidx; 625 uint32_t fl_sidx; 626 uint32_t fl_db_val; 627 u_int fl_hwidx:4; 628 629 u_int nid; /* netmap ring # for this queue */ 630 631 /* infrequently used items after this */ 632 633 bus_dma_tag_t iq_desc_tag; 634 bus_dmamap_t iq_desc_map; 635 bus_addr_t iq_ba; 636 int intr_idx; 637 638 bus_dma_tag_t fl_desc_tag; 639 bus_dmamap_t fl_desc_map; 640 bus_addr_t fl_ba; 641} __aligned(CACHE_LINE_SIZE); 642 643struct sge_nm_txq { 644 struct tx_desc *desc; 645 uint16_t cidx; 646 uint16_t pidx; 647 uint16_t sidx; 648 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 649 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 650 uint16_t dbidx; /* pidx of the most recent doorbell */ 651 uint16_t doorbells; 652 volatile uint32_t *udb; 653 u_int udb_qid; 654 u_int cntxt_id; 655 __be32 cpl_ctrl0; /* for convenience */ 656 u_int nid; /* netmap ring # for this queue */ 657 658 /* infrequently used items after this */ 659 660 bus_dma_tag_t desc_tag; 661 bus_dmamap_t desc_map; 662 bus_addr_t ba; 663 int iqidx; 664} __aligned(CACHE_LINE_SIZE); 665 666struct sge { 667 int nrxq; /* total # of Ethernet rx queues */ 668 int ntxq; /* total # of Ethernet tx tx queues */ 669 int nofldrxq; /* total # of TOE rx queues */ 670 int nofldtxq; /* total # of TOE tx queues */ 671 int nnmrxq; /* total # of netmap rx queues */ 672 int nnmtxq; /* total # of netmap tx queues */ 673 int niq; /* total # of ingress queues */ 674 int neq; /* total # of egress queues */ 675 676 struct sge_iq fwq; /* Firmware event queue */ 677 struct sge_wrq mgmtq; /* Management queue (control queue) */ 678 struct sge_wrq *ctrlq; /* Control queues */ 679 struct sge_txq *txq; /* NIC tx queues */ 680 struct sge_rxq *rxq; /* NIC rx queues */ 681 struct sge_wrq *ofld_txq; /* TOE tx queues */ 682 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 683 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 684 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 685 686 uint16_t iq_start; 687 int eq_start; 688 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 689 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 690 691 int8_t safe_hwidx1; /* may not have room for metadata */ 692 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 693 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 694 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 695}; 696 697struct rss_header; 698typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 699 struct mbuf *); 700typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 701typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 702 703struct adapter { 704 SLIST_ENTRY(adapter) link; 705 device_t dev; 706 struct cdev *cdev; 707 708 /* PCIe register resources */ 709 int regs_rid; 710 struct resource *regs_res; 711 int msix_rid; 712 struct resource *msix_res; 713 bus_space_handle_t bh; 714 bus_space_tag_t bt; 715 bus_size_t mmio_len; 716 int udbs_rid; 717 struct resource *udbs_res; 718 volatile uint8_t *udbs_base; 719 720 unsigned int pf; 721 unsigned int mbox; 722 unsigned int vpd_busy; 723 unsigned int vpd_flag; 724 725 /* Interrupt information */ 726 int intr_type; 727 int intr_count; 728 struct irq { 729 struct resource *res; 730 int rid; 731 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 732 void *tag; 733 struct sge_rxq *rxq; 734 struct sge_nm_rxq *nm_rxq; 735 } __aligned(CACHE_LINE_SIZE) *irq; 736 737 bus_dma_tag_t dmat; /* Parent DMA tag */ 738 739 struct sge sge; 740 int lro_timeout; 741 742 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 743 struct port_info *port[MAX_NPORTS]; 744 uint8_t chan_map[MAX_NCHAN]; 745 746 void *tom_softc; /* (struct tom_data *) */ 747 struct tom_tunables tt; 748 void *iwarp_softc; /* (struct c4iw_dev *) */ 749 void *iscsi_softc; 750 struct l2t_data *l2t; /* L2 table */ 751 struct tid_info tids; 752 753 uint16_t doorbells; 754 int offload_map; /* ports with IFCAP_TOE enabled */ 755 int active_ulds; /* ULDs activated on this adapter */ 756 int flags; 757 int debug_flags; 758 759 char ifp_lockname[16]; 760 struct mtx ifp_lock; 761 struct ifnet *ifp; /* tracer ifp */ 762 struct ifmedia media; 763 int traceq; /* iq used by all tracers, -1 if none */ 764 int tracer_valid; /* bitmap of valid tracers */ 765 int tracer_enabled; /* bitmap of enabled tracers */ 766 767 char fw_version[32]; 768 char cfg_file[32]; 769 u_int cfcsum; 770 struct adapter_params params; 771 const struct chip_params *chip_params; 772 struct t4_virt_res vres; 773 774 uint16_t nbmcaps; 775 uint16_t linkcaps; 776 uint16_t switchcaps; 777 uint16_t niccaps; 778 uint16_t toecaps; 779 uint16_t rdmacaps; 780 uint16_t tlscaps; 781 uint16_t iscsicaps; 782 uint16_t fcoecaps; 783 784 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 785 786 struct mtx sc_lock; 787 char lockname[16]; 788 789 /* Starving free lists */ 790 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 791 TAILQ_HEAD(, sge_fl) sfl; 792 struct callout sfl_callout; 793 794 struct mtx regwin_lock; /* for indirect reads and memory windows */ 795 796 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 797 fw_msg_handler_t fw_msg_handler[7]; /* NUM_FW6_TYPES */ 798 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 799 800 const char *last_op; 801 const void *last_op_thr; 802 int last_op_flags; 803 804 int sc_do_rxcopy; 805}; 806 807#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 808#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 809#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 810#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 811 812#define ASSERT_SYNCHRONIZED_OP(sc) \ 813 KASSERT(IS_BUSY(sc) && \ 814 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 815 ("%s: operation not synchronized.", __func__)) 816 817#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 818#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 819#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 820#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 821 822#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 823#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 824#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 825#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 826#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 827 828#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 829#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 830#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 831#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 832 833#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 834#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 835#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 836#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 837#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 838 839#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 840#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 841#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 842#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 843#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 844 845#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 846 do { \ 847 if (sc->debug_flags & DF_DUMP_MBOX) { \ 848 log(LOG_NOTICE, \ 849 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 850 "%016llx %016llx %016llx %016llx\n", \ 851 device_get_nameunit(sc->dev), mbox, \ 852 (unsigned long long)t4_read_reg64(sc, data_reg), \ 853 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 854 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 855 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 856 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 857 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 858 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 859 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 860 } \ 861 } while (0) 862 863#define for_each_txq(vi, iter, q) \ 864 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 865 iter < vi->ntxq; ++iter, ++q) 866#define for_each_rxq(vi, iter, q) \ 867 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 868 iter < vi->nrxq; ++iter, ++q) 869#define for_each_ofld_txq(vi, iter, q) \ 870 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 871 iter < vi->nofldtxq; ++iter, ++q) 872#define for_each_ofld_rxq(vi, iter, q) \ 873 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 874 iter < vi->nofldrxq; ++iter, ++q) 875#define for_each_nm_txq(vi, iter, q) \ 876 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 877 iter < vi->nnmtxq; ++iter, ++q) 878#define for_each_nm_rxq(vi, iter, q) \ 879 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 880 iter < vi->nnmrxq; ++iter, ++q) 881#define for_each_vi(_pi, _iter, _vi) \ 882 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 883 ++(_iter), ++(_vi)) 884 885#define IDXINCR(idx, incr, wrap) do { \ 886 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 887} while (0) 888#define IDXDIFF(head, tail, wrap) \ 889 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 890 891/* One for errors, one for firmware events */ 892#define T4_EXTRA_INTR 2 893 894static inline uint32_t 895t4_read_reg(struct adapter *sc, uint32_t reg) 896{ 897 898 return bus_space_read_4(sc->bt, sc->bh, reg); 899} 900 901static inline void 902t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 903{ 904 905 bus_space_write_4(sc->bt, sc->bh, reg, val); 906} 907 908static inline uint64_t 909t4_read_reg64(struct adapter *sc, uint32_t reg) 910{ 911 912 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 913} 914 915static inline void 916t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 917{ 918 919 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 920} 921 922static inline void 923t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 924{ 925 926 *val = pci_read_config(sc->dev, reg, 1); 927} 928 929static inline void 930t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 931{ 932 933 pci_write_config(sc->dev, reg, val, 1); 934} 935 936static inline void 937t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 938{ 939 940 *val = pci_read_config(sc->dev, reg, 2); 941} 942 943static inline void 944t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 945{ 946 947 pci_write_config(sc->dev, reg, val, 2); 948} 949 950static inline void 951t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 952{ 953 954 *val = pci_read_config(sc->dev, reg, 4); 955} 956 957static inline void 958t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 959{ 960 961 pci_write_config(sc->dev, reg, val, 4); 962} 963 964static inline struct port_info * 965adap2pinfo(struct adapter *sc, int idx) 966{ 967 968 return (sc->port[idx]); 969} 970 971static inline void 972t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 973{ 974 975 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN); 976} 977 978static inline bool 979is_10G_port(const struct port_info *pi) 980{ 981 982 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 983} 984 985static inline bool 986is_40G_port(const struct port_info *pi) 987{ 988 989 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 990} 991 992static inline int 993tx_resume_threshold(struct sge_eq *eq) 994{ 995 996 /* not quite the same as qsize / 4, but this will do. */ 997 return (eq->sidx / 4); 998} 999 1000static inline int 1001t4_use_ldst(struct adapter *sc) 1002{ 1003 1004#ifdef notyet 1005 return (sc->flags & FW_OK || !sc->use_bd); 1006#else 1007 return (0); 1008#endif 1009} 1010 1011/* t4_main.c */ 1012int t4_os_find_pci_capability(struct adapter *, int); 1013int t4_os_pci_save_state(struct adapter *); 1014int t4_os_pci_restore_state(struct adapter *); 1015void t4_os_portmod_changed(const struct adapter *, int); 1016void t4_os_link_changed(struct adapter *, int, int, int); 1017void t4_iterate(void (*)(struct adapter *, void *), void *); 1018int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 1019int t4_register_an_handler(struct adapter *, an_handler_t); 1020int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 1021int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1022int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1023void doom_vi(struct adapter *, struct vi_info *); 1024void end_synchronized_op(struct adapter *, int); 1025int update_mac_settings(struct ifnet *, int); 1026int adapter_full_init(struct adapter *); 1027int adapter_full_uninit(struct adapter *); 1028uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1029int vi_full_init(struct vi_info *); 1030int vi_full_uninit(struct vi_info *); 1031void vi_sysctls(struct vi_info *); 1032void vi_tick(void *); 1033 1034#ifdef DEV_NETMAP 1035/* t4_netmap.c */ 1036void cxgbe_nm_attach(struct vi_info *); 1037void cxgbe_nm_detach(struct vi_info *); 1038void t4_nm_intr(void *); 1039#endif 1040 1041/* t4_sge.c */ 1042void t4_sge_modload(void); 1043void t4_sge_modunload(void); 1044uint64_t t4_sge_extfree_refs(void); 1045void t4_init_sge_cpl_handlers(struct adapter *); 1046void t4_tweak_chip_settings(struct adapter *); 1047int t4_read_chip_settings(struct adapter *); 1048int t4_create_dma_tag(struct adapter *); 1049void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1050 struct sysctl_oid_list *); 1051int t4_destroy_dma_tag(struct adapter *); 1052int t4_setup_adapter_queues(struct adapter *); 1053int t4_teardown_adapter_queues(struct adapter *); 1054int t4_setup_vi_queues(struct vi_info *); 1055int t4_teardown_vi_queues(struct vi_info *); 1056void t4_intr_all(void *); 1057void t4_intr(void *); 1058void t4_vi_intr(void *); 1059void t4_intr_err(void *); 1060void t4_intr_evt(void *); 1061void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1062void t4_update_fl_bufsize(struct ifnet *); 1063int parse_pkt(struct mbuf **); 1064void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1065void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1066int tnl_cong(struct port_info *, int); 1067 1068/* t4_tracer.c */ 1069struct t4_tracer; 1070void t4_tracer_modload(void); 1071void t4_tracer_modunload(void); 1072void t4_tracer_port_detach(struct adapter *); 1073int t4_get_tracer(struct adapter *, struct t4_tracer *); 1074int t4_set_tracer(struct adapter *, struct t4_tracer *); 1075int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1076int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1077 1078static inline struct wrqe * 1079alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1080{ 1081 int len = offsetof(struct wrqe, wr) + wr_len; 1082 struct wrqe *wr; 1083 1084 wr = malloc(len, M_CXGBE, M_NOWAIT); 1085 if (__predict_false(wr == NULL)) 1086 return (NULL); 1087 wr->wr_len = wr_len; 1088 wr->wrq = wrq; 1089 return (wr); 1090} 1091 1092static inline void * 1093wrtod(struct wrqe *wr) 1094{ 1095 return (&wr->wr[0]); 1096} 1097 1098static inline void 1099free_wrqe(struct wrqe *wr) 1100{ 1101 free(wr, M_CXGBE); 1102} 1103 1104static inline void 1105t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1106{ 1107 struct sge_wrq *wrq = wr->wrq; 1108 1109 TXQ_LOCK(wrq); 1110 t4_wrq_tx_locked(sc, wrq, wr); 1111 TXQ_UNLOCK(wrq); 1112} 1113 1114#endif 1115