1167514Skmacy/************************************************************************** 2167514Skmacy 3189643SgnnCopyright (c) 2007-2009, Chelsio Inc. 4167514SkmacyAll rights reserved. 5167514Skmacy 6167514SkmacyRedistribution and use in source and binary forms, with or without 7167514Skmacymodification, are permitted provided that the following conditions are met: 8167514Skmacy 9167514Skmacy 1. Redistributions of source code must retain the above copyright notice, 10167514Skmacy this list of conditions and the following disclaimer. 11167514Skmacy 12170076Skmacy 2. Neither the name of the Chelsio Corporation nor the names of its 13167514Skmacy contributors may be used to endorse or promote products derived from 14167514Skmacy this software without specific prior written permission. 15167514Skmacy 16167514SkmacyTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17167514SkmacyAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18167514SkmacyIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19167514SkmacyARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20167514SkmacyLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21167514SkmacyCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22167514SkmacySUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23167514SkmacyINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24167514SkmacyCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25167514SkmacyARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26167514SkmacyPOSSIBILITY OF SUCH DAMAGE. 27167514Skmacy 28167514Skmacy$FreeBSD$ 29167514Skmacy 30167514Skmacy***************************************************************************/ 31167514Skmacy#ifndef __CHELSIO_COMMON_H 32167514Skmacy#define __CHELSIO_COMMON_H 33167514Skmacy 34170076Skmacy#include <cxgb_osdep.h> 35167514Skmacy 36167514Skmacyenum { 37170654Skmacy MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */ 38167514Skmacy EEPROMSIZE = 8192, /* Serial EEPROM size */ 39172096Skmacy SERNUM_LEN = 16, /* Serial # length */ 40185157Sgnn ECNUM_LEN = 16, /* EC # length */ 41167514Skmacy RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 42167514Skmacy TCB_SIZE = 128, /* TCB size */ 43167514Skmacy NMTUS = 16, /* size of MTU table */ 44167514Skmacy NCCTRL_WIN = 32, /* # of congestion control windows */ 45167746Skmacy NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 46170654Skmacy PROTO_SRAM_LINES = 128, /* size of protocol sram */ 47180583Skmacy EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */ 48167514Skmacy}; 49167514Skmacy 50170654Skmacy#define MAX_RX_COALESCING_LEN 12288U 51167514Skmacy 52167514Skmacyenum { 53167514Skmacy PAUSE_RX = 1 << 0, 54167514Skmacy PAUSE_TX = 1 << 1, 55167514Skmacy PAUSE_AUTONEG = 1 << 2 56167514Skmacy}; 57167514Skmacy 58167514Skmacyenum { 59197791Snp SUPPORTED_LINK_IRQ = 1 << 24, 60197791Snp /* skip 25 */ 61197791Snp SUPPORTED_MISC_IRQ = 1 << 26, 62197791Snp SUPPORTED_IRQ = (SUPPORTED_LINK_IRQ | SUPPORTED_MISC_IRQ), 63167514Skmacy}; 64167514Skmacy 65167514Skmacyenum { /* adapter interrupt-maintained statistics */ 66167514Skmacy STAT_ULP_CH0_PBL_OOB, 67167514Skmacy STAT_ULP_CH1_PBL_OOB, 68167514Skmacy STAT_PCI_CORR_ECC, 69167514Skmacy 70167514Skmacy IRQ_NUM_STATS /* keep last */ 71167514Skmacy}; 72167514Skmacy 73167514Skmacyenum { 74170654Skmacy TP_VERSION_MAJOR = 1, 75171471Skmacy TP_VERSION_MINOR = 1, 76171471Skmacy TP_VERSION_MICRO = 0 77170654Skmacy}; 78170654Skmacy 79170654Skmacy#define S_TP_VERSION_MAJOR 16 80170654Skmacy#define M_TP_VERSION_MAJOR 0xFF 81170654Skmacy#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 82170654Skmacy#define G_TP_VERSION_MAJOR(x) \ 83170654Skmacy (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 84170654Skmacy 85170654Skmacy#define S_TP_VERSION_MINOR 8 86170654Skmacy#define M_TP_VERSION_MINOR 0xFF 87170654Skmacy#define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 88170654Skmacy#define G_TP_VERSION_MINOR(x) \ 89170654Skmacy (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 90170654Skmacy 91170654Skmacy#define S_TP_VERSION_MICRO 0 92170654Skmacy#define M_TP_VERSION_MICRO 0xFF 93170654Skmacy#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 94170654Skmacy#define G_TP_VERSION_MICRO(x) \ 95170654Skmacy (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 96170654Skmacy 97170654Skmacyenum { 98189643Sgnn FW_VERSION_MAJOR = 7, 99220009Snp FW_VERSION_MINOR = 11, 100167746Skmacy FW_VERSION_MICRO = 0 101167746Skmacy}; 102167746Skmacy 103167746Skmacyenum { 104189643Sgnn LA_CTRL = 0x80, 105189643Sgnn LA_DATA = 0x84, 106189643Sgnn LA_ENTRIES = 512 107189643Sgnn}; 108189643Sgnn 109189643Sgnnenum { 110189643Sgnn IOQ_ENTRIES = 7 111189643Sgnn}; 112189643Sgnn 113189643Sgnnenum { 114167514Skmacy SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 115167514Skmacy SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 116167514Skmacy SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 117167514Skmacy}; 118167514Skmacy 119167514Skmacyenum sge_context_type { /* SGE egress context types */ 120181614Skmacy SGE_CNTXT_RDMA = 0, 121181614Skmacy SGE_CNTXT_ETH = 2, 122181614Skmacy SGE_CNTXT_OFLD = 4, 123181614Skmacy SGE_CNTXT_CTRL = 5 124167514Skmacy}; 125167514Skmacy 126167514Skmacyenum { 127167514Skmacy AN_PKT_SIZE = 32, /* async notification packet size */ 128167514Skmacy IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 129167514Skmacy}; 130167514Skmacy 131167514Skmacystruct sg_ent { /* SGE scatter/gather entry */ 132180583Skmacy __be32 len[2]; 133180583Skmacy __be64 addr[2]; 134167514Skmacy}; 135167514Skmacy 136167514Skmacy#ifndef SGE_NUM_GENBITS 137167514Skmacy/* Must be 1 or 2 */ 138167514Skmacy# define SGE_NUM_GENBITS 2 139167514Skmacy#endif 140167514Skmacy 141167514Skmacy#define TX_DESC_FLITS 16U 142167514Skmacy#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 143167514Skmacy 144181614Skmacy#define MAX_PHYINTRS 4 145181614Skmacy 146167514Skmacystruct cphy; 147167514Skmacy 148167514Skmacystruct mdio_ops { 149167514Skmacy int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, 150167514Skmacy int reg_addr, unsigned int *val); 151181614Skmacy int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, 152167514Skmacy int reg_addr, unsigned int val); 153167514Skmacy}; 154167514Skmacy 155167514Skmacystruct adapter_info { 156170654Skmacy unsigned char nports0; /* # of ports on channel 0 */ 157170654Skmacy unsigned char nports1; /* # of ports on channel 1 */ 158167514Skmacy unsigned char phy_base_addr; /* MDIO PHY base address */ 159167514Skmacy unsigned int gpio_out; /* GPIO output settings */ 160181614Skmacy unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */ 161167514Skmacy unsigned long caps; /* adapter capabilities */ 162167514Skmacy const struct mdio_ops *mdio_ops; /* MDIO operations */ 163167514Skmacy const char *desc; /* product description */ 164167514Skmacy}; 165167514Skmacy 166167514Skmacystruct mc5_stats { 167167514Skmacy unsigned long parity_err; 168167514Skmacy unsigned long active_rgn_full; 169167514Skmacy unsigned long nfa_srch_err; 170167514Skmacy unsigned long unknown_cmd; 171167514Skmacy unsigned long reqq_parity_err; 172167514Skmacy unsigned long dispq_parity_err; 173167514Skmacy unsigned long del_act_empty; 174167514Skmacy}; 175167514Skmacy 176167514Skmacystruct mc7_stats { 177167514Skmacy unsigned long corr_err; 178167514Skmacy unsigned long uncorr_err; 179167514Skmacy unsigned long parity_err; 180167514Skmacy unsigned long addr_err; 181167514Skmacy}; 182167514Skmacy 183167514Skmacystruct mac_stats { 184167514Skmacy u64 tx_octets; /* total # of octets in good frames */ 185167514Skmacy u64 tx_octets_bad; /* total # of octets in error frames */ 186167514Skmacy u64 tx_frames; /* all good frames */ 187167514Skmacy u64 tx_mcast_frames; /* good multicast frames */ 188167514Skmacy u64 tx_bcast_frames; /* good broadcast frames */ 189167514Skmacy u64 tx_pause; /* # of transmitted pause frames */ 190167514Skmacy u64 tx_deferred; /* frames with deferred transmissions */ 191167514Skmacy u64 tx_late_collisions; /* # of late collisions */ 192167514Skmacy u64 tx_total_collisions; /* # of total collisions */ 193167514Skmacy u64 tx_excess_collisions; /* frame errors from excessive collissions */ 194167514Skmacy u64 tx_underrun; /* # of Tx FIFO underruns */ 195167514Skmacy u64 tx_len_errs; /* # of Tx length errors */ 196167514Skmacy u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 197167514Skmacy u64 tx_excess_deferral; /* # of frames with excessive deferral */ 198167514Skmacy u64 tx_fcs_errs; /* # of frames with bad FCS */ 199167514Skmacy 200167514Skmacy u64 tx_frames_64; /* # of Tx frames in a particular range */ 201167514Skmacy u64 tx_frames_65_127; 202167514Skmacy u64 tx_frames_128_255; 203167514Skmacy u64 tx_frames_256_511; 204167514Skmacy u64 tx_frames_512_1023; 205167514Skmacy u64 tx_frames_1024_1518; 206167514Skmacy u64 tx_frames_1519_max; 207167514Skmacy 208167514Skmacy u64 rx_octets; /* total # of octets in good frames */ 209167514Skmacy u64 rx_octets_bad; /* total # of octets in error frames */ 210167514Skmacy u64 rx_frames; /* all good frames */ 211167514Skmacy u64 rx_mcast_frames; /* good multicast frames */ 212167514Skmacy u64 rx_bcast_frames; /* good broadcast frames */ 213167514Skmacy u64 rx_pause; /* # of received pause frames */ 214167514Skmacy u64 rx_fcs_errs; /* # of received frames with bad FCS */ 215167514Skmacy u64 rx_align_errs; /* alignment errors */ 216167514Skmacy u64 rx_symbol_errs; /* symbol errors */ 217167514Skmacy u64 rx_data_errs; /* data errors */ 218167514Skmacy u64 rx_sequence_errs; /* sequence errors */ 219167514Skmacy u64 rx_runt; /* # of runt frames */ 220167514Skmacy u64 rx_jabber; /* # of jabber frames */ 221167514Skmacy u64 rx_short; /* # of short frames */ 222167514Skmacy u64 rx_too_long; /* # of oversized frames */ 223167514Skmacy u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 224167514Skmacy 225167514Skmacy u64 rx_frames_64; /* # of Rx frames in a particular range */ 226167514Skmacy u64 rx_frames_65_127; 227167514Skmacy u64 rx_frames_128_255; 228167514Skmacy u64 rx_frames_256_511; 229167514Skmacy u64 rx_frames_512_1023; 230167514Skmacy u64 rx_frames_1024_1518; 231167514Skmacy u64 rx_frames_1519_max; 232167514Skmacy 233167514Skmacy u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 234167514Skmacy 235167514Skmacy unsigned long tx_fifo_parity_err; 236167514Skmacy unsigned long rx_fifo_parity_err; 237167514Skmacy unsigned long tx_fifo_urun; 238167514Skmacy unsigned long rx_fifo_ovfl; 239167514Skmacy unsigned long serdes_signal_loss; 240167514Skmacy unsigned long xaui_pcs_ctc_err; 241167514Skmacy unsigned long xaui_pcs_align_change; 242167746Skmacy 243167746Skmacy unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 244167746Skmacy unsigned long num_resets; /* # times reset due to stuck TX */ 245189643Sgnn 246189643Sgnn unsigned long link_faults; /* # detected link faults */ 247167514Skmacy}; 248167514Skmacy 249167514Skmacystruct tp_mib_stats { 250167514Skmacy u32 ipInReceive_hi; 251167514Skmacy u32 ipInReceive_lo; 252167514Skmacy u32 ipInHdrErrors_hi; 253167514Skmacy u32 ipInHdrErrors_lo; 254167514Skmacy u32 ipInAddrErrors_hi; 255167514Skmacy u32 ipInAddrErrors_lo; 256167514Skmacy u32 ipInUnknownProtos_hi; 257167514Skmacy u32 ipInUnknownProtos_lo; 258167514Skmacy u32 ipInDiscards_hi; 259167514Skmacy u32 ipInDiscards_lo; 260167514Skmacy u32 ipInDelivers_hi; 261167514Skmacy u32 ipInDelivers_lo; 262167514Skmacy u32 ipOutRequests_hi; 263167514Skmacy u32 ipOutRequests_lo; 264167514Skmacy u32 ipOutDiscards_hi; 265167514Skmacy u32 ipOutDiscards_lo; 266167514Skmacy u32 ipOutNoRoutes_hi; 267167514Skmacy u32 ipOutNoRoutes_lo; 268167514Skmacy u32 ipReasmTimeout; 269167514Skmacy u32 ipReasmReqds; 270167514Skmacy u32 ipReasmOKs; 271167514Skmacy u32 ipReasmFails; 272167514Skmacy 273167514Skmacy u32 reserved[8]; 274167514Skmacy 275167514Skmacy u32 tcpActiveOpens; 276167514Skmacy u32 tcpPassiveOpens; 277167514Skmacy u32 tcpAttemptFails; 278167514Skmacy u32 tcpEstabResets; 279167514Skmacy u32 tcpOutRsts; 280167514Skmacy u32 tcpCurrEstab; 281167514Skmacy u32 tcpInSegs_hi; 282167514Skmacy u32 tcpInSegs_lo; 283167514Skmacy u32 tcpOutSegs_hi; 284167514Skmacy u32 tcpOutSegs_lo; 285167514Skmacy u32 tcpRetransSeg_hi; 286167514Skmacy u32 tcpRetransSeg_lo; 287167514Skmacy u32 tcpInErrs_hi; 288167514Skmacy u32 tcpInErrs_lo; 289167514Skmacy u32 tcpRtoMin; 290167514Skmacy u32 tcpRtoMax; 291167514Skmacy}; 292167514Skmacy 293167514Skmacystruct tp_params { 294167514Skmacy unsigned int nchan; /* # of channels */ 295167514Skmacy unsigned int pmrx_size; /* total PMRX capacity */ 296167514Skmacy unsigned int pmtx_size; /* total PMTX capacity */ 297167514Skmacy unsigned int cm_size; /* total CM capacity */ 298167514Skmacy unsigned int chan_rx_size; /* per channel Rx size */ 299167514Skmacy unsigned int chan_tx_size; /* per channel Tx size */ 300167514Skmacy unsigned int rx_pg_size; /* Rx page size */ 301167514Skmacy unsigned int tx_pg_size; /* Tx page size */ 302167514Skmacy unsigned int rx_num_pgs; /* # of Rx pages */ 303167514Skmacy unsigned int tx_num_pgs; /* # of Tx pages */ 304167514Skmacy unsigned int ntimer_qs; /* # of timer queues */ 305170654Skmacy unsigned int tre; /* log2 of core clocks per TP tick */ 306167746Skmacy unsigned int dack_re; /* DACK timer resolution */ 307167514Skmacy}; 308167514Skmacy 309167514Skmacystruct qset_params { /* SGE queue set parameters */ 310167514Skmacy unsigned int polling; /* polling/interrupt service for rspq */ 311170654Skmacy unsigned int lro; /* large receive offload */ 312180583Skmacy unsigned int coalesce_usecs; /* irq coalescing timer */ 313167514Skmacy unsigned int rspq_size; /* # of entries in response queue */ 314167514Skmacy unsigned int fl_size; /* # of entries in regular free list */ 315167514Skmacy unsigned int jumbo_size; /* # of entries in jumbo free list */ 316205950Snp unsigned int jumbo_buf_size; /* buffer size of jumbo entry */ 317167514Skmacy unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 318167514Skmacy unsigned int cong_thres; /* FL congestion threshold */ 319167746Skmacy unsigned int vector; /* Interrupt (line or vector) number */ 320167514Skmacy}; 321167514Skmacy 322167514Skmacystruct sge_params { 323167514Skmacy unsigned int max_pkt_size; /* max offload pkt size */ 324167514Skmacy struct qset_params qset[SGE_QSETS]; 325167514Skmacy}; 326167514Skmacy 327167514Skmacystruct mc5_params { 328167514Skmacy unsigned int mode; /* selects MC5 width */ 329167514Skmacy unsigned int nservers; /* size of server region */ 330167514Skmacy unsigned int nfilters; /* size of filter region */ 331167514Skmacy unsigned int nroutes; /* size of routing region */ 332167514Skmacy}; 333167514Skmacy 334167514Skmacy/* Default MC5 region sizes */ 335167514Skmacyenum { 336167514Skmacy DEFAULT_NSERVERS = 512, 337167514Skmacy DEFAULT_NFILTERS = 128 338167514Skmacy}; 339167514Skmacy 340167514Skmacy/* MC5 modes, these must be non-0 */ 341167514Skmacyenum { 342167514Skmacy MC5_MODE_144_BIT = 1, 343167514Skmacy MC5_MODE_72_BIT = 2 344167514Skmacy}; 345167514Skmacy 346169978Skmacy/* MC5 min active region size */ 347169978Skmacyenum { MC5_MIN_TIDS = 16 }; 348169978Skmacy 349167514Skmacystruct vpd_params { 350167514Skmacy unsigned int cclk; 351167514Skmacy unsigned int mclk; 352167514Skmacy unsigned int uclk; 353167514Skmacy unsigned int mdc; 354167514Skmacy unsigned int mem_timing; 355172096Skmacy u8 sn[SERNUM_LEN + 1]; 356185157Sgnn u8 ec[ECNUM_LEN + 1]; 357167514Skmacy u8 eth_base[6]; 358167514Skmacy u8 port_type[MAX_NPORTS]; 359167514Skmacy unsigned short xauicfg[2]; 360167514Skmacy}; 361167514Skmacy 362189643Sgnnstruct generic_vpd { 363189643Sgnn u32 offset; 364189643Sgnn u32 len; 365189643Sgnn u8 *data; 366189643Sgnn}; 367189643Sgnn 368189643Sgnnenum { MAX_VPD_BYTES = 32000 }; 369189643Sgnn 370167514Skmacystruct pci_params { 371167514Skmacy unsigned int vpd_cap_addr; 372167514Skmacy unsigned int pcie_cap_addr; 373167514Skmacy unsigned short speed; 374167514Skmacy unsigned char width; 375167514Skmacy unsigned char variant; 376167514Skmacy}; 377167514Skmacy 378167514Skmacyenum { 379167514Skmacy PCI_VARIANT_PCI, 380167514Skmacy PCI_VARIANT_PCIX_MODE1_PARITY, 381167514Skmacy PCI_VARIANT_PCIX_MODE1_ECC, 382167514Skmacy PCI_VARIANT_PCIX_266_MODE2, 383167514Skmacy PCI_VARIANT_PCIE 384167514Skmacy}; 385167514Skmacy 386167514Skmacystruct adapter_params { 387167514Skmacy struct sge_params sge; 388167514Skmacy struct mc5_params mc5; 389167514Skmacy struct tp_params tp; 390167514Skmacy struct vpd_params vpd; 391167514Skmacy struct pci_params pci; 392167514Skmacy 393167514Skmacy const struct adapter_info *info; 394167514Skmacy 395167514Skmacy unsigned short mtus[NMTUS]; 396167514Skmacy unsigned short a_wnd[NCCTRL_WIN]; 397167514Skmacy unsigned short b_wnd[NCCTRL_WIN]; 398167514Skmacy unsigned int nports; /* # of ethernet ports */ 399170654Skmacy unsigned int chan_map; /* bitmap of in-use Tx channels */ 400167514Skmacy unsigned int stats_update_period; /* MAC stats accumulation period */ 401167514Skmacy unsigned int linkpoll_period; /* link poll period in 0.1s */ 402167514Skmacy unsigned int rev; /* chip revision */ 403169978Skmacy unsigned int offload; 404167514Skmacy}; 405167514Skmacy 406167746Skmacyenum { /* chip revisions */ 407167746Skmacy T3_REV_A = 0, 408167746Skmacy T3_REV_B = 2, 409167746Skmacy T3_REV_B2 = 3, 410171471Skmacy T3_REV_C = 4, 411167746Skmacy}; 412167746Skmacy 413167514Skmacystruct trace_params { 414167514Skmacy u32 sip; 415181614Skmacy u32 sip_mask; 416167514Skmacy u32 dip; 417181614Skmacy u32 dip_mask; 418167514Skmacy u16 sport; 419167514Skmacy u16 sport_mask; 420167514Skmacy u16 dport; 421167514Skmacy u16 dport_mask; 422167514Skmacy u32 vlan:12; 423167514Skmacy u32 vlan_mask:12; 424167514Skmacy u32 intf:4; 425167514Skmacy u32 intf_mask:4; 426167514Skmacy u8 proto; 427167514Skmacy u8 proto_mask; 428167514Skmacy}; 429167514Skmacy 430167514Skmacystruct link_config { 431167514Skmacy unsigned int supported; /* link capabilities */ 432167514Skmacy unsigned int advertising; /* advertised capabilities */ 433181614Skmacy unsigned short requested_speed; /* speed user has requested */ 434167514Skmacy unsigned short speed; /* actual link speed */ 435181614Skmacy unsigned char requested_duplex; /* duplex user has requested */ 436167514Skmacy unsigned char duplex; /* actual link duplex */ 437167514Skmacy unsigned char requested_fc; /* flow control user has requested */ 438167514Skmacy unsigned char fc; /* actual link flow control */ 439167514Skmacy unsigned char autoneg; /* autonegotiating? */ 440181614Skmacy unsigned int link_ok; /* link up? */ 441167514Skmacy}; 442167514Skmacy 443167514Skmacy#define SPEED_INVALID 0xffff 444167514Skmacy#define DUPLEX_INVALID 0xff 445167514Skmacy 446167514Skmacystruct mc5 { 447167514Skmacy adapter_t *adapter; 448167514Skmacy unsigned int tcam_size; 449167514Skmacy unsigned char part_type; 450167514Skmacy unsigned char parity_enabled; 451167514Skmacy unsigned char mode; 452167514Skmacy struct mc5_stats stats; 453167514Skmacy}; 454167514Skmacy 455167514Skmacystatic inline unsigned int t3_mc5_size(const struct mc5 *p) 456167514Skmacy{ 457167514Skmacy return p->tcam_size; 458167514Skmacy} 459167514Skmacy 460167514Skmacystruct mc7 { 461167514Skmacy adapter_t *adapter; /* backpointer to adapter */ 462167514Skmacy unsigned int size; /* memory size in bytes */ 463167514Skmacy unsigned int width; /* MC7 interface width */ 464167514Skmacy unsigned int offset; /* register address offset for MC7 instance */ 465167514Skmacy const char *name; /* name of MC7 instance */ 466167514Skmacy struct mc7_stats stats; /* MC7 statistics */ 467167514Skmacy}; 468167514Skmacy 469167514Skmacystatic inline unsigned int t3_mc7_size(const struct mc7 *p) 470167514Skmacy{ 471167514Skmacy return p->size; 472167514Skmacy} 473167514Skmacy 474167514Skmacystruct cmac { 475167514Skmacy adapter_t *adapter; 476167514Skmacy unsigned int offset; 477170654Skmacy unsigned char nucast; /* # of address filters for unicast MACs */ 478170654Skmacy unsigned char multiport; /* multiple ports connected to this MAC */ 479170654Skmacy unsigned char ext_port; /* external MAC port */ 480170654Skmacy unsigned char promisc_map; /* which external ports are promiscuous */ 481169978Skmacy unsigned int tx_tcnt; 482169978Skmacy unsigned int tx_xcnt; 483169978Skmacy u64 tx_mcnt; 484169978Skmacy unsigned int rx_xcnt; 485171471Skmacy unsigned int rx_ocnt; 486169978Skmacy u64 rx_mcnt; 487167746Skmacy unsigned int toggle_cnt; 488167746Skmacy unsigned int txen; 489197791Snp unsigned int was_reset; 490172096Skmacy u64 rx_pause; 491167514Skmacy struct mac_stats stats; 492167514Skmacy}; 493167514Skmacy 494167514Skmacyenum { 495167514Skmacy MAC_DIRECTION_RX = 1, 496167514Skmacy MAC_DIRECTION_TX = 2, 497167514Skmacy MAC_RXFIFO_SIZE = 32768 498167514Skmacy}; 499167514Skmacy 500180583Skmacy/* IEEE 802.3 specified MDIO devices */ 501167514Skmacyenum { 502167514Skmacy MDIO_DEV_PMA_PMD = 1, 503167514Skmacy MDIO_DEV_WIS = 2, 504167514Skmacy MDIO_DEV_PCS = 3, 505180583Skmacy MDIO_DEV_XGXS = 4, 506180583Skmacy MDIO_DEV_ANEG = 7, 507180583Skmacy MDIO_DEV_VEND1 = 30, 508180583Skmacy MDIO_DEV_VEND2 = 31 509167514Skmacy}; 510167514Skmacy 511180583Skmacy/* LASI control and status registers */ 512180583Skmacyenum { 513180583Skmacy RX_ALARM_CTRL = 0x9000, 514180583Skmacy TX_ALARM_CTRL = 0x9001, 515180583Skmacy LASI_CTRL = 0x9002, 516180583Skmacy RX_ALARM_STAT = 0x9003, 517180583Skmacy TX_ALARM_STAT = 0x9004, 518180583Skmacy LASI_STAT = 0x9005 519180583Skmacy}; 520180583Skmacy 521167514Skmacy/* PHY loopback direction */ 522167514Skmacyenum { 523167514Skmacy PHY_LOOPBACK_TX = 1, 524167514Skmacy PHY_LOOPBACK_RX = 2 525167514Skmacy}; 526167514Skmacy 527167514Skmacy/* PHY interrupt types */ 528167514Skmacyenum { 529167514Skmacy cphy_cause_link_change = 1, 530181614Skmacy cphy_cause_fifo_error = 2, 531181614Skmacy cphy_cause_module_change = 4, 532197791Snp cphy_cause_alarm = 8, 533167514Skmacy}; 534167514Skmacy 535181614Skmacy/* PHY module types */ 536181614Skmacyenum { 537181614Skmacy phy_modtype_none, 538181614Skmacy phy_modtype_sr, 539181614Skmacy phy_modtype_lr, 540181614Skmacy phy_modtype_lrm, 541181614Skmacy phy_modtype_twinax, 542181614Skmacy phy_modtype_twinax_long, 543181614Skmacy phy_modtype_unknown 544181614Skmacy}; 545181614Skmacy 546277343Snpenum { 547277343Snp PHY_LINK_DOWN = 0, 548277343Snp PHY_LINK_UP, 549277343Snp PHY_LINK_PARTIAL 550277343Snp}; 551277343Snp 552167514Skmacy/* PHY operations */ 553167514Skmacystruct cphy_ops { 554167514Skmacy int (*reset)(struct cphy *phy, int wait); 555167514Skmacy 556167514Skmacy int (*intr_enable)(struct cphy *phy); 557167514Skmacy int (*intr_disable)(struct cphy *phy); 558167514Skmacy int (*intr_clear)(struct cphy *phy); 559167514Skmacy int (*intr_handler)(struct cphy *phy); 560167514Skmacy 561167514Skmacy int (*autoneg_enable)(struct cphy *phy); 562167514Skmacy int (*autoneg_restart)(struct cphy *phy); 563167514Skmacy 564167514Skmacy int (*advertise)(struct cphy *phy, unsigned int advertise_map); 565167514Skmacy int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 566167514Skmacy int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 567277343Snp int (*get_link_status)(struct cphy *phy, int *link_state, int *speed, 568167514Skmacy int *duplex, int *fc); 569167514Skmacy int (*power_down)(struct cphy *phy, int enable); 570167514Skmacy}; 571167514Skmacy 572167514Skmacy/* A PHY instance */ 573167514Skmacystruct cphy { 574181614Skmacy u8 addr; /* PHY address */ 575181614Skmacy u8 modtype; /* PHY module type */ 576277343Snp u8 rst; 577197791Snp unsigned int priv; /* scratch pad */ 578176472Skmacy unsigned int caps; /* PHY capabilities */ 579167514Skmacy adapter_t *adapter; /* associated adapter */ 580197791Snp pinfo_t *pinfo; /* associated port */ 581176472Skmacy const char *desc; /* PHY description */ 582167514Skmacy unsigned long fifo_errors; /* FIFO over/under-flows */ 583167514Skmacy const struct cphy_ops *ops; /* PHY operations */ 584167514Skmacy int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 585167514Skmacy int reg_addr, unsigned int *val); 586167514Skmacy int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, 587167514Skmacy int reg_addr, unsigned int val); 588167514Skmacy}; 589167514Skmacy 590167514Skmacy/* Convenience MDIO read/write wrappers */ 591167514Skmacystatic inline int mdio_read(struct cphy *phy, int mmd, int reg, 592167514Skmacy unsigned int *valp) 593167514Skmacy{ 594181614Skmacy return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); 595167514Skmacy} 596167514Skmacy 597167514Skmacystatic inline int mdio_write(struct cphy *phy, int mmd, int reg, 598167514Skmacy unsigned int val) 599167514Skmacy{ 600181614Skmacy return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); 601167514Skmacy} 602167514Skmacy 603167514Skmacy/* Convenience initializer */ 604197791Snpstatic inline void cphy_init(struct cphy *phy, adapter_t *adapter, pinfo_t *pinfo, 605167514Skmacy int phy_addr, struct cphy_ops *phy_ops, 606180583Skmacy const struct mdio_ops *mdio_ops, unsigned int caps, 607180583Skmacy const char *desc) 608167514Skmacy{ 609181614Skmacy phy->addr = (u8)phy_addr; 610181614Skmacy phy->caps = caps; 611167514Skmacy phy->adapter = adapter; 612197791Snp phy->pinfo = pinfo; 613176472Skmacy phy->desc = desc; 614167514Skmacy phy->ops = phy_ops; 615167514Skmacy if (mdio_ops) { 616167514Skmacy phy->mdio_read = mdio_ops->read; 617167514Skmacy phy->mdio_write = mdio_ops->write; 618167514Skmacy } 619167514Skmacy} 620167514Skmacy 621167514Skmacy/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 622167514Skmacy#define MAC_STATS_ACCUM_SECS 180 623167514Skmacy 624171471Skmacy/* The external MAC needs accumulation every 30 seconds */ 625171471Skmacy#define VSC_STATS_ACCUM_SECS 30 626171471Skmacy 627167514Skmacy#define XGM_REG(reg_addr, idx) \ 628167514Skmacy ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 629167514Skmacy 630167514Skmacystruct addr_val_pair { 631167514Skmacy unsigned int reg_addr; 632167514Skmacy unsigned int val; 633167514Skmacy}; 634167514Skmacy 635170076Skmacy#include <cxgb_adapter.h> 636167514Skmacy 637167514Skmacy#ifndef PCI_VENDOR_ID_CHELSIO 638167514Skmacy# define PCI_VENDOR_ID_CHELSIO 0x1425 639167514Skmacy#endif 640167514Skmacy 641167514Skmacy#define for_each_port(adapter, iter) \ 642167514Skmacy for (iter = 0; iter < (adapter)->params.nports; ++iter) 643167514Skmacy 644167514Skmacy#define adapter_info(adap) ((adap)->params.info) 645167514Skmacy 646167514Skmacystatic inline int uses_xaui(const adapter_t *adap) 647167514Skmacy{ 648167514Skmacy return adapter_info(adap)->caps & SUPPORTED_AUI; 649167514Skmacy} 650167514Skmacy 651167514Skmacystatic inline int is_10G(const adapter_t *adap) 652167514Skmacy{ 653167514Skmacy return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 654167514Skmacy} 655167514Skmacy 656167514Skmacystatic inline int is_offload(const adapter_t *adap) 657167514Skmacy{ 658169978Skmacy return adap->params.offload; 659167514Skmacy} 660167514Skmacy 661167514Skmacystatic inline unsigned int core_ticks_per_usec(const adapter_t *adap) 662167514Skmacy{ 663167514Skmacy return adap->params.vpd.cclk / 1000; 664167514Skmacy} 665167514Skmacy 666167746Skmacystatic inline unsigned int dack_ticks_to_usec(const adapter_t *adap, 667167746Skmacy unsigned int ticks) 668167746Skmacy{ 669167746Skmacy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 670167746Skmacy} 671167746Skmacy 672167514Skmacystatic inline unsigned int is_pcie(const adapter_t *adap) 673167514Skmacy{ 674167514Skmacy return adap->params.pci.variant == PCI_VARIANT_PCIE; 675167514Skmacy} 676167514Skmacy 677167514Skmacyvoid t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val); 678167514Skmacyvoid t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, 679167514Skmacy unsigned int offset); 680167514Skmacyint t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, 681167514Skmacy int attempts, int delay, u32 *valp); 682167514Skmacy 683167514Skmacystatic inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, 684167514Skmacy int polarity, int attempts, int delay) 685167514Skmacy{ 686167514Skmacy return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 687167514Skmacy delay, NULL); 688167514Skmacy} 689167514Skmacy 690167514Skmacyint t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 691167514Skmacy unsigned int set); 692167514Skmacyint t3_phy_reset(struct cphy *phy, int mmd, int wait); 693167514Skmacyint t3_phy_advertise(struct cphy *phy, unsigned int advert); 694180583Skmacyint t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); 695167514Skmacyint t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 696180583Skmacyint t3_phy_lasi_intr_enable(struct cphy *phy); 697180583Skmacyint t3_phy_lasi_intr_disable(struct cphy *phy); 698180583Skmacyint t3_phy_lasi_intr_clear(struct cphy *phy); 699180583Skmacyint t3_phy_lasi_intr_handler(struct cphy *phy); 700167514Skmacy 701167514Skmacyvoid t3_intr_enable(adapter_t *adapter); 702167514Skmacyvoid t3_intr_disable(adapter_t *adapter); 703167514Skmacyvoid t3_intr_clear(adapter_t *adapter); 704189643Sgnnvoid t3_xgm_intr_enable(adapter_t *adapter, int idx); 705189643Sgnnvoid t3_xgm_intr_disable(adapter_t *adapter, int idx); 706167514Skmacyvoid t3_port_intr_enable(adapter_t *adapter, int idx); 707167514Skmacyvoid t3_port_intr_disable(adapter_t *adapter, int idx); 708167514Skmacyvoid t3_port_intr_clear(adapter_t *adapter, int idx); 709167514Skmacyint t3_slow_intr_handler(adapter_t *adapter); 710167514Skmacy 711167514Skmacyvoid t3_link_changed(adapter_t *adapter, int port_id); 712167514Skmacyint t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 713167514Skmacyconst struct adapter_info *t3_get_adapter_info(unsigned int board_id); 714167514Skmacyint t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); 715167514Skmacyint t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data); 716167514Skmacyint t3_seeprom_wp(adapter_t *adapter, int enable); 717189643Sgnnint t3_get_vpd_len(adapter_t *adapter, struct generic_vpd *vpd); 718189643Sgnnint t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd); 719167514Skmacyint t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, 720167514Skmacy u32 *data, int byte_oriented); 721171471Skmacyint t3_get_tp_version(adapter_t *adapter, u32 *vers); 722189643Sgnnint t3_check_tpsram_version(adapter_t *adapter); 723171471Skmacyint t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size); 724180583Skmacyint t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size); 725167514Skmacyint t3_get_fw_version(adapter_t *adapter, u32 *vers); 726189643Sgnnint t3_check_fw_version(adapter_t *adapter); 727180583Skmacyint t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size); 728167514Skmacyint t3_init_hw(adapter_t *adapter, u32 fw_params); 729167514Skmacyvoid mac_prep(struct cmac *mac, adapter_t *adapter, int index); 730167514Skmacyvoid early_hw_init(adapter_t *adapter, const struct adapter_info *ai); 731189643Sgnnint t3_reset_adapter(adapter_t *adapter); 732167514Skmacyint t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset); 733181614Skmacyint t3_reinit_adapter(adapter_t *adap); 734167514Skmacyvoid t3_led_ready(adapter_t *adapter); 735167514Skmacyvoid t3_fatal_err(adapter_t *adapter); 736167514Skmacyvoid t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on); 737180583Skmacyvoid t3_enable_filters(adapter_t *adap); 738189643Sgnnvoid t3_disable_filters(adapter_t *adap); 739177340Skmacyvoid t3_tp_set_offload_mode(adapter_t *adap, int enable); 740167514Skmacyvoid t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, 741167514Skmacy const u16 *rspq); 742167514Skmacyint t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map); 743171471Skmacyint t3_set_proto_sram(adapter_t *adap, const u8 *data); 744167514Skmacyint t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask); 745167514Skmacyvoid t3_port_failover(adapter_t *adapter, int port); 746167514Skmacyvoid t3_failover_done(adapter_t *adapter, int port); 747167514Skmacyvoid t3_failover_clear(adapter_t *adapter); 748167514Skmacyint t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, 749167514Skmacy unsigned int *valp); 750167514Skmacyint t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 751167514Skmacy u64 *buf); 752167514Skmacy 753197791Snpint t3_mac_init(struct cmac *mac); 754167514Skmacyvoid t3b_pcs_reset(struct cmac *mac); 755211346Snpvoid t3c_pcs_force_los(struct cmac *mac); 756189643Sgnnvoid t3_mac_disable_exact_filters(struct cmac *mac); 757189643Sgnnvoid t3_mac_enable_exact_filters(struct cmac *mac); 758167514Skmacyint t3_mac_enable(struct cmac *mac, int which); 759167514Skmacyint t3_mac_disable(struct cmac *mac, int which); 760167514Skmacyint t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 761167514Skmacyint t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 762167514Skmacyint t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 763170654Skmacyint t3_mac_set_num_ucast(struct cmac *mac, unsigned char n); 764167514Skmacyconst struct mac_stats *t3_mac_update_stats(struct cmac *mac); 765167514Skmacyint t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, 766167514Skmacy int fc); 767167746Skmacyint t3b2_mac_watchdog_task(struct cmac *mac); 768167514Skmacy 769167514Skmacyvoid t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode); 770167514Skmacyint t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 771167514Skmacy unsigned int nroutes); 772167514Skmacyvoid t3_mc5_intr_handler(struct mc5 *mc5); 773167514Skmacyint t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 774167514Skmacy u32 *buf); 775167514Skmacy 776167514Skmacyint t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh); 777167514Skmacyvoid t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size); 778167514Skmacyvoid t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps); 779167514Skmacyvoid t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], 780181614Skmacy unsigned short alpha[NCCTRL_WIN], 781167514Skmacy unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 782167514Skmacyvoid t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]); 783167514Skmacyvoid t3_get_cong_cntl_tab(adapter_t *adap, 784167514Skmacy unsigned short incr[NMTUS][NCCTRL_WIN]); 785167514Skmacyvoid t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, 786167514Skmacy int filter_index, int invert, int enable); 787189643Sgnnvoid t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp, 788189643Sgnn int filter_index, int *inverted, int *enabled); 789167514Skmacyint t3_config_sched(adapter_t *adap, unsigned int kbps, int sched); 790167746Skmacyint t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg); 791167746Skmacyvoid t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, 792167746Skmacy unsigned int *ipg); 793167746Skmacyvoid t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]); 794167746Skmacyvoid t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, 795167746Skmacy unsigned int start, unsigned int n); 796167514Skmacy 797189643Sgnnint t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index, 798189643Sgnn u32 *size, void *data); 799189643Sgnnint t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data); 800189643Sgnn 801167514Skmacyvoid t3_sge_prep(adapter_t *adap, struct sge_params *p); 802167514Skmacyvoid t3_sge_init(adapter_t *adap, struct sge_params *p); 803167514Skmacyint t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, 804167514Skmacy enum sge_context_type type, int respq, u64 base_addr, 805167514Skmacy unsigned int size, unsigned int token, int gen, 806167514Skmacy unsigned int cidx); 807167514Skmacyint t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, 808167514Skmacy u64 base_addr, unsigned int size, unsigned int esize, 809167514Skmacy unsigned int cong_thres, int gen, unsigned int cidx); 810167514Skmacyint t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, 811167514Skmacy u64 base_addr, unsigned int size, 812167514Skmacy unsigned int fl_thres, int gen, unsigned int cidx); 813167514Skmacyint t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, 814167514Skmacy unsigned int size, int rspq, int ovfl_mode, 815167514Skmacy unsigned int credits, unsigned int credit_thres); 816167514Skmacyint t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable); 817167514Skmacyint t3_sge_disable_fl(adapter_t *adapter, unsigned int id); 818167514Skmacyint t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id); 819167514Skmacyint t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id); 820167514Skmacyint t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]); 821167514Skmacyint t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]); 822167514Skmacyint t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]); 823167514Skmacyint t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]); 824167514Skmacyint t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, 825167514Skmacy unsigned int credits); 826167514Skmacy 827170654Skmacyint t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n); 828170654Skmacyint t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n); 829170654Skmacyint t3_vsc7323_init(adapter_t *adap, int nports); 830170654Skmacyint t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port); 831171471Skmacyint t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port); 832170654Skmacyint t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port); 833170654Skmacyint t3_vsc7323_enable(adapter_t *adap, int port, int which); 834170654Skmacyint t3_vsc7323_disable(adapter_t *adap, int port, int which); 835170654Skmacyconst struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac); 836170654Skmacy 837197791Snpint t3_i2c_read8(adapter_t *adapter, int chained, u8 *valp); 838197791Snpint t3_i2c_write8(adapter_t *adapter, int chained, u8 val); 839197791Snp 840189643Sgnnint t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, 841189643Sgnn unsigned int *valp); 842189643Sgnnint t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, 843189643Sgnn unsigned int val); 844189643Sgnn 845197791Snpint t3_mv88e1xxx_phy_prep(pinfo_t *pinfo, int phy_addr, 846180583Skmacy const struct mdio_ops *mdio_ops); 847197791Snpint t3_vsc8211_phy_prep(pinfo_t *pinfo, int phy_addr, 848180583Skmacy const struct mdio_ops *mdio_ops); 849197791Snpint t3_vsc8211_fifo_depth(adapter_t *adap, unsigned int mtu, int port); 850197791Snpint t3_ael1002_phy_prep(pinfo_t *pinfo, int phy_addr, 851180583Skmacy const struct mdio_ops *mdio_ops); 852197791Snpint t3_ael1006_phy_prep(pinfo_t *pinfo, int phy_addr, 853180583Skmacy const struct mdio_ops *mdio_ops); 854197791Snpint t3_ael2005_phy_prep(pinfo_t *pinfo, int phy_addr, 855180583Skmacy const struct mdio_ops *mdio_ops); 856197791Snpint t3_ael2020_phy_prep(pinfo_t *pinfo, int phy_addr, 857197791Snp const struct mdio_ops *mdio_ops); 858197791Snpint t3_qt2045_phy_prep(pinfo_t *pinfo, int phy_addr, 859180583Skmacy const struct mdio_ops *mdio_ops); 860197791Snpint t3_tn1010_phy_prep(pinfo_t *pinfo, int phy_addr, 861180583Skmacy const struct mdio_ops *mdio_ops); 862197791Snpint t3_xaui_direct_phy_prep(pinfo_t *pinfo, int phy_addr, 863180583Skmacy const struct mdio_ops *mdio_ops); 864197791Snpint t3_aq100x_phy_prep(pinfo_t *pinfo, int phy_addr, 865197791Snp const struct mdio_ops *mdio_ops); 866167514Skmacy#endif /* __CHELSIO_COMMON_H */ 867