1118611Snjl/*-
2118611Snjl * Copyright (c) 1997,1998 Maxim Bolotin and Oleg Sharoiko.
3118611Snjl * All rights reserved.
4118611Snjl *
5118611Snjl * Redistribution and use in source and binary forms, with or without
6118611Snjl * modification, are permitted provided that the following conditions
7217365Sjkim * are met:
8245582Sjkim * 1. Redistributions of source code must retain the above copyright
9118611Snjl *    notice unmodified, this list of conditions, and the following
10118611Snjl *    disclaimer.
11217365Sjkim * 2. Redistributions in binary form must reproduce the above copyright
12217365Sjkim *    notice, this list of conditions and the following disclaimer in the
13217365Sjkim *    documentation and/or other materials provided with the distribution.
14217365Sjkim *
15217365Sjkim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16217365Sjkim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17217365Sjkim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18217365Sjkim * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19217365Sjkim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20217365Sjkim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21217365Sjkim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22217365Sjkim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23217365Sjkim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24217365Sjkim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25118611Snjl * SUCH DAMAGE.
26217365Sjkim *
27217365Sjkim */
28217365Sjkim
29118611Snjl#include <sys/cdefs.h>
30217365Sjkim__FBSDID("$FreeBSD$");
31217365Sjkim
32217365Sjkim/*
33217365Sjkim *
34217365Sjkim * Device driver for Crystal Semiconductor CS8920 based ethernet
35217365Sjkim *   adapters. By Maxim Bolotin and Oleg Sharoiko, 27-April-1997
36217365Sjkim */
37217365Sjkim
38217365Sjkim/*
39217365Sjkim#define	 CS_DEBUG
40217365Sjkim */
41217365Sjkim
42217365Sjkim#include <sys/param.h>
43118611Snjl#include <sys/systm.h>
44151937Sjkim#include <sys/malloc.h>
45118611Snjl#include <sys/mbuf.h>
46193529Sjkim#include <sys/socket.h>
47193529Sjkim#include <sys/sockio.h>
48193529Sjkim#include <sys/kernel.h>
49118611Snjl#include <sys/sysctl.h>
50249112Sjkim#include <sys/syslog.h>
51118611Snjl
52249112Sjkim#include <sys/module.h>
53118611Snjl#include <sys/bus.h>
54249112Sjkim#include <machine/bus.h>
55151937Sjkim#include <sys/rman.h>
56118611Snjl#include <machine/resource.h>
57151937Sjkim
58249112Sjkim#include <net/if.h>
59249112Sjkim#include <net/if_arp.h>
60151937Sjkim#include <net/if_dl.h>
61151937Sjkim#include <net/if_media.h>
62151937Sjkim#include <net/if_types.h>
63151937Sjkim#include <net/ethernet.h>
64151937Sjkim#include <net/bpf.h>
65151937Sjkim
66151937Sjkim#include <dev/cs/if_csvar.h>
67249112Sjkim#include <dev/cs/if_csreg.h>
68249112Sjkim
69249112Sjkim#ifdef  CS_USE_64K_DMA
70249112Sjkim#define CS_DMA_BUFFER_SIZE 65536
71249112Sjkim#else
72151937Sjkim#define CS_DMA_BUFFER_SIZE 16384
73151937Sjkim#endif
74249112Sjkim
75249112Sjkimstatic void	cs_init(void *);
76151937Sjkimstatic void	cs_init_locked(struct cs_softc *);
77151937Sjkimstatic int	cs_ioctl(struct ifnet *, u_long, caddr_t);
78151937Sjkimstatic void	cs_start(struct ifnet *);
79151937Sjkimstatic void	cs_start_locked(struct ifnet *);
80151937Sjkimstatic void	cs_stop(struct cs_softc *);
81151937Sjkimstatic void	cs_reset(struct cs_softc *);
82151937Sjkimstatic void	cs_watchdog(void *);
83118611Snjl
84118611Snjlstatic int	cs_mediachange(struct ifnet *);
85245582Sjkimstatic void	cs_mediastatus(struct ifnet *, struct ifmediareq *);
86245582Sjkimstatic int      cs_mediaset(struct cs_softc *, int);
87249112Sjkim
88245582Sjkimstatic void	cs_write_mbufs(struct cs_softc*, struct mbuf*);
89245582Sjkimstatic void	cs_xmit_buf(struct cs_softc*);
90245582Sjkimstatic int	cs_get_packet(struct cs_softc*);
91245582Sjkimstatic void	cs_setmode(struct cs_softc*);
92245582Sjkim
93245582Sjkimstatic int	get_eeprom_data(struct cs_softc *sc, int, int, uint16_t *);
94245582Sjkimstatic int	get_eeprom_cksum(int, int, uint16_t *);
95245582Sjkimstatic int	wait_eeprom_ready( struct cs_softc *);
96245582Sjkimstatic void	control_dc_dc( struct cs_softc *, int );
97245582Sjkimstatic int	enable_tp(struct cs_softc *);
98245582Sjkimstatic int	enable_aui(struct cs_softc *);
99245582Sjkimstatic int	enable_bnc(struct cs_softc *);
100245582Sjkimstatic int      cs_duplex_auto(struct cs_softc *);
101245582Sjkim
102245582Sjkimdevclass_t cs_devclass;
103245582Sjkimdriver_intr_t	csintr;
104245582Sjkim
105245582Sjkim/* sysctl vars */
106245582Sjkimstatic SYSCTL_NODE(_hw, OID_AUTO, cs, CTLFLAG_RD, 0, "cs device parameters");
107245582Sjkim
108245582Sjkimint	cs_ignore_cksum_failure = 0;
109245582SjkimTUNABLE_INT("hw.cs.ignore_checksum_failure", &cs_ignore_cksum_failure);
110245582SjkimSYSCTL_INT(_hw_cs, OID_AUTO, ignore_checksum_failure, CTLFLAG_RW,
111245582Sjkim    &cs_ignore_cksum_failure, 0,
112245582Sjkim  "ignore checksum errors in cs card EEPROM");
113245582Sjkim
114245582Sjkimstatic int	cs_recv_delay = 570;
115245582SjkimTUNABLE_INT("hw.cs.recv_delay", &cs_recv_delay);
116245582SjkimSYSCTL_INT(_hw_cs, OID_AUTO, recv_delay, CTLFLAG_RW, &cs_recv_delay, 570, "");
117245582Sjkim
118245582Sjkimstatic int cs8900_eeint2irq[16] = {
119245582Sjkim	 10,  11,  12,   5, 255, 255, 255, 255,
120245582Sjkim	255, 255, 255, 255, 255, 255, 255, 255
121245582Sjkim};
122245582Sjkim
123245582Sjkimstatic int cs8900_irq2eeint[16] = {
124245582Sjkim	255, 255, 255, 255, 255,   3, 255, 255,
125249112Sjkim	255,   0,   1,   2, 255, 255, 255, 255
126167802Sjkim};
127249112Sjkim
128167802Sjkimstatic int
129167802Sjkimget_eeprom_data(struct cs_softc *sc, int off, int len, uint16_t *buffer)
130167802Sjkim{
131167802Sjkim	int i;
132167802Sjkim
133167802Sjkim#ifdef CS_DEBUG
134249112Sjkim	device_printf(sc->dev, "EEPROM data from %x for %x:\n", off, len);
135118611Snjl#endif
136249112Sjkim	for (i=0; i < len; i++) {
137118611Snjl		if (wait_eeprom_ready(sc) < 0)
138245582Sjkim			return (-1);
139118611Snjl		/* Send command to EEPROM to read */
140249112Sjkim		cs_writereg(sc, PP_EECMD, (off + i) | EEPROM_READ_CMD);
141249112Sjkim		if (wait_eeprom_ready(sc) < 0)
142118611Snjl			return (-1);
143118611Snjl		buffer[i] = cs_readreg(sc, PP_EEData);
144118611Snjl
145151937Sjkim#ifdef CS_DEBUG
146249112Sjkim		printf("%04x ",buffer[i]);
147249112Sjkim#endif
148118611Snjl	}
149118611Snjl
150249112Sjkim#ifdef CS_DEBUG
151118611Snjl	printf("\n");
152249112Sjkim#endif
153249112Sjkim	return (0);
154249112Sjkim}
155249112Sjkim
156249112Sjkimstatic int
157249112Sjkimget_eeprom_cksum(int off, int len, uint16_t *buffer)
158249112Sjkim{
159118611Snjl	int i;
160250838Sjkim	uint16_t cksum=0;
161250838Sjkim
162249112Sjkim	for (i = 0; i < len; i++)
163118611Snjl		cksum += buffer[i];
164249112Sjkim	cksum &= 0xffff;
165249112Sjkim	if (cksum == 0 || cs_ignore_cksum_failure)
166249112Sjkim		return (0);
167249112Sjkim	return (-1);
168249112Sjkim}
169249112Sjkim
170118611Snjlstatic int
171118611Snjlwait_eeprom_ready(struct cs_softc *sc)
172249112Sjkim{
173118611Snjl	int i;
174249112Sjkim
175249112Sjkim	/*
176118611Snjl	 * From the CS8900A datasheet, section 3.5.2:
177249112Sjkim	 * "Before issuing any command to the EEPROM, the host must wait
178118611Snjl	 * for the SIBUSY bit (Register 16, SelfST, bit 8) to clear.  After
179249112Sjkim	 * each command has been issued, the host must wait again for SIBUSY
180118611Snjl	 * to clear."
181118611Snjl	 *
182118611Snjl	 * Before we issue the command, we should be !busy, so that will
183118611Snjl	 * be fast.  The datasheet suggests that clock out from the part
184118611Snjl	 * per word will be on the order of 25us, which is consistant with
185118611Snjl	 * the 1MHz serial clock and 16bits...  We should never hit 100,
186118611Snjl	 * let alone 15,000 here.  The original code did an unconditional
187118611Snjl	 * 30ms DELAY here.  Bad Kharma.  cs_readreg takes ~2us.
188118611Snjl	 */
189118611Snjl	for (i = 0; i < 15000; i++)	/* 30ms max */
190118611Snjl		if (!(cs_readreg(sc, PP_SelfST) & SI_BUSY))
191118611Snjl			return (0);
192118611Snjl	return (1);
193118611Snjl}
194118611Snjl
195151937Sjkimstatic void
196118611Snjlcontrol_dc_dc(struct cs_softc *sc, int on_not_off)
197118611Snjl{
198118611Snjl	unsigned int self_control = HCB1_ENBL;
199118611Snjl
200118611Snjl	if (((sc->adapter_cnf & A_CNF_DC_DC_POLARITY)!=0) ^ on_not_off)
201118611Snjl		self_control |= HCB1;
202118611Snjl	else
203167802Sjkim		self_control &= ~HCB1;
204118611Snjl	cs_writereg(sc, PP_SelfCTL, self_control);
205118611Snjl	DELAY(500000);	/* Bad! */
206118611Snjl}
207118611Snjl
208167802Sjkim
209167802Sjkimstatic int
210167802Sjkimcs_duplex_auto(struct cs_softc *sc)
211167802Sjkim{
212167802Sjkim	int i, error=0;
213167802Sjkim
214167802Sjkim	cs_writereg(sc, PP_AutoNegCTL,
215118611Snjl	    RE_NEG_NOW | ALLOW_FDX | AUTO_NEG_ENABLE);
216118611Snjl	for (i=0; cs_readreg(sc, PP_AutoNegST) & AUTO_NEG_BUSY; i++) {
217118611Snjl		if (i > 4000) {
218118611Snjl			device_printf(sc->dev,
219118611Snjl			    "full/half duplex auto negotiation timeout\n");
220118611Snjl			error = ETIMEDOUT;
221118611Snjl			break;
222118611Snjl		}
223118611Snjl		DELAY(1000);
224118611Snjl	}
225118611Snjl	return (error);
226118611Snjl}
227118611Snjl
228118611Snjlstatic int
229118611Snjlenable_tp(struct cs_softc *sc)
230118611Snjl{
231118611Snjl
232118611Snjl	cs_writereg(sc, PP_LineCTL, sc->line_ctl & ~AUI_ONLY);
233249112Sjkim	control_dc_dc(sc, 0);
234118611Snjl	return (0);
235249112Sjkim}
236118611Snjl
237118611Snjlstatic int
238118611Snjlenable_aui(struct cs_softc *sc)
239249112Sjkim{
240118611Snjl
241118611Snjl	cs_writereg(sc, PP_LineCTL,
242118611Snjl	    (sc->line_ctl & ~AUTO_AUI_10BASET) | AUI_ONLY);
243249112Sjkim	control_dc_dc(sc, 0);
244249112Sjkim	return (0);
245151937Sjkim}
246118611Snjl
247118611Snjlstatic int
248249112Sjkimenable_bnc(struct cs_softc *sc)
249118611Snjl{
250118611Snjl
251118611Snjl	cs_writereg(sc, PP_LineCTL,
252118611Snjl	    (sc->line_ctl & ~AUTO_AUI_10BASET) | AUI_ONLY);
253249112Sjkim	control_dc_dc(sc, 1);
254249112Sjkim	return (0);
255249112Sjkim}
256118611Snjl
257118611Snjlint
258118611Snjlcs_cs89x0_probe(device_t dev)
259249112Sjkim{
260249112Sjkim	int i;
261249112Sjkim	int error;
262249112Sjkim	u_long irq, junk;
263249112Sjkim	struct cs_softc *sc = device_get_softc(dev);
264118611Snjl	unsigned rev_type = 0;
265118611Snjl	uint16_t id;
266249112Sjkim	char chip_revision;
267118611Snjl	uint16_t eeprom_buff[CHKSUM_LEN];
268249112Sjkim	int chip_type, pp_isaint, pp_isadma;
269249112Sjkim
270250838Sjkim	sc->dev = dev;
271249112Sjkim	error = cs_alloc_port(dev, 0, CS_89x0_IO_PORTS);
272118611Snjl	if (error)
273250838Sjkim		return (error);
274249112Sjkim
275118611Snjl	if ((cs_inw(sc, ADD_PORT) & ADD_MASK) != ADD_SIG) {
276118611Snjl		/* Chip not detected. Let's try to reset it */
277118611Snjl		if (bootverbose)
278118611Snjl			device_printf(dev, "trying to reset the chip.\n");
279118611Snjl		cs_outw(sc, ADD_PORT, PP_SelfCTL);
280118611Snjl		i = cs_inw(sc, DATA_PORT);
281118611Snjl		cs_outw(sc, ADD_PORT, PP_SelfCTL);
282249112Sjkim		cs_outw(sc, DATA_PORT, i | POWER_ON_RESET);
283118611Snjl		if ((cs_inw(sc, ADD_PORT) & ADD_MASK) != ADD_SIG)
284118611Snjl			return (ENXIO);
285118611Snjl	}
286118611Snjl
287241973Sjkim	for (i = 0; i < 10000; i++) {
288118611Snjl		id = cs_readreg(sc, PP_ChipID);
289118611Snjl		if (id == CHIP_EISA_ID_SIG)
290118611Snjl			break;
291118611Snjl	}
292118611Snjl	if (i == 10000)
293118611Snjl		return (ENXIO);
294151937Sjkim
295118611Snjl	rev_type = cs_readreg(sc, PRODUCT_ID_ADD);
296118611Snjl	chip_type = rev_type & ~REVISON_BITS;
297118611Snjl	chip_revision = ((rev_type & REVISON_BITS) >> 8) + 'A';
298118611Snjl
299118611Snjl	sc->chip_type = chip_type;
300118611Snjl
301118611Snjl	if (chip_type == CS8900) {
302118611Snjl		pp_isaint = PP_CS8900_ISAINT;
303118611Snjl		pp_isadma = PP_CS8900_ISADMA;
304118611Snjl		sc->send_cmd = TX_CS8900_AFTER_ALL;
305118611Snjl	} else {
306118611Snjl		pp_isaint = PP_CS8920_ISAINT;
307118611Snjl		pp_isadma = PP_CS8920_ISADMA;
308118611Snjl		sc->send_cmd = TX_CS8920_AFTER_ALL;
309151937Sjkim	}
310151937Sjkim
311151937Sjkim	/*
312118611Snjl	 * Clear some fields so that fail of EEPROM will left them clean
313118611Snjl	 */
314118611Snjl	sc->auto_neg_cnf = 0;
315118611Snjl	sc->adapter_cnf  = 0;
316118611Snjl	sc->isa_config   = 0;
317118611Snjl
318118611Snjl	/*
319118611Snjl	 * If no interrupt specified, use what the board tells us.
320118611Snjl	 */
321118611Snjl	error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
322118611Snjl
323118611Snjl	/*
324118611Snjl	 * Get data from EEPROM
325250838Sjkim	 */
326118611Snjl	if((cs_readreg(sc, PP_SelfST) & EEPROM_PRESENT) == 0) {
327118611Snjl		device_printf(dev, "No EEPROM, assuming defaults.\n");
328118611Snjl	} else if (get_eeprom_data(sc,START_EEPROM_DATA,CHKSUM_LEN, eeprom_buff)<0) {
329250838Sjkim		device_printf(dev, "EEPROM read failed, assuming defaults.\n");
330118611Snjl	} else if (get_eeprom_cksum(START_EEPROM_DATA,CHKSUM_LEN, eeprom_buff)<0) {
331118611Snjl		device_printf(dev, "EEPROM cheksum bad, assuming defaults.\n");
332118611Snjl	} else {
333118611Snjl		sc->auto_neg_cnf = eeprom_buff[AUTO_NEG_CNF_OFFSET];
334250838Sjkim		sc->adapter_cnf = eeprom_buff[ADAPTER_CNF_OFFSET];
335118611Snjl		sc->isa_config = eeprom_buff[ISA_CNF_OFFSET];
336118611Snjl		for (i=0; i<ETHER_ADDR_LEN/2; i++) {
337118611Snjl			sc->enaddr[i*2] = eeprom_buff[i];
338250838Sjkim			sc->enaddr[i*2+1] = eeprom_buff[i] >> 8;
339118611Snjl		}
340118611Snjl		/*
341118611Snjl		 * If no interrupt specified, use what the
342118611Snjl		 * board tells us.
343118611Snjl		 */
344118611Snjl		if (error) {
345118611Snjl			irq = sc->isa_config & INT_NO_MASK;
346118611Snjl			error = 0;
347118611Snjl			if (chip_type == CS8900) {
348118611Snjl				irq = cs8900_eeint2irq[irq];
349250838Sjkim			} else {
350118611Snjl				if (irq > CS8920_NO_INTS)
351250838Sjkim					irq = 255;
352118611Snjl			}
353118611Snjl			if (irq == 255) {
354118611Snjl				device_printf(dev, "invalid irq in EEPROM.\n");
355118611Snjl				error = EINVAL;
356118611Snjl			}
357118611Snjl			if (!error)
358118611Snjl				bus_set_resource(dev, SYS_RES_IRQ, 0,
359118611Snjl				    irq, 1);
360118611Snjl		}
361118611Snjl	}
362118611Snjl
363118611Snjl	if (!error && !(sc->flags & CS_NO_IRQ)) {
364118611Snjl		if (chip_type == CS8900) {
365118611Snjl			if (irq < 16)
366118611Snjl				irq = cs8900_irq2eeint[irq];
367118611Snjl			else
368118611Snjl				irq = 255;
369118611Snjl		} else {
370151937Sjkim			if (irq > CS8920_NO_INTS)
371151937Sjkim				irq = 255;
372118611Snjl		}
373118611Snjl		if (irq == 255)
374118611Snjl			error = EINVAL;
375118611Snjl	}
376151937Sjkim
377151937Sjkim	if (error) {
378118611Snjl	       	device_printf(dev, "Unknown or invalid irq\n");
379118611Snjl		return (error);
380118611Snjl	}
381118611Snjl
382151937Sjkim	if (!(sc->flags & CS_NO_IRQ))
383151937Sjkim		cs_writereg(sc, pp_isaint, irq);
384118611Snjl
385118611Snjl	/*
386118611Snjl	 * Temporary disabled
387118611Snjl	 *
388151937Sjkim	if (drq>0)
389151937Sjkim		cs_writereg(sc, pp_isadma, drq);
390118611Snjl	else {
391118611Snjl		device_printf(dev, "incorrect drq\n",);
392118611Snjl		return (0);
393118611Snjl	}
394118611Snjl	*/
395118611Snjl
396118611Snjl	if (bootverbose)
397151937Sjkim		 device_printf(dev, "CS89%c0%s rev %c media%s%s%s\n",
398151937Sjkim			chip_type == CS8900 ? '0' : '2',
399118611Snjl			chip_type == CS8920M ? "M" : "",
400118611Snjl			chip_revision,
401118611Snjl			(sc->adapter_cnf & A_CNF_10B_T) ? " TP"  : "",
402118611Snjl			(sc->adapter_cnf & A_CNF_AUI)   ? " AUI" : "",
403118611Snjl			(sc->adapter_cnf & A_CNF_10B_2) ? " BNC" : "");
404151937Sjkim
405118611Snjl	if ((sc->adapter_cnf & A_CNF_EXTND_10B_2) &&
406151937Sjkim	    (sc->adapter_cnf & A_CNF_LOW_RX_SQUELCH))
407151937Sjkim		sc->line_ctl = LOW_RX_SQUELCH;
408151937Sjkim	else
409151937Sjkim		sc->line_ctl = 0;
410151937Sjkim
411118611Snjl	return (0);
412118611Snjl}
413118611Snjl
414118611Snjl/*
415118611Snjl * Allocate a port resource with the given resource id.
416118611Snjl */
417151937Sjkimint
418118611Snjlcs_alloc_port(device_t dev, int rid, int size)
419151937Sjkim{
420151937Sjkim	struct cs_softc *sc = device_get_softc(dev);
421151937Sjkim	struct resource *res;
422151937Sjkim
423151937Sjkim	res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
424151937Sjkim	    0ul, ~0ul, size, RF_ACTIVE);
425118611Snjl	if (res == NULL)
426118611Snjl		return (ENOENT);
427118611Snjl	sc->port_rid = rid;
428118611Snjl	sc->port_res = res;
429167802Sjkim	return (0);
430167802Sjkim}
431167802Sjkim
432167802Sjkim/*
433167802Sjkim * Allocate an irq resource with the given resource id.
434167802Sjkim */
435118611Snjlint
436118611Snjlcs_alloc_irq(device_t dev, int rid)
437118611Snjl{
438118611Snjl	struct cs_softc *sc = device_get_softc(dev);
439250838Sjkim	struct resource *res;
440118611Snjl
441250838Sjkim	res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
442118611Snjl	if (res == NULL)
443118611Snjl		return (ENOENT);
444118611Snjl	sc->irq_rid = rid;
445118611Snjl	sc->irq_res = res;
446118611Snjl	return (0);
447118611Snjl}
448118611Snjl
449118611Snjl/*
450118611Snjl * Release all resources
451118611Snjl */
452118611Snjlvoid
453118611Snjlcs_release_resources(device_t dev)
454118611Snjl{
455118611Snjl	struct cs_softc *sc = device_get_softc(dev);
456118611Snjl
457118611Snjl	if (sc->port_res) {
458118611Snjl		bus_release_resource(dev, SYS_RES_IOPORT,
459118611Snjl		    sc->port_rid, sc->port_res);
460118611Snjl		sc->port_res = 0;
461118611Snjl	}
462118611Snjl	if (sc->irq_res) {
463118611Snjl		bus_release_resource(dev, SYS_RES_IRQ,
464151937Sjkim		    sc->irq_rid, sc->irq_res);
465151937Sjkim		sc->irq_res = 0;
466151937Sjkim	}
467151937Sjkim}
468151937Sjkim
469151937Sjkim/*
470118611Snjl * Install the interface into kernel networking data structures
471118611Snjl */
472167802Sjkimint
473167802Sjkimcs_attach(device_t dev)
474167802Sjkim{
475167802Sjkim	int error, media=0;
476167802Sjkim	struct cs_softc *sc = device_get_softc(dev);
477167802Sjkim	struct ifnet *ifp;
478167802Sjkim
479167802Sjkim	sc->dev = dev;
480167802Sjkim
481167802Sjkim	ifp = sc->ifp = if_alloc(IFT_ETHER);
482167802Sjkim	if (ifp == NULL) {
483167802Sjkim		device_printf(dev, "can not if_alloc()\n");
484167802Sjkim		cs_release_resources(dev);
485167802Sjkim		return (ENOMEM);
486167802Sjkim	}
487167802Sjkim
488167802Sjkim	mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
489167802Sjkim	    MTX_DEF);
490118611Snjl	callout_init_mtx(&sc->timer, &sc->lock, 0);
491250838Sjkim
492151937Sjkim	CS_LOCK(sc);
493151937Sjkim	cs_stop(sc);
494118611Snjl	CS_UNLOCK(sc);
495118611Snjl
496118611Snjl	ifp->if_softc=sc;
497118611Snjl	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
498118611Snjl	ifp->if_start=cs_start;
499118611Snjl	ifp->if_ioctl=cs_ioctl;
500118611Snjl	ifp->if_init=cs_init;
501118611Snjl	IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
502118611Snjl
503118611Snjl	ifp->if_flags=(IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
504118611Snjl
505118611Snjl	/*
506118611Snjl	 * this code still in progress (DMA support)
507118611Snjl	 *
508118611Snjl
509118611Snjl	sc->recv_ring=malloc(CS_DMA_BUFFER_SIZE<<1, M_DEVBUF, M_NOWAIT);
510118611Snjl	if (sc->recv_ring == NULL) {
511118611Snjl		log(LOG_ERR,
512118611Snjl		"%s: Couldn't allocate memory for NIC\n", ifp->if_xname);
513118611Snjl		return(0);
514118611Snjl	}
515118611Snjl	if ((sc->recv_ring-(sc->recv_ring & 0x1FFFF))
516118611Snjl	    < (128*1024-CS_DMA_BUFFER_SIZE))
517118611Snjl	    sc->recv_ring+=16*1024;
518118611Snjl
519118611Snjl	*/
520118611Snjl
521118611Snjl	sc->buffer=malloc(ETHER_MAX_LEN-ETHER_CRC_LEN,M_DEVBUF,M_NOWAIT);
522118611Snjl	if (sc->buffer == NULL) {
523118611Snjl		device_printf(sc->dev, "Couldn't allocate memory for NIC\n");
524118611Snjl		if_free(ifp);
525118611Snjl		mtx_destroy(&sc->lock);
526118611Snjl		cs_release_resources(dev);
527118611Snjl		return(ENOMEM);
528118611Snjl	}
529118611Snjl
530118611Snjl	/*
531118611Snjl	 * Initialize the media structures.
532118611Snjl	 */
533118611Snjl	ifmedia_init(&sc->media, 0, cs_mediachange, cs_mediastatus);
534118611Snjl
535118611Snjl	if (sc->adapter_cnf & A_CNF_10B_T) {
536118611Snjl		ifmedia_add(&sc->media, IFM_ETHER|IFM_10_T, 0, NULL);
537118611Snjl		if (sc->chip_type != CS8900) {
538118611Snjl			ifmedia_add(&sc->media,
539118611Snjl				IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
540118611Snjl			ifmedia_add(&sc->media,
541118611Snjl				IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
542151937Sjkim		}
543151937Sjkim	}
544118611Snjl
545118611Snjl	if (sc->adapter_cnf & A_CNF_10B_2)
546118611Snjl		ifmedia_add(&sc->media, IFM_ETHER|IFM_10_2, 0, NULL);
547118611Snjl
548151937Sjkim	if (sc->adapter_cnf & A_CNF_AUI)
549151937Sjkim		ifmedia_add(&sc->media, IFM_ETHER|IFM_10_5, 0, NULL);
550118611Snjl
551118611Snjl	if (sc->adapter_cnf & A_CNF_MEDIA)
552118611Snjl		ifmedia_add(&sc->media, IFM_ETHER|IFM_AUTO, 0, NULL);
553118611Snjl
554151937Sjkim	/* Set default media from EEPROM */
555151937Sjkim	switch (sc->adapter_cnf & A_CNF_MEDIA_TYPE) {
556118611Snjl	case A_CNF_MEDIA_AUTO:  media = IFM_ETHER|IFM_AUTO; break;
557118611Snjl	case A_CNF_MEDIA_10B_T: media = IFM_ETHER|IFM_10_T; break;
558118611Snjl	case A_CNF_MEDIA_10B_2: media = IFM_ETHER|IFM_10_2; break;
559118611Snjl	case A_CNF_MEDIA_AUI:   media = IFM_ETHER|IFM_10_5; break;
560151937Sjkim	default:
561151937Sjkim		device_printf(sc->dev, "no media, assuming 10baseT\n");
562118611Snjl		sc->adapter_cnf |= A_CNF_10B_T;
563118611Snjl		ifmedia_add(&sc->media, IFM_ETHER|IFM_10_T, 0, NULL);
564118611Snjl		if (sc->chip_type != CS8900) {
565167802Sjkim			ifmedia_add(&sc->media,
566118611Snjl			    IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
567118611Snjl			ifmedia_add(&sc->media,
568118611Snjl			    IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
569118611Snjl		}
570250838Sjkim		media = IFM_ETHER | IFM_10_T;
571118611Snjl		break;
572250838Sjkim	}
573118611Snjl	ifmedia_set(&sc->media, media);
574118611Snjl	cs_mediaset(sc, media);
575118611Snjl
576118611Snjl	ether_ifattach(ifp, sc->enaddr);
577118611Snjl
578118611Snjl  	error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
579118611Snjl	    NULL, csintr, sc, &sc->irq_handle);
580118611Snjl	if (error) {
581118611Snjl		ether_ifdetach(ifp);
582167802Sjkim		free(sc->buffer, M_DEVBUF);
583167802Sjkim		if_free(ifp);
584167802Sjkim		mtx_destroy(&sc->lock);
585167802Sjkim		cs_release_resources(dev);
586167802Sjkim		return (error);
587167802Sjkim	}
588151937Sjkim
589151937Sjkim	return (0);
590118611Snjl}
591118611Snjl
592118611Snjlint
593250838Sjkimcs_detach(device_t dev)
594118611Snjl{
595118611Snjl	struct cs_softc *sc;
596118611Snjl	struct ifnet *ifp;
597249112Sjkim
598249112Sjkim	sc = device_get_softc(dev);
599249112Sjkim	ifp = sc->ifp;
600249112Sjkim
601249112Sjkim	CS_LOCK(sc);
602249112Sjkim	cs_stop(sc);
603249112Sjkim	CS_UNLOCK(sc);
604249112Sjkim	callout_drain(&sc->timer);
605249112Sjkim	ether_ifdetach(ifp);
606249112Sjkim	bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
607249112Sjkim	cs_release_resources(dev);
608249112Sjkim	free(sc->buffer, M_DEVBUF);
609249112Sjkim	if_free(ifp);
610249112Sjkim	mtx_destroy(&sc->lock);
611249112Sjkim	return (0);
612249112Sjkim}
613249112Sjkim
614249112Sjkim/*
615249112Sjkim * Initialize the board
616249112Sjkim */
617249112Sjkimstatic void
618249112Sjkimcs_init(void *xsc)
619249112Sjkim{
620249112Sjkim	struct cs_softc *sc=(struct cs_softc *)xsc;
621249112Sjkim
622249112Sjkim	CS_LOCK(sc);
623249112Sjkim	cs_init_locked(sc);
624249112Sjkim	CS_UNLOCK(sc);
625249112Sjkim}
626249112Sjkim
627249112Sjkimstatic void
628249112Sjkimcs_init_locked(struct cs_softc *sc)
629249112Sjkim{
630249112Sjkim	struct ifnet *ifp = sc->ifp;
631249112Sjkim	int i, rx_cfg;
632249112Sjkim
633249112Sjkim	/*
634249112Sjkim	 * reset watchdog timer
635249112Sjkim	 */
636249112Sjkim	sc->tx_timeout = 0;
637249112Sjkim	sc->buf_len = 0;
638249112Sjkim
639249112Sjkim	/*
640249112Sjkim	 * Hardware initialization of cs
641249112Sjkim	 */
642249112Sjkim
643249112Sjkim	/* Enable receiver and transmitter */
644249112Sjkim	cs_writereg(sc, PP_LineCTL,
645249112Sjkim		cs_readreg(sc, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON);
646249112Sjkim
647249112Sjkim	/* Configure the receiver mode */
648249112Sjkim	cs_setmode(sc);
649249112Sjkim
650249112Sjkim	/*
651249112Sjkim	 * This defines what type of frames will cause interrupts
652249112Sjkim	 * Bad frames should generate interrupts so that the driver
653249112Sjkim	 * could track statistics of discarded packets
654249112Sjkim	 */
655	rx_cfg = RX_OK_ENBL | RX_CRC_ERROR_ENBL | RX_RUNT_ENBL |
656		 RX_EXTRA_DATA_ENBL;
657	if (sc->isa_config & STREAM_TRANSFER)
658		rx_cfg |= RX_STREAM_ENBL;
659	cs_writereg(sc, PP_RxCFG, rx_cfg);
660	cs_writereg(sc, PP_TxCFG, TX_LOST_CRS_ENBL |
661		    TX_SQE_ERROR_ENBL | TX_OK_ENBL | TX_LATE_COL_ENBL |
662		    TX_JBR_ENBL | TX_ANY_COL_ENBL | TX_16_COL_ENBL);
663	cs_writereg(sc, PP_BufCFG, READY_FOR_TX_ENBL |
664		    RX_MISS_COUNT_OVRFLOW_ENBL | TX_COL_COUNT_OVRFLOW_ENBL |
665		    TX_UNDERRUN_ENBL /*| RX_DMA_ENBL*/);
666
667	/* Write MAC address into IA filter */
668	for (i=0; i<ETHER_ADDR_LEN/2; i++)
669		cs_writereg(sc, PP_IA + i * 2,
670		    sc->enaddr[i * 2] |
671		    (sc->enaddr[i * 2 + 1] << 8) );
672
673	/*
674	 * Now enable everything
675	 */
676/*
677#ifdef	CS_USE_64K_DMA
678	cs_writereg(sc, PP_BusCTL, ENABLE_IRQ | RX_DMA_SIZE_64K);
679#else
680	cs_writereg(sc, PP_BusCTL, ENABLE_IRQ);
681#endif
682*/
683	cs_writereg(sc, PP_BusCTL, ENABLE_IRQ);
684
685	/*
686	 * Set running and clear output active flags
687	 */
688	sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
689	sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
690	callout_reset(&sc->timer, hz, cs_watchdog, sc);
691
692	/*
693	 * Start sending process
694	 */
695	cs_start_locked(ifp);
696}
697
698/*
699 * Get the packet from the board and send it to the upper layer.
700 */
701static int
702cs_get_packet(struct cs_softc *sc)
703{
704	struct ifnet *ifp = sc->ifp;
705	int status, length;
706	struct ether_header *eh;
707	struct mbuf *m;
708
709#ifdef CS_DEBUG
710	int i;
711#endif
712
713	status = cs_inw(sc, RX_FRAME_PORT);
714	length = cs_inw(sc, RX_FRAME_PORT);
715
716#ifdef CS_DEBUG
717	device_printf(sc->dev, "rcvd: stat %x, len %d\n",
718		status, length);
719#endif
720
721	if (!(status & RX_OK)) {
722#ifdef CS_DEBUG
723		device_printf(sc->dev, "bad pkt stat %x\n", status);
724#endif
725		ifp->if_ierrors++;
726		return (-1);
727	}
728
729	MGETHDR(m, M_NOWAIT, MT_DATA);
730	if (m==NULL)
731		return (-1);
732
733	if (length > MHLEN) {
734		MCLGET(m, M_NOWAIT);
735		if (!(m->m_flags & M_EXT)) {
736			m_freem(m);
737			return (-1);
738		}
739	}
740
741	/* Initialize packet's header info */
742	m->m_pkthdr.rcvif = ifp;
743	m->m_pkthdr.len = length;
744	m->m_len = length;
745
746	/* Get the data */
747	bus_read_multi_2(sc->port_res, RX_FRAME_PORT, mtod(m, uint16_t *),
748	    (length + 1) >> 1);
749
750	eh = mtod(m, struct ether_header *);
751
752#ifdef CS_DEBUG
753	for (i=0;i<length;i++)
754	     printf(" %02x",(unsigned char)*((char *)(m->m_data+i)));
755	printf( "\n" );
756#endif
757
758	if (status & (RX_IA | RX_BROADCAST) ||
759	    (ifp->if_flags & IFF_MULTICAST && status & RX_HASHED)) {
760		/* Feed the packet to the upper layer */
761		(*ifp->if_input)(ifp, m);
762		ifp->if_ipackets++;
763		if (length == ETHER_MAX_LEN-ETHER_CRC_LEN)
764			DELAY(cs_recv_delay);
765	} else {
766		m_freem(m);
767	}
768
769	return (0);
770}
771
772/*
773 * Handle interrupts
774 */
775void
776csintr(void *arg)
777{
778	struct cs_softc *sc = (struct cs_softc*) arg;
779	struct ifnet *ifp = sc->ifp;
780	int status;
781
782#ifdef CS_DEBUG
783	device_printf(sc->dev, "Interrupt.\n");
784#endif
785
786	CS_LOCK(sc);
787	while ((status=cs_inw(sc, ISQ_PORT))) {
788
789#ifdef CS_DEBUG
790		device_printf(sc->dev, "from ISQ: %04x\n", status);
791#endif
792
793		switch (status & ISQ_EVENT_MASK) {
794		case ISQ_RECEIVER_EVENT:
795			cs_get_packet(sc);
796			break;
797
798		case ISQ_TRANSMITTER_EVENT:
799			if (status & TX_OK)
800				ifp->if_opackets++;
801			else
802				ifp->if_oerrors++;
803			ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
804			sc->tx_timeout = 0;
805			break;
806
807		case ISQ_BUFFER_EVENT:
808			if (status & READY_FOR_TX) {
809				ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
810				sc->tx_timeout = 0;
811			}
812
813			if (status & TX_UNDERRUN) {
814				ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
815				sc->tx_timeout = 0;
816				ifp->if_oerrors++;
817			}
818			break;
819
820		case ISQ_RX_MISS_EVENT:
821			ifp->if_ierrors+=(status>>6);
822			break;
823
824		case ISQ_TX_COL_EVENT:
825			ifp->if_collisions+=(status>>6);
826			break;
827		}
828	}
829
830	if (!(ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
831		cs_start_locked(ifp);
832	}
833	CS_UNLOCK(sc);
834}
835
836/*
837 * Save the data in buffer
838 */
839
840static void
841cs_write_mbufs( struct cs_softc *sc, struct mbuf *m )
842{
843	int len;
844	struct mbuf *mp;
845	unsigned char *data, *buf;
846
847	for (mp=m, buf=sc->buffer, sc->buf_len=0; mp != NULL; mp=mp->m_next) {
848		len = mp->m_len;
849
850		/*
851		 * Ignore empty parts
852		 */
853		if (!len)
854			continue;
855
856		/*
857		 * Find actual data address
858		 */
859		data = mtod(mp, caddr_t);
860
861		bcopy((caddr_t) data, (caddr_t) buf, len);
862		buf += len;
863		sc->buf_len += len;
864	}
865}
866
867
868static void
869cs_xmit_buf( struct cs_softc *sc )
870{
871	bus_write_multi_2(sc->port_res, TX_FRAME_PORT, (uint16_t *)sc->buffer,
872	    (sc->buf_len + 1) >> 1);
873	sc->buf_len = 0;
874}
875
876static void
877cs_start(struct ifnet *ifp)
878{
879	struct cs_softc *sc = ifp->if_softc;
880
881	CS_LOCK(sc);
882	cs_start_locked(ifp);
883	CS_UNLOCK(sc);
884}
885
886static void
887cs_start_locked(struct ifnet *ifp)
888{
889	int length;
890	struct mbuf *m, *mp;
891	struct cs_softc *sc = ifp->if_softc;
892
893	for (;;) {
894		if (sc->buf_len)
895			length = sc->buf_len;
896		else {
897			IF_DEQUEUE( &ifp->if_snd, m );
898
899			if (m==NULL) {
900				return;
901			}
902
903			for (length=0, mp=m; mp != NULL; mp=mp->m_next)
904				length += mp->m_len;
905
906			/* Skip zero-length packets */
907			if (length == 0) {
908				m_freem(m);
909				continue;
910			}
911
912			cs_write_mbufs(sc, m);
913
914			BPF_MTAP(ifp, m);
915
916			m_freem(m);
917		}
918
919		/*
920		 * Issue a SEND command
921		 */
922		cs_outw(sc, TX_CMD_PORT, sc->send_cmd);
923		cs_outw(sc, TX_LEN_PORT, length );
924
925		/*
926		 * If there's no free space in the buffer then leave
927		 * this packet for the next time: indicate output active
928		 * and return.
929		 */
930		if (!(cs_readreg(sc, PP_BusST) & READY_FOR_TX_NOW)) {
931			sc->tx_timeout = sc->buf_len;
932			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
933			return;
934		}
935
936		cs_xmit_buf(sc);
937
938		/*
939		 * Set the watchdog timer in case we never hear
940		 * from board again. (I don't know about correct
941		 * value for this timeout)
942		 */
943		sc->tx_timeout = length;
944
945		ifp->if_drv_flags |= IFF_DRV_OACTIVE;
946		return;
947	}
948}
949
950/*
951 * Stop everything on the interface
952 */
953static void
954cs_stop(struct cs_softc *sc)
955{
956
957	CS_ASSERT_LOCKED(sc);
958	cs_writereg(sc, PP_RxCFG, 0);
959	cs_writereg(sc, PP_TxCFG, 0);
960	cs_writereg(sc, PP_BufCFG, 0);
961	cs_writereg(sc, PP_BusCTL, 0);
962
963	sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
964	sc->tx_timeout = 0;
965	callout_stop(&sc->timer);
966}
967
968/*
969 * Reset the interface
970 */
971static void
972cs_reset(struct cs_softc *sc)
973{
974
975	CS_ASSERT_LOCKED(sc);
976	cs_stop(sc);
977	cs_init_locked(sc);
978}
979
980static uint16_t
981cs_hash_index(struct sockaddr_dl *addr)
982{
983	uint32_t crc;
984	uint16_t idx;
985	caddr_t lla;
986
987	lla = LLADDR(addr);
988	crc = ether_crc32_le(lla, ETHER_ADDR_LEN);
989	idx = crc >> 26;
990
991	return (idx);
992}
993
994static void
995cs_setmode(struct cs_softc *sc)
996{
997	int rx_ctl;
998	uint16_t af[4];
999	uint16_t port, mask, index;
1000	struct ifnet *ifp = sc->ifp;
1001	struct ifmultiaddr *ifma;
1002
1003	/* Stop the receiver while changing filters */
1004	cs_writereg(sc, PP_LineCTL, cs_readreg(sc, PP_LineCTL) & ~SERIAL_RX_ON);
1005
1006	if (ifp->if_flags & IFF_PROMISC) {
1007		/* Turn on promiscuous mode. */
1008		rx_ctl = RX_OK_ACCEPT | RX_PROM_ACCEPT;
1009	} else if (ifp->if_flags & IFF_MULTICAST) {
1010		/* Allow receiving frames with multicast addresses */
1011		rx_ctl = RX_IA_ACCEPT | RX_BROADCAST_ACCEPT |
1012			 RX_OK_ACCEPT | RX_MULTCAST_ACCEPT;
1013
1014		/* Start with an empty filter */
1015		af[0] = af[1] = af[2] = af[3] = 0x0000;
1016
1017		if (ifp->if_flags & IFF_ALLMULTI) {
1018			/* Accept all multicast frames */
1019			af[0] = af[1] = af[2] = af[3] = 0xffff;
1020		} else {
1021			/*
1022			 * Set up the filter to only accept multicast
1023			 * frames we're interested in.
1024			 */
1025			if_maddr_rlock(ifp);
1026			TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1027				struct sockaddr_dl *dl =
1028				    (struct sockaddr_dl *)ifma->ifma_addr;
1029
1030				index = cs_hash_index(dl);
1031				port = (u_int16_t) (index >> 4);
1032				mask = (u_int16_t) (1 << (index & 0xf));
1033				af[port] |= mask;
1034			}
1035			if_maddr_runlock(ifp);
1036		}
1037
1038		cs_writereg(sc, PP_LAF + 0, af[0]);
1039		cs_writereg(sc, PP_LAF + 2, af[1]);
1040		cs_writereg(sc, PP_LAF + 4, af[2]);
1041		cs_writereg(sc, PP_LAF + 6, af[3]);
1042	} else {
1043		/*
1044		 * Receive only good frames addressed for us and
1045		 * good broadcasts.
1046		 */
1047		rx_ctl = RX_IA_ACCEPT | RX_BROADCAST_ACCEPT |
1048			 RX_OK_ACCEPT;
1049	}
1050
1051	/* Set up the filter */
1052	cs_writereg(sc, PP_RxCTL, RX_DEF_ACCEPT | rx_ctl);
1053
1054	/* Turn on receiver */
1055	cs_writereg(sc, PP_LineCTL, cs_readreg(sc, PP_LineCTL) | SERIAL_RX_ON);
1056}
1057
1058static int
1059cs_ioctl(register struct ifnet *ifp, u_long command, caddr_t data)
1060{
1061	struct cs_softc *sc=ifp->if_softc;
1062	struct ifreq *ifr = (struct ifreq *)data;
1063	int error=0;
1064
1065#ifdef CS_DEBUG
1066	if_printf(ifp, "%s command=%lx\n", __func__, command);
1067#endif
1068
1069	switch (command) {
1070	case SIOCSIFFLAGS:
1071		/*
1072		 * Switch interface state between "running" and
1073		 * "stopped", reflecting the UP flag.
1074		 */
1075		CS_LOCK(sc);
1076		if (sc->ifp->if_flags & IFF_UP) {
1077			if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING)==0) {
1078				cs_init_locked(sc);
1079			}
1080		} else {
1081			if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING)!=0) {
1082				cs_stop(sc);
1083			}
1084		}
1085		/*
1086		 * Promiscuous and/or multicast flags may have changed,
1087		 * so reprogram the multicast filter and/or receive mode.
1088		 *
1089		 * See note about multicasts in cs_setmode
1090		 */
1091		cs_setmode(sc);
1092		CS_UNLOCK(sc);
1093		break;
1094
1095	case SIOCADDMULTI:
1096	case SIOCDELMULTI:
1097	    /*
1098	     * Multicast list has changed; set the hardware filter
1099	     * accordingly.
1100	     *
1101	     * See note about multicasts in cs_setmode
1102	     */
1103	    CS_LOCK(sc);
1104	    cs_setmode(sc);
1105	    CS_UNLOCK(sc);
1106	    error = 0;
1107	    break;
1108
1109	case SIOCSIFMEDIA:
1110	case SIOCGIFMEDIA:
1111		error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1112		break;
1113
1114	default:
1115		error = ether_ioctl(ifp, command, data);
1116		break;
1117	}
1118
1119	return (error);
1120}
1121
1122/*
1123 * Device timeout/watchdog routine. Entered if the device neglects to
1124 * generate an interrupt after a transmit has been started on it.
1125 */
1126static void
1127cs_watchdog(void *arg)
1128{
1129	struct cs_softc *sc = arg;
1130	struct ifnet *ifp = sc->ifp;
1131
1132	CS_ASSERT_LOCKED(sc);
1133	if (sc->tx_timeout && --sc->tx_timeout == 0) {
1134		ifp->if_oerrors++;
1135		log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
1136
1137		/* Reset the interface */
1138		if (ifp->if_flags & IFF_UP)
1139			cs_reset(sc);
1140		else
1141			cs_stop(sc);
1142	}
1143	callout_reset(&sc->timer, hz, cs_watchdog, sc);
1144}
1145
1146static int
1147cs_mediachange(struct ifnet *ifp)
1148{
1149	struct cs_softc *sc = ifp->if_softc;
1150	struct ifmedia *ifm = &sc->media;
1151	int error;
1152
1153	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1154		return (EINVAL);
1155
1156	CS_LOCK(sc);
1157	error = cs_mediaset(sc, ifm->ifm_media);
1158	CS_UNLOCK(sc);
1159	return (error);
1160}
1161
1162static void
1163cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
1164{
1165	int line_status;
1166	struct cs_softc *sc = ifp->if_softc;
1167
1168	CS_LOCK(sc);
1169	ifmr->ifm_active = IFM_ETHER;
1170	line_status = cs_readreg(sc, PP_LineST);
1171	if (line_status & TENBASET_ON) {
1172		ifmr->ifm_active |= IFM_10_T;
1173		if (sc->chip_type != CS8900) {
1174			if (cs_readreg(sc, PP_AutoNegST) & FDX_ACTIVE)
1175				ifmr->ifm_active |= IFM_FDX;
1176			if (cs_readreg(sc, PP_AutoNegST) & HDX_ACTIVE)
1177				ifmr->ifm_active |= IFM_HDX;
1178		}
1179		ifmr->ifm_status = IFM_AVALID;
1180		if (line_status & LINK_OK)
1181			ifmr->ifm_status |= IFM_ACTIVE;
1182	} else {
1183		if (line_status & AUI_ON) {
1184			cs_writereg(sc, PP_SelfCTL, cs_readreg(sc, PP_SelfCTL) |
1185			    HCB1_ENBL);
1186			if (((sc->adapter_cnf & A_CNF_DC_DC_POLARITY)!=0)^
1187			    (cs_readreg(sc, PP_SelfCTL) & HCB1))
1188				ifmr->ifm_active |= IFM_10_2;
1189			else
1190				ifmr->ifm_active |= IFM_10_5;
1191		}
1192	}
1193	CS_UNLOCK(sc);
1194}
1195
1196static int
1197cs_mediaset(struct cs_softc *sc, int media)
1198{
1199	int error = 0;
1200
1201	/* Stop the receiver & transmitter */
1202	cs_writereg(sc, PP_LineCTL, cs_readreg(sc, PP_LineCTL) &
1203	    ~(SERIAL_RX_ON | SERIAL_TX_ON));
1204
1205#ifdef CS_DEBUG
1206	device_printf(sc->dev, "%s media=%x\n", __func__, media);
1207#endif
1208
1209	switch (IFM_SUBTYPE(media)) {
1210	default:
1211	case IFM_AUTO:
1212		/*
1213		 * This chip makes it a little hard to support this, so treat
1214		 * it as IFM_10_T, auto duplex.
1215		 */
1216		enable_tp(sc);
1217		cs_duplex_auto(sc);
1218		break;
1219	case IFM_10_T:
1220		enable_tp(sc);
1221		if (media & IFM_FDX)
1222			cs_duplex_full(sc);
1223		else if (media & IFM_HDX)
1224			cs_duplex_half(sc);
1225		else
1226			error = cs_duplex_auto(sc);
1227		break;
1228	case IFM_10_2:
1229		enable_bnc(sc);
1230		break;
1231	case IFM_10_5:
1232		enable_aui(sc);
1233		break;
1234	}
1235
1236	/*
1237	 * Turn the transmitter & receiver back on
1238	 */
1239	cs_writereg(sc, PP_LineCTL, cs_readreg(sc, PP_LineCTL) |
1240	    SERIAL_RX_ON | SERIAL_TX_ON);
1241
1242	return (error);
1243}
1244