168349Sobrien/*- 268349Sobrien * Copyright (c) 2007, Juniper Networks, Inc. 368349Sobrien * Copyright (c) 2012-2013, SRI International 468349Sobrien * All rights reserved. 568349Sobrien * 668349Sobrien * Portions of this software were developed by SRI International and the 768349Sobrien * University of Cambridge Computer Laboratory under DARPA/AFRL contract 868349Sobrien * (FA8750-10-C-0237) ("CTSRD"), as part of the DARPA CRASH research 968349Sobrien * programme. 1068349Sobrien * 1168349Sobrien * Redistribution and use in source and binary forms, with or without 1268349Sobrien * modification, are permitted provided that the following conditions 1368349Sobrien * are met: 1468349Sobrien * 1. Redistributions of source code must retain the above copyright 1568349Sobrien * notice, this list of conditions and the following disclaimer. 1668349Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1768349Sobrien * notice, this list of conditions and the following disclaimer in the 1868349Sobrien * documentation and/or other materials provided with the distribution. 1968349Sobrien * 3. Neither the name of the author nor the names of any co-contributors 2068349Sobrien * may be used to endorse or promote products derived from this software 2168349Sobrien * without specific prior written permission. 2268349Sobrien * 2368349Sobrien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 2468349Sobrien * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2568349Sobrien * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2668349Sobrien * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2768349Sobrien * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 2868349Sobrien * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2968349Sobrien * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 3068349Sobrien * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 3168349Sobrien * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3268349Sobrien * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3380588Sobrien * SUCH DAMAGE. 3480588Sobrien * 3580588Sobrien * $FreeBSD$ 3680588Sobrien */ 3780588Sobrien 3880588Sobrien#ifndef _DEV_CFI_REG_H_ 3980588Sobrien#define _DEV_CFI_REG_H_ 4080588Sobrien 4180588Sobrienstruct cfi_qry { 4280588Sobrien u_char reserved[16]; 4380588Sobrien u_char ident[3]; /* "QRY" */ 4480588Sobrien u_char pri_vend[2]; 4580588Sobrien u_char pri_vend_eqt[2]; 4680588Sobrien u_char alt_vend[2]; 4780588Sobrien u_char alt_vend_eqt[2]; 4880588Sobrien /* System Interface Information. */ 4980588Sobrien u_char min_vcc; 5080588Sobrien u_char max_vcc; 51 u_char min_vpp; 52 u_char max_vpp; 53 u_char tto_byte_write; /* 2**n microseconds. */ 54 u_char tto_buf_write; /* 2**n microseconds. */ 55 u_char tto_block_erase; /* 2**n milliseconds. */ 56 u_char tto_chip_erase; /* 2**n milliseconds. */ 57 u_char mto_byte_write; /* 2**n times typical t/o. */ 58 u_char mto_buf_write; /* 2**n times typical t/o. */ 59 u_char mto_block_erase; /* 2**n times typical t/o. */ 60 u_char mto_chip_erase; /* 2**n times typical t/o. */ 61 /* Device Geometry Definition. */ 62 u_char size; /* 2**n bytes. */ 63 u_char iface[2]; 64 u_char max_buf_write_size[2]; /* 2**n. */ 65 u_char nregions; /* Number of erase regions. */ 66 u_char region[4]; /* Single entry. */ 67 /* Additional entries follow. */ 68 /* Primary Vendor-specific Extended Query table follows. */ 69 /* Alternate Vendor-specific Extended Query table follows. */ 70}; 71 72#define CFI_QRY_CMD_ADDR 0x55 73#define CFI_QRY_CMD_DATA 0x98 74 75#define CFI_QRY_IDENT offsetof(struct cfi_qry, ident) 76#define CFI_QRY_VEND offsetof(struct cfi_qry, pri_vend) 77 78#define CFI_QRY_TTO_WRITE offsetof(struct cfi_qry, tto_byte_write) 79#define CFI_QRY_TTO_BUFWRITE offsetof(struct cfi_qry, tto_buf_write) 80#define CFI_QRY_TTO_ERASE offsetof(struct cfi_qry, tto_block_erase) 81#define CFI_QRY_MTO_WRITE offsetof(struct cfi_qry, mto_byte_write) 82#define CFI_QRY_MTO_BUFWRITE offsetof(struct cfi_qry, mto_buf_write) 83#define CFI_QRY_MTO_ERASE offsetof(struct cfi_qry, mto_block_erase) 84 85#define CFI_QRY_SIZE offsetof(struct cfi_qry, size) 86#define CFI_QRY_IFACE offsetof(struct cfi_qry, iface) 87#define CFI_QRY_MAXBUF offsetof(struct cfi_qry, max_buf_write_size) 88#define CFI_QRY_NREGIONS offsetof(struct cfi_qry, nregions) 89#define CFI_QRY_REGION0 offsetof(struct cfi_qry, region) 90#define CFI_QRY_REGION(x) (CFI_QRY_REGION0 + (x) * 4) 91 92#define CFI_VEND_NONE 0x0000 93#define CFI_VEND_INTEL_ECS 0x0001 94#define CFI_VEND_AMD_SCS 0x0002 95#define CFI_VEND_INTEL_SCS 0x0003 96#define CFI_VEND_AMD_ECS 0x0004 97#define CFI_VEND_MITSUBISHI_SCS 0x0100 98#define CFI_VEND_MITSUBISHI_ECS 0x0101 99 100#define CFI_IFACE_X8 0x0000 101#define CFI_IFACE_X16 0x0001 102#define CFI_IFACE_X8X16 0x0002 103#define CFI_IFACE_X32 0x0003 104#define CFI_IFACE_X16X32 0x0005 105 106/* Standard Command Set (aka Basic Command Set) */ 107#define CFI_BCS_BLOCK_ERASE 0x20 108#define CFI_BCS_PROGRAM 0x40 109#define CFI_BCS_CLEAR_STATUS 0x50 110#define CFI_BCS_READ_STATUS 0x70 111#define CFI_BCS_ERASE_SUSPEND 0xb0 112#define CFI_BCS_ERASE_RESUME 0xd0 /* Equals CONFIRM */ 113#define CFI_BCS_CONFIRM 0xd0 114#define CFI_BCS_BUF_PROG_SETUP 0xe8 115#define CFI_BCS_READ_ARRAY 0xff 116 117/* Intel commands. */ 118#define CFI_INTEL_LB 0x01 /* Lock Block */ 119#define CFI_INTEL_LBS 0x60 /* Lock Block Setup */ 120#define CFI_INTEL_READ_ID 0x90 /* Read Identifier */ 121#define CFI_INTEL_PP_SETUP 0xc0 /* Protection Program Setup */ 122#define CFI_INTEL_UB 0xd0 /* Unlock Block */ 123 124/* NB: these are addresses for 16-bit accesses */ 125#define CFI_INTEL_PLR 0x80 /* Protection Lock Register */ 126#define CFI_INTEL_PR(n) (0x81+(n)) /* Protection Register */ 127 128/* Status register definitions */ 129#define CFI_INTEL_STATUS_WSMS 0x0080 /* Write Machine Status */ 130#define CFI_INTEL_STATUS_ESS 0x0040 /* Erase Suspend Status */ 131#define CFI_INTEL_STATUS_ECLBS 0x0020 /* Erase and Clear Lock-Bit Status */ 132#define CFI_INTEL_STATUS_PSLBS 0x0010 /* Program and Set Lock-Bit Status */ 133#define CFI_INTEL_STATUS_VPENS 0x0008 /* Programming Voltage Status */ 134#define CFI_INTEL_STATUS_PSS 0x0004 /* Program Suspend Status */ 135#define CFI_INTEL_STATUS_DPS 0x0002 /* Device Protect Status */ 136#define CFI_INTEL_STATUS_RSVD 0x0001 /* reserved */ 137 138/* eXtended Status register definitions */ 139#define CFI_INTEL_XSTATUS_WBS 0x8000 /* Write Buffer Status */ 140#define CFI_INTEL_XSTATUS_RSVD 0x7f00 /* reserved */ 141 142/* AMD commands. */ 143#define CFI_AMD_BLOCK_ERASE 0x30 144#define CFI_AMD_UNLOCK_ACK 0x55 145#define CFI_AMD_ERASE_SECTOR 0x80 146#define CFI_AMD_PROGRAM 0xa0 147#define CFI_AMD_UNLOCK 0xaa 148 149#define AMD_ADDR_START 0xaaa 150#define AMD_ADDR_ACK 0x555 151 152#endif /* _DEV_CFI_REG_H_ */ 153