10SN/A/* 210269SN/A * Copyright (c) 2007 The DragonFly Project. All rights reserved. 30SN/A * 40SN/A * This code is derived from software contributed to The DragonFly Project 50SN/A * by Sepherosa Ziehau <sepherosa@gmail.com> 60SN/A * 72362SN/A * Redistribution and use in source and binary forms, with or without 80SN/A * modification, are permitted provided that the following conditions 92362SN/A * are met: 100SN/A * 110SN/A * 1. Redistributions of source code must retain the above copyright 120SN/A * notice, this list of conditions and the following disclaimer. 130SN/A * 2. Redistributions in binary form must reproduce the above copyright 140SN/A * notice, this list of conditions and the following disclaimer in 150SN/A * the documentation and/or other materials provided with the 160SN/A * distribution. 170SN/A * 3. Neither the name of The DragonFly Project nor the names of its 180SN/A * contributors may be used to endorse or promote products derived 190SN/A * from this software without specific, prior written permission. 200SN/A * 212362SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 222362SN/A * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 232362SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 240SN/A * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 250SN/A * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 260SN/A * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 270SN/A * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 280SN/A * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 290SN/A * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 300SN/A * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 310SN/A * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 320SN/A * SUCH DAMAGE. 330SN/A * 340SN/A * $DragonFly: src/sys/dev/netif/bwi/if_bwivar.h,v 1.14 2008/02/15 11:15:38 sephe Exp $ 350SN/A * $FreeBSD$ 360SN/A */ 370SN/A 380SN/A#ifndef _IF_BWIVAR_H 390SN/A#define _IF_BWIVAR_H 400SN/A 410SN/A#define BWI_ALIGN 0x1000 420SN/A#define BWI_RING_ALIGN BWI_ALIGN 430SN/A#define BWI_BUS_SPACE_MAXADDR 0x3fffffff 440SN/A 450SN/A#define BWI_TX_NRING 6 460SN/A#define BWI_TXRX_NRING 6 470SN/A#define BWI_TX_NDESC 128 480SN/A#define BWI_RX_NDESC 64 490SN/A#define BWI_TXSTATS_NDESC 64 500SN/A#define BWI_TX_NSPRDESC 2 510SN/A#define BWI_TX_DATA_RING 1 520SN/A 530SN/A/* XXX Onoe/Sample/AMRR probably need different configuration */ 540SN/A#define BWI_SHRETRY 7 550SN/A#define BWI_LGRETRY 4 560SN/A#define BWI_SHRETRY_FB 3 570SN/A#define BWI_LGRETRY_FB 2 580SN/A 590SN/A#define BWI_LED_EVENT_NONE -1 600SN/A#define BWI_LED_EVENT_POLL 0 610SN/A#define BWI_LED_EVENT_TX 1 620SN/A#define BWI_LED_EVENT_RX 2 630SN/A#define BWI_LED_SLOWDOWN(dur) (dur) = (((dur) * 3) / 2) 640SN/A 650SN/Aenum bwi_txpwrcb_type { 660SN/A BWI_TXPWR_INIT = 0, 670SN/A BWI_TXPWR_FORCE = 1, 680SN/A BWI_TXPWR_CALIB = 2 690SN/A}; 700SN/A 710SN/A#define BWI_NOISE_FLOOR -95 /* TODO: noise floor calc */ 720SN/A#define BWI_FRAME_MIN_LEN(hdr) \ 730SN/A ((hdr) + sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN) 740SN/A 750SN/A#define CSR_READ_4(sc, reg) \ 760SN/A bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 770SN/A#define CSR_READ_2(sc, reg) \ 780SN/A bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 790SN/A 800SN/A#define CSR_WRITE_4(sc, reg, val) \ 810SN/A bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 820SN/A#define CSR_WRITE_2(sc, reg, val) \ 830SN/A bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 840SN/A 850SN/A#define CSR_SETBITS_4(sc, reg, bits) \ 860SN/A CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits)) 870SN/A#define CSR_SETBITS_2(sc, reg, bits) \ 880SN/A CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits)) 890SN/A 900SN/A#define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \ 910SN/A CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits)) 920SN/A#define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \ 930SN/A CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits)) 940SN/A 950SN/A#define CSR_CLRBITS_4(sc, reg, bits) \ 960SN/A CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits)) 970SN/A#define CSR_CLRBITS_2(sc, reg, bits) \ 980SN/A CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits)) 990SN/A 1000SN/A#ifdef BWI_DEBUG 1010SN/A 1020SN/A#define DPRINTF(sc, dbg, fmt, ...) \ 1030SN/Ado { \ 1040SN/A if ((sc)->sc_debug & (dbg)) \ 1050SN/A device_printf((sc)->sc_dev, fmt, __VA_ARGS__); \ 1060SN/A} while (0) 1070SN/A 1080SN/A#define _DPRINTF(sc, dbg, fmt, ...) \ 1090SN/Ado { \ 1100SN/A if ((sc)->sc_debug & (dbg)) \ 1110SN/A printf(fmt, __VA_ARGS__); \ 1120SN/A} while (0) 1130SN/A 1140SN/A#else /* !BWI_DEBUG */ 1150SN/A 1160SN/A#define DPRINTF(sc, dbg, fmt, ...) ((void)0) 1170SN/A#define _DPRINTF(sc, dbg, fmt, ...) ((void)0) 1180SN/A 1190SN/A#endif /* BWI_DEBUG */ 1200SN/A 1210SN/Astruct bwi_desc32 { 1220SN/A /* Little endian */ 1230SN/A uint32_t ctrl; 1240SN/A uint32_t addr; /* BWI_DESC32_A_ */ 1250SN/A} __packed; 1260SN/A 1270SN/A#define BWI_DESC32_A_FUNC_TXRX 0x1 1280SN/A#define BWI_DESC32_A_FUNC_MASK __BITS(31, 30) 1290SN/A#define BWI_DESC32_A_ADDR_MASK __BITS(29, 0) 1300SN/A 1310SN/A#define BWI_DESC32_C_BUFLEN_MASK __BITS(12, 0) 1320SN/A#define BWI_DESC32_C_ADDRHI_MASK __BITS(17, 16) 1330SN/A#define BWI_DESC32_C_EOR __BIT(28) 1340SN/A#define BWI_DESC32_C_INTR __BIT(29) 1350SN/A#define BWI_DESC32_C_FRAME_END __BIT(30) 1360SN/A#define BWI_DESC32_C_FRAME_START __BIT(31) 1370SN/A 1380SN/Astruct bwi_desc64 { 1390SN/A /* Little endian */ 1400SN/A uint32_t ctrl0; 1410SN/A uint32_t ctrl1; 1420SN/A uint32_t addr_lo; 1430SN/A uint32_t addr_hi; 1440SN/A} __packed; 1450SN/A 1460SN/Astruct bwi_rxbuf_hdr { 1470SN/A /* Little endian */ 1480SN/A uint16_t rxh_buflen; /* exclude bwi_rxbuf_hdr */ 1490SN/A uint8_t rxh_pad1[2]; 1500SN/A uint16_t rxh_flags1; /* BWI_RXH_F1_ */ 1510SN/A uint8_t rxh_rssi; 1520SN/A uint8_t rxh_sq; 1530SN/A uint16_t rxh_phyinfo; /* BWI_RXH_PHYINFO_ */ 1540SN/A uint16_t rxh_flags3; /* BWI_RXH_F3_ */ 1550SN/A uint16_t rxh_flags2; /* BWI_RXH_F2_ */ 1560SN/A uint16_t rxh_tsf; 1570SN/A uint8_t rxh_pad3[14]; /* Padded to 30bytes */ 1580SN/A} __packed; 1590SN/A 1600SN/A#define BWI_RXH_F1_BCM2053_RSSI __BIT(14) 1610SN/A#define BWI_RXH_F1_SHPREAMBLE __BIT(7) 1620SN/A#define BWI_RXH_F1_OFDM __BIT(0) 1630SN/A 1640SN/A#define BWI_RXH_F2_TYPE2FRAME __BIT(2) 1650SN/A 1660SN/A#define BWI_RXH_F3_BCM2050_RSSI __BIT(10) 1670SN/A 1680SN/A#define BWI_RXH_PHYINFO_LNAGAIN __BITS(15, 14) 1690SN/A 1700SN/Astruct bwi_txbuf_hdr { 1710SN/A /* Little endian */ 1720SN/A uint32_t txh_mac_ctrl; /* BWI_TXH_MAC_C_ */ 1730SN/A uint8_t txh_fc[2]; 1740SN/A uint16_t txh_unknown1; 1750SN/A uint16_t txh_phy_ctrl; /* BWI_TXH_PHY_C_ */ 1760SN/A uint8_t txh_ivs[16]; 1770SN/A uint8_t txh_addr1[IEEE80211_ADDR_LEN]; 1780SN/A uint16_t txh_unknown2; 1790SN/A uint8_t txh_rts_fb_plcp[4]; 1800SN/A uint16_t txh_rts_fb_duration; 1810SN/A uint8_t txh_fb_plcp[4]; 1820SN/A uint16_t txh_fb_duration; 1830SN/A uint8_t txh_pad2[2]; 1840SN/A uint16_t txh_id; /* BWI_TXH_ID_ */ 1850SN/A uint16_t txh_unknown3; 1860SN/A uint8_t txh_rts_plcp[6]; 1870SN/A uint8_t txh_rts_fc[2]; 1880SN/A uint16_t txh_rts_duration; 1890SN/A uint8_t txh_rts_ra[IEEE80211_ADDR_LEN]; 1900SN/A uint8_t txh_rts_ta[IEEE80211_ADDR_LEN]; 1910SN/A uint8_t txh_pad3[2]; 1920SN/A uint8_t txh_plcp[6]; 1930SN/A} __packed; 1940SN/A 1950SN/A#define BWI_TXH_ID_RING_MASK __BITS(15, 13) 1960SN/A#define BWI_TXH_ID_IDX_MASK __BITS(12, 0) 1970SN/A 1980SN/A#define BWI_TXH_PHY_C_OFDM __BIT(0) 1990SN/A#define BWI_TXH_PHY_C_SHPREAMBLE __BIT(4) 2000SN/A#define BWI_TXH_PHY_C_ANTMODE_MASK __BITS(9, 8) 20110269SN/A 20210269SN/A#define BWI_TXH_MAC_C_ACK __BIT(0) 20310269SN/A#define BWI_TXH_MAC_C_FIRST_FRAG __BIT(3) 2040SN/A#define BWI_TXH_MAC_C_HWSEQ __BIT(4) 2050SN/A#define BWI_TXH_MAC_C_FB_OFDM __BIT(8) 2060SN/A 2070SN/Astruct bwi_txstats { 2080SN/A /* Little endian */ 2090SN/A uint8_t txs_pad1[4]; 21010269SN/A uint16_t txs_id; 21110269SN/A uint8_t txs_flags; /* BWI_TXS_F_ */ 2120SN/A uint8_t txs_txcnt; /* BWI_TXS_TXCNT_ */ 2130SN/A uint8_t txs_pad2[2]; 2140SN/A uint16_t txs_seq; 2150SN/A uint16_t txs_unknown; 2160SN/A uint8_t txs_pad3[2]; /* Padded to 16bytes */ 2170SN/A} __packed; 2180SN/A 2190SN/A#define BWI_TXS_TXCNT_DATA __BITS(7, 4) 2200SN/A 2210SN/A#define BWI_TXS_F_ACKED __BIT(0) 22210269SN/A#define BWI_TXS_F_PENDING __BIT(5) 2230SN/A 22410269SN/Astruct bwi_ring_data { 2250SN/A uint32_t rdata_txrx_ctrl; 2260SN/A bus_dmamap_t rdata_dmap; 2270SN/A bus_addr_t rdata_paddr; 2280SN/A void *rdata_desc; 2290SN/A}; 2300SN/A 23110269SN/Astruct bwi_txbuf { 23210269SN/A struct mbuf *tb_mbuf; 2330SN/A bus_dmamap_t tb_dmap; 2340SN/A 2350SN/A struct ieee80211_node *tb_ni; 2360SN/A int tb_rate[2]; 2370SN/A}; 2380SN/A 2390SN/Astruct bwi_txbuf_data { 2400SN/A struct bwi_txbuf tbd_buf[BWI_TX_NDESC]; 2410SN/A int tbd_used; 2420SN/A int tbd_idx; 2430SN/A}; 2440SN/A 2450SN/Astruct bwi_rxbuf { 2460SN/A struct mbuf *rb_mbuf; 2470SN/A bus_addr_t rb_paddr; 2480SN/A bus_dmamap_t rb_dmap; 2490SN/A}; 2500SN/A 2510SN/Astruct bwi_rxbuf_data { 2520SN/A struct bwi_rxbuf rbd_buf[BWI_RX_NDESC]; 2530SN/A bus_dmamap_t rbd_tmp_dmap; 2540SN/A int rbd_idx; 2550SN/A}; 2560SN/A 2570SN/Astruct bwi_txstats_data { 2580SN/A bus_dma_tag_t stats_ring_dtag; 2590SN/A bus_dmamap_t stats_ring_dmap; 2600SN/A bus_addr_t stats_ring_paddr; 26110269SN/A void *stats_ring; 26210269SN/A 2630SN/A bus_dma_tag_t stats_dtag; 2640SN/A bus_dmamap_t stats_dmap; 2650SN/A bus_addr_t stats_paddr; 2660SN/A struct bwi_txstats *stats; 2670SN/A 2680SN/A uint32_t stats_ctrl_base; 2690SN/A int stats_idx; 2700SN/A}; 2710SN/A 2720SN/Astruct bwi_fwhdr { 2730SN/A /* Big endian */ 2740SN/A uint8_t fw_type; /* BWI_FW_T_ */ 2750SN/A uint8_t fw_gen; /* BWI_FW_GEN */ 2760SN/A uint8_t fw_pad[2]; 2770SN/A uint32_t fw_size; 2780SN/A#define fw_iv_cnt fw_size 2790SN/A} __packed; 2800SN/A 2810SN/A#define BWI_FWHDR_SZ sizeof(struct bwi_fwhdr) 2820SN/A 2830SN/A#define BWI_FW_T_UCODE 'u' 2840SN/A#define BWI_FW_T_PCM 'p' 2850SN/A#define BWI_FW_T_IV 'i' 2860SN/A 2870SN/A#define BWI_FW_GEN_1 1 2880SN/A 2890SN/A#define BWI_FW_VERSION3 3 2900SN/A#define BWI_FW_VERSION4 4 2910SN/A#define BWI_FW_VERSION3_REVMAX 0x128 2920SN/A 2930SN/A#define BWI_FW_PATH "bwi_v%d_" 2940SN/A#define BWI_FW_STUB_PATH BWI_FW_PATH "ucode" 2950SN/A#define BWI_FW_UCODE_PATH BWI_FW_PATH "ucode%d" 2960SN/A#define BWI_FW_PCM_PATH BWI_FW_PATH "pcm%d" 2970SN/A#define BWI_FW_IV_PATH BWI_FW_PATH "b0g0initvals%d" 2980SN/A#define BWI_FW_IV_EXT_PATH BWI_FW_PATH "b0g0bsinitvals%d" 2990SN/A 3000SN/Astruct bwi_fw_iv { 301 /* Big endian */ 302 uint16_t iv_ofs; 303 union { 304 uint32_t val32; 305 uint16_t val16; 306 } iv_val; 307} __packed; 308 309#define BWI_FW_IV_OFS_MASK __BITS(14, 0) 310#define BWI_FW_IV_IS_32BIT __BIT(15) 311 312struct bwi_led { 313 uint8_t l_flags; /* BWI_LED_F_ */ 314 uint8_t l_act; /* BWI_LED_ACT_ */ 315 uint8_t l_mask; 316}; 317 318#define BWI_LED_F_ACTLOW 0x1 319#define BWI_LED_F_BLINK 0x2 320#define BWI_LED_F_POLLABLE 0x4 321#define BWI_LED_F_SLOW 0x8 322 323enum bwi_clock_mode { 324 BWI_CLOCK_MODE_SLOW, 325 BWI_CLOCK_MODE_FAST, 326 BWI_CLOCK_MODE_DYN 327}; 328 329struct bwi_regwin { 330 uint32_t rw_flags; /* BWI_REGWIN_F_ */ 331 uint16_t rw_type; /* BWI_REGWIN_T_ */ 332 uint8_t rw_id; 333 uint8_t rw_rev; 334}; 335 336#define BWI_REGWIN_F_EXIST 0x1 337 338#define BWI_CREATE_REGWIN(rw, id, type, rev) \ 339do { \ 340 (rw)->rw_flags = BWI_REGWIN_F_EXIST; \ 341 (rw)->rw_type = (type); \ 342 (rw)->rw_id = (id); \ 343 (rw)->rw_rev = (rev); \ 344} while (0) 345 346#define BWI_REGWIN_EXIST(rw) ((rw)->rw_flags & BWI_REGWIN_F_EXIST) 347#define BWI_GPIO_REGWIN(sc) \ 348 (BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ? \ 349 &(sc)->sc_com_regwin : &(sc)->sc_bus_regwin) 350 351struct bwi_mac; 352 353struct bwi_phy { 354 enum ieee80211_phymode phy_mode; 355 int phy_rev; 356 int phy_version; 357 358 uint32_t phy_flags; /* BWI_PHY_F_ */ 359 uint16_t phy_tbl_ctrl; 360 uint16_t phy_tbl_data_lo; 361 uint16_t phy_tbl_data_hi; 362 363 void (*phy_init)(struct bwi_mac *); 364}; 365 366#define BWI_PHY_F_CALIBRATED 0x1 367#define BWI_PHY_F_LINKED 0x2 368#define BWI_CLEAR_PHY_FLAGS (BWI_PHY_F_CALIBRATED) 369 370/* TX power control */ 371struct bwi_tpctl { 372 uint16_t bbp_atten; /* BBP attenuation: 4bits */ 373 uint16_t rf_atten; /* RF attenuation */ 374 uint16_t tp_ctrl1; /* ??: 3bits */ 375 uint16_t tp_ctrl2; /* ??: 4bits */ 376}; 377 378#define BWI_RF_ATTEN_FACTOR 4 379#define BWI_RF_ATTEN_MAX0 9 380#define BWI_RF_ATTEN_MAX1 31 381#define BWI_BBP_ATTEN_MAX 11 382#define BWI_TPCTL1_MAX 7 383 384struct bwi_rf_lo { 385 int8_t ctrl_lo; 386 int8_t ctrl_hi; 387}; 388 389struct bwi_rf { 390 uint16_t rf_type; /* BWI_RF_T_ */ 391 uint16_t rf_manu; 392 int rf_rev; 393 394 uint32_t rf_flags; /* BWI_RF_F_ */ 395 396#define BWI_RFLO_MAX 56 397 struct bwi_rf_lo rf_lo[BWI_RFLO_MAX]; 398 uint8_t rf_lo_used[8]; 399 400#define BWI_INVALID_NRSSI -1000 401 int16_t rf_nrssi[2]; /* Narrow RSSI */ 402 int32_t rf_nrssi_slope; 403 404#define BWI_NRSSI_TBLSZ 64 405 int8_t rf_nrssi_table[BWI_NRSSI_TBLSZ]; 406 407 uint16_t rf_lo_gain; /* loopback gain */ 408 uint16_t rf_rx_gain; /* TRSW RX gain */ 409 410 uint16_t rf_calib; /* RF calibration value */ 411 u_int rf_curchan; /* current channel */ 412 413 uint16_t rf_ctrl_rd; 414 int rf_ctrl_adj; 415 void (*rf_off)(struct bwi_mac *); 416 void (*rf_on)(struct bwi_mac *); 417 418 void (*rf_set_nrssi_thr)(struct bwi_mac *); 419 void (*rf_calc_nrssi_slope)(struct bwi_mac *); 420 int (*rf_calc_rssi) 421 (struct bwi_mac *, 422 const struct bwi_rxbuf_hdr *); 423 int (*rf_calc_noise)(struct bwi_mac *); 424 425 void (*rf_lo_update)(struct bwi_mac *); 426 427#define BWI_TSSI_MAX 64 428 int8_t rf_txpower_map0[BWI_TSSI_MAX]; 429 /* Indexed by TSSI */ 430 int rf_idle_tssi0; 431 432 int8_t rf_txpower_map[BWI_TSSI_MAX]; 433 int rf_idle_tssi; 434 435 int rf_base_tssi; 436 437 int rf_txpower_max; /* dBm */ 438 439 int rf_ant_mode; /* BWI_ANT_MODE_ */ 440}; 441 442#define BWI_RF_F_INITED 0x1 443#define BWI_RF_F_ON 0x2 444#define BWI_RF_CLEAR_FLAGS (BWI_RF_F_INITED) 445 446#define BWI_ANT_MODE_0 0 447#define BWI_ANT_MODE_1 1 448#define BWI_ANT_MODE_UNKN 2 449#define BWI_ANT_MODE_AUTO 3 450 451struct bwi_softc; 452struct firmware; 453 454struct bwi_mac { 455 struct bwi_regwin mac_regwin; /* MUST be first field */ 456#define mac_rw_flags mac_regwin.rw_flags 457#define mac_type mac_regwin.rw_type 458#define mac_id mac_regwin.rw_id 459#define mac_rev mac_regwin.rw_rev 460 461 struct bwi_softc *mac_sc; 462 463 struct bwi_phy mac_phy; /* PHY I/F */ 464 struct bwi_rf mac_rf; /* RF I/F */ 465 466 struct bwi_tpctl mac_tpctl; /* TX power control */ 467 uint32_t mac_flags; /* BWI_MAC_F_ */ 468 469 const struct firmware *mac_stub; 470 const struct firmware *mac_ucode; 471 const struct firmware *mac_pcm; 472 const struct firmware *mac_iv; 473 const struct firmware *mac_iv_ext; 474}; 475 476#define BWI_MAC_F_BSWAP 0x1 477#define BWI_MAC_F_TPCTL_INITED 0x2 478#define BWI_MAC_F_HAS_TXSTATS 0x4 479#define BWI_MAC_F_INITED 0x8 480#define BWI_MAC_F_ENABLED 0x10 481#define BWI_MAC_F_LOCKED 0x20 /* for debug */ 482#define BWI_MAC_F_TPCTL_ERROR 0x40 483#define BWI_MAC_F_PHYE_RESET 0x80 484 485#define BWI_CREATE_MAC(mac, sc, id, rev) \ 486do { \ 487 BWI_CREATE_REGWIN(&(mac)->mac_regwin, \ 488 (id), \ 489 BWI_REGWIN_T_MAC, \ 490 (rev)); \ 491 (mac)->mac_sc = (sc); \ 492} while (0) 493 494#define BWI_MAC_MAX 2 495#define BWI_LED_MAX 4 496 497enum bwi_bus_space { 498 BWI_BUS_SPACE_30BIT = 1, 499 BWI_BUS_SPACE_32BIT, 500 BWI_BUS_SPACE_64BIT 501}; 502 503#define BWI_TX_RADIOTAP_PRESENT \ 504 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 505 (1 << IEEE80211_RADIOTAP_RATE) | \ 506 (1 << IEEE80211_RADIOTAP_CHANNEL)) 507 508struct bwi_tx_radiotap_hdr { 509 struct ieee80211_radiotap_header wt_ihdr; 510 uint8_t wt_flags; 511 uint8_t wt_rate; 512 uint16_t wt_chan_freq; 513 uint16_t wt_chan_flags; 514}; 515 516#define BWI_RX_RADIOTAP_PRESENT \ 517 ((1 << IEEE80211_RADIOTAP_TSFT) | \ 518 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 519 (1 << IEEE80211_RADIOTAP_RATE) | \ 520 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 521 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 522 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) 523 524struct bwi_rx_radiotap_hdr { 525 struct ieee80211_radiotap_header wr_ihdr; 526 uint64_t wr_tsf; 527 uint8_t wr_flags; 528 uint8_t wr_rate; 529 uint16_t wr_chan_freq; 530 uint16_t wr_chan_flags; 531 int8_t wr_antsignal; 532 int8_t wr_antnoise; 533 /* TODO: sq */ 534}; 535 536struct bwi_vap { 537 struct ieee80211vap bv_vap; 538 int (*bv_newstate)(struct ieee80211vap *, 539 enum ieee80211_state, int); 540}; 541#define BWI_VAP(vap) ((struct bwi_vap *)(vap)) 542 543struct bwi_softc { 544 struct ifnet *sc_ifp; 545 uint32_t sc_flags; /* BWI_F_ */ 546 device_t sc_dev; 547 struct mtx sc_mtx; 548 int sc_invalid; 549 550 uint32_t sc_cap; /* BWI_CAP_ */ 551 uint16_t sc_bbp_id; /* BWI_BBPID_ */ 552 uint8_t sc_bbp_rev; 553 uint8_t sc_bbp_pkg; 554 555 uint8_t sc_pci_revid; 556 uint16_t sc_pci_did; 557 uint16_t sc_pci_subvid; 558 uint16_t sc_pci_subdid; 559 560 uint16_t sc_card_flags; /* BWI_CARD_F_ */ 561 uint16_t sc_pwron_delay; 562 int sc_locale; 563 564 int sc_irq_rid; 565 struct resource *sc_irq_res; 566 void *sc_irq_handle; 567 568 int sc_mem_rid; 569 struct resource *sc_mem_res; 570 bus_space_tag_t sc_mem_bt; 571 bus_space_handle_t sc_mem_bh; 572 573 struct callout sc_calib_ch; 574 struct callout sc_watchdog_timer; 575 576 struct bwi_regwin *sc_cur_regwin; 577 struct bwi_regwin sc_com_regwin; 578 struct bwi_regwin sc_bus_regwin; 579 580 int sc_nmac; 581 struct bwi_mac sc_mac[BWI_MAC_MAX]; 582 583 int sc_rx_rate; 584 int sc_tx_rate; 585 enum bwi_txpwrcb_type sc_txpwrcb_type; 586 587 int sc_led_blinking; 588 int sc_led_ticks; 589 struct bwi_led *sc_blink_led; 590 struct callout sc_led_blink_ch; 591 int sc_led_blink_offdur; 592 struct bwi_led sc_leds[BWI_LED_MAX]; 593 594 enum bwi_bus_space sc_bus_space; 595 bus_dma_tag_t sc_parent_dtag; 596 597 bus_dma_tag_t sc_buf_dtag; 598 struct bwi_txbuf_data sc_tx_bdata[BWI_TX_NRING]; 599 struct bwi_rxbuf_data sc_rx_bdata; 600 601 bus_dma_tag_t sc_txring_dtag; 602 struct bwi_ring_data sc_tx_rdata[BWI_TX_NRING]; 603 bus_dma_tag_t sc_rxring_dtag; 604 struct bwi_ring_data sc_rx_rdata; 605 606 struct bwi_txstats_data *sc_txstats; 607 608 int sc_tx_timer; 609 const struct ieee80211_rate_table *sc_rates; 610 611 struct bwi_tx_radiotap_hdr sc_tx_th; 612 struct bwi_rx_radiotap_hdr sc_rx_th; 613 614 struct taskqueue *sc_tq; 615 struct task sc_restart_task; 616 617 int (*sc_init_tx_ring)(struct bwi_softc *, int); 618 void (*sc_free_tx_ring)(struct bwi_softc *, int); 619 620 int (*sc_init_rx_ring)(struct bwi_softc *); 621 void (*sc_free_rx_ring)(struct bwi_softc *); 622 623 int (*sc_init_txstats)(struct bwi_softc *); 624 void (*sc_free_txstats)(struct bwi_softc *); 625 626 void (*sc_setup_rxdesc) 627 (struct bwi_softc *, int, bus_addr_t, int); 628 int (*sc_rxeof)(struct bwi_softc *); 629 630 void (*sc_setup_txdesc) 631 (struct bwi_softc *, struct bwi_ring_data *, 632 int, bus_addr_t, int); 633 void (*sc_start_tx) 634 (struct bwi_softc *, uint32_t, int); 635 636 void (*sc_txeof_status)(struct bwi_softc *); 637 638 /* Sysctl variables */ 639 int sc_fw_version; /* BWI_FW_VERSION[34] */ 640 int sc_dwell_time; /* milliseconds */ 641 int sc_led_idle; 642 int sc_led_blink; 643 int sc_txpwr_calib; 644 uint32_t sc_debug; /* BWI_DBG_ */ 645}; 646 647#define BWI_F_BUS_INITED 0x1 648#define BWI_F_PROMISC 0x2 649#define BWI_F_STOP 0x4 650 651#define BWI_DBG_MAC 0x00000001 652#define BWI_DBG_RF 0x00000002 653#define BWI_DBG_PHY 0x00000004 654#define BWI_DBG_MISC 0x00000008 655 656#define BWI_DBG_ATTACH 0x00000010 657#define BWI_DBG_INIT 0x00000020 658#define BWI_DBG_FIRMWARE 0x00000040 659#define BWI_DBG_80211 0x00000080 660#define BWI_DBG_TXPOWER 0x00000100 661#define BWI_DBG_INTR 0x00000200 662#define BWI_DBG_RX 0x00000400 663#define BWI_DBG_TX 0x00000800 664#define BWI_DBG_TXEOF 0x00001000 665#define BWI_DBG_LED 0x00002000 666 667#define BWI_LOCK_INIT(sc) \ 668 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->sc_dev), \ 669 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 670#define BWI_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) 671#define BWI_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 672#define BWI_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 673#define BWI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 674 675int bwi_attach(struct bwi_softc *); 676int bwi_detach(struct bwi_softc *); 677void bwi_suspend(struct bwi_softc *); 678void bwi_resume(struct bwi_softc *); 679int bwi_shutdown(struct bwi_softc *); 680void bwi_intr(void *); 681 682int bwi_bus_init(struct bwi_softc *, struct bwi_mac *mac); 683 684uint16_t bwi_read_sprom(struct bwi_softc *, uint16_t); 685int bwi_regwin_switch(struct bwi_softc *, struct bwi_regwin *, 686 struct bwi_regwin **); 687int bwi_regwin_is_enabled(struct bwi_softc *, struct bwi_regwin *); 688void bwi_regwin_enable(struct bwi_softc *, struct bwi_regwin *, 689 uint32_t); 690void bwi_regwin_disable(struct bwi_softc *, struct bwi_regwin *, 691 uint32_t); 692 693#define abs(a) __builtin_abs(a) 694 695/* XXX does not belong here */ 696struct ieee80211_ds_plcp_hdr { 697 uint8_t i_signal; 698 uint8_t i_service; 699 uint16_t i_length; 700 uint16_t i_crc; 701} __packed; 702 703#endif /* !_IF_BWIVAR_H */ 704