if_bm.c revision 226995
1/*- 2 * Copyright 2008 Nathan Whitehorn. All rights reserved. 3 * Copyright 2003 by Peter Grehan. All rights reserved. 4 * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * From: 30 * NetBSD: if_bm.c,v 1.9.2.1 2000/11/01 15:02:49 tv Exp 31 */ 32 33/* 34 * BMAC/BMAC+ Macio cell 10/100 ethernet driver 35 * The low-cost, low-feature Apple variant of the Sun HME 36 */ 37 38#include <sys/cdefs.h> 39__FBSDID("$FreeBSD: head/sys/dev/bm/if_bm.c 226995 2011-11-01 16:13:59Z marius $"); 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/sockio.h> 44#include <sys/endian.h> 45#include <sys/mbuf.h> 46#include <sys/module.h> 47#include <sys/malloc.h> 48#include <sys/kernel.h> 49#include <sys/socket.h> 50 51#include <net/bpf.h> 52#include <net/if.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58 59#include <machine/pio.h> 60#include <machine/bus.h> 61#include <machine/resource.h> 62#include <sys/bus.h> 63#include <sys/rman.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/mii_bitbang.h> 67#include <dev/mii/miivar.h> 68 69#include <dev/ofw/ofw_bus.h> 70#include <dev/ofw/openfirm.h> 71#include <machine/dbdma.h> 72 73MODULE_DEPEND(bm, ether, 1, 1, 1); 74MODULE_DEPEND(bm, miibus, 1, 1, 1); 75 76/* "controller miibus0" required. See GENERIC if you get errors here. */ 77#include "miibus_if.h" 78 79#include "if_bmreg.h" 80#include "if_bmvar.h" 81 82static int bm_probe (device_t); 83static int bm_attach (device_t); 84static int bm_detach (device_t); 85static int bm_shutdown (device_t); 86 87static void bm_start (struct ifnet *); 88static void bm_start_locked (struct ifnet *); 89static int bm_encap (struct bm_softc *sc, struct mbuf **m_head); 90static int bm_ioctl (struct ifnet *, u_long, caddr_t); 91static void bm_init (void *); 92static void bm_init_locked (struct bm_softc *sc); 93static void bm_chip_setup (struct bm_softc *sc); 94static void bm_stop (struct bm_softc *sc); 95static void bm_setladrf (struct bm_softc *sc); 96static void bm_dummypacket (struct bm_softc *sc); 97static void bm_txintr (void *xsc); 98static void bm_rxintr (void *xsc); 99 100static int bm_add_rxbuf (struct bm_softc *sc, int i); 101static int bm_add_rxbuf_dma (struct bm_softc *sc, int i); 102static void bm_enable_interrupts (struct bm_softc *sc); 103static void bm_disable_interrupts (struct bm_softc *sc); 104static void bm_tick (void *xsc); 105 106static int bm_ifmedia_upd (struct ifnet *); 107static void bm_ifmedia_sts (struct ifnet *, struct ifmediareq *); 108 109static int bm_miibus_readreg (device_t, int, int); 110static int bm_miibus_writereg (device_t, int, int, int); 111static void bm_miibus_statchg (device_t); 112 113/* 114 * MII bit-bang glue 115 */ 116static uint32_t bm_mii_bitbang_read(device_t); 117static void bm_mii_bitbang_write(device_t, uint32_t); 118 119static const struct mii_bitbang_ops bm_mii_bitbang_ops = { 120 bm_mii_bitbang_read, 121 bm_mii_bitbang_write, 122 { 123 BM_MII_DATAOUT, /* MII_BIT_MDO */ 124 BM_MII_DATAIN, /* MII_BIT_MDI */ 125 BM_MII_CLK, /* MII_BIT_MDC */ 126 BM_MII_OENABLE, /* MII_BIT_DIR_HOST_PHY */ 127 0, /* MII_BIT_DIR_PHY_HOST */ 128 } 129}; 130 131static device_method_t bm_methods[] = { 132 /* Device interface */ 133 DEVMETHOD(device_probe, bm_probe), 134 DEVMETHOD(device_attach, bm_attach), 135 DEVMETHOD(device_detach, bm_detach), 136 DEVMETHOD(device_shutdown, bm_shutdown), 137 138 /* bus interface, for miibus */ 139 DEVMETHOD(bus_print_child, bus_generic_print_child), 140 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 141 142 /* MII interface */ 143 DEVMETHOD(miibus_readreg, bm_miibus_readreg), 144 DEVMETHOD(miibus_writereg, bm_miibus_writereg), 145 DEVMETHOD(miibus_statchg, bm_miibus_statchg), 146 { 0, 0 } 147}; 148 149static driver_t bm_macio_driver = { 150 "bm", 151 bm_methods, 152 sizeof(struct bm_softc) 153}; 154 155static devclass_t bm_devclass; 156 157DRIVER_MODULE(bm, macio, bm_macio_driver, bm_devclass, 0, 0); 158DRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0); 159 160/* 161 * MII internal routines 162 */ 163 164/* 165 * Write the MII serial port for the MII bit-bang module. 166 */ 167static void 168bm_mii_bitbang_write(device_t dev, uint32_t val) 169{ 170 struct bm_softc *sc; 171 172 sc = device_get_softc(dev); 173 174 CSR_WRITE_2(sc, BM_MII_CSR, val); 175 CSR_BARRIER(sc, BM_MII_CSR, 2, 176 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 177} 178 179/* 180 * Read the MII serial port for the MII bit-bang module. 181 */ 182static uint32_t 183bm_mii_bitbang_read(device_t dev) 184{ 185 struct bm_softc *sc; 186 uint32_t reg; 187 188 sc = device_get_softc(dev); 189 190 reg = CSR_READ_2(sc, BM_MII_CSR); 191 CSR_BARRIER(sc, BM_MII_CSR, 2, 192 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 193 194 return (reg); 195} 196 197/* 198 * MII bus i/f 199 */ 200static int 201bm_miibus_readreg(device_t dev, int phy, int reg) 202{ 203 204 return (mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg)); 205} 206 207static int 208bm_miibus_writereg(device_t dev, int phy, int reg, int data) 209{ 210 211 mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg); 212 213 return (0); 214} 215 216static void 217bm_miibus_statchg(device_t dev) 218{ 219 struct bm_softc *sc = device_get_softc(dev); 220 uint16_t reg; 221 int new_duplex; 222 223 reg = CSR_READ_2(sc, BM_TX_CONFIG); 224 new_duplex = IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX; 225 226 if (new_duplex != sc->sc_duplex) { 227 /* Turn off TX MAC while we fiddle its settings */ 228 reg &= ~BM_ENABLE; 229 230 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 231 while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE) 232 DELAY(10); 233 } 234 235 if (new_duplex && !sc->sc_duplex) 236 reg |= BM_TX_IGNORECOLL | BM_TX_FULLDPX; 237 else if (!new_duplex && sc->sc_duplex) 238 reg &= ~(BM_TX_IGNORECOLL | BM_TX_FULLDPX); 239 240 if (new_duplex != sc->sc_duplex) { 241 /* Turn TX MAC back on */ 242 reg |= BM_ENABLE; 243 244 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 245 sc->sc_duplex = new_duplex; 246 } 247} 248 249/* 250 * ifmedia/mii callbacks 251 */ 252static int 253bm_ifmedia_upd(struct ifnet *ifp) 254{ 255 struct bm_softc *sc = ifp->if_softc; 256 int error; 257 258 BM_LOCK(sc); 259 error = mii_mediachg(sc->sc_mii); 260 BM_UNLOCK(sc); 261 return (error); 262} 263 264static void 265bm_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifm) 266{ 267 struct bm_softc *sc = ifp->if_softc; 268 269 BM_LOCK(sc); 270 mii_pollstat(sc->sc_mii); 271 ifm->ifm_active = sc->sc_mii->mii_media_active; 272 ifm->ifm_status = sc->sc_mii->mii_media_status; 273 BM_UNLOCK(sc); 274} 275 276/* 277 * Macio probe/attach 278 */ 279static int 280bm_probe(device_t dev) 281{ 282 const char *dname = ofw_bus_get_name(dev); 283 const char *dcompat = ofw_bus_get_compat(dev); 284 285 /* 286 * BMAC+ cells have a name of "ethernet" and 287 * a compatible property of "bmac+" 288 */ 289 if (strcmp(dname, "bmac") == 0) { 290 device_set_desc(dev, "Apple BMAC Ethernet Adaptor"); 291 } else if (strcmp(dcompat, "bmac+") == 0) { 292 device_set_desc(dev, "Apple BMAC+ Ethernet Adaptor"); 293 } else 294 return (ENXIO); 295 296 return (0); 297} 298 299static int 300bm_attach(device_t dev) 301{ 302 phandle_t node; 303 u_char *eaddr; 304 struct ifnet *ifp; 305 int error, cellid, i; 306 struct bm_txsoft *txs; 307 struct bm_softc *sc = device_get_softc(dev); 308 309 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 310 ifp->if_softc = sc; 311 sc->sc_dev = dev; 312 sc->sc_duplex = ~IFM_FDX; 313 314 error = 0; 315 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 316 MTX_DEF); 317 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 318 319 /* Check for an improved version of Paddington */ 320 sc->sc_streaming = 0; 321 cellid = -1; 322 node = ofw_bus_get_node(dev); 323 324 OF_getprop(node, "cell-id", &cellid, sizeof(cellid)); 325 if (cellid >= 0xc4) 326 sc->sc_streaming = 1; 327 328 sc->sc_memrid = 0; 329 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 330 &sc->sc_memrid, RF_ACTIVE); 331 if (sc->sc_memr == NULL) { 332 device_printf(dev, "Could not alloc chip registers!\n"); 333 return (ENXIO); 334 } 335 336 sc->sc_txdmarid = BM_TXDMA_REGISTERS; 337 sc->sc_rxdmarid = BM_RXDMA_REGISTERS; 338 339 sc->sc_txdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 340 &sc->sc_txdmarid, RF_ACTIVE); 341 sc->sc_rxdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 342 &sc->sc_rxdmarid, RF_ACTIVE); 343 344 if (sc->sc_txdmar == NULL || sc->sc_rxdmar == NULL) { 345 device_printf(dev, "Could not map DBDMA registers!\n"); 346 return (ENXIO); 347 } 348 349 error = dbdma_allocate_channel(sc->sc_txdmar, 0, bus_get_dma_tag(dev), 350 BM_MAX_DMA_COMMANDS, &sc->sc_txdma); 351 error += dbdma_allocate_channel(sc->sc_rxdmar, 0, bus_get_dma_tag(dev), 352 BM_MAX_DMA_COMMANDS, &sc->sc_rxdma); 353 354 if (error) { 355 device_printf(dev,"Could not allocate DBDMA channel!\n"); 356 return (ENXIO); 357 } 358 359 /* alloc DMA tags and buffers */ 360 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 361 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 362 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 363 NULL, &sc->sc_pdma_tag); 364 365 if (error) { 366 device_printf(dev,"Could not allocate DMA tag!\n"); 367 return (ENXIO); 368 } 369 370 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 371 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 372 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdma_tag); 373 374 if (error) { 375 device_printf(dev,"Could not allocate RX DMA channel!\n"); 376 return (ENXIO); 377 } 378 379 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 380 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * BM_NTXSEGS, BM_NTXSEGS, 381 MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdma_tag); 382 383 if (error) { 384 device_printf(dev,"Could not allocate TX DMA tag!\n"); 385 return (ENXIO); 386 } 387 388 /* init transmit descriptors */ 389 STAILQ_INIT(&sc->sc_txfreeq); 390 STAILQ_INIT(&sc->sc_txdirtyq); 391 392 /* create TX DMA maps */ 393 error = ENOMEM; 394 for (i = 0; i < BM_MAX_TX_PACKETS; i++) { 395 txs = &sc->sc_txsoft[i]; 396 txs->txs_mbuf = NULL; 397 error = bus_dmamap_create(sc->sc_tdma_tag, 0, &txs->txs_dmamap); 398 if (error) { 399 device_printf(sc->sc_dev, 400 "unable to create TX DMA map %d, error = %d\n", 401 i, error); 402 } 403 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 404 } 405 406 /* Create the receive buffer DMA maps. */ 407 for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 408 error = bus_dmamap_create(sc->sc_rdma_tag, 0, 409 &sc->sc_rxsoft[i].rxs_dmamap); 410 if (error) { 411 device_printf(sc->sc_dev, 412 "unable to create RX DMA map %d, error = %d\n", 413 i, error); 414 } 415 sc->sc_rxsoft[i].rxs_mbuf = NULL; 416 } 417 418 /* alloc interrupt */ 419 bm_disable_interrupts(sc); 420 421 sc->sc_txdmairqid = BM_TXDMA_INTERRUPT; 422 sc->sc_txdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 423 &sc->sc_txdmairqid, RF_ACTIVE); 424 425 if (error) { 426 device_printf(dev,"Could not allocate TX interrupt!\n"); 427 return (ENXIO); 428 } 429 430 bus_setup_intr(dev,sc->sc_txdmairq, 431 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_txintr, sc, 432 &sc->sc_txihtx); 433 434 sc->sc_rxdmairqid = BM_RXDMA_INTERRUPT; 435 sc->sc_rxdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 436 &sc->sc_rxdmairqid, RF_ACTIVE); 437 438 if (error) { 439 device_printf(dev,"Could not allocate RX interrupt!\n"); 440 return (ENXIO); 441 } 442 443 bus_setup_intr(dev,sc->sc_rxdmairq, 444 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_rxintr, sc, 445 &sc->sc_rxih); 446 447 /* 448 * Get the ethernet address from OpenFirmware 449 */ 450 eaddr = sc->sc_enaddr; 451 OF_getprop(node, "local-mac-address", eaddr, ETHER_ADDR_LEN); 452 453 /* 454 * Setup MII 455 * On Apple BMAC controllers, we end up in a weird state of 456 * partially-completed autonegotiation on boot. So we force 457 * autonegotation to try again. 458 */ 459 error = mii_attach(dev, &sc->sc_miibus, ifp, bm_ifmedia_upd, 460 bm_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 461 MIIF_FORCEANEG); 462 if (error != 0) { 463 device_printf(dev, "attaching PHYs failed\n"); 464 return (error); 465 } 466 467 /* reset the adapter */ 468 bm_chip_setup(sc); 469 470 sc->sc_mii = device_get_softc(sc->sc_miibus); 471 472 if_initname(ifp, device_get_name(sc->sc_dev), 473 device_get_unit(sc->sc_dev)); 474 ifp->if_mtu = ETHERMTU; 475 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 476 ifp->if_start = bm_start; 477 ifp->if_ioctl = bm_ioctl; 478 ifp->if_init = bm_init; 479 IFQ_SET_MAXLEN(&ifp->if_snd, BM_MAX_TX_PACKETS); 480 ifp->if_snd.ifq_drv_maxlen = BM_MAX_TX_PACKETS; 481 IFQ_SET_READY(&ifp->if_snd); 482 483 /* Attach the interface. */ 484 ether_ifattach(ifp, sc->sc_enaddr); 485 ifp->if_hwassist = 0; 486 487 return (0); 488} 489 490static int 491bm_detach(device_t dev) 492{ 493 struct bm_softc *sc = device_get_softc(dev); 494 495 BM_LOCK(sc); 496 bm_stop(sc); 497 BM_UNLOCK(sc); 498 499 callout_drain(&sc->sc_tick_ch); 500 ether_ifdetach(sc->sc_ifp); 501 bus_teardown_intr(dev, sc->sc_txdmairq, sc->sc_txihtx); 502 bus_teardown_intr(dev, sc->sc_rxdmairq, sc->sc_rxih); 503 504 dbdma_free_channel(sc->sc_txdma); 505 dbdma_free_channel(sc->sc_rxdma); 506 507 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr); 508 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_txdmarid, 509 sc->sc_txdmar); 510 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rxdmarid, 511 sc->sc_rxdmar); 512 513 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_txdmairqid, 514 sc->sc_txdmairq); 515 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rxdmairqid, 516 sc->sc_rxdmairq); 517 518 mtx_destroy(&sc->sc_mtx); 519 if_free(sc->sc_ifp); 520 521 return (0); 522} 523 524static int 525bm_shutdown(device_t dev) 526{ 527 struct bm_softc *sc; 528 529 sc = device_get_softc(dev); 530 531 BM_LOCK(sc); 532 bm_stop(sc); 533 BM_UNLOCK(sc); 534 535 return (0); 536} 537 538static void 539bm_dummypacket(struct bm_softc *sc) 540{ 541 struct mbuf *m; 542 struct ifnet *ifp; 543 544 ifp = sc->sc_ifp; 545 546 MGETHDR(m, M_DONTWAIT, MT_DATA); 547 548 if (m == NULL) 549 return; 550 551 bcopy(sc->sc_enaddr, 552 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 553 bcopy(sc->sc_enaddr, 554 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 555 mtod(m, struct ether_header *)->ether_type = htons(3); 556 mtod(m, unsigned char *)[14] = 0; 557 mtod(m, unsigned char *)[15] = 0; 558 mtod(m, unsigned char *)[16] = 0xE3; 559 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 560 IF_ENQUEUE(&ifp->if_snd, m); 561 bm_start_locked(ifp); 562} 563 564static void 565bm_rxintr(void *xsc) 566{ 567 struct bm_softc *sc = xsc; 568 struct ifnet *ifp = sc->sc_ifp; 569 struct mbuf *m; 570 int i, prev_stop, new_stop; 571 uint16_t status; 572 573 BM_LOCK(sc); 574 575 status = dbdma_get_chan_status(sc->sc_rxdma); 576 if (status & DBDMA_STATUS_DEAD) { 577 dbdma_reset(sc->sc_rxdma); 578 BM_UNLOCK(sc); 579 return; 580 } 581 if (!(status & DBDMA_STATUS_RUN)) { 582 device_printf(sc->sc_dev,"Bad RX Interrupt!\n"); 583 BM_UNLOCK(sc); 584 return; 585 } 586 587 prev_stop = sc->next_rxdma_slot - 1; 588 if (prev_stop < 0) 589 prev_stop = sc->rxdma_loop_slot - 1; 590 591 if (prev_stop < 0) { 592 BM_UNLOCK(sc); 593 return; 594 } 595 596 new_stop = -1; 597 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_POSTREAD); 598 599 for (i = sc->next_rxdma_slot; i < BM_MAX_RX_PACKETS; i++) { 600 if (i == sc->rxdma_loop_slot) 601 i = 0; 602 603 if (i == prev_stop) 604 break; 605 606 status = dbdma_get_cmd_status(sc->sc_rxdma, i); 607 608 if (status == 0) 609 break; 610 611 m = sc->sc_rxsoft[i].rxs_mbuf; 612 613 if (bm_add_rxbuf(sc, i)) { 614 ifp->if_ierrors++; 615 m = NULL; 616 continue; 617 } 618 619 if (m == NULL) 620 continue; 621 622 ifp->if_ipackets++; 623 m->m_pkthdr.rcvif = ifp; 624 m->m_len -= (dbdma_get_residuals(sc->sc_rxdma, i) + 2); 625 m->m_pkthdr.len = m->m_len; 626 627 /* Send up the stack */ 628 BM_UNLOCK(sc); 629 (*ifp->if_input)(ifp, m); 630 BM_LOCK(sc); 631 632 /* Clear all fields on this command */ 633 bm_add_rxbuf_dma(sc, i); 634 635 new_stop = i; 636 } 637 638 /* Change the last packet we processed to the ring buffer terminator, 639 * and restore a receive buffer to the old terminator */ 640 if (new_stop >= 0) { 641 dbdma_insert_stop(sc->sc_rxdma, new_stop); 642 bm_add_rxbuf_dma(sc, prev_stop); 643 if (i < sc->rxdma_loop_slot) 644 sc->next_rxdma_slot = i; 645 else 646 sc->next_rxdma_slot = 0; 647 } 648 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 649 650 dbdma_wake(sc->sc_rxdma); 651 652 BM_UNLOCK(sc); 653} 654 655static void 656bm_txintr(void *xsc) 657{ 658 struct bm_softc *sc = xsc; 659 struct ifnet *ifp = sc->sc_ifp; 660 struct bm_txsoft *txs; 661 int progress = 0; 662 663 BM_LOCK(sc); 664 665 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 666 if (!dbdma_get_cmd_status(sc->sc_txdma, txs->txs_lastdesc)) 667 break; 668 669 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 670 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 671 672 if (txs->txs_mbuf != NULL) { 673 m_freem(txs->txs_mbuf); 674 txs->txs_mbuf = NULL; 675 } 676 677 /* Set the first used TXDMA slot to the location of the 678 * STOP/NOP command associated with this packet. */ 679 680 sc->first_used_txdma_slot = txs->txs_stopdesc; 681 682 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 683 684 ifp->if_opackets++; 685 progress = 1; 686 } 687 688 if (progress) { 689 /* 690 * We freed some descriptors, so reset IFF_DRV_OACTIVE 691 * and restart. 692 */ 693 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 694 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 695 696 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 697 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 698 bm_start_locked(ifp); 699 } 700 701 BM_UNLOCK(sc); 702} 703 704static void 705bm_start(struct ifnet *ifp) 706{ 707 struct bm_softc *sc = ifp->if_softc; 708 709 BM_LOCK(sc); 710 bm_start_locked(ifp); 711 BM_UNLOCK(sc); 712} 713 714static void 715bm_start_locked(struct ifnet *ifp) 716{ 717 struct bm_softc *sc = ifp->if_softc; 718 struct mbuf *mb_head; 719 int prev_stop; 720 int txqueued = 0; 721 722 /* 723 * We lay out our DBDMA program in the following manner: 724 * OUTPUT_MORE 725 * ... 726 * OUTPUT_LAST (+ Interrupt) 727 * STOP 728 * 729 * To extend the channel, we append a new program, 730 * then replace STOP with NOP and wake the channel. 731 * If we stalled on the STOP already, the program proceeds, 732 * if not it will sail through the NOP. 733 */ 734 735 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 736 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 737 738 if (mb_head == NULL) 739 break; 740 741 prev_stop = sc->next_txdma_slot - 1; 742 743 if (bm_encap(sc, &mb_head)) { 744 /* Put the packet back and stop */ 745 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 746 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 747 break; 748 } 749 750 dbdma_insert_nop(sc->sc_txdma, prev_stop); 751 752 txqueued = 1; 753 754 BPF_MTAP(ifp, mb_head); 755 } 756 757 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 758 759 if (txqueued) { 760 dbdma_wake(sc->sc_txdma); 761 sc->sc_wdog_timer = 5; 762 } 763} 764 765static int 766bm_encap(struct bm_softc *sc, struct mbuf **m_head) 767{ 768 bus_dma_segment_t segs[BM_NTXSEGS]; 769 struct bm_txsoft *txs; 770 struct mbuf *m; 771 int nsegs = BM_NTXSEGS; 772 int error = 0; 773 uint8_t branch_type; 774 int i; 775 776 /* Limit the command size to the number of free DBDMA slots */ 777 778 if (sc->next_txdma_slot >= sc->first_used_txdma_slot) 779 nsegs = BM_MAX_DMA_COMMANDS - 2 - sc->next_txdma_slot + 780 sc->first_used_txdma_slot; /* -2 for branch and indexing */ 781 else 782 nsegs = sc->first_used_txdma_slot - sc->next_txdma_slot; 783 784 /* Remove one slot for the STOP/NOP terminator */ 785 nsegs--; 786 787 if (nsegs > BM_NTXSEGS) 788 nsegs = BM_NTXSEGS; 789 790 /* Get a work queue entry. */ 791 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 792 /* Ran out of descriptors. */ 793 return (ENOBUFS); 794 } 795 796 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, txs->txs_dmamap, 797 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 798 799 if (error == EFBIG) { 800 m = m_collapse(*m_head, M_DONTWAIT, nsegs); 801 if (m == NULL) { 802 m_freem(*m_head); 803 *m_head = NULL; 804 return (ENOBUFS); 805 } 806 *m_head = m; 807 808 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, 809 txs->txs_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 810 if (error != 0) { 811 m_freem(*m_head); 812 *m_head = NULL; 813 return (error); 814 } 815 } else if (error != 0) 816 return (error); 817 818 if (nsegs == 0) { 819 m_freem(*m_head); 820 *m_head = NULL; 821 return (EIO); 822 } 823 824 txs->txs_ndescs = nsegs; 825 txs->txs_firstdesc = sc->next_txdma_slot; 826 827 for (i = 0; i < nsegs; i++) { 828 /* Loop back to the beginning if this is our last slot */ 829 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) 830 branch_type = DBDMA_ALWAYS; 831 else 832 branch_type = DBDMA_NEVER; 833 834 if (i+1 == nsegs) 835 txs->txs_lastdesc = sc->next_txdma_slot; 836 837 dbdma_insert_command(sc->sc_txdma, sc->next_txdma_slot++, 838 (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE : DBDMA_OUTPUT_LAST, 839 0, segs[i].ds_addr, segs[i].ds_len, 840 (i + 1 < nsegs) ? DBDMA_NEVER : DBDMA_ALWAYS, 841 branch_type, DBDMA_NEVER, 0); 842 843 if (branch_type == DBDMA_ALWAYS) 844 sc->next_txdma_slot = 0; 845 } 846 847 /* We have a corner case where the STOP command is the last slot, 848 * but you can't branch in STOP commands. So add a NOP branch here 849 * and the STOP in slot 0. */ 850 851 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) { 852 dbdma_insert_branch(sc->sc_txdma, sc->next_txdma_slot, 0); 853 sc->next_txdma_slot = 0; 854 } 855 856 txs->txs_stopdesc = sc->next_txdma_slot; 857 dbdma_insert_stop(sc->sc_txdma, sc->next_txdma_slot++); 858 859 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 860 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 861 txs->txs_mbuf = *m_head; 862 863 return (0); 864} 865 866static int 867bm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 868{ 869 struct bm_softc *sc = ifp->if_softc; 870 struct ifreq *ifr = (struct ifreq *)data; 871 int error; 872 873 error = 0; 874 875 switch(cmd) { 876 case SIOCSIFFLAGS: 877 BM_LOCK(sc); 878 if ((ifp->if_flags & IFF_UP) != 0) { 879 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 880 ((ifp->if_flags ^ sc->sc_ifpflags) & 881 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 882 bm_setladrf(sc); 883 else 884 bm_init_locked(sc); 885 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 886 bm_stop(sc); 887 sc->sc_ifpflags = ifp->if_flags; 888 BM_UNLOCK(sc); 889 break; 890 case SIOCADDMULTI: 891 case SIOCDELMULTI: 892 BM_LOCK(sc); 893 bm_setladrf(sc); 894 BM_UNLOCK(sc); 895 case SIOCGIFMEDIA: 896 case SIOCSIFMEDIA: 897 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 898 break; 899 default: 900 error = ether_ioctl(ifp, cmd, data); 901 break; 902 } 903 904 return (error); 905} 906 907static void 908bm_setladrf(struct bm_softc *sc) 909{ 910 struct ifnet *ifp = sc->sc_ifp; 911 struct ifmultiaddr *inm; 912 uint16_t hash[4]; 913 uint16_t reg; 914 uint32_t crc; 915 916 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS; 917 918 /* Turn off RX MAC while we fiddle its settings */ 919 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 920 while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE) 921 DELAY(10); 922 923 if ((ifp->if_flags & IFF_PROMISC) != 0) { 924 reg |= BM_PROMISC; 925 926 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 927 928 DELAY(15); 929 930 reg = CSR_READ_2(sc, BM_RX_CONFIG); 931 reg |= BM_ENABLE; 932 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 933 return; 934 } 935 936 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 937 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 938 } else { 939 /* Clear the hash table. */ 940 memset(hash, 0, sizeof(hash)); 941 942 if_maddr_rlock(ifp); 943 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 944 if (inm->ifma_addr->sa_family != AF_LINK) 945 continue; 946 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 947 inm->ifma_addr), ETHER_ADDR_LEN); 948 949 /* We just want the 6 most significant bits */ 950 crc >>= 26; 951 952 /* Set the corresponding bit in the filter. */ 953 hash[crc >> 4] |= 1 << (crc & 0xf); 954 } 955 if_maddr_runlock(ifp); 956 } 957 958 /* Write out new hash table */ 959 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]); 960 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]); 961 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]); 962 CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]); 963 964 /* And turn the RX MAC back on, this time with the hash bit set */ 965 reg |= BM_HASH_FILTER_ENABLE; 966 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 967 968 while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE)) 969 DELAY(10); 970 971 reg = CSR_READ_2(sc, BM_RX_CONFIG); 972 reg |= BM_ENABLE; 973 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 974} 975 976static void 977bm_init(void *xsc) 978{ 979 struct bm_softc *sc = xsc; 980 981 BM_LOCK(sc); 982 bm_init_locked(sc); 983 BM_UNLOCK(sc); 984} 985 986static void 987bm_chip_setup(struct bm_softc *sc) 988{ 989 uint16_t reg; 990 uint16_t *eaddr_sect; 991 992 eaddr_sect = (uint16_t *)(sc->sc_enaddr); 993 dbdma_stop(sc->sc_txdma); 994 dbdma_stop(sc->sc_rxdma); 995 996 /* Reset chip */ 997 CSR_WRITE_2(sc, BM_RX_RESET, 0x0000); 998 CSR_WRITE_2(sc, BM_TX_RESET, 0x0001); 999 do { 1000 DELAY(10); 1001 reg = CSR_READ_2(sc, BM_TX_RESET); 1002 } while (reg & 0x0001); 1003 1004 /* Some random junk. OS X uses the system time. We use 1005 * the low 16 bits of the MAC address. */ 1006 CSR_WRITE_2(sc, BM_TX_RANDSEED, eaddr_sect[2]); 1007 1008 /* Enable transmit */ 1009 reg = CSR_READ_2(sc, BM_TX_IFC); 1010 reg |= BM_ENABLE; 1011 CSR_WRITE_2(sc, BM_TX_IFC, reg); 1012 1013 CSR_READ_2(sc, BM_TX_PEAKCNT); 1014} 1015 1016static void 1017bm_stop(struct bm_softc *sc) 1018{ 1019 struct bm_txsoft *txs; 1020 uint16_t reg; 1021 1022 /* Disable TX and RX MACs */ 1023 reg = CSR_READ_2(sc, BM_TX_CONFIG); 1024 reg &= ~BM_ENABLE; 1025 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1026 1027 reg = CSR_READ_2(sc, BM_RX_CONFIG); 1028 reg &= ~BM_ENABLE; 1029 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1030 1031 DELAY(100); 1032 1033 /* Stop DMA engine */ 1034 dbdma_stop(sc->sc_rxdma); 1035 dbdma_stop(sc->sc_txdma); 1036 sc->next_rxdma_slot = 0; 1037 sc->rxdma_loop_slot = 0; 1038 1039 /* Disable interrupts */ 1040 bm_disable_interrupts(sc); 1041 1042 /* Don't worry about pending transmits anymore */ 1043 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1044 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1045 if (txs->txs_ndescs != 0) { 1046 bus_dmamap_sync(sc->sc_tdma_tag, txs->txs_dmamap, 1047 BUS_DMASYNC_POSTWRITE); 1048 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 1049 if (txs->txs_mbuf != NULL) { 1050 m_freem(txs->txs_mbuf); 1051 txs->txs_mbuf = NULL; 1052 } 1053 } 1054 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1055 } 1056 1057 /* And we're down */ 1058 sc->sc_ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1059 sc->sc_wdog_timer = 0; 1060 callout_stop(&sc->sc_tick_ch); 1061} 1062 1063static void 1064bm_init_locked(struct bm_softc *sc) 1065{ 1066 uint16_t reg; 1067 uint16_t *eaddr_sect; 1068 struct bm_rxsoft *rxs; 1069 int i; 1070 1071 eaddr_sect = (uint16_t *)(sc->sc_enaddr); 1072 1073 /* Zero RX slot info and stop DMA */ 1074 dbdma_stop(sc->sc_rxdma); 1075 dbdma_stop(sc->sc_txdma); 1076 sc->next_rxdma_slot = 0; 1077 sc->rxdma_loop_slot = 0; 1078 1079 /* Initialize TX/RX DBDMA programs */ 1080 dbdma_insert_stop(sc->sc_rxdma, 0); 1081 dbdma_insert_stop(sc->sc_txdma, 0); 1082 dbdma_set_current_cmd(sc->sc_rxdma, 0); 1083 dbdma_set_current_cmd(sc->sc_txdma, 0); 1084 1085 sc->next_rxdma_slot = 0; 1086 sc->next_txdma_slot = 1; 1087 sc->first_used_txdma_slot = 0; 1088 1089 for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 1090 rxs = &sc->sc_rxsoft[i]; 1091 rxs->dbdma_slot = i; 1092 1093 if (rxs->rxs_mbuf == NULL) { 1094 bm_add_rxbuf(sc, i); 1095 1096 if (rxs->rxs_mbuf == NULL) { 1097 /* If we can't add anymore, mark the problem */ 1098 rxs->dbdma_slot = -1; 1099 break; 1100 } 1101 } 1102 1103 if (i > 0) 1104 bm_add_rxbuf_dma(sc, i); 1105 } 1106 1107 /* 1108 * Now terminate the RX ring buffer, and follow with the loop to 1109 * the beginning. 1110 */ 1111 dbdma_insert_stop(sc->sc_rxdma, i - 1); 1112 dbdma_insert_branch(sc->sc_rxdma, i, 0); 1113 sc->rxdma_loop_slot = i; 1114 1115 /* Now add in the first element of the RX DMA chain */ 1116 bm_add_rxbuf_dma(sc, 0); 1117 1118 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 1119 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 1120 1121 /* Zero collision counters */ 1122 CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1123 CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1124 CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1125 CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1126 1127 /* Zero receive counters */ 1128 CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1129 CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1130 CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1131 CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1132 CSR_WRITE_2(sc, BM_RXCV, 0); 1133 1134 /* Prime transmit */ 1135 CSR_WRITE_2(sc, BM_TX_THRESH, 0xff); 1136 1137 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0); 1138 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001); 1139 1140 /* Prime receive */ 1141 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0); 1142 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001); 1143 1144 /* Clear status reg */ 1145 CSR_READ_2(sc, BM_STATUS); 1146 1147 /* Zero hash filters */ 1148 CSR_WRITE_2(sc, BM_HASHTAB0, 0); 1149 CSR_WRITE_2(sc, BM_HASHTAB1, 0); 1150 CSR_WRITE_2(sc, BM_HASHTAB2, 0); 1151 CSR_WRITE_2(sc, BM_HASHTAB3, 0); 1152 1153 /* Write MAC address to chip */ 1154 CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]); 1155 CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]); 1156 CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]); 1157 1158 /* Final receive engine setup */ 1159 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS | BM_HASH_FILTER_ENABLE; 1160 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1161 1162 /* Now turn it all on! */ 1163 dbdma_reset(sc->sc_rxdma); 1164 dbdma_reset(sc->sc_txdma); 1165 1166 /* Enable RX and TX MACs. Setting the address filter has 1167 * the side effect of enabling the RX MAC. */ 1168 bm_setladrf(sc); 1169 1170 reg = CSR_READ_2(sc, BM_TX_CONFIG); 1171 reg |= BM_ENABLE; 1172 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1173 1174 /* 1175 * Enable interrupts, unwedge the controller with a dummy packet, 1176 * and nudge the DMA queue. 1177 */ 1178 bm_enable_interrupts(sc); 1179 bm_dummypacket(sc); 1180 dbdma_wake(sc->sc_rxdma); /* Nudge RXDMA */ 1181 1182 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING; 1183 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1184 sc->sc_ifpflags = sc->sc_ifp->if_flags; 1185 1186 /* Resync PHY and MAC states */ 1187 sc->sc_mii = device_get_softc(sc->sc_miibus); 1188 sc->sc_duplex = ~IFM_FDX; 1189 mii_mediachg(sc->sc_mii); 1190 1191 /* Start the one second timer. */ 1192 sc->sc_wdog_timer = 0; 1193 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1194} 1195 1196static void 1197bm_tick(void *arg) 1198{ 1199 struct bm_softc *sc = arg; 1200 1201 /* Read error counters */ 1202 sc->sc_ifp->if_collisions += CSR_READ_2(sc, BM_TX_NCCNT) + 1203 CSR_READ_2(sc, BM_TX_FCCNT) + CSR_READ_2(sc, BM_TX_EXCNT) + 1204 CSR_READ_2(sc, BM_TX_LTCNT); 1205 1206 sc->sc_ifp->if_ierrors += CSR_READ_2(sc, BM_RX_LECNT) + 1207 CSR_READ_2(sc, BM_RX_AECNT) + CSR_READ_2(sc, BM_RX_FECNT); 1208 1209 /* Zero collision counters */ 1210 CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1211 CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1212 CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1213 CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1214 1215 /* Zero receive counters */ 1216 CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1217 CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1218 CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1219 CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1220 CSR_WRITE_2(sc, BM_RXCV, 0); 1221 1222 /* Check for link changes and run watchdog */ 1223 mii_tick(sc->sc_mii); 1224 bm_miibus_statchg(sc->sc_dev); 1225 1226 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) { 1227 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1228 return; 1229 } 1230 1231 /* Problems */ 1232 device_printf(sc->sc_dev, "device timeout\n"); 1233 1234 bm_init_locked(sc); 1235} 1236 1237static int 1238bm_add_rxbuf(struct bm_softc *sc, int idx) 1239{ 1240 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1241 struct mbuf *m; 1242 bus_dma_segment_t segs[1]; 1243 int error, nsegs; 1244 1245 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1246 if (m == NULL) 1247 return (ENOBUFS); 1248 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1249 1250 if (rxs->rxs_mbuf != NULL) { 1251 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, 1252 BUS_DMASYNC_POSTREAD); 1253 bus_dmamap_unload(sc->sc_rdma_tag, rxs->rxs_dmamap); 1254 } 1255 1256 error = bus_dmamap_load_mbuf_sg(sc->sc_rdma_tag, rxs->rxs_dmamap, m, 1257 segs, &nsegs, BUS_DMA_NOWAIT); 1258 if (error != 0) { 1259 device_printf(sc->sc_dev, 1260 "cannot load RS DMA map %d, error = %d\n", idx, error); 1261 m_freem(m); 1262 return (error); 1263 } 1264 /* If nsegs is wrong then the stack is corrupt. */ 1265 KASSERT(nsegs == 1, 1266 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1267 rxs->rxs_mbuf = m; 1268 rxs->segment = segs[0]; 1269 1270 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 1271 1272 return (0); 1273} 1274 1275static int 1276bm_add_rxbuf_dma(struct bm_softc *sc, int idx) 1277{ 1278 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1279 1280 dbdma_insert_command(sc->sc_rxdma, idx, DBDMA_INPUT_LAST, 0, 1281 rxs->segment.ds_addr, rxs->segment.ds_len, DBDMA_ALWAYS, 1282 DBDMA_NEVER, DBDMA_NEVER, 0); 1283 1284 return (0); 1285} 1286 1287static void 1288bm_enable_interrupts(struct bm_softc *sc) 1289{ 1290 CSR_WRITE_2(sc, BM_INTR_DISABLE, 1291 (sc->sc_streaming) ? BM_INTR_NONE : BM_INTR_NORMAL); 1292} 1293 1294static void 1295bm_disable_interrupts(struct bm_softc *sc) 1296{ 1297 CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE); 1298} 1299