if_bm.c revision 179645
1/*- 2 * Copyright 2008 Nathan Whitehorn. All rights reserved. 3 * Copyright 2003 by Peter Grehan. All rights reserved. 4 * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * From: 30 * NetBSD: if_bm.c,v 1.9.2.1 2000/11/01 15:02:49 tv Exp 31 */ 32 33/* 34 * BMAC/BMAC+ Macio cell 10/100 ethernet driver 35 * The low-cost, low-feature Apple variant of the Sun HME 36 */ 37 38#include <sys/cdefs.h> 39__FBSDID("$FreeBSD: head/sys/dev/bm/if_bm.c 179645 2008-06-07 22:58:32Z marcel $"); 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/sockio.h> 44#include <sys/endian.h> 45#include <sys/mbuf.h> 46#include <sys/module.h> 47#include <sys/malloc.h> 48#include <sys/kernel.h> 49#include <sys/socket.h> 50 51#include <net/bpf.h> 52#include <net/if.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58 59#include <machine/pio.h> 60#include <machine/bus.h> 61#include <machine/resource.h> 62#include <sys/bus.h> 63#include <sys/rman.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67 68#include <dev/ofw/ofw_bus.h> 69#include <dev/ofw/openfirm.h> 70#include <machine/dbdma.h> 71 72MODULE_DEPEND(bm, ether, 1, 1, 1); 73MODULE_DEPEND(bm, miibus, 1, 1, 1); 74 75/* "controller miibus0" required. See GENERIC if you get errors here. */ 76#include "miibus_if.h" 77 78#include "if_bmreg.h" 79#include "if_bmvar.h" 80 81static int bm_probe (device_t); 82static int bm_attach (device_t); 83static int bm_detach (device_t); 84static void bm_shutdown (device_t); 85 86static void bm_start (struct ifnet *); 87static void bm_start_locked (struct ifnet *); 88static int bm_encap (struct bm_softc *sc, struct mbuf **m_head); 89static int bm_ioctl (struct ifnet *, u_long, caddr_t); 90static void bm_init (void *); 91static void bm_init_locked (struct bm_softc *sc); 92static void bm_chip_setup (struct bm_softc *sc); 93static void bm_stop (struct bm_softc *sc); 94static void bm_setladrf (struct bm_softc *sc); 95static void bm_dummypacket (struct bm_softc *sc); 96static void bm_txintr (void *xsc); 97static void bm_rxintr (void *xsc); 98 99static int bm_add_rxbuf (struct bm_softc *sc, int i); 100static int bm_add_rxbuf_dma (struct bm_softc *sc, int i); 101static void bm_enable_interrupts (struct bm_softc *sc); 102static void bm_disable_interrupts (struct bm_softc *sc); 103static void bm_tick (void *xsc); 104static int bm_watchdog (struct bm_softc *sc); 105 106static int bm_ifmedia_upd (struct ifnet *); 107static void bm_ifmedia_sts (struct ifnet *, struct ifmediareq *); 108 109static void bm_miicsr_dwrite (struct bm_softc *, u_int16_t); 110static void bm_mii_writebit (struct bm_softc *, int); 111static int bm_mii_readbit (struct bm_softc *); 112static void bm_mii_sync (struct bm_softc *); 113static void bm_mii_send (struct bm_softc *, u_int32_t, int); 114static int bm_mii_readreg (struct bm_softc *, struct bm_mii_frame *); 115static int bm_mii_writereg (struct bm_softc *, struct bm_mii_frame *); 116static int bm_miibus_readreg (device_t, int, int); 117static int bm_miibus_writereg (device_t, int, int, int); 118static void bm_miibus_statchg (device_t); 119 120static device_method_t bm_methods[] = { 121 /* Device interface */ 122 DEVMETHOD(device_probe, bm_probe), 123 DEVMETHOD(device_attach, bm_attach), 124 DEVMETHOD(device_detach, bm_detach), 125 DEVMETHOD(device_shutdown, bm_shutdown), 126 127 /* bus interface, for miibus */ 128 DEVMETHOD(bus_print_child, bus_generic_print_child), 129 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 130 131 /* MII interface */ 132 DEVMETHOD(miibus_readreg, bm_miibus_readreg), 133 DEVMETHOD(miibus_writereg, bm_miibus_writereg), 134 DEVMETHOD(miibus_statchg, bm_miibus_statchg), 135 { 0, 0 } 136}; 137 138static driver_t bm_macio_driver = { 139 "bm", 140 bm_methods, 141 sizeof(struct bm_softc) 142}; 143 144static devclass_t bm_devclass; 145 146DRIVER_MODULE(bm, macio, bm_macio_driver, bm_devclass, 0, 0); 147DRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0); 148 149/* 150 * MII internal routines 151 */ 152 153/* 154 * Write to the MII csr, introducing a delay to allow valid 155 * MII clock pulses to be formed 156 */ 157static void 158bm_miicsr_dwrite(struct bm_softc *sc, u_int16_t val) 159{ 160 CSR_WRITE_2(sc, BM_MII_CSR, val); 161 /* 162 * Assume this is a clock toggle and generate a 1us delay 163 * to cover both MII's 160ns high/low minimum and 400ns 164 * cycle miniumum 165 */ 166 DELAY(1); 167} 168 169/* 170 * Write a bit to the MII bus. 171 */ 172static void 173bm_mii_writebit(struct bm_softc *sc, int bit) 174{ 175 u_int16_t regval; 176 177 regval = BM_MII_OENABLE; 178 if (bit) 179 regval |= BM_MII_DATAOUT; 180 181 bm_miicsr_dwrite(sc, regval); 182 bm_miicsr_dwrite(sc, regval | BM_MII_CLK); 183 bm_miicsr_dwrite(sc, regval); 184} 185 186/* 187 * Read a bit from the MII bus. 188 */ 189static int 190bm_mii_readbit(struct bm_softc *sc) 191{ 192 u_int16_t regval, bitin; 193 194 /* ~BM_MII_OENABLE */ 195 regval = 0; 196 197 bm_miicsr_dwrite(sc, regval); 198 bm_miicsr_dwrite(sc, regval | BM_MII_CLK); 199 bm_miicsr_dwrite(sc, regval); 200 bitin = CSR_READ_2(sc, BM_MII_CSR) & BM_MII_DATAIN; 201 202 return (bitin == BM_MII_DATAIN); 203} 204 205/* 206 * Sync the PHYs by setting data bit and strobing the clock 32 times. 207 */ 208static void 209bm_mii_sync(struct bm_softc *sc) 210{ 211 int i; 212 u_int16_t regval; 213 214 regval = BM_MII_OENABLE | BM_MII_DATAOUT; 215 216 bm_miicsr_dwrite(sc, regval); 217 for (i = 0; i < 32; i++) { 218 bm_miicsr_dwrite(sc, regval | BM_MII_CLK); 219 bm_miicsr_dwrite(sc, regval); 220 } 221} 222 223/* 224 * Clock a series of bits through the MII. 225 */ 226static void 227bm_mii_send(struct bm_softc *sc, u_int32_t bits, int cnt) 228{ 229 int i; 230 231 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 232 bm_mii_writebit(sc, bits & i); 233} 234 235/* 236 * Read a PHY register through the MII. 237 */ 238static int 239bm_mii_readreg(struct bm_softc *sc, struct bm_mii_frame *frame) 240{ 241 int i, ack, bit; 242 243 BM_LOCK(sc); 244 245 /* 246 * Set up frame for RX. 247 */ 248 frame->mii_stdelim = BM_MII_STARTDELIM; 249 frame->mii_opcode = BM_MII_READOP; 250 frame->mii_turnaround = 0; 251 frame->mii_data = 0; 252 253 /* 254 * Sync the PHYs 255 */ 256 bm_mii_sync(sc); 257 258 /* 259 * Send command/address info 260 */ 261 bm_mii_send(sc, frame->mii_stdelim, 2); 262 bm_mii_send(sc, frame->mii_opcode, 2); 263 bm_mii_send(sc, frame->mii_phyaddr, 5); 264 bm_mii_send(sc, frame->mii_regaddr, 5); 265 266 /* 267 * Check for ack. 268 */ 269 ack = bm_mii_readbit(sc); 270 271 /* 272 * Now try reading data bits. If the ack failed, we still 273 * need to clock through 16 cycles to keep the PHY(s) in sync. 274 */ 275 for (i = 0x8000; i; i >>= 1) { 276 bit = bm_mii_readbit(sc); 277 if (!ack && bit) 278 frame->mii_data |= i; 279 } 280 281 /* 282 * Skip through idle bit-times 283 */ 284 bm_mii_writebit(sc, 0); 285 bm_mii_writebit(sc, 0); 286 287 BM_UNLOCK(sc); 288 289 return ((ack) ? 1 : 0); 290} 291 292/* 293 * Write to a PHY register through the MII. 294 */ 295static int 296bm_mii_writereg(struct bm_softc *sc, struct bm_mii_frame *frame) 297{ 298 BM_LOCK(sc); 299 300 /* 301 * Set up frame for tx 302 */ 303 frame->mii_stdelim = BM_MII_STARTDELIM; 304 frame->mii_opcode = BM_MII_WRITEOP; 305 frame->mii_turnaround = BM_MII_TURNAROUND; 306 307 /* 308 * Sync the phy and start the bitbang write sequence 309 */ 310 bm_mii_sync(sc); 311 312 bm_mii_send(sc, frame->mii_stdelim, 2); 313 bm_mii_send(sc, frame->mii_opcode, 2); 314 bm_mii_send(sc, frame->mii_phyaddr, 5); 315 bm_mii_send(sc, frame->mii_regaddr, 5); 316 bm_mii_send(sc, frame->mii_turnaround, 2); 317 bm_mii_send(sc, frame->mii_data, 16); 318 319 /* 320 * Idle bit. 321 */ 322 bm_mii_writebit(sc, 0); 323 324 BM_UNLOCK(sc); 325 326 return (0); 327} 328 329/* 330 * MII bus i/f 331 */ 332static int 333bm_miibus_readreg(device_t dev, int phy, int reg) 334{ 335 struct bm_softc *sc; 336 struct bm_mii_frame frame; 337 338 sc = device_get_softc(dev); 339 bzero(&frame, sizeof(frame)); 340 341 frame.mii_phyaddr = phy; 342 frame.mii_regaddr = reg; 343 344 bm_mii_readreg(sc, &frame); 345 346 return (frame.mii_data); 347} 348 349static int 350bm_miibus_writereg(device_t dev, int phy, int reg, int data) 351{ 352 struct bm_softc *sc; 353 struct bm_mii_frame frame; 354 355 sc = device_get_softc(dev); 356 bzero(&frame, sizeof(frame)); 357 358 frame.mii_phyaddr = phy; 359 frame.mii_regaddr = reg; 360 frame.mii_data = data; 361 362 bm_mii_writereg(sc, &frame); 363 364 return (0); 365} 366 367static void 368bm_miibus_statchg(device_t dev) 369{ 370 struct bm_softc *sc = device_get_softc(dev); 371 uint16_t reg; 372 int new_duplex; 373 374 reg = CSR_READ_2(sc, BM_TX_CONFIG); 375 new_duplex = IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX; 376 377 if (new_duplex != sc->sc_duplex) { 378 /* Turn off TX MAC while we fiddle its settings */ 379 reg &= ~BM_ENABLE; 380 381 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 382 while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE) 383 DELAY(10); 384 } 385 386 if (new_duplex && !sc->sc_duplex) 387 reg |= BM_TX_IGNORECOLL | BM_TX_FULLDPX; 388 else if (!new_duplex && sc->sc_duplex) 389 reg &= ~(BM_TX_IGNORECOLL | BM_TX_FULLDPX); 390 391 if (new_duplex != sc->sc_duplex) { 392 /* Turn TX MAC back on */ 393 reg |= BM_ENABLE; 394 395 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 396 sc->sc_duplex = new_duplex; 397 } 398} 399 400/* 401 * ifmedia/mii callbacks 402 */ 403static int 404bm_ifmedia_upd(struct ifnet *ifp) 405{ 406 struct bm_softc *sc = ifp->if_softc; 407 int error; 408 409 BM_LOCK(sc); 410 error = mii_mediachg(sc->sc_mii); 411 BM_UNLOCK(sc); 412 return (error); 413} 414 415static void 416bm_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifm) 417{ 418 struct bm_softc *sc = ifp->if_softc; 419 420 BM_LOCK(sc); 421 mii_pollstat(sc->sc_mii); 422 ifm->ifm_active = sc->sc_mii->mii_media_active; 423 ifm->ifm_status = sc->sc_mii->mii_media_status; 424 BM_UNLOCK(sc); 425} 426 427/* 428 * Macio probe/attach 429 */ 430static int 431bm_probe(device_t dev) 432{ 433 const char *dname = ofw_bus_get_name(dev); 434 const char *dcompat = ofw_bus_get_compat(dev); 435 436 /* 437 * BMAC+ cells have a name of "ethernet" and 438 * a compatible property of "bmac+" 439 */ 440 if (strcmp(dname, "bmac") == 0) { 441 device_set_desc(dev, "Apple BMAC Ethernet Adaptor"); 442 } else if (strcmp(dcompat, "bmac+") == 0) { 443 device_set_desc(dev, "Apple BMAC+ Ethernet Adaptor"); 444 } else 445 return (ENXIO); 446 447 return (0); 448} 449 450static int 451bm_attach(device_t dev) 452{ 453 phandle_t node; 454 u_char *eaddr; 455 struct ifnet *ifp; 456 int error, cellid, i; 457 struct bm_txsoft *txs; 458 struct bm_softc *sc = device_get_softc(dev); 459 460 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 461 ifp->if_softc = sc; 462 sc->sc_dev = dev; 463 sc->sc_duplex = ~IFM_FDX; 464 465 error = 0; 466 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 467 MTX_DEF | MTX_RECURSE); 468 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 469 470 /* Check for an improved version of Paddington */ 471 sc->sc_streaming = 0; 472 cellid = -1; 473 node = ofw_bus_get_node(dev); 474 475 OF_getprop(node, "cell-id", &cellid, sizeof(cellid)); 476 if (cellid >= 0xc4) 477 sc->sc_streaming = 1; 478 479 sc->sc_memrid = 0; 480 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 481 &sc->sc_memrid, RF_ACTIVE); 482 if (sc->sc_memr == NULL) { 483 device_printf(dev, "Could not alloc chip registers!\n"); 484 return (ENXIO); 485 } 486 487 sc->sc_btag = rman_get_bustag(sc->sc_memr); 488 sc->sc_bhandle = rman_get_bushandle(sc->sc_memr); 489 490 sc->sc_txdmarid = BM_TXDMA_REGISTERS; 491 sc->sc_rxdmarid = BM_RXDMA_REGISTERS; 492 493 sc->sc_txdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 494 &sc->sc_txdmarid, RF_ACTIVE); 495 sc->sc_rxdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 496 &sc->sc_rxdmarid, RF_ACTIVE); 497 498 if (sc->sc_txdmar == NULL || sc->sc_rxdmar == NULL) { 499 device_printf(dev, "Could not map DBDMA registers!\n"); 500 return (ENXIO); 501 } 502 503 error = dbdma_allocate_channel(sc->sc_txdmar, bus_get_dma_tag(dev), 504 BM_MAX_DMA_COMMANDS, &sc->sc_txdma); 505 error += dbdma_allocate_channel(sc->sc_rxdmar, bus_get_dma_tag(dev), 506 BM_MAX_DMA_COMMANDS, &sc->sc_rxdma); 507 508 if (error) { 509 device_printf(dev,"Could not allocate DBDMA channel!\n"); 510 return (ENXIO); 511 } 512 513 /* alloc DMA tags and buffers */ 514 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 515 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 516 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 517 NULL, &sc->sc_pdma_tag); 518 519 if (error) { 520 device_printf(dev,"Could not allocate DMA tag!\n"); 521 return (ENXIO); 522 } 523 524 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 525 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 526 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdma_tag); 527 528 if (error) { 529 device_printf(dev,"Could not allocate RX DMA channel!\n"); 530 return (ENXIO); 531 } 532 533 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 534 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * BM_NTXSEGS, BM_NTXSEGS, 535 MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdma_tag); 536 537 if (error) { 538 device_printf(dev,"Could not allocate TX DMA tag!\n"); 539 return (ENXIO); 540 } 541 542 /* init transmit descriptors */ 543 STAILQ_INIT(&sc->sc_txfreeq); 544 STAILQ_INIT(&sc->sc_txdirtyq); 545 546 /* create TX DMA maps */ 547 error = ENOMEM; 548 for (i = 0; i < BM_MAX_TX_PACKETS; i++) { 549 txs = &sc->sc_txsoft[i]; 550 txs->txs_mbuf = NULL; 551 error = bus_dmamap_create(sc->sc_tdma_tag, 0, &txs->txs_dmamap); 552 if (error) { 553 device_printf(sc->sc_dev, 554 "unable to create TX DMA map %d, error = %d\n", 555 i, error); 556 } 557 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 558 } 559 560 /* Create the receive buffer DMA maps. */ 561 for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 562 error = bus_dmamap_create(sc->sc_rdma_tag, 0, 563 &sc->sc_rxsoft[i].rxs_dmamap); 564 if (error) { 565 device_printf(sc->sc_dev, 566 "unable to create RX DMA map %d, error = %d\n", 567 i, error); 568 } 569 sc->sc_rxsoft[i].rxs_mbuf = NULL; 570 } 571 572 /* alloc interrupt */ 573 574 sc->sc_txdmairqid = BM_TXDMA_INTERRUPT; 575 sc->sc_txdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 576 &sc->sc_txdmairqid, RF_ACTIVE); 577 578 if (error) { 579 device_printf(dev,"Could not allocate TX interrupt!\n"); 580 return (ENXIO); 581 } 582 583 bus_setup_intr(dev,sc->sc_txdmairq, 584 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_txintr, sc, 585 &sc->sc_txihtx); 586 587 sc->sc_rxdmairqid = BM_RXDMA_INTERRUPT; 588 sc->sc_rxdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 589 &sc->sc_rxdmairqid, RF_ACTIVE); 590 591 if (error) { 592 device_printf(dev,"Could not allocate RX interrupt!\n"); 593 return (ENXIO); 594 } 595 596 bus_setup_intr(dev,sc->sc_rxdmairq, 597 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_rxintr, sc, 598 &sc->sc_rxih); 599 600 /* 601 * Get the ethernet address from OpenFirmware 602 */ 603 eaddr = sc->sc_enaddr; 604 OF_getprop(node, "local-mac-address", eaddr, ETHER_ADDR_LEN); 605 606 /* reset the adapter */ 607 bm_chip_setup(sc); 608 609 /* setup MII */ 610 error = mii_phy_probe(dev, &sc->sc_miibus, bm_ifmedia_upd, 611 bm_ifmedia_sts); 612 if (error != 0) 613 device_printf(dev,"PHY probe failed: %d\n", error); 614 615 sc->sc_mii = device_get_softc(sc->sc_miibus); 616 617 if_initname(ifp, device_get_name(sc->sc_dev), 618 device_get_unit(sc->sc_dev)); 619 ifp->if_mtu = ETHERMTU; 620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 621 ifp->if_start = bm_start; 622 ifp->if_ioctl = bm_ioctl; 623 ifp->if_init = bm_init; 624 IFQ_SET_MAXLEN(&ifp->if_snd, BM_MAX_TX_PACKETS); 625 ifp->if_snd.ifq_drv_maxlen = BM_MAX_TX_PACKETS; 626 IFQ_SET_READY(&ifp->if_snd); 627 628 /* Attach the interface. */ 629 ether_ifattach(ifp, sc->sc_enaddr); 630 631 ifp->if_data.ifi_hdrlen = sizeof(struct ether_header); 632 ifp->if_hwassist = 0; 633 634 return (0); 635} 636 637static int 638bm_detach(device_t dev) 639{ 640 struct bm_softc *sc = device_get_softc(dev); 641 642 callout_drain(&sc->sc_tick_ch); 643 644 BM_LOCK(sc); 645 bm_stop(sc); 646 647 dbdma_free_channel(sc->sc_txdma); 648 dbdma_free_channel(sc->sc_rxdma); 649 650 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr); 651 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_txdmarid, 652 sc->sc_txdmar); 653 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rxdmarid, 654 sc->sc_rxdmar); 655 656 bus_teardown_intr(dev, sc->sc_txdmairq, sc->sc_txihtx); 657 bus_teardown_intr(dev, sc->sc_rxdmairq, sc->sc_rxih); 658 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_txdmairqid, 659 sc->sc_txdmairq); 660 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rxdmairqid, 661 sc->sc_rxdmairq); 662 BM_UNLOCK(sc); 663 664 mtx_destroy(&sc->sc_mtx); 665 666 return (0); 667} 668 669static void 670bm_shutdown(device_t dev) 671{ 672 bm_stop(device_get_softc(dev)); 673} 674 675static void 676bm_dummypacket(struct bm_softc *sc) 677{ 678 struct mbuf *m; 679 struct ifnet *ifp; 680 681 ifp = sc->sc_ifp; 682 683 MGETHDR(m, M_DONTWAIT, MT_DATA); 684 685 if (m == NULL) 686 return; 687 688 bcopy(sc->sc_enaddr, 689 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 690 bcopy(sc->sc_enaddr, 691 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 692 mtod(m, struct ether_header *)->ether_type = htons(3); 693 mtod(m, unsigned char *)[14] = 0; 694 mtod(m, unsigned char *)[15] = 0; 695 mtod(m, unsigned char *)[16] = 0xE3; 696 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 697 IF_ENQUEUE(&ifp->if_snd, m); 698 bm_start(ifp); 699} 700 701static void 702bm_rxintr(void *xsc) 703{ 704 struct bm_softc *sc = xsc; 705 struct ifnet *ifp = sc->sc_ifp; 706 struct mbuf *m; 707 int i, prev_stop, new_stop; 708 uint16_t status; 709 710 BM_LOCK(sc); 711 712 status = dbdma_get_chan_status(sc->sc_rxdma); 713 if (status & DBDMA_STATUS_DEAD) { 714 dbdma_reset(sc->sc_rxdma); 715 BM_UNLOCK(sc); 716 return; 717 } 718 if (!(status & DBDMA_STATUS_RUN)) { 719 device_printf(sc->sc_dev,"Bad RX Interrupt!\n"); 720 BM_UNLOCK(sc); 721 return; 722 } 723 724 prev_stop = sc->next_rxdma_slot - 1; 725 if (prev_stop < 0) 726 prev_stop = sc->rxdma_loop_slot - 1; 727 728 if (prev_stop < 0) { 729 BM_UNLOCK(sc); 730 return; 731 } 732 733 new_stop = -1; 734 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_POSTREAD); 735 736 for (i = sc->next_rxdma_slot; i < BM_MAX_RX_PACKETS; i++) { 737 if (i == sc->rxdma_loop_slot) 738 i = 0; 739 740 if (i == prev_stop) 741 break; 742 743 status = dbdma_get_cmd_status(sc->sc_rxdma, i); 744 745 if (status == 0) 746 break; 747 748 m = sc->sc_rxsoft[i].rxs_mbuf; 749 750 if (bm_add_rxbuf(sc, i)) { 751 ifp->if_ierrors++; 752 m = NULL; 753 continue; 754 } 755 756 if (m == NULL) 757 continue; 758 759 ifp->if_ipackets++; 760 m->m_pkthdr.rcvif = ifp; 761 m->m_len -= (dbdma_get_residuals(sc->sc_rxdma, i) + 2); 762 m->m_pkthdr.len = m->m_len; 763 764 /* Send up the stack */ 765 BM_UNLOCK(sc); 766 (*ifp->if_input)(ifp, m); 767 BM_LOCK(sc); 768 769 /* Clear all fields on this command */ 770 bm_add_rxbuf_dma(sc, i); 771 772 new_stop = i; 773 } 774 775 /* Change the last packet we processed to the ring buffer terminator, 776 * and restore a receive buffer to the old terminator */ 777 if (new_stop >= 0) { 778 dbdma_insert_stop(sc->sc_rxdma, new_stop); 779 bm_add_rxbuf_dma(sc, prev_stop); 780 if (i < sc->rxdma_loop_slot) 781 sc->next_rxdma_slot = i; 782 else 783 sc->next_rxdma_slot = 0; 784 } 785 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 786 787 dbdma_wake(sc->sc_rxdma); 788 789 BM_UNLOCK(sc); 790} 791 792static void 793bm_txintr(void *xsc) 794{ 795 struct bm_softc *sc = xsc; 796 struct ifnet *ifp = sc->sc_ifp; 797 struct bm_txsoft *txs; 798 int progress = 0; 799 800 BM_LOCK(sc); 801 802 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 803 if (!dbdma_get_cmd_status(sc->sc_txdma, txs->txs_lastdesc)) 804 break; 805 806 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 807 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 808 809 if (txs->txs_mbuf != NULL) { 810 m_freem(txs->txs_mbuf); 811 txs->txs_mbuf = NULL; 812 } 813 814 /* Set the first used TXDMA slot to the location of the 815 * STOP/NOP command associated with this packet. */ 816 817 sc->first_used_txdma_slot = txs->txs_stopdesc; 818 819 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 820 821 ifp->if_opackets++; 822 progress = 1; 823 } 824 825 if (progress) { 826 /* 827 * We freed some descriptors, so reset IFF_DRV_OACTIVE 828 * and restart. 829 */ 830 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 831 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 832 833 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 834 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 835 bm_start_locked(ifp); 836 } 837 838 BM_UNLOCK(sc); 839} 840 841static void 842bm_start(struct ifnet *ifp) 843{ 844 struct bm_softc *sc = ifp->if_softc; 845 846 BM_LOCK(sc); 847 bm_start_locked(ifp); 848 BM_UNLOCK(sc); 849} 850 851static void 852bm_start_locked(struct ifnet *ifp) 853{ 854 struct bm_softc *sc = ifp->if_softc; 855 struct mbuf *mb_head; 856 int prev_stop; 857 int txqueued = 0; 858 859 /* 860 * We lay out our DBDMA program in the following manner: 861 * OUTPUT_MORE 862 * ... 863 * OUTPUT_LAST (+ Interrupt) 864 * STOP 865 * 866 * To extend the channel, we append a new program, 867 * then replace STOP with NOP and wake the channel. 868 * If we stalled on the STOP already, the program proceeds, 869 * if not it will sail through the NOP. 870 */ 871 872 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 873 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 874 875 if (mb_head == NULL) 876 break; 877 878 prev_stop = sc->next_txdma_slot - 1; 879 880 if (bm_encap(sc, &mb_head)) { 881 /* Put the packet back and stop */ 882 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 883 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 884 break; 885 } 886 887 dbdma_insert_nop(sc->sc_txdma, prev_stop); 888 889 txqueued = 1; 890 891 BPF_MTAP(ifp, mb_head); 892 } 893 894 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 895 896 if (txqueued) { 897 dbdma_wake(sc->sc_txdma); 898 sc->sc_wdog_timer = 5; 899 } 900} 901 902static int 903bm_encap(struct bm_softc *sc, struct mbuf **m_head) 904{ 905 bus_dma_segment_t segs[BM_NTXSEGS]; 906 struct bm_txsoft *txs; 907 struct mbuf *m; 908 int nsegs = BM_NTXSEGS; 909 int error = 0; 910 uint8_t branch_type; 911 int i; 912 913 /* Limit the command size to the number of free DBDMA slots */ 914 915 if (sc->next_txdma_slot >= sc->first_used_txdma_slot) 916 nsegs = BM_MAX_DMA_COMMANDS - 2 - sc->next_txdma_slot + 917 sc->first_used_txdma_slot; /* -2 for branch and indexing */ 918 else 919 nsegs = sc->first_used_txdma_slot - sc->next_txdma_slot; 920 921 /* Remove one slot for the STOP/NOP terminator */ 922 nsegs--; 923 924 if (nsegs > BM_NTXSEGS) 925 nsegs = BM_NTXSEGS; 926 927 /* Get a work queue entry. */ 928 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 929 /* Ran out of descriptors. */ 930 return (ENOBUFS); 931 } 932 933 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, txs->txs_dmamap, 934 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 935 936 if (error == EFBIG) { 937 m = m_collapse(*m_head, M_DONTWAIT, nsegs); 938 if (m == NULL) { 939 m_freem(*m_head); 940 *m_head = NULL; 941 return (ENOBUFS); 942 } 943 *m_head = m; 944 945 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, 946 txs->txs_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 947 if (error != 0) { 948 m_freem(*m_head); 949 *m_head = NULL; 950 return (error); 951 } 952 } else if (error != 0) 953 return (error); 954 955 if (nsegs == 0) { 956 m_freem(*m_head); 957 *m_head = NULL; 958 return (EIO); 959 } 960 961 txs->txs_ndescs = nsegs; 962 txs->txs_firstdesc = sc->next_txdma_slot; 963 964 for (i = 0; i < nsegs; i++) { 965 /* Loop back to the beginning if this is our last slot */ 966 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) 967 branch_type = DBDMA_ALWAYS; 968 else 969 branch_type = DBDMA_NEVER; 970 971 if (i+1 == nsegs) 972 txs->txs_lastdesc = sc->next_txdma_slot; 973 974 dbdma_insert_command(sc->sc_txdma, sc->next_txdma_slot++, 975 (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE : DBDMA_OUTPUT_LAST, 976 0, segs[i].ds_addr, segs[i].ds_len, 977 (i + 1 < nsegs) ? DBDMA_NEVER : DBDMA_ALWAYS, 978 branch_type, DBDMA_NEVER, 0); 979 980 if (branch_type == DBDMA_ALWAYS) 981 sc->next_txdma_slot = 0; 982 } 983 984 /* We have a corner case where the STOP command is the last slot, 985 * but you can't branch in STOP commands. So add a NOP branch here 986 * and the STOP in slot 0. */ 987 988 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) { 989 dbdma_insert_branch(sc->sc_txdma, sc->next_txdma_slot, 0); 990 sc->next_txdma_slot = 0; 991 } 992 993 txs->txs_stopdesc = sc->next_txdma_slot; 994 dbdma_insert_stop(sc->sc_txdma, sc->next_txdma_slot++); 995 996 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 997 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 998 txs->txs_mbuf = *m_head; 999 1000 return (0); 1001} 1002 1003static int 1004bm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1005{ 1006 struct bm_softc *sc = ifp->if_softc; 1007 struct ifreq *ifr = (struct ifreq *)data; 1008 int error; 1009 1010 error = 0; 1011 1012 switch(cmd) { 1013 case SIOCSIFFLAGS: 1014 BM_LOCK(sc); 1015 if ((ifp->if_flags & IFF_UP) != 0) { 1016 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1017 ((ifp->if_flags ^ sc->sc_ifpflags) & 1018 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 1019 bm_setladrf(sc); 1020 else 1021 bm_init_locked(sc); 1022 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1023 bm_stop(sc); 1024 sc->sc_ifpflags = ifp->if_flags; 1025 BM_UNLOCK(sc); 1026 break; 1027 case SIOCADDMULTI: 1028 case SIOCDELMULTI: 1029 BM_LOCK(sc); 1030 bm_setladrf(sc); 1031 BM_UNLOCK(sc); 1032 case SIOCGIFMEDIA: 1033 case SIOCSIFMEDIA: 1034 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 1035 break; 1036 default: 1037 error = ether_ioctl(ifp, cmd, data); 1038 break; 1039 } 1040 1041 return (error); 1042} 1043 1044static void 1045bm_setladrf(struct bm_softc *sc) 1046{ 1047 struct ifnet *ifp = sc->sc_ifp; 1048 struct ifmultiaddr *inm; 1049 uint16_t hash[4]; 1050 uint16_t reg; 1051 uint32_t crc; 1052 1053 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS; 1054 1055 /* Turn off RX MAC while we fiddle its settings */ 1056 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1057 while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE) 1058 DELAY(10); 1059 1060 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1061 reg |= BM_PROMISC; 1062 1063 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1064 1065 DELAY(15); 1066 1067 reg = CSR_READ_2(sc, BM_RX_CONFIG); 1068 reg |= BM_ENABLE; 1069 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1070 return; 1071 } 1072 1073 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 1074 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1075 } else { 1076 /* Clear the hash table. */ 1077 memset(hash, 0, sizeof(hash)); 1078 1079 IF_ADDR_LOCK(ifp); 1080 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 1081 if (inm->ifma_addr->sa_family != AF_LINK) 1082 continue; 1083 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1084 inm->ifma_addr), ETHER_ADDR_LEN); 1085 1086 /* We just want the 6 most significant bits */ 1087 crc >>= 26; 1088 1089 /* Set the corresponding bit in the filter. */ 1090 hash[crc >> 4] |= 1 << (crc & 0xf); 1091 } 1092 IF_ADDR_UNLOCK(ifp); 1093 } 1094 1095 /* Write out new hash table */ 1096 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]); 1097 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]); 1098 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]); 1099 CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]); 1100 1101 /* And turn the RX MAC back on, this time with the hash bit set */ 1102 reg |= BM_HASH_FILTER_ENABLE; 1103 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1104 1105 while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE)) 1106 DELAY(10); 1107 1108 reg = CSR_READ_2(sc, BM_RX_CONFIG); 1109 reg |= BM_ENABLE; 1110 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1111} 1112 1113static void 1114bm_init(void *xsc) 1115{ 1116 struct bm_softc *sc = xsc; 1117 1118 BM_LOCK(sc); 1119 bm_init_locked(sc); 1120 BM_UNLOCK(sc); 1121} 1122 1123static void 1124bm_chip_setup(struct bm_softc *sc) 1125{ 1126 uint16_t reg; 1127 uint16_t *eaddr_sect; 1128 char hrow_path[128]; 1129 ihandle_t hrow_ih; 1130 1131 eaddr_sect = (uint16_t *)(sc->sc_enaddr); 1132 1133 /* Enable BMAC cell */ 1134 OF_package_to_path(OF_parent(ofw_bus_get_node(sc->sc_dev)), 1135 hrow_path, sizeof(hrow_path)); 1136 hrow_ih = OF_open(hrow_path); 1137 if (hrow_ih == -1) { 1138 device_printf(sc->sc_dev, 1139 "Enabling BMAC cell failed! Hoping it's already active.\n"); 1140 } else { 1141 OF_call_method("enable-enet", hrow_ih, 0, 0); 1142 OF_close(hrow_ih); 1143 } 1144 1145 /* Reset chip */ 1146 CSR_WRITE_2(sc, BM_RX_RESET, 0x0000); 1147 CSR_WRITE_2(sc, BM_TX_RESET, 0x0001); 1148 do { 1149 reg = CSR_READ_2(sc, BM_TX_RESET); 1150 } while (reg & 0x0001); 1151 1152 /* Some random junk. OS X uses the system time. We use 1153 * the low 16 bits of the MAC address. */ 1154 CSR_WRITE_2(sc, BM_TX_RANDSEED, eaddr_sect[2]); 1155 1156 /* Enable transmit */ 1157 reg = CSR_READ_2(sc, BM_TX_IFC); 1158 reg |= BM_ENABLE; 1159 CSR_WRITE_2(sc, BM_TX_IFC, reg); 1160 1161 CSR_READ_2(sc, BM_TX_PEAKCNT); 1162} 1163 1164static void 1165bm_stop(struct bm_softc *sc) 1166{ 1167 struct bm_txsoft *txs; 1168 uint16_t reg; 1169 1170 /* Disable TX and RX MACs */ 1171 reg = CSR_READ_2(sc, BM_TX_CONFIG); 1172 reg &= ~BM_ENABLE; 1173 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1174 1175 reg = CSR_READ_2(sc, BM_RX_CONFIG); 1176 reg &= ~BM_ENABLE; 1177 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1178 1179 DELAY(100); 1180 1181 /* Stop DMA engine */ 1182 dbdma_stop(sc->sc_rxdma); 1183 dbdma_stop(sc->sc_txdma); 1184 sc->next_rxdma_slot = 0; 1185 sc->rxdma_loop_slot = 0; 1186 1187 /* Disable interrupts */ 1188 bm_disable_interrupts(sc); 1189 1190 /* Don't worry about pending transmits anymore */ 1191 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1192 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1193 if (txs->txs_ndescs != 0) { 1194 bus_dmamap_sync(sc->sc_tdma_tag, txs->txs_dmamap, 1195 BUS_DMASYNC_POSTWRITE); 1196 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 1197 if (txs->txs_mbuf != NULL) { 1198 m_freem(txs->txs_mbuf); 1199 txs->txs_mbuf = NULL; 1200 } 1201 } 1202 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1203 } 1204 1205 /* And we're down */ 1206 sc->sc_ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1207 sc->sc_wdog_timer = 0; 1208} 1209 1210static void 1211bm_init_locked(struct bm_softc *sc) 1212{ 1213 uint16_t reg; 1214 uint16_t *eaddr_sect; 1215 struct bm_rxsoft *rxs; 1216 int i; 1217 1218 eaddr_sect = (uint16_t *)(sc->sc_enaddr); 1219 1220 /* Zero RX slot info and stop DMA */ 1221 dbdma_stop(sc->sc_rxdma); 1222 dbdma_stop(sc->sc_txdma); 1223 sc->next_rxdma_slot = 0; 1224 sc->rxdma_loop_slot = 0; 1225 1226 /* Initialize TX/RX DBDMA programs */ 1227 dbdma_insert_stop(sc->sc_rxdma, 0); 1228 dbdma_insert_stop(sc->sc_txdma, 0); 1229 dbdma_set_current_cmd(sc->sc_rxdma, 0); 1230 dbdma_set_current_cmd(sc->sc_txdma, 0); 1231 1232 sc->next_rxdma_slot = 0; 1233 sc->next_txdma_slot = 1; 1234 sc->first_used_txdma_slot = 0; 1235 1236 for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 1237 rxs = &sc->sc_rxsoft[i]; 1238 rxs->dbdma_slot = i; 1239 1240 if (rxs->rxs_mbuf == NULL) { 1241 bm_add_rxbuf(sc, i); 1242 1243 if (rxs->rxs_mbuf == NULL) { 1244 /* If we can't add anymore, mark the problem */ 1245 rxs->dbdma_slot = -1; 1246 break; 1247 } 1248 } 1249 1250 if (i > 0) 1251 bm_add_rxbuf_dma(sc, i); 1252 } 1253 1254 /* 1255 * Now terminate the RX ring buffer, and follow with the loop to 1256 * the beginning. 1257 */ 1258 dbdma_insert_stop(sc->sc_rxdma, i - 1); 1259 dbdma_insert_branch(sc->sc_rxdma, i, 0); 1260 sc->rxdma_loop_slot = i; 1261 1262 /* Now add in the first element of the RX DMA chain */ 1263 bm_add_rxbuf_dma(sc, 0); 1264 1265 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 1266 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 1267 1268 /* Zero collision counters */ 1269 CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1270 CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1271 CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1272 CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1273 1274 /* Zero receive counters */ 1275 CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1276 CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1277 CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1278 CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1279 CSR_WRITE_2(sc, BM_RXCV, 0); 1280 1281 /* Prime transmit */ 1282 CSR_WRITE_2(sc, BM_TX_THRESH, 0xff); 1283 1284 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0); 1285 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001); 1286 1287 /* Prime receive */ 1288 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0); 1289 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001); 1290 1291 /* Clear status reg */ 1292 CSR_READ_2(sc, BM_STATUS); 1293 1294 /* Zero hash filters */ 1295 CSR_WRITE_2(sc, BM_HASHTAB0, 0); 1296 CSR_WRITE_2(sc, BM_HASHTAB1, 0); 1297 CSR_WRITE_2(sc, BM_HASHTAB2, 0); 1298 CSR_WRITE_2(sc, BM_HASHTAB3, 0); 1299 1300 /* Write MAC address to chip */ 1301 CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]); 1302 CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]); 1303 CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]); 1304 1305 /* Final receive engine setup */ 1306 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS | BM_HASH_FILTER_ENABLE; 1307 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1308 1309 /* Now turn it all on! */ 1310 dbdma_reset(sc->sc_rxdma); 1311 dbdma_reset(sc->sc_txdma); 1312 1313 /* Enable RX and TX MACs. Setting the address filter has 1314 * the side effect of enabling the RX MAC. */ 1315 bm_setladrf(sc); 1316 1317 reg = CSR_READ_2(sc, BM_TX_CONFIG); 1318 reg |= BM_ENABLE; 1319 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1320 1321 /* 1322 * Enable interrupts, unwedge the controller with a dummy packet, 1323 * and nudge the DMA queue. 1324 */ 1325 bm_enable_interrupts(sc); 1326 bm_dummypacket(sc); 1327 dbdma_wake(sc->sc_rxdma); /* Nudge RXDMA */ 1328 1329 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING; 1330 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1331 sc->sc_ifpflags = sc->sc_ifp->if_flags; 1332 1333 /* Resync PHY and MAC states */ 1334 sc->sc_mii = device_get_softc(sc->sc_miibus); 1335 sc->sc_duplex = ~IFM_FDX; 1336 mii_mediachg(sc->sc_mii); 1337 1338 /* Start the one second timer. */ 1339 sc->sc_wdog_timer = 0; 1340 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1341} 1342 1343static void 1344bm_tick(void *arg) 1345{ 1346 struct bm_softc *sc = arg; 1347 1348 /* Read error counters */ 1349 sc->sc_ifp->if_collisions += CSR_READ_2(sc, BM_TX_NCCNT) + 1350 CSR_READ_2(sc, BM_TX_FCCNT) + CSR_READ_2(sc, BM_TX_EXCNT) + 1351 CSR_READ_2(sc, BM_TX_LTCNT); 1352 1353 sc->sc_ifp->if_ierrors += CSR_READ_2(sc, BM_RX_LECNT) + 1354 CSR_READ_2(sc, BM_RX_AECNT) + CSR_READ_2(sc, BM_RX_FECNT); 1355 1356 /* Zero collision counters */ 1357 CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1358 CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1359 CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1360 CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1361 1362 /* Zero receive counters */ 1363 CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1364 CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1365 CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1366 CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1367 CSR_WRITE_2(sc, BM_RXCV, 0); 1368 1369 /* Check for link changes and run watchdog */ 1370 mii_tick(sc->sc_mii); 1371 bm_miibus_statchg(sc->sc_dev); 1372 1373 if (bm_watchdog(sc) == EJUSTRETURN) 1374 return; 1375 1376 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1377} 1378 1379static int 1380bm_watchdog(struct bm_softc *sc) 1381{ 1382 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 1383 return (0); 1384 1385 device_printf(sc->sc_dev, "device timeout\n"); 1386 1387 bm_init_locked(sc); 1388 return (EJUSTRETURN); 1389} 1390 1391static int 1392bm_add_rxbuf(struct bm_softc *sc, int idx) 1393{ 1394 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1395 struct mbuf *m; 1396 bus_dma_segment_t segs[1]; 1397 int error, nsegs; 1398 1399 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1400 if (m == NULL) 1401 return (ENOBUFS); 1402 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1403 1404 if (rxs->rxs_mbuf != NULL) { 1405 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, 1406 BUS_DMASYNC_POSTREAD); 1407 bus_dmamap_unload(sc->sc_rdma_tag, rxs->rxs_dmamap); 1408 } 1409 1410 error = bus_dmamap_load_mbuf_sg(sc->sc_rdma_tag, rxs->rxs_dmamap, m, 1411 segs, &nsegs, BUS_DMA_NOWAIT); 1412 if (error != 0) { 1413 device_printf(sc->sc_dev, 1414 "cannot load RS DMA map %d, error = %d\n", idx, error); 1415 m_freem(m); 1416 return (error); 1417 } 1418 /* If nsegs is wrong then the stack is corrupt. */ 1419 KASSERT(nsegs == 1, 1420 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1421 rxs->rxs_mbuf = m; 1422 rxs->segment = segs[0]; 1423 1424 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 1425 1426 return (0); 1427} 1428 1429static int 1430bm_add_rxbuf_dma(struct bm_softc *sc, int idx) 1431{ 1432 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1433 1434 dbdma_insert_command(sc->sc_rxdma, idx, DBDMA_INPUT_LAST, 0, 1435 rxs->segment.ds_addr, rxs->segment.ds_len, DBDMA_ALWAYS, 1436 DBDMA_NEVER, DBDMA_NEVER, 0); 1437 1438 return (0); 1439} 1440 1441static void 1442bm_enable_interrupts(struct bm_softc *sc) 1443{ 1444 CSR_WRITE_2(sc, BM_INTR_DISABLE, 1445 (sc->sc_streaming) ? BM_INTR_NONE : BM_INTR_NORMAL); 1446} 1447 1448static void 1449bm_disable_interrupts(struct bm_softc *sc) 1450{ 1451 CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE); 1452} 1453