if_bge.c revision 264940
1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: stable/10/sys/dev/bge/if_bge.c 264940 2014-04-25 21:28:39Z marius $"); 36 37/* 38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69#ifdef HAVE_KERNEL_OPTION_HEADERS 70#include "opt_device_polling.h" 71#endif 72 73#include <sys/param.h> 74#include <sys/endian.h> 75#include <sys/systm.h> 76#include <sys/sockio.h> 77#include <sys/mbuf.h> 78#include <sys/malloc.h> 79#include <sys/kernel.h> 80#include <sys/module.h> 81#include <sys/socket.h> 82#include <sys/sysctl.h> 83#include <sys/taskqueue.h> 84 85#include <net/if.h> 86#include <net/if_arp.h> 87#include <net/ethernet.h> 88#include <net/if_dl.h> 89#include <net/if_media.h> 90 91#include <net/bpf.h> 92 93#include <net/if_types.h> 94#include <net/if_vlan_var.h> 95 96#include <netinet/in_systm.h> 97#include <netinet/in.h> 98#include <netinet/ip.h> 99#include <netinet/tcp.h> 100 101#include <machine/bus.h> 102#include <machine/resource.h> 103#include <sys/bus.h> 104#include <sys/rman.h> 105 106#include <dev/mii/mii.h> 107#include <dev/mii/miivar.h> 108#include "miidevs.h" 109#include <dev/mii/brgphyreg.h> 110 111#ifdef __sparc64__ 112#include <dev/ofw/ofw_bus.h> 113#include <dev/ofw/openfirm.h> 114#include <machine/ofw_machdep.h> 115#include <machine/ver.h> 116#endif 117 118#include <dev/pci/pcireg.h> 119#include <dev/pci/pcivar.h> 120 121#include <dev/bge/if_bgereg.h> 122 123#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 124#define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126MODULE_DEPEND(bge, pci, 1, 1, 1); 127MODULE_DEPEND(bge, ether, 1, 1, 1); 128MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130/* "device miibus" required. See GENERIC if you get errors here. */ 131#include "miibus_if.h" 132 133/* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142} bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 }, 227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 }, 230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 }, 232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 }, 233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 235 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 236 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 237 238 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 239 240 { TC_VENDORID, TC_DEVICEID_3C996 }, 241 242 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 243 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 244 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 245 246 { 0, 0 } 247}; 248 249static const struct bge_vendor { 250 uint16_t v_id; 251 const char *v_name; 252} bge_vendors[] = { 253 { ALTEON_VENDORID, "Alteon" }, 254 { ALTIMA_VENDORID, "Altima" }, 255 { APPLE_VENDORID, "Apple" }, 256 { BCOM_VENDORID, "Broadcom" }, 257 { SK_VENDORID, "SysKonnect" }, 258 { TC_VENDORID, "3Com" }, 259 { FJTSU_VENDORID, "Fujitsu" }, 260 261 { 0, NULL } 262}; 263 264static const struct bge_revision { 265 uint32_t br_chipid; 266 const char *br_name; 267} bge_revisions[] = { 268 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 269 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 270 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 271 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 272 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 273 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 274 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 275 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 276 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 277 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 278 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 279 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 280 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 281 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 282 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 283 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 284 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 285 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 286 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 287 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 288 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 289 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 290 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 291 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 292 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 293 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 294 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 295 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 296 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 297 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 298 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 299 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 300 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 301 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 302 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 303 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 304 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 305 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 306 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 307 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 308 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 309 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 310 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 311 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 312 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 313 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 314 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 315 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 316 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 317 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 318 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 319 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 320 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 321 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 322 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 323 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 324 /* 5754 and 5787 share the same ASIC ID */ 325 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 326 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 327 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 328 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 329 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 330 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 331 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 332 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 333 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 334 335 { 0, NULL } 336}; 337 338/* 339 * Some defaults for major revisions, so that newer steppings 340 * that we don't know about have a shot at working. 341 */ 342static const struct bge_revision bge_majorrevs[] = { 343 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 344 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 345 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 346 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 347 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 348 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 349 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 350 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 351 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 352 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 353 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 354 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 355 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 356 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 357 /* 5754 and 5787 share the same ASIC ID */ 358 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 359 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 360 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 361 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 362 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 363 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 364 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 365 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 366 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 367 368 { 0, NULL } 369}; 370 371#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 372#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 373#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 374#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 375#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 376#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 377#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 378#define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 379 380static uint32_t bge_chipid(device_t); 381static const struct bge_vendor * bge_lookup_vendor(uint16_t); 382static const struct bge_revision * bge_lookup_rev(uint32_t); 383 384typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 385 386static int bge_probe(device_t); 387static int bge_attach(device_t); 388static int bge_detach(device_t); 389static int bge_suspend(device_t); 390static int bge_resume(device_t); 391static void bge_release_resources(struct bge_softc *); 392static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 393static int bge_dma_alloc(struct bge_softc *); 394static void bge_dma_free(struct bge_softc *); 395static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 396 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 397 398static void bge_devinfo(struct bge_softc *); 399static int bge_mbox_reorder(struct bge_softc *); 400 401static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 402static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 403static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 404static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 405static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 406 407static void bge_txeof(struct bge_softc *, uint16_t); 408static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 409static int bge_rxeof(struct bge_softc *, uint16_t, int); 410 411static void bge_asf_driver_up (struct bge_softc *); 412static void bge_tick(void *); 413static void bge_stats_clear_regs(struct bge_softc *); 414static void bge_stats_update(struct bge_softc *); 415static void bge_stats_update_regs(struct bge_softc *); 416static struct mbuf *bge_check_short_dma(struct mbuf *); 417static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 418 uint16_t *, uint16_t *); 419static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 420 421static void bge_intr(void *); 422static int bge_msi_intr(void *); 423static void bge_intr_task(void *, int); 424static void bge_start_locked(struct ifnet *); 425static void bge_start(struct ifnet *); 426static int bge_ioctl(struct ifnet *, u_long, caddr_t); 427static void bge_init_locked(struct bge_softc *); 428static void bge_init(void *); 429static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 430static void bge_stop(struct bge_softc *); 431static void bge_watchdog(struct bge_softc *); 432static int bge_shutdown(device_t); 433static int bge_ifmedia_upd_locked(struct ifnet *); 434static int bge_ifmedia_upd(struct ifnet *); 435static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 436 437static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 438static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 439 440static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 441static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 442 443static void bge_setpromisc(struct bge_softc *); 444static void bge_setmulti(struct bge_softc *); 445static void bge_setvlan(struct bge_softc *); 446 447static __inline void bge_rxreuse_std(struct bge_softc *, int); 448static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 449static int bge_newbuf_std(struct bge_softc *, int); 450static int bge_newbuf_jumbo(struct bge_softc *, int); 451static int bge_init_rx_ring_std(struct bge_softc *); 452static void bge_free_rx_ring_std(struct bge_softc *); 453static int bge_init_rx_ring_jumbo(struct bge_softc *); 454static void bge_free_rx_ring_jumbo(struct bge_softc *); 455static void bge_free_tx_ring(struct bge_softc *); 456static int bge_init_tx_ring(struct bge_softc *); 457 458static int bge_chipinit(struct bge_softc *); 459static int bge_blockinit(struct bge_softc *); 460static uint32_t bge_dma_swap_options(struct bge_softc *); 461 462static int bge_has_eaddr(struct bge_softc *); 463static uint32_t bge_readmem_ind(struct bge_softc *, int); 464static void bge_writemem_ind(struct bge_softc *, int, int); 465static void bge_writembx(struct bge_softc *, int, int); 466#ifdef notdef 467static uint32_t bge_readreg_ind(struct bge_softc *, int); 468#endif 469static void bge_writemem_direct(struct bge_softc *, int, int); 470static void bge_writereg_ind(struct bge_softc *, int, int); 471 472static int bge_miibus_readreg(device_t, int, int); 473static int bge_miibus_writereg(device_t, int, int, int); 474static void bge_miibus_statchg(device_t); 475#ifdef DEVICE_POLLING 476static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 477#endif 478 479#define BGE_RESET_SHUTDOWN 0 480#define BGE_RESET_START 1 481#define BGE_RESET_SUSPEND 2 482static void bge_sig_post_reset(struct bge_softc *, int); 483static void bge_sig_legacy(struct bge_softc *, int); 484static void bge_sig_pre_reset(struct bge_softc *, int); 485static void bge_stop_fw(struct bge_softc *); 486static int bge_reset(struct bge_softc *); 487static void bge_link_upd(struct bge_softc *); 488 489static void bge_ape_lock_init(struct bge_softc *); 490static void bge_ape_read_fw_ver(struct bge_softc *); 491static int bge_ape_lock(struct bge_softc *, int); 492static void bge_ape_unlock(struct bge_softc *, int); 493static void bge_ape_send_event(struct bge_softc *, uint32_t); 494static void bge_ape_driver_state_change(struct bge_softc *, int); 495 496/* 497 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 498 * leak information to untrusted users. It is also known to cause alignment 499 * traps on certain architectures. 500 */ 501#ifdef BGE_REGISTER_DEBUG 502static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 503static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 504static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 505static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 506#endif 507static void bge_add_sysctls(struct bge_softc *); 508static void bge_add_sysctl_stats_regs(struct bge_softc *, 509 struct sysctl_ctx_list *, struct sysctl_oid_list *); 510static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 511 struct sysctl_oid_list *); 512static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 513 514static device_method_t bge_methods[] = { 515 /* Device interface */ 516 DEVMETHOD(device_probe, bge_probe), 517 DEVMETHOD(device_attach, bge_attach), 518 DEVMETHOD(device_detach, bge_detach), 519 DEVMETHOD(device_shutdown, bge_shutdown), 520 DEVMETHOD(device_suspend, bge_suspend), 521 DEVMETHOD(device_resume, bge_resume), 522 523 /* MII interface */ 524 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 525 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 526 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 527 528 DEVMETHOD_END 529}; 530 531static driver_t bge_driver = { 532 "bge", 533 bge_methods, 534 sizeof(struct bge_softc) 535}; 536 537static devclass_t bge_devclass; 538 539DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 540DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 541 542static int bge_allow_asf = 1; 543 544TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 545 546static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 547SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 548 "Allow ASF mode if available"); 549 550#define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 551#define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 552#define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 553#define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 554#define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 555 556static int 557bge_has_eaddr(struct bge_softc *sc) 558{ 559#ifdef __sparc64__ 560 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 561 device_t dev; 562 uint32_t subvendor; 563 564 dev = sc->bge_dev; 565 566 /* 567 * The on-board BGEs found in sun4u machines aren't fitted with 568 * an EEPROM which means that we have to obtain the MAC address 569 * via OFW and that some tests will always fail. We distinguish 570 * such BGEs by the subvendor ID, which also has to be obtained 571 * from OFW instead of the PCI configuration space as the latter 572 * indicates Broadcom as the subvendor of the netboot interface. 573 * For early Blade 1500 and 2500 we even have to check the OFW 574 * device path as the subvendor ID always defaults to Broadcom 575 * there. 576 */ 577 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 578 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 579 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 580 return (0); 581 memset(buf, 0, sizeof(buf)); 582 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 583 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 584 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 585 return (0); 586 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 587 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 588 return (0); 589 } 590#endif 591 return (1); 592} 593 594static uint32_t 595bge_readmem_ind(struct bge_softc *sc, int off) 596{ 597 device_t dev; 598 uint32_t val; 599 600 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 601 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 602 return (0); 603 604 dev = sc->bge_dev; 605 606 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 607 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 608 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 609 return (val); 610} 611 612static void 613bge_writemem_ind(struct bge_softc *sc, int off, int val) 614{ 615 device_t dev; 616 617 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 618 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 619 return; 620 621 dev = sc->bge_dev; 622 623 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 624 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 625 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 626} 627 628#ifdef notdef 629static uint32_t 630bge_readreg_ind(struct bge_softc *sc, int off) 631{ 632 device_t dev; 633 634 dev = sc->bge_dev; 635 636 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 637 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 638} 639#endif 640 641static void 642bge_writereg_ind(struct bge_softc *sc, int off, int val) 643{ 644 device_t dev; 645 646 dev = sc->bge_dev; 647 648 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 649 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 650} 651 652static void 653bge_writemem_direct(struct bge_softc *sc, int off, int val) 654{ 655 CSR_WRITE_4(sc, off, val); 656} 657 658static void 659bge_writembx(struct bge_softc *sc, int off, int val) 660{ 661 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 662 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 663 664 CSR_WRITE_4(sc, off, val); 665 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 666 CSR_READ_4(sc, off); 667} 668 669/* 670 * Clear all stale locks and select the lock for this driver instance. 671 */ 672static void 673bge_ape_lock_init(struct bge_softc *sc) 674{ 675 uint32_t bit, regbase; 676 int i; 677 678 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 679 regbase = BGE_APE_LOCK_GRANT; 680 else 681 regbase = BGE_APE_PER_LOCK_GRANT; 682 683 /* Clear any stale locks. */ 684 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 685 switch (i) { 686 case BGE_APE_LOCK_PHY0: 687 case BGE_APE_LOCK_PHY1: 688 case BGE_APE_LOCK_PHY2: 689 case BGE_APE_LOCK_PHY3: 690 bit = BGE_APE_LOCK_GRANT_DRIVER0; 691 break; 692 default: 693 if (sc->bge_func_addr == 0) 694 bit = BGE_APE_LOCK_GRANT_DRIVER0; 695 else 696 bit = (1 << sc->bge_func_addr); 697 } 698 APE_WRITE_4(sc, regbase + 4 * i, bit); 699 } 700 701 /* Select the PHY lock based on the device's function number. */ 702 switch (sc->bge_func_addr) { 703 case 0: 704 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 705 break; 706 case 1: 707 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 708 break; 709 case 2: 710 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 711 break; 712 case 3: 713 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 714 break; 715 default: 716 device_printf(sc->bge_dev, 717 "PHY lock not supported on this function\n"); 718 } 719} 720 721/* 722 * Check for APE firmware, set flags, and print version info. 723 */ 724static void 725bge_ape_read_fw_ver(struct bge_softc *sc) 726{ 727 const char *fwtype; 728 uint32_t apedata, features; 729 730 /* Check for a valid APE signature in shared memory. */ 731 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 732 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 733 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 734 return; 735 } 736 737 /* Check if APE firmware is running. */ 738 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 739 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 740 device_printf(sc->bge_dev, "APE signature found " 741 "but FW status not ready! 0x%08x\n", apedata); 742 return; 743 } 744 745 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 746 747 /* Fetch the APE firwmare type and version. */ 748 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 749 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 750 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 751 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 752 fwtype = "NCSI"; 753 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 754 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 755 fwtype = "DASH"; 756 } else 757 fwtype = "UNKN"; 758 759 /* Print the APE firmware version. */ 760 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 761 fwtype, 762 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 763 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 764 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 765 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 766} 767 768static int 769bge_ape_lock(struct bge_softc *sc, int locknum) 770{ 771 uint32_t bit, gnt, req, status; 772 int i, off; 773 774 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 775 return (0); 776 777 /* Lock request/grant registers have different bases. */ 778 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 779 req = BGE_APE_LOCK_REQ; 780 gnt = BGE_APE_LOCK_GRANT; 781 } else { 782 req = BGE_APE_PER_LOCK_REQ; 783 gnt = BGE_APE_PER_LOCK_GRANT; 784 } 785 786 off = 4 * locknum; 787 788 switch (locknum) { 789 case BGE_APE_LOCK_GPIO: 790 /* Lock required when using GPIO. */ 791 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 792 return (0); 793 if (sc->bge_func_addr == 0) 794 bit = BGE_APE_LOCK_REQ_DRIVER0; 795 else 796 bit = (1 << sc->bge_func_addr); 797 break; 798 case BGE_APE_LOCK_GRC: 799 /* Lock required to reset the device. */ 800 if (sc->bge_func_addr == 0) 801 bit = BGE_APE_LOCK_REQ_DRIVER0; 802 else 803 bit = (1 << sc->bge_func_addr); 804 break; 805 case BGE_APE_LOCK_MEM: 806 /* Lock required when accessing certain APE memory. */ 807 if (sc->bge_func_addr == 0) 808 bit = BGE_APE_LOCK_REQ_DRIVER0; 809 else 810 bit = (1 << sc->bge_func_addr); 811 break; 812 case BGE_APE_LOCK_PHY0: 813 case BGE_APE_LOCK_PHY1: 814 case BGE_APE_LOCK_PHY2: 815 case BGE_APE_LOCK_PHY3: 816 /* Lock required when accessing PHYs. */ 817 bit = BGE_APE_LOCK_REQ_DRIVER0; 818 break; 819 default: 820 return (EINVAL); 821 } 822 823 /* Request a lock. */ 824 APE_WRITE_4(sc, req + off, bit); 825 826 /* Wait up to 1 second to acquire lock. */ 827 for (i = 0; i < 20000; i++) { 828 status = APE_READ_4(sc, gnt + off); 829 if (status == bit) 830 break; 831 DELAY(50); 832 } 833 834 /* Handle any errors. */ 835 if (status != bit) { 836 device_printf(sc->bge_dev, "APE lock %d request failed! " 837 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 838 locknum, req + off, bit & 0xFFFF, gnt + off, 839 status & 0xFFFF); 840 /* Revoke the lock request. */ 841 APE_WRITE_4(sc, gnt + off, bit); 842 return (EBUSY); 843 } 844 845 return (0); 846} 847 848static void 849bge_ape_unlock(struct bge_softc *sc, int locknum) 850{ 851 uint32_t bit, gnt; 852 int off; 853 854 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 855 return; 856 857 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 858 gnt = BGE_APE_LOCK_GRANT; 859 else 860 gnt = BGE_APE_PER_LOCK_GRANT; 861 862 off = 4 * locknum; 863 864 switch (locknum) { 865 case BGE_APE_LOCK_GPIO: 866 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 867 return; 868 if (sc->bge_func_addr == 0) 869 bit = BGE_APE_LOCK_GRANT_DRIVER0; 870 else 871 bit = (1 << sc->bge_func_addr); 872 break; 873 case BGE_APE_LOCK_GRC: 874 if (sc->bge_func_addr == 0) 875 bit = BGE_APE_LOCK_GRANT_DRIVER0; 876 else 877 bit = (1 << sc->bge_func_addr); 878 break; 879 case BGE_APE_LOCK_MEM: 880 if (sc->bge_func_addr == 0) 881 bit = BGE_APE_LOCK_GRANT_DRIVER0; 882 else 883 bit = (1 << sc->bge_func_addr); 884 break; 885 case BGE_APE_LOCK_PHY0: 886 case BGE_APE_LOCK_PHY1: 887 case BGE_APE_LOCK_PHY2: 888 case BGE_APE_LOCK_PHY3: 889 bit = BGE_APE_LOCK_GRANT_DRIVER0; 890 break; 891 default: 892 return; 893 } 894 895 APE_WRITE_4(sc, gnt + off, bit); 896} 897 898/* 899 * Send an event to the APE firmware. 900 */ 901static void 902bge_ape_send_event(struct bge_softc *sc, uint32_t event) 903{ 904 uint32_t apedata; 905 int i; 906 907 /* NCSI does not support APE events. */ 908 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 909 return; 910 911 /* Wait up to 1ms for APE to service previous event. */ 912 for (i = 10; i > 0; i--) { 913 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 914 break; 915 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 916 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 917 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 918 BGE_APE_EVENT_STATUS_EVENT_PENDING); 919 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 920 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 921 break; 922 } 923 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 924 DELAY(100); 925 } 926 if (i == 0) 927 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 928 event); 929} 930 931static void 932bge_ape_driver_state_change(struct bge_softc *sc, int kind) 933{ 934 uint32_t apedata, event; 935 936 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 937 return; 938 939 switch (kind) { 940 case BGE_RESET_START: 941 /* If this is the first load, clear the load counter. */ 942 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 943 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 944 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 945 else { 946 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 947 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 948 } 949 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 950 BGE_APE_HOST_SEG_SIG_MAGIC); 951 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 952 BGE_APE_HOST_SEG_LEN_MAGIC); 953 954 /* Add some version info if bge(4) supports it. */ 955 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 956 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 957 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 958 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 959 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 960 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 961 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 962 BGE_APE_HOST_DRVR_STATE_START); 963 event = BGE_APE_EVENT_STATUS_STATE_START; 964 break; 965 case BGE_RESET_SHUTDOWN: 966 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 967 BGE_APE_HOST_DRVR_STATE_UNLOAD); 968 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 969 break; 970 case BGE_RESET_SUSPEND: 971 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 972 break; 973 default: 974 return; 975 } 976 977 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 978 BGE_APE_EVENT_STATUS_STATE_CHNGE); 979} 980 981/* 982 * Map a single buffer address. 983 */ 984 985static void 986bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 987{ 988 struct bge_dmamap_arg *ctx; 989 990 if (error) 991 return; 992 993 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 994 995 ctx = arg; 996 ctx->bge_busaddr = segs->ds_addr; 997} 998 999static uint8_t 1000bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1001{ 1002 uint32_t access, byte = 0; 1003 int i; 1004 1005 /* Lock. */ 1006 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1007 for (i = 0; i < 8000; i++) { 1008 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1009 break; 1010 DELAY(20); 1011 } 1012 if (i == 8000) 1013 return (1); 1014 1015 /* Enable access. */ 1016 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1017 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1018 1019 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1020 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1021 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1022 DELAY(10); 1023 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1024 DELAY(10); 1025 break; 1026 } 1027 } 1028 1029 if (i == BGE_TIMEOUT * 10) { 1030 if_printf(sc->bge_ifp, "nvram read timed out\n"); 1031 return (1); 1032 } 1033 1034 /* Get result. */ 1035 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1036 1037 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1038 1039 /* Disable access. */ 1040 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1041 1042 /* Unlock. */ 1043 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1044 CSR_READ_4(sc, BGE_NVRAM_SWARB); 1045 1046 return (0); 1047} 1048 1049/* 1050 * Read a sequence of bytes from NVRAM. 1051 */ 1052static int 1053bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1054{ 1055 int err = 0, i; 1056 uint8_t byte = 0; 1057 1058 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1059 return (1); 1060 1061 for (i = 0; i < cnt; i++) { 1062 err = bge_nvram_getbyte(sc, off + i, &byte); 1063 if (err) 1064 break; 1065 *(dest + i) = byte; 1066 } 1067 1068 return (err ? 1 : 0); 1069} 1070 1071/* 1072 * Read a byte of data stored in the EEPROM at address 'addr.' The 1073 * BCM570x supports both the traditional bitbang interface and an 1074 * auto access interface for reading the EEPROM. We use the auto 1075 * access method. 1076 */ 1077static uint8_t 1078bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1079{ 1080 int i; 1081 uint32_t byte = 0; 1082 1083 /* 1084 * Enable use of auto EEPROM access so we can avoid 1085 * having to use the bitbang method. 1086 */ 1087 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1088 1089 /* Reset the EEPROM, load the clock period. */ 1090 CSR_WRITE_4(sc, BGE_EE_ADDR, 1091 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1092 DELAY(20); 1093 1094 /* Issue the read EEPROM command. */ 1095 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1096 1097 /* Wait for completion */ 1098 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 1099 DELAY(10); 1100 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1101 break; 1102 } 1103 1104 if (i == BGE_TIMEOUT * 10) { 1105 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1106 return (1); 1107 } 1108 1109 /* Get result. */ 1110 byte = CSR_READ_4(sc, BGE_EE_DATA); 1111 1112 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1113 1114 return (0); 1115} 1116 1117/* 1118 * Read a sequence of bytes from the EEPROM. 1119 */ 1120static int 1121bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1122{ 1123 int i, error = 0; 1124 uint8_t byte = 0; 1125 1126 for (i = 0; i < cnt; i++) { 1127 error = bge_eeprom_getbyte(sc, off + i, &byte); 1128 if (error) 1129 break; 1130 *(dest + i) = byte; 1131 } 1132 1133 return (error ? 1 : 0); 1134} 1135 1136static int 1137bge_miibus_readreg(device_t dev, int phy, int reg) 1138{ 1139 struct bge_softc *sc; 1140 uint32_t val; 1141 int i; 1142 1143 sc = device_get_softc(dev); 1144 1145 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1146 return (0); 1147 1148 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1149 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1150 CSR_WRITE_4(sc, BGE_MI_MODE, 1151 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1152 DELAY(80); 1153 } 1154 1155 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1156 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1157 1158 /* Poll for the PHY register access to complete. */ 1159 for (i = 0; i < BGE_TIMEOUT; i++) { 1160 DELAY(10); 1161 val = CSR_READ_4(sc, BGE_MI_COMM); 1162 if ((val & BGE_MICOMM_BUSY) == 0) { 1163 DELAY(5); 1164 val = CSR_READ_4(sc, BGE_MI_COMM); 1165 break; 1166 } 1167 } 1168 1169 if (i == BGE_TIMEOUT) { 1170 device_printf(sc->bge_dev, 1171 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1172 phy, reg, val); 1173 val = 0; 1174 } 1175 1176 /* Restore the autopoll bit if necessary. */ 1177 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1178 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1179 DELAY(80); 1180 } 1181 1182 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1183 1184 if (val & BGE_MICOMM_READFAIL) 1185 return (0); 1186 1187 return (val & 0xFFFF); 1188} 1189 1190static int 1191bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1192{ 1193 struct bge_softc *sc; 1194 int i; 1195 1196 sc = device_get_softc(dev); 1197 1198 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1199 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1200 return (0); 1201 1202 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1203 return (0); 1204 1205 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1206 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1207 CSR_WRITE_4(sc, BGE_MI_MODE, 1208 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1209 DELAY(80); 1210 } 1211 1212 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1213 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1214 1215 for (i = 0; i < BGE_TIMEOUT; i++) { 1216 DELAY(10); 1217 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1218 DELAY(5); 1219 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 1220 break; 1221 } 1222 } 1223 1224 /* Restore the autopoll bit if necessary. */ 1225 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1226 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1227 DELAY(80); 1228 } 1229 1230 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1231 1232 if (i == BGE_TIMEOUT) 1233 device_printf(sc->bge_dev, 1234 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1235 phy, reg, val); 1236 1237 return (0); 1238} 1239 1240static void 1241bge_miibus_statchg(device_t dev) 1242{ 1243 struct bge_softc *sc; 1244 struct mii_data *mii; 1245 uint32_t mac_mode, rx_mode, tx_mode; 1246 1247 sc = device_get_softc(dev); 1248 if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1249 return; 1250 mii = device_get_softc(sc->bge_miibus); 1251 1252 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1253 (IFM_ACTIVE | IFM_AVALID)) { 1254 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1255 case IFM_10_T: 1256 case IFM_100_TX: 1257 sc->bge_link = 1; 1258 break; 1259 case IFM_1000_T: 1260 case IFM_1000_SX: 1261 case IFM_2500_SX: 1262 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1263 sc->bge_link = 1; 1264 else 1265 sc->bge_link = 0; 1266 break; 1267 default: 1268 sc->bge_link = 0; 1269 break; 1270 } 1271 } else 1272 sc->bge_link = 0; 1273 if (sc->bge_link == 0) 1274 return; 1275 1276 /* 1277 * APE firmware touches these registers to keep the MAC 1278 * connected to the outside world. Try to keep the 1279 * accesses atomic. 1280 */ 1281 1282 /* Set the port mode (MII/GMII) to match the link speed. */ 1283 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1284 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1285 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1286 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1287 1288 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1289 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1290 mac_mode |= BGE_PORTMODE_GMII; 1291 else 1292 mac_mode |= BGE_PORTMODE_MII; 1293 1294 /* Set MAC flow control behavior to match link flow control settings. */ 1295 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1296 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1297 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1298 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1299 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1300 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1301 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1302 } else 1303 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1304 1305 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1306 DELAY(40); 1307 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1308 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1309} 1310 1311/* 1312 * Intialize a standard receive ring descriptor. 1313 */ 1314static int 1315bge_newbuf_std(struct bge_softc *sc, int i) 1316{ 1317 struct mbuf *m; 1318 struct bge_rx_bd *r; 1319 bus_dma_segment_t segs[1]; 1320 bus_dmamap_t map; 1321 int error, nsegs; 1322 1323 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1324 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1325 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1326 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1327 if (m == NULL) 1328 return (ENOBUFS); 1329 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1330 } else { 1331 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1332 if (m == NULL) 1333 return (ENOBUFS); 1334 m->m_len = m->m_pkthdr.len = MCLBYTES; 1335 } 1336 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1337 m_adj(m, ETHER_ALIGN); 1338 1339 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1340 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1341 if (error != 0) { 1342 m_freem(m); 1343 return (error); 1344 } 1345 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1346 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1347 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1348 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1349 sc->bge_cdata.bge_rx_std_dmamap[i]); 1350 } 1351 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1352 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1353 sc->bge_cdata.bge_rx_std_sparemap = map; 1354 sc->bge_cdata.bge_rx_std_chain[i] = m; 1355 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1356 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1357 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1358 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1359 r->bge_flags = BGE_RXBDFLAG_END; 1360 r->bge_len = segs[0].ds_len; 1361 r->bge_idx = i; 1362 1363 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1364 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1365 1366 return (0); 1367} 1368 1369/* 1370 * Initialize a jumbo receive ring descriptor. This allocates 1371 * a jumbo buffer from the pool managed internally by the driver. 1372 */ 1373static int 1374bge_newbuf_jumbo(struct bge_softc *sc, int i) 1375{ 1376 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1377 bus_dmamap_t map; 1378 struct bge_extrx_bd *r; 1379 struct mbuf *m; 1380 int error, nsegs; 1381 1382 MGETHDR(m, M_NOWAIT, MT_DATA); 1383 if (m == NULL) 1384 return (ENOBUFS); 1385 1386 m_cljget(m, M_NOWAIT, MJUM9BYTES); 1387 if (!(m->m_flags & M_EXT)) { 1388 m_freem(m); 1389 return (ENOBUFS); 1390 } 1391 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1392 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1393 m_adj(m, ETHER_ALIGN); 1394 1395 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1396 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1397 if (error != 0) { 1398 m_freem(m); 1399 return (error); 1400 } 1401 1402 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1403 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1404 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1405 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1406 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1407 } 1408 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1409 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1410 sc->bge_cdata.bge_rx_jumbo_sparemap; 1411 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1412 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1413 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1414 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1415 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1416 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1417 1418 /* 1419 * Fill in the extended RX buffer descriptor. 1420 */ 1421 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1422 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1423 r->bge_idx = i; 1424 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1425 switch (nsegs) { 1426 case 4: 1427 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1428 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1429 r->bge_len3 = segs[3].ds_len; 1430 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1431 case 3: 1432 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1433 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1434 r->bge_len2 = segs[2].ds_len; 1435 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1436 case 2: 1437 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1438 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1439 r->bge_len1 = segs[1].ds_len; 1440 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1441 case 1: 1442 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1443 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1444 r->bge_len0 = segs[0].ds_len; 1445 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1446 break; 1447 default: 1448 panic("%s: %d segments\n", __func__, nsegs); 1449 } 1450 1451 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1452 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1453 1454 return (0); 1455} 1456 1457static int 1458bge_init_rx_ring_std(struct bge_softc *sc) 1459{ 1460 int error, i; 1461 1462 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1463 sc->bge_std = 0; 1464 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1465 if ((error = bge_newbuf_std(sc, i)) != 0) 1466 return (error); 1467 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1468 } 1469 1470 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1471 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1472 1473 sc->bge_std = 0; 1474 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1475 1476 return (0); 1477} 1478 1479static void 1480bge_free_rx_ring_std(struct bge_softc *sc) 1481{ 1482 int i; 1483 1484 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1485 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1486 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1487 sc->bge_cdata.bge_rx_std_dmamap[i], 1488 BUS_DMASYNC_POSTREAD); 1489 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1490 sc->bge_cdata.bge_rx_std_dmamap[i]); 1491 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1492 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1493 } 1494 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1495 sizeof(struct bge_rx_bd)); 1496 } 1497} 1498 1499static int 1500bge_init_rx_ring_jumbo(struct bge_softc *sc) 1501{ 1502 struct bge_rcb *rcb; 1503 int error, i; 1504 1505 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1506 sc->bge_jumbo = 0; 1507 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1508 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1509 return (error); 1510 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1511 } 1512 1513 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1514 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1515 1516 sc->bge_jumbo = 0; 1517 1518 /* Enable the jumbo receive producer ring. */ 1519 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1520 rcb->bge_maxlen_flags = 1521 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1522 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1523 1524 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1525 1526 return (0); 1527} 1528 1529static void 1530bge_free_rx_ring_jumbo(struct bge_softc *sc) 1531{ 1532 int i; 1533 1534 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1535 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1536 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1537 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1538 BUS_DMASYNC_POSTREAD); 1539 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1540 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1541 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1542 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1543 } 1544 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1545 sizeof(struct bge_extrx_bd)); 1546 } 1547} 1548 1549static void 1550bge_free_tx_ring(struct bge_softc *sc) 1551{ 1552 int i; 1553 1554 if (sc->bge_ldata.bge_tx_ring == NULL) 1555 return; 1556 1557 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1558 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1559 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1560 sc->bge_cdata.bge_tx_dmamap[i], 1561 BUS_DMASYNC_POSTWRITE); 1562 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1563 sc->bge_cdata.bge_tx_dmamap[i]); 1564 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1565 sc->bge_cdata.bge_tx_chain[i] = NULL; 1566 } 1567 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1568 sizeof(struct bge_tx_bd)); 1569 } 1570} 1571 1572static int 1573bge_init_tx_ring(struct bge_softc *sc) 1574{ 1575 sc->bge_txcnt = 0; 1576 sc->bge_tx_saved_considx = 0; 1577 1578 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1579 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1580 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1581 1582 /* Initialize transmit producer index for host-memory send ring. */ 1583 sc->bge_tx_prodidx = 0; 1584 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1585 1586 /* 5700 b2 errata */ 1587 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1588 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1589 1590 /* NIC-memory send ring not used; initialize to zero. */ 1591 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1592 /* 5700 b2 errata */ 1593 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1594 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1595 1596 return (0); 1597} 1598 1599static void 1600bge_setpromisc(struct bge_softc *sc) 1601{ 1602 struct ifnet *ifp; 1603 1604 BGE_LOCK_ASSERT(sc); 1605 1606 ifp = sc->bge_ifp; 1607 1608 /* Enable or disable promiscuous mode as needed. */ 1609 if (ifp->if_flags & IFF_PROMISC) 1610 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1611 else 1612 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1613} 1614 1615static void 1616bge_setmulti(struct bge_softc *sc) 1617{ 1618 struct ifnet *ifp; 1619 struct ifmultiaddr *ifma; 1620 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1621 int h, i; 1622 1623 BGE_LOCK_ASSERT(sc); 1624 1625 ifp = sc->bge_ifp; 1626 1627 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1628 for (i = 0; i < 4; i++) 1629 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1630 return; 1631 } 1632 1633 /* First, zot all the existing filters. */ 1634 for (i = 0; i < 4; i++) 1635 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1636 1637 /* Now program new ones. */ 1638 if_maddr_rlock(ifp); 1639 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1640 if (ifma->ifma_addr->sa_family != AF_LINK) 1641 continue; 1642 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1643 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1644 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1645 } 1646 if_maddr_runlock(ifp); 1647 1648 for (i = 0; i < 4; i++) 1649 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1650} 1651 1652static void 1653bge_setvlan(struct bge_softc *sc) 1654{ 1655 struct ifnet *ifp; 1656 1657 BGE_LOCK_ASSERT(sc); 1658 1659 ifp = sc->bge_ifp; 1660 1661 /* Enable or disable VLAN tag stripping as needed. */ 1662 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1663 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1664 else 1665 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1666} 1667 1668static void 1669bge_sig_pre_reset(struct bge_softc *sc, int type) 1670{ 1671 1672 /* 1673 * Some chips don't like this so only do this if ASF is enabled 1674 */ 1675 if (sc->bge_asf_mode) 1676 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1677 1678 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1679 switch (type) { 1680 case BGE_RESET_START: 1681 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1682 BGE_FW_DRV_STATE_START); 1683 break; 1684 case BGE_RESET_SHUTDOWN: 1685 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1686 BGE_FW_DRV_STATE_UNLOAD); 1687 break; 1688 case BGE_RESET_SUSPEND: 1689 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1690 BGE_FW_DRV_STATE_SUSPEND); 1691 break; 1692 } 1693 } 1694 1695 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1696 bge_ape_driver_state_change(sc, type); 1697} 1698 1699static void 1700bge_sig_post_reset(struct bge_softc *sc, int type) 1701{ 1702 1703 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1704 switch (type) { 1705 case BGE_RESET_START: 1706 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1707 BGE_FW_DRV_STATE_START_DONE); 1708 /* START DONE */ 1709 break; 1710 case BGE_RESET_SHUTDOWN: 1711 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1712 BGE_FW_DRV_STATE_UNLOAD_DONE); 1713 break; 1714 } 1715 } 1716 if (type == BGE_RESET_SHUTDOWN) 1717 bge_ape_driver_state_change(sc, type); 1718} 1719 1720static void 1721bge_sig_legacy(struct bge_softc *sc, int type) 1722{ 1723 1724 if (sc->bge_asf_mode) { 1725 switch (type) { 1726 case BGE_RESET_START: 1727 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1728 BGE_FW_DRV_STATE_START); 1729 break; 1730 case BGE_RESET_SHUTDOWN: 1731 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1732 BGE_FW_DRV_STATE_UNLOAD); 1733 break; 1734 } 1735 } 1736} 1737 1738static void 1739bge_stop_fw(struct bge_softc *sc) 1740{ 1741 int i; 1742 1743 if (sc->bge_asf_mode) { 1744 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1745 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1746 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1747 1748 for (i = 0; i < 100; i++ ) { 1749 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1750 BGE_RX_CPU_DRV_EVENT)) 1751 break; 1752 DELAY(10); 1753 } 1754 } 1755} 1756 1757static uint32_t 1758bge_dma_swap_options(struct bge_softc *sc) 1759{ 1760 uint32_t dma_options; 1761 1762 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1763 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1764#if BYTE_ORDER == BIG_ENDIAN 1765 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1766#endif 1767 return (dma_options); 1768} 1769 1770/* 1771 * Do endian, PCI and DMA initialization. 1772 */ 1773static int 1774bge_chipinit(struct bge_softc *sc) 1775{ 1776 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1777 uint16_t val; 1778 int i; 1779 1780 /* Set endianness before we access any non-PCI registers. */ 1781 misc_ctl = BGE_INIT; 1782 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1783 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1784 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1785 1786 /* 1787 * Clear the MAC statistics block in the NIC's 1788 * internal memory. 1789 */ 1790 for (i = BGE_STATS_BLOCK; 1791 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1792 BGE_MEMWIN_WRITE(sc, i, 0); 1793 1794 for (i = BGE_STATUS_BLOCK; 1795 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1796 BGE_MEMWIN_WRITE(sc, i, 0); 1797 1798 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1799 /* 1800 * Fix data corruption caused by non-qword write with WB. 1801 * Fix master abort in PCI mode. 1802 * Fix PCI latency timer. 1803 */ 1804 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1805 val |= (1 << 10) | (1 << 12) | (1 << 13); 1806 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1807 } 1808 1809 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 || 1810 sc->bge_asicrev == BGE_ASICREV_BCM57766) { 1811 /* 1812 * For the 57766 and non Ax versions of 57765, bootcode 1813 * needs to setup the PCIE Fast Training Sequence (FTS) 1814 * value to prevent transmit hangs. 1815 */ 1816 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) { 1817 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1818 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | 1819 BGE_CPMU_PADRNG_CTL_RDIV2); 1820 } 1821 } 1822 1823 /* 1824 * Set up the PCI DMA control register. 1825 */ 1826 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1827 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1828 if (sc->bge_flags & BGE_FLAG_PCIE) { 1829 if (sc->bge_mps >= 256) 1830 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1831 else 1832 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1833 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1834 if (BGE_IS_5714_FAMILY(sc)) { 1835 /* 256 bytes for read and write. */ 1836 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1837 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1838 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1839 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1840 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1841 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1842 /* 1843 * In the BCM5703, the DMA read watermark should 1844 * be set to less than or equal to the maximum 1845 * memory read byte count of the PCI-X command 1846 * register. 1847 */ 1848 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1849 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1850 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1851 /* 1536 bytes for read, 384 bytes for write. */ 1852 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1853 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1854 } else { 1855 /* 384 bytes for read and write. */ 1856 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1857 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1858 0x0F; 1859 } 1860 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1861 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1862 uint32_t tmp; 1863 1864 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1865 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1866 if (tmp == 6 || tmp == 7) 1867 dma_rw_ctl |= 1868 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1869 1870 /* Set PCI-X DMA write workaround. */ 1871 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1872 } 1873 } else { 1874 /* Conventional PCI bus: 256 bytes for read and write. */ 1875 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1876 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1877 1878 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1879 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1880 dma_rw_ctl |= 0x0F; 1881 } 1882 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1883 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1884 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1885 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1886 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1887 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1888 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1889 if (BGE_IS_5717_PLUS(sc)) { 1890 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1891 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1892 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1893 /* 1894 * Enable HW workaround for controllers that misinterpret 1895 * a status tag update and leave interrupts permanently 1896 * disabled. 1897 */ 1898 if (!BGE_IS_57765_PLUS(sc) && 1899 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1900 sc->bge_asicrev != BGE_ASICREV_BCM5762) 1901 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1902 } 1903 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1904 1905 /* 1906 * Set up general mode register. 1907 */ 1908 mode_ctl = bge_dma_swap_options(sc); 1909 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 1910 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 1911 /* Retain Host-2-BMC settings written by APE firmware. */ 1912 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1913 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1914 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1915 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1916 } 1917 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1918 BGE_MODECTL_TX_NO_PHDR_CSUM; 1919 1920 /* 1921 * BCM5701 B5 have a bug causing data corruption when using 1922 * 64-bit DMA reads, which can be terminated early and then 1923 * completed later as 32-bit accesses, in combination with 1924 * certain bridges. 1925 */ 1926 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1927 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1928 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1929 1930 /* 1931 * Tell the firmware the driver is running 1932 */ 1933 if (sc->bge_asf_mode & ASF_STACKUP) 1934 mode_ctl |= BGE_MODECTL_STACKUP; 1935 1936 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1937 1938 /* 1939 * Disable memory write invalidate. Apparently it is not supported 1940 * properly by these devices. Also ensure that INTx isn't disabled, 1941 * as these chips need it even when using MSI. 1942 */ 1943 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1944 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1945 1946 /* Set the timer prescaler (always 66 MHz). */ 1947 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1948 1949 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1950 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1951 DELAY(40); /* XXX */ 1952 1953 /* Put PHY into ready state */ 1954 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1955 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1956 DELAY(40); 1957 } 1958 1959 return (0); 1960} 1961 1962static int 1963bge_blockinit(struct bge_softc *sc) 1964{ 1965 struct bge_rcb *rcb; 1966 bus_size_t vrcb; 1967 bge_hostaddr taddr; 1968 uint32_t dmactl, rdmareg, val; 1969 int i, limit; 1970 1971 /* 1972 * Initialize the memory window pointer register so that 1973 * we can access the first 32K of internal NIC RAM. This will 1974 * allow us to set up the TX send ring RCBs and the RX return 1975 * ring RCBs, plus other things which live in NIC memory. 1976 */ 1977 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1978 1979 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1980 1981 if (!(BGE_IS_5705_PLUS(sc))) { 1982 /* Configure mbuf memory pool */ 1983 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1984 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1985 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1986 else 1987 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1988 1989 /* Configure DMA resource pool */ 1990 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1991 BGE_DMA_DESCRIPTORS); 1992 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1993 } 1994 1995 /* Configure mbuf pool watermarks */ 1996 if (BGE_IS_5717_PLUS(sc)) { 1997 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1998 if (sc->bge_ifp->if_mtu > ETHERMTU) { 1999 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2000 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2001 } else { 2002 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2003 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2004 } 2005 } else if (!BGE_IS_5705_PLUS(sc)) { 2006 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2007 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2008 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2009 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2010 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2011 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2012 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2013 } else { 2014 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2015 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2016 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2017 } 2018 2019 /* Configure DMA resource watermarks */ 2020 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2021 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2022 2023 /* Enable buffer manager */ 2024 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 2025 /* 2026 * Change the arbitration algorithm of TXMBUF read request to 2027 * round-robin instead of priority based for BCM5719. When 2028 * TXFIFO is almost empty, RDMA will hold its request until 2029 * TXFIFO is not almost empty. 2030 */ 2031 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2032 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2033 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2034 2035 /* Poll for buffer manager start indication */ 2036 for (i = 0; i < BGE_TIMEOUT; i++) { 2037 DELAY(10); 2038 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2039 break; 2040 } 2041 2042 if (i == BGE_TIMEOUT) { 2043 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 2044 return (ENXIO); 2045 } 2046 2047 /* Enable flow-through queues */ 2048 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2049 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2050 2051 /* Wait until queue initialization is complete */ 2052 for (i = 0; i < BGE_TIMEOUT; i++) { 2053 DELAY(10); 2054 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2055 break; 2056 } 2057 2058 if (i == BGE_TIMEOUT) { 2059 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 2060 return (ENXIO); 2061 } 2062 2063 /* 2064 * Summary of rings supported by the controller: 2065 * 2066 * Standard Receive Producer Ring 2067 * - This ring is used to feed receive buffers for "standard" 2068 * sized frames (typically 1536 bytes) to the controller. 2069 * 2070 * Jumbo Receive Producer Ring 2071 * - This ring is used to feed receive buffers for jumbo sized 2072 * frames (i.e. anything bigger than the "standard" frames) 2073 * to the controller. 2074 * 2075 * Mini Receive Producer Ring 2076 * - This ring is used to feed receive buffers for "mini" 2077 * sized frames to the controller. 2078 * - This feature required external memory for the controller 2079 * but was never used in a production system. Should always 2080 * be disabled. 2081 * 2082 * Receive Return Ring 2083 * - After the controller has placed an incoming frame into a 2084 * receive buffer that buffer is moved into a receive return 2085 * ring. The driver is then responsible to passing the 2086 * buffer up to the stack. Many versions of the controller 2087 * support multiple RR rings. 2088 * 2089 * Send Ring 2090 * - This ring is used for outgoing frames. Many versions of 2091 * the controller support multiple send rings. 2092 */ 2093 2094 /* Initialize the standard receive producer ring control block. */ 2095 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2096 rcb->bge_hostaddr.bge_addr_lo = 2097 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2098 rcb->bge_hostaddr.bge_addr_hi = 2099 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2100 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2101 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 2102 if (BGE_IS_5717_PLUS(sc)) { 2103 /* 2104 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2105 * Bits 15-2 : Maximum RX frame size 2106 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2107 * Bit 0 : Reserved 2108 */ 2109 rcb->bge_maxlen_flags = 2110 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2111 } else if (BGE_IS_5705_PLUS(sc)) { 2112 /* 2113 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2114 * Bits 15-2 : Reserved (should be 0) 2115 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2116 * Bit 0 : Reserved 2117 */ 2118 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2119 } else { 2120 /* 2121 * Ring size is always XXX entries 2122 * Bits 31-16: Maximum RX frame size 2123 * Bits 15-2 : Reserved (should be 0) 2124 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2125 * Bit 0 : Reserved 2126 */ 2127 rcb->bge_maxlen_flags = 2128 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2129 } 2130 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2131 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2132 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2133 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2134 else 2135 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2136 /* Write the standard receive producer ring control block. */ 2137 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2138 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2139 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2140 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2141 2142 /* Reset the standard receive producer ring producer index. */ 2143 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2144 2145 /* 2146 * Initialize the jumbo RX producer ring control 2147 * block. We set the 'ring disabled' bit in the 2148 * flags field until we're actually ready to start 2149 * using this ring (i.e. once we set the MTU 2150 * high enough to require it). 2151 */ 2152 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2153 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 2154 /* Get the jumbo receive producer ring RCB parameters. */ 2155 rcb->bge_hostaddr.bge_addr_lo = 2156 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2157 rcb->bge_hostaddr.bge_addr_hi = 2158 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2159 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2160 sc->bge_cdata.bge_rx_jumbo_ring_map, 2161 BUS_DMASYNC_PREREAD); 2162 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2163 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2164 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2165 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2166 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2167 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2168 else 2169 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2170 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2171 rcb->bge_hostaddr.bge_addr_hi); 2172 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2173 rcb->bge_hostaddr.bge_addr_lo); 2174 /* Program the jumbo receive producer ring RCB parameters. */ 2175 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2176 rcb->bge_maxlen_flags); 2177 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2178 /* Reset the jumbo receive producer ring producer index. */ 2179 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2180 } 2181 2182 /* Disable the mini receive producer ring RCB. */ 2183 if (BGE_IS_5700_FAMILY(sc)) { 2184 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 2185 rcb->bge_maxlen_flags = 2186 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2187 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2188 rcb->bge_maxlen_flags); 2189 /* Reset the mini receive producer ring producer index. */ 2190 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2191 } 2192 2193 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2194 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2195 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2196 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2197 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2198 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2199 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2200 } 2201 /* 2202 * The BD ring replenish thresholds control how often the 2203 * hardware fetches new BD's from the producer rings in host 2204 * memory. Setting the value too low on a busy system can 2205 * starve the hardware and recue the throughpout. 2206 * 2207 * Set the BD ring replentish thresholds. The recommended 2208 * values are 1/8th the number of descriptors allocated to 2209 * each ring. 2210 * XXX The 5754 requires a lower threshold, so it might be a 2211 * requirement of all 575x family chips. The Linux driver sets 2212 * the lower threshold for all 5705 family chips as well, but there 2213 * are reports that it might not need to be so strict. 2214 * 2215 * XXX Linux does some extra fiddling here for the 5906 parts as 2216 * well. 2217 */ 2218 if (BGE_IS_5705_PLUS(sc)) 2219 val = 8; 2220 else 2221 val = BGE_STD_RX_RING_CNT / 8; 2222 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 2223 if (BGE_IS_JUMBO_CAPABLE(sc)) 2224 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 2225 BGE_JUMBO_RX_RING_CNT/8); 2226 if (BGE_IS_5717_PLUS(sc)) { 2227 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 2228 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 2229 } 2230 2231 /* 2232 * Disable all send rings by setting the 'ring disabled' bit 2233 * in the flags field of all the TX send ring control blocks, 2234 * located in NIC memory. 2235 */ 2236 if (!BGE_IS_5705_PLUS(sc)) 2237 /* 5700 to 5704 had 16 send rings. */ 2238 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2239 else if (BGE_IS_57765_PLUS(sc) || 2240 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2241 limit = 2; 2242 else if (BGE_IS_5717_PLUS(sc)) 2243 limit = 4; 2244 else 2245 limit = 1; 2246 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2247 for (i = 0; i < limit; i++) { 2248 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2249 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2250 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2251 vrcb += sizeof(struct bge_rcb); 2252 } 2253 2254 /* Configure send ring RCB 0 (we use only the first ring) */ 2255 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2256 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2257 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2258 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2259 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2260 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2261 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2262 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 2263 else 2264 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2265 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2266 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2267 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2268 2269 /* 2270 * Disable all receive return rings by setting the 2271 * 'ring diabled' bit in the flags field of all the receive 2272 * return ring control blocks, located in NIC memory. 2273 */ 2274 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2275 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2276 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2277 /* Should be 17, use 16 until we get an SRAM map. */ 2278 limit = 16; 2279 } else if (!BGE_IS_5705_PLUS(sc)) 2280 limit = BGE_RX_RINGS_MAX; 2281 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2282 sc->bge_asicrev == BGE_ASICREV_BCM5762 || 2283 BGE_IS_57765_PLUS(sc)) 2284 limit = 4; 2285 else 2286 limit = 1; 2287 /* Disable all receive return rings. */ 2288 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2289 for (i = 0; i < limit; i++) { 2290 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2291 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2292 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2293 BGE_RCB_FLAG_RING_DISABLED); 2294 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2295 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2296 (i * (sizeof(uint64_t))), 0); 2297 vrcb += sizeof(struct bge_rcb); 2298 } 2299 2300 /* 2301 * Set up receive return ring 0. Note that the NIC address 2302 * for RX return rings is 0x0. The return rings live entirely 2303 * within the host, so the nicaddr field in the RCB isn't used. 2304 */ 2305 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2306 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2307 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2308 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2309 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2310 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2311 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2312 2313 /* Set random backoff seed for TX */ 2314 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2315 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 2316 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 2317 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) & 2318 BGE_TX_BACKOFF_SEED_MASK); 2319 2320 /* Set inter-packet gap */ 2321 val = 0x2620; 2322 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2323 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2324 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2325 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2326 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2327 2328 /* 2329 * Specify which ring to use for packets that don't match 2330 * any RX rules. 2331 */ 2332 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2333 2334 /* 2335 * Configure number of RX lists. One interrupt distribution 2336 * list, sixteen active lists, one bad frames class. 2337 */ 2338 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2339 2340 /* Inialize RX list placement stats mask. */ 2341 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2342 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2343 2344 /* Disable host coalescing until we get it set up */ 2345 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2346 2347 /* Poll to make sure it's shut down. */ 2348 for (i = 0; i < BGE_TIMEOUT; i++) { 2349 DELAY(10); 2350 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2351 break; 2352 } 2353 2354 if (i == BGE_TIMEOUT) { 2355 device_printf(sc->bge_dev, 2356 "host coalescing engine failed to idle\n"); 2357 return (ENXIO); 2358 } 2359 2360 /* Set up host coalescing defaults */ 2361 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2362 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2363 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2364 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2365 if (!(BGE_IS_5705_PLUS(sc))) { 2366 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2367 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2368 } 2369 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2370 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 2371 2372 /* Set up address of statistics block */ 2373 if (!(BGE_IS_5705_PLUS(sc))) { 2374 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2375 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 2376 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2377 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 2378 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2379 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2380 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2381 } 2382 2383 /* Set up address of status block */ 2384 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2385 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 2386 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2387 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2388 2389 /* Set up status block size. */ 2390 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2391 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2392 val = BGE_STATBLKSZ_FULL; 2393 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2394 } else { 2395 val = BGE_STATBLKSZ_32BYTE; 2396 bzero(sc->bge_ldata.bge_status_block, 32); 2397 } 2398 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2399 sc->bge_cdata.bge_status_map, 2400 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2401 2402 /* Turn on host coalescing state machine */ 2403 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2404 2405 /* Turn on RX BD completion state machine and enable attentions */ 2406 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2407 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2408 2409 /* Turn on RX list placement state machine */ 2410 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2411 2412 /* Turn on RX list selector state machine. */ 2413 if (!(BGE_IS_5705_PLUS(sc))) 2414 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2415 2416 /* Turn on DMA, clear stats. */ 2417 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2418 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2419 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2420 BGE_MACMODE_FRMHDR_DMA_ENB; 2421 2422 if (sc->bge_flags & BGE_FLAG_TBI) 2423 val |= BGE_PORTMODE_TBI; 2424 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2425 val |= BGE_PORTMODE_GMII; 2426 else 2427 val |= BGE_PORTMODE_MII; 2428 2429 /* Allow APE to send/receive frames. */ 2430 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2431 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2432 2433 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2434 DELAY(40); 2435 2436 /* Set misc. local control, enable interrupts on attentions */ 2437 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2438 2439#ifdef notdef 2440 /* Assert GPIO pins for PHY reset */ 2441 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2442 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2443 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2444 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2445#endif 2446 2447 /* Turn on DMA completion state machine */ 2448 if (!(BGE_IS_5705_PLUS(sc))) 2449 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2450 2451 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2452 2453 /* Enable host coalescing bug fix. */ 2454 if (BGE_IS_5755_PLUS(sc)) 2455 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2456 2457 /* Request larger DMA burst size to get better performance. */ 2458 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2459 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2460 2461 /* Turn on write DMA state machine */ 2462 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2463 DELAY(40); 2464 2465 /* Turn on read DMA state machine */ 2466 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2467 2468 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2469 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2470 2471 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2472 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2473 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2474 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2475 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2476 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2477 if (sc->bge_flags & BGE_FLAG_PCIE) 2478 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2479 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2480 val |= BGE_RDMAMODE_TSO4_ENABLE; 2481 if (sc->bge_flags & BGE_FLAG_TSO3 || 2482 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2483 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2484 val |= BGE_RDMAMODE_TSO6_ENABLE; 2485 } 2486 2487 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2488 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2489 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2490 BGE_RDMAMODE_H2BNC_VLAN_DET; 2491 /* 2492 * Allow multiple outstanding read requests from 2493 * non-LSO read DMA engine. 2494 */ 2495 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2496 } 2497 2498 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2499 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2500 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2501 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2502 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) { 2503 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 2504 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2505 else 2506 rdmareg = BGE_RDMA_RSRVCTRL; 2507 dmactl = CSR_READ_4(sc, rdmareg); 2508 /* 2509 * Adjust tx margin to prevent TX data corruption and 2510 * fix internal FIFO overflow. 2511 */ 2512 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2513 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2514 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2515 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2516 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2517 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2518 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2519 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2520 } 2521 /* 2522 * Enable fix for read DMA FIFO overruns. 2523 * The fix is to limit the number of RX BDs 2524 * the hardware would fetch at a fime. 2525 */ 2526 CSR_WRITE_4(sc, rdmareg, dmactl | 2527 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2528 } 2529 2530 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2531 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2532 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2533 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2534 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2535 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2536 /* 2537 * Allow 4KB burst length reads for non-LSO frames. 2538 * Enable 512B burst length reads for buffer descriptors. 2539 */ 2540 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2541 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2542 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2543 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2544 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2545 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2546 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2547 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2548 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2549 } 2550 2551 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2552 DELAY(40); 2553 2554 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 2555 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2556 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2557 if ((val & 0xFFFF) > BGE_FRAMELEN) 2558 break; 2559 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2560 break; 2561 } 2562 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2563 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2564 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2565 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2566 else 2567 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2568 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2569 } 2570 } 2571 2572 /* Turn on RX data completion state machine */ 2573 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2574 2575 /* Turn on RX BD initiator state machine */ 2576 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2577 2578 /* Turn on RX data and RX BD initiator state machine */ 2579 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2580 2581 /* Turn on Mbuf cluster free state machine */ 2582 if (!(BGE_IS_5705_PLUS(sc))) 2583 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2584 2585 /* Turn on send BD completion state machine */ 2586 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2587 2588 /* Turn on send data completion state machine */ 2589 val = BGE_SDCMODE_ENABLE; 2590 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2591 val |= BGE_SDCMODE_CDELAY; 2592 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2593 2594 /* Turn on send data initiator state machine */ 2595 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2596 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2597 BGE_SDIMODE_HW_LSO_PRE_DMA); 2598 else 2599 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2600 2601 /* Turn on send BD initiator state machine */ 2602 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2603 2604 /* Turn on send BD selector state machine */ 2605 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2606 2607 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2608 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2609 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2610 2611 /* ack/clear link change events */ 2612 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2613 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2614 BGE_MACSTAT_LINK_CHANGED); 2615 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2616 2617 /* 2618 * Enable attention when the link has changed state for 2619 * devices that use auto polling. 2620 */ 2621 if (sc->bge_flags & BGE_FLAG_TBI) { 2622 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2623 } else { 2624 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2625 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2626 DELAY(80); 2627 } 2628 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2629 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2630 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2631 BGE_EVTENB_MI_INTERRUPT); 2632 } 2633 2634 /* 2635 * Clear any pending link state attention. 2636 * Otherwise some link state change events may be lost until attention 2637 * is cleared by bge_intr() -> bge_link_upd() sequence. 2638 * It's not necessary on newer BCM chips - perhaps enabling link 2639 * state change attentions implies clearing pending attention. 2640 */ 2641 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2642 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2643 BGE_MACSTAT_LINK_CHANGED); 2644 2645 /* Enable link state change attentions. */ 2646 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2647 2648 return (0); 2649} 2650 2651static const struct bge_revision * 2652bge_lookup_rev(uint32_t chipid) 2653{ 2654 const struct bge_revision *br; 2655 2656 for (br = bge_revisions; br->br_name != NULL; br++) { 2657 if (br->br_chipid == chipid) 2658 return (br); 2659 } 2660 2661 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2662 if (br->br_chipid == BGE_ASICREV(chipid)) 2663 return (br); 2664 } 2665 2666 return (NULL); 2667} 2668 2669static const struct bge_vendor * 2670bge_lookup_vendor(uint16_t vid) 2671{ 2672 const struct bge_vendor *v; 2673 2674 for (v = bge_vendors; v->v_name != NULL; v++) 2675 if (v->v_id == vid) 2676 return (v); 2677 2678 return (NULL); 2679} 2680 2681static uint32_t 2682bge_chipid(device_t dev) 2683{ 2684 uint32_t id; 2685 2686 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2687 BGE_PCIMISCCTL_ASICREV_SHIFT; 2688 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2689 /* 2690 * Find the ASCI revision. Different chips use different 2691 * registers. 2692 */ 2693 switch (pci_get_device(dev)) { 2694 case BCOM_DEVICEID_BCM5717: 2695 case BCOM_DEVICEID_BCM5718: 2696 case BCOM_DEVICEID_BCM5719: 2697 case BCOM_DEVICEID_BCM5720: 2698 case BCOM_DEVICEID_BCM5725: 2699 case BCOM_DEVICEID_BCM5727: 2700 case BCOM_DEVICEID_BCM5762: 2701 case BCOM_DEVICEID_BCM57764: 2702 case BCOM_DEVICEID_BCM57767: 2703 case BCOM_DEVICEID_BCM57787: 2704 id = pci_read_config(dev, 2705 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2706 break; 2707 case BCOM_DEVICEID_BCM57761: 2708 case BCOM_DEVICEID_BCM57762: 2709 case BCOM_DEVICEID_BCM57765: 2710 case BCOM_DEVICEID_BCM57766: 2711 case BCOM_DEVICEID_BCM57781: 2712 case BCOM_DEVICEID_BCM57782: 2713 case BCOM_DEVICEID_BCM57785: 2714 case BCOM_DEVICEID_BCM57786: 2715 case BCOM_DEVICEID_BCM57791: 2716 case BCOM_DEVICEID_BCM57795: 2717 id = pci_read_config(dev, 2718 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2719 break; 2720 default: 2721 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2722 } 2723 } 2724 return (id); 2725} 2726 2727/* 2728 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2729 * against our list and return its name if we find a match. 2730 * 2731 * Note that since the Broadcom controller contains VPD support, we 2732 * try to get the device name string from the controller itself instead 2733 * of the compiled-in string. It guarantees we'll always announce the 2734 * right product name. We fall back to the compiled-in string when 2735 * VPD is unavailable or corrupt. 2736 */ 2737static int 2738bge_probe(device_t dev) 2739{ 2740 char buf[96]; 2741 char model[64]; 2742 const struct bge_revision *br; 2743 const char *pname; 2744 struct bge_softc *sc; 2745 const struct bge_type *t = bge_devs; 2746 const struct bge_vendor *v; 2747 uint32_t id; 2748 uint16_t did, vid; 2749 2750 sc = device_get_softc(dev); 2751 sc->bge_dev = dev; 2752 vid = pci_get_vendor(dev); 2753 did = pci_get_device(dev); 2754 while(t->bge_vid != 0) { 2755 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2756 id = bge_chipid(dev); 2757 br = bge_lookup_rev(id); 2758 if (bge_has_eaddr(sc) && 2759 pci_get_vpd_ident(dev, &pname) == 0) 2760 snprintf(model, sizeof(model), "%s", pname); 2761 else { 2762 v = bge_lookup_vendor(vid); 2763 snprintf(model, sizeof(model), "%s %s", 2764 v != NULL ? v->v_name : "Unknown", 2765 br != NULL ? br->br_name : 2766 "NetXtreme/NetLink Ethernet Controller"); 2767 } 2768 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", 2769 model, br != NULL ? "" : "unknown ", id); 2770 device_set_desc_copy(dev, buf); 2771 return (BUS_PROBE_DEFAULT); 2772 } 2773 t++; 2774 } 2775 2776 return (ENXIO); 2777} 2778 2779static void 2780bge_dma_free(struct bge_softc *sc) 2781{ 2782 int i; 2783 2784 /* Destroy DMA maps for RX buffers. */ 2785 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2786 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2787 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2788 sc->bge_cdata.bge_rx_std_dmamap[i]); 2789 } 2790 if (sc->bge_cdata.bge_rx_std_sparemap) 2791 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2792 sc->bge_cdata.bge_rx_std_sparemap); 2793 2794 /* Destroy DMA maps for jumbo RX buffers. */ 2795 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2796 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2797 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2798 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2799 } 2800 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2801 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2802 sc->bge_cdata.bge_rx_jumbo_sparemap); 2803 2804 /* Destroy DMA maps for TX buffers. */ 2805 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2806 if (sc->bge_cdata.bge_tx_dmamap[i]) 2807 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2808 sc->bge_cdata.bge_tx_dmamap[i]); 2809 } 2810 2811 if (sc->bge_cdata.bge_rx_mtag) 2812 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2813 if (sc->bge_cdata.bge_mtag_jumbo) 2814 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2815 if (sc->bge_cdata.bge_tx_mtag) 2816 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2817 2818 /* Destroy standard RX ring. */ 2819 if (sc->bge_cdata.bge_rx_std_ring_map) 2820 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2821 sc->bge_cdata.bge_rx_std_ring_map); 2822 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2823 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2824 sc->bge_ldata.bge_rx_std_ring, 2825 sc->bge_cdata.bge_rx_std_ring_map); 2826 2827 if (sc->bge_cdata.bge_rx_std_ring_tag) 2828 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2829 2830 /* Destroy jumbo RX ring. */ 2831 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2832 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2833 sc->bge_cdata.bge_rx_jumbo_ring_map); 2834 2835 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2836 sc->bge_ldata.bge_rx_jumbo_ring) 2837 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2838 sc->bge_ldata.bge_rx_jumbo_ring, 2839 sc->bge_cdata.bge_rx_jumbo_ring_map); 2840 2841 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2842 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2843 2844 /* Destroy RX return ring. */ 2845 if (sc->bge_cdata.bge_rx_return_ring_map) 2846 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2847 sc->bge_cdata.bge_rx_return_ring_map); 2848 2849 if (sc->bge_cdata.bge_rx_return_ring_map && 2850 sc->bge_ldata.bge_rx_return_ring) 2851 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2852 sc->bge_ldata.bge_rx_return_ring, 2853 sc->bge_cdata.bge_rx_return_ring_map); 2854 2855 if (sc->bge_cdata.bge_rx_return_ring_tag) 2856 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2857 2858 /* Destroy TX ring. */ 2859 if (sc->bge_cdata.bge_tx_ring_map) 2860 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2861 sc->bge_cdata.bge_tx_ring_map); 2862 2863 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2864 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2865 sc->bge_ldata.bge_tx_ring, 2866 sc->bge_cdata.bge_tx_ring_map); 2867 2868 if (sc->bge_cdata.bge_tx_ring_tag) 2869 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2870 2871 /* Destroy status block. */ 2872 if (sc->bge_cdata.bge_status_map) 2873 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2874 sc->bge_cdata.bge_status_map); 2875 2876 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2877 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2878 sc->bge_ldata.bge_status_block, 2879 sc->bge_cdata.bge_status_map); 2880 2881 if (sc->bge_cdata.bge_status_tag) 2882 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2883 2884 /* Destroy statistics block. */ 2885 if (sc->bge_cdata.bge_stats_map) 2886 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2887 sc->bge_cdata.bge_stats_map); 2888 2889 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2890 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2891 sc->bge_ldata.bge_stats, 2892 sc->bge_cdata.bge_stats_map); 2893 2894 if (sc->bge_cdata.bge_stats_tag) 2895 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2896 2897 if (sc->bge_cdata.bge_buffer_tag) 2898 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2899 2900 /* Destroy the parent tag. */ 2901 if (sc->bge_cdata.bge_parent_tag) 2902 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2903} 2904 2905static int 2906bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2907 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2908 bus_addr_t *paddr, const char *msg) 2909{ 2910 struct bge_dmamap_arg ctx; 2911 int error; 2912 2913 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2914 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2915 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2916 if (error != 0) { 2917 device_printf(sc->bge_dev, 2918 "could not create %s dma tag\n", msg); 2919 return (ENOMEM); 2920 } 2921 /* Allocate DMA'able memory for ring. */ 2922 error = bus_dmamem_alloc(*tag, (void **)ring, 2923 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2924 if (error != 0) { 2925 device_printf(sc->bge_dev, 2926 "could not allocate DMA'able memory for %s\n", msg); 2927 return (ENOMEM); 2928 } 2929 /* Load the address of the ring. */ 2930 ctx.bge_busaddr = 0; 2931 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2932 &ctx, BUS_DMA_NOWAIT); 2933 if (error != 0) { 2934 device_printf(sc->bge_dev, 2935 "could not load DMA'able memory for %s\n", msg); 2936 return (ENOMEM); 2937 } 2938 *paddr = ctx.bge_busaddr; 2939 return (0); 2940} 2941 2942static int 2943bge_dma_alloc(struct bge_softc *sc) 2944{ 2945 bus_addr_t lowaddr; 2946 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz; 2947 int i, error; 2948 2949 lowaddr = BUS_SPACE_MAXADDR; 2950 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2951 lowaddr = BGE_DMA_MAXADDR; 2952 /* 2953 * Allocate the parent bus DMA tag appropriate for PCI. 2954 */ 2955 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2956 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2957 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2958 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2959 if (error != 0) { 2960 device_printf(sc->bge_dev, 2961 "could not allocate parent dma tag\n"); 2962 return (ENOMEM); 2963 } 2964 2965 /* Create tag for standard RX ring. */ 2966 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2967 &sc->bge_cdata.bge_rx_std_ring_tag, 2968 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2969 &sc->bge_cdata.bge_rx_std_ring_map, 2970 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2971 if (error) 2972 return (error); 2973 2974 /* Create tag for RX return ring. */ 2975 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2976 &sc->bge_cdata.bge_rx_return_ring_tag, 2977 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2978 &sc->bge_cdata.bge_rx_return_ring_map, 2979 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2980 if (error) 2981 return (error); 2982 2983 /* Create tag for TX ring. */ 2984 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2985 &sc->bge_cdata.bge_tx_ring_tag, 2986 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2987 &sc->bge_cdata.bge_tx_ring_map, 2988 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2989 if (error) 2990 return (error); 2991 2992 /* 2993 * Create tag for status block. 2994 * Because we only use single Tx/Rx/Rx return ring, use 2995 * minimum status block size except BCM5700 AX/BX which 2996 * seems to want to see full status block size regardless 2997 * of configured number of ring. 2998 */ 2999 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3000 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 3001 sbsz = BGE_STATUS_BLK_SZ; 3002 else 3003 sbsz = 32; 3004 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 3005 &sc->bge_cdata.bge_status_tag, 3006 (uint8_t **)&sc->bge_ldata.bge_status_block, 3007 &sc->bge_cdata.bge_status_map, 3008 &sc->bge_ldata.bge_status_block_paddr, "status block"); 3009 if (error) 3010 return (error); 3011 3012 /* Create tag for statistics block. */ 3013 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 3014 &sc->bge_cdata.bge_stats_tag, 3015 (uint8_t **)&sc->bge_ldata.bge_stats, 3016 &sc->bge_cdata.bge_stats_map, 3017 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 3018 if (error) 3019 return (error); 3020 3021 /* Create tag for jumbo RX ring. */ 3022 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3023 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 3024 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 3025 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 3026 &sc->bge_cdata.bge_rx_jumbo_ring_map, 3027 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 3028 if (error) 3029 return (error); 3030 } 3031 3032 /* Create parent tag for buffers. */ 3033 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 3034 /* 3035 * XXX 3036 * watchdog timeout issue was observed on BCM5704 which 3037 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 3038 * Both limiting DMA address space to 32bits and flushing 3039 * mailbox write seem to address the issue. 3040 */ 3041 if (sc->bge_pcixcap != 0) 3042 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3043 } 3044 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr, 3045 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 3046 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3047 &sc->bge_cdata.bge_buffer_tag); 3048 if (error != 0) { 3049 device_printf(sc->bge_dev, 3050 "could not allocate buffer dma tag\n"); 3051 return (ENOMEM); 3052 } 3053 /* Create tag for Tx mbufs. */ 3054 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 3055 txsegsz = BGE_TSOSEG_SZ; 3056 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 3057 } else { 3058 txsegsz = MCLBYTES; 3059 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 3060 } 3061 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 3062 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 3063 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 3064 &sc->bge_cdata.bge_tx_mtag); 3065 3066 if (error) { 3067 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 3068 return (ENOMEM); 3069 } 3070 3071 /* Create tag for Rx mbufs. */ 3072 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 3073 rxmaxsegsz = MJUM9BYTES; 3074 else 3075 rxmaxsegsz = MCLBYTES; 3076 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 3077 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 3078 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 3079 3080 if (error) { 3081 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3082 return (ENOMEM); 3083 } 3084 3085 /* Create DMA maps for RX buffers. */ 3086 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3087 &sc->bge_cdata.bge_rx_std_sparemap); 3088 if (error) { 3089 device_printf(sc->bge_dev, 3090 "can't create spare DMA map for RX\n"); 3091 return (ENOMEM); 3092 } 3093 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 3094 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3095 &sc->bge_cdata.bge_rx_std_dmamap[i]); 3096 if (error) { 3097 device_printf(sc->bge_dev, 3098 "can't create DMA map for RX\n"); 3099 return (ENOMEM); 3100 } 3101 } 3102 3103 /* Create DMA maps for TX buffers. */ 3104 for (i = 0; i < BGE_TX_RING_CNT; i++) { 3105 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3106 &sc->bge_cdata.bge_tx_dmamap[i]); 3107 if (error) { 3108 device_printf(sc->bge_dev, 3109 "can't create DMA map for TX\n"); 3110 return (ENOMEM); 3111 } 3112 } 3113 3114 /* Create tags for jumbo RX buffers. */ 3115 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3116 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 3117 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 3118 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 3119 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3120 if (error) { 3121 device_printf(sc->bge_dev, 3122 "could not allocate jumbo dma tag\n"); 3123 return (ENOMEM); 3124 } 3125 /* Create DMA maps for jumbo RX buffers. */ 3126 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3127 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3128 if (error) { 3129 device_printf(sc->bge_dev, 3130 "can't create spare DMA map for jumbo RX\n"); 3131 return (ENOMEM); 3132 } 3133 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3134 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3135 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3136 if (error) { 3137 device_printf(sc->bge_dev, 3138 "can't create DMA map for jumbo RX\n"); 3139 return (ENOMEM); 3140 } 3141 } 3142 } 3143 3144 return (0); 3145} 3146 3147/* 3148 * Return true if this device has more than one port. 3149 */ 3150static int 3151bge_has_multiple_ports(struct bge_softc *sc) 3152{ 3153 device_t dev = sc->bge_dev; 3154 u_int b, d, f, fscan, s; 3155 3156 d = pci_get_domain(dev); 3157 b = pci_get_bus(dev); 3158 s = pci_get_slot(dev); 3159 f = pci_get_function(dev); 3160 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 3161 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3162 return (1); 3163 return (0); 3164} 3165 3166/* 3167 * Return true if MSI can be used with this device. 3168 */ 3169static int 3170bge_can_use_msi(struct bge_softc *sc) 3171{ 3172 int can_use_msi = 0; 3173 3174 if (sc->bge_msi == 0) 3175 return (0); 3176 3177 /* Disable MSI for polling(4). */ 3178#ifdef DEVICE_POLLING 3179 return (0); 3180#endif 3181 switch (sc->bge_asicrev) { 3182 case BGE_ASICREV_BCM5714_A0: 3183 case BGE_ASICREV_BCM5714: 3184 /* 3185 * Apparently, MSI doesn't work when these chips are 3186 * configured in single-port mode. 3187 */ 3188 if (bge_has_multiple_ports(sc)) 3189 can_use_msi = 1; 3190 break; 3191 case BGE_ASICREV_BCM5750: 3192 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3193 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3194 can_use_msi = 1; 3195 break; 3196 default: 3197 if (BGE_IS_575X_PLUS(sc)) 3198 can_use_msi = 1; 3199 } 3200 return (can_use_msi); 3201} 3202 3203static int 3204bge_mbox_reorder(struct bge_softc *sc) 3205{ 3206 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3207 static const struct mbox_reorder { 3208 const uint16_t vendor; 3209 const uint16_t device; 3210 const char *desc; 3211 } mbox_reorder_lists[] = { 3212 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3213 }; 3214 devclass_t pci, pcib; 3215 device_t bus, dev; 3216 int i; 3217 3218 pci = devclass_find("pci"); 3219 pcib = devclass_find("pcib"); 3220 dev = sc->bge_dev; 3221 bus = device_get_parent(dev); 3222 for (;;) { 3223 dev = device_get_parent(bus); 3224 bus = device_get_parent(dev); 3225 if (device_get_devclass(dev) != pcib) 3226 break; 3227 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3228 if (pci_get_vendor(dev) == 3229 mbox_reorder_lists[i].vendor && 3230 pci_get_device(dev) == 3231 mbox_reorder_lists[i].device) { 3232 device_printf(sc->bge_dev, 3233 "enabling MBOX workaround for %s\n", 3234 mbox_reorder_lists[i].desc); 3235 return (1); 3236 } 3237 } 3238 if (device_get_devclass(bus) != pci) 3239 break; 3240 } 3241 return (0); 3242} 3243 3244static void 3245bge_devinfo(struct bge_softc *sc) 3246{ 3247 uint32_t cfg, clk; 3248 3249 device_printf(sc->bge_dev, 3250 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3251 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3252 if (sc->bge_flags & BGE_FLAG_PCIE) 3253 printf("PCI-E\n"); 3254 else if (sc->bge_flags & BGE_FLAG_PCIX) { 3255 printf("PCI-X "); 3256 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3257 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3258 clk = 133; 3259 else { 3260 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3261 switch (clk) { 3262 case 0: 3263 clk = 33; 3264 break; 3265 case 2: 3266 clk = 50; 3267 break; 3268 case 4: 3269 clk = 66; 3270 break; 3271 case 6: 3272 clk = 100; 3273 break; 3274 case 7: 3275 clk = 133; 3276 break; 3277 } 3278 } 3279 printf("%u MHz\n", clk); 3280 } else { 3281 if (sc->bge_pcixcap != 0) 3282 printf("PCI on PCI-X "); 3283 else 3284 printf("PCI "); 3285 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3286 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3287 clk = 66; 3288 else 3289 clk = 33; 3290 if (cfg & BGE_PCISTATE_32BIT_BUS) 3291 printf("%u MHz; 32bit\n", clk); 3292 else 3293 printf("%u MHz; 64bit\n", clk); 3294 } 3295} 3296 3297static int 3298bge_attach(device_t dev) 3299{ 3300 struct ifnet *ifp; 3301 struct bge_softc *sc; 3302 uint32_t hwcfg = 0, misccfg, pcistate; 3303 u_char eaddr[ETHER_ADDR_LEN]; 3304 int capmask, error, reg, rid, trys; 3305 3306 sc = device_get_softc(dev); 3307 sc->bge_dev = dev; 3308 3309 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3310 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3311 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3312 3313 pci_enable_busmaster(dev); 3314 3315 /* 3316 * Allocate control/status registers. 3317 */ 3318 rid = PCIR_BAR(0); 3319 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3320 RF_ACTIVE); 3321 3322 if (sc->bge_res == NULL) { 3323 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 3324 error = ENXIO; 3325 goto fail; 3326 } 3327 3328 /* Save various chip information. */ 3329 sc->bge_func_addr = pci_get_function(dev); 3330 sc->bge_chipid = bge_chipid(dev); 3331 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3332 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3333 3334 /* Set default PHY address. */ 3335 sc->bge_phy_addr = 1; 3336 /* 3337 * PHY address mapping for various devices. 3338 * 3339 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 3340 * ---------+-------+-------+-------+-------+ 3341 * BCM57XX | 1 | X | X | X | 3342 * BCM5704 | 1 | X | 1 | X | 3343 * BCM5717 | 1 | 8 | 2 | 9 | 3344 * BCM5719 | 1 | 8 | 2 | 9 | 3345 * BCM5720 | 1 | 8 | 2 | 9 | 3346 * 3347 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3348 * ---------+-------+-------+-------+-------+ 3349 * BCM57XX | X | X | X | X | 3350 * BCM5704 | X | X | X | X | 3351 * BCM5717 | X | X | X | X | 3352 * BCM5719 | 3 | 10 | 4 | 11 | 3353 * BCM5720 | X | X | X | X | 3354 * 3355 * Other addresses may respond but they are not 3356 * IEEE compliant PHYs and should be ignored. 3357 */ 3358 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 3359 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3360 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3361 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 3362 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 3363 BGE_SGDIGSTS_IS_SERDES) 3364 sc->bge_phy_addr = sc->bge_func_addr + 8; 3365 else 3366 sc->bge_phy_addr = sc->bge_func_addr + 1; 3367 } else { 3368 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 3369 BGE_CPMU_PHY_STRAP_IS_SERDES) 3370 sc->bge_phy_addr = sc->bge_func_addr + 8; 3371 else 3372 sc->bge_phy_addr = sc->bge_func_addr + 1; 3373 } 3374 } 3375 3376 if (bge_has_eaddr(sc)) 3377 sc->bge_flags |= BGE_FLAG_EADDR; 3378 3379 /* Save chipset family. */ 3380 switch (sc->bge_asicrev) { 3381 case BGE_ASICREV_BCM5762: 3382 case BGE_ASICREV_BCM57765: 3383 case BGE_ASICREV_BCM57766: 3384 sc->bge_flags |= BGE_FLAG_57765_PLUS; 3385 /* FALLTHROUGH */ 3386 case BGE_ASICREV_BCM5717: 3387 case BGE_ASICREV_BCM5719: 3388 case BGE_ASICREV_BCM5720: 3389 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3390 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3391 BGE_FLAG_JUMBO_FRAME; 3392 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3393 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3394 /* 3395 * Enable work around for DMA engine miscalculation 3396 * of TXMBUF available space. 3397 */ 3398 sc->bge_flags |= BGE_FLAG_RDMA_BUG; 3399 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3400 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3401 /* Jumbo frame on BCM5719 A0 does not work. */ 3402 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3403 } 3404 } 3405 break; 3406 case BGE_ASICREV_BCM5755: 3407 case BGE_ASICREV_BCM5761: 3408 case BGE_ASICREV_BCM5784: 3409 case BGE_ASICREV_BCM5785: 3410 case BGE_ASICREV_BCM5787: 3411 case BGE_ASICREV_BCM57780: 3412 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3413 BGE_FLAG_5705_PLUS; 3414 break; 3415 case BGE_ASICREV_BCM5700: 3416 case BGE_ASICREV_BCM5701: 3417 case BGE_ASICREV_BCM5703: 3418 case BGE_ASICREV_BCM5704: 3419 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3420 break; 3421 case BGE_ASICREV_BCM5714_A0: 3422 case BGE_ASICREV_BCM5780: 3423 case BGE_ASICREV_BCM5714: 3424 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3425 /* FALLTHROUGH */ 3426 case BGE_ASICREV_BCM5750: 3427 case BGE_ASICREV_BCM5752: 3428 case BGE_ASICREV_BCM5906: 3429 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3430 /* FALLTHROUGH */ 3431 case BGE_ASICREV_BCM5705: 3432 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3433 break; 3434 } 3435 3436 /* Identify chips with APE processor. */ 3437 switch (sc->bge_asicrev) { 3438 case BGE_ASICREV_BCM5717: 3439 case BGE_ASICREV_BCM5719: 3440 case BGE_ASICREV_BCM5720: 3441 case BGE_ASICREV_BCM5761: 3442 case BGE_ASICREV_BCM5762: 3443 sc->bge_flags |= BGE_FLAG_APE; 3444 break; 3445 } 3446 3447 /* Chips with APE need BAR2 access for APE registers/memory. */ 3448 if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3449 rid = PCIR_BAR(2); 3450 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3451 RF_ACTIVE); 3452 if (sc->bge_res2 == NULL) { 3453 device_printf (sc->bge_dev, 3454 "couldn't map BAR2 memory\n"); 3455 error = ENXIO; 3456 goto fail; 3457 } 3458 3459 /* Enable APE register/memory access by host driver. */ 3460 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3461 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3462 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3463 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3464 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3465 3466 bge_ape_lock_init(sc); 3467 bge_ape_read_fw_ver(sc); 3468 } 3469 3470 /* Add SYSCTLs, requires the chipset family to be set. */ 3471 bge_add_sysctls(sc); 3472 3473 /* Identify the chips that use an CPMU. */ 3474 if (BGE_IS_5717_PLUS(sc) || 3475 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3476 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3477 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3478 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3479 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3480 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3481 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3482 else 3483 sc->bge_mi_mode = BGE_MIMODE_BASE; 3484 /* Enable auto polling for BCM570[0-5]. */ 3485 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3486 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3487 3488 /* 3489 * All Broadcom controllers have 4GB boundary DMA bug. 3490 * Whenever an address crosses a multiple of the 4GB boundary 3491 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3492 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3493 * state machine will lockup and cause the device to hang. 3494 */ 3495 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3496 3497 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3498 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3499 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3500 3501 /* 3502 * BCM5719 cannot handle DMA requests for DMA segments that 3503 * have larger than 4KB in size. However the maximum DMA 3504 * segment size created in DMA tag is 4KB for TSO, so we 3505 * wouldn't encounter the issue here. 3506 */ 3507 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3508 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3509 3510 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3511 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3512 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3513 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3514 sc->bge_flags |= BGE_FLAG_5788; 3515 } 3516 3517 capmask = BMSR_DEFCAPMASK; 3518 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3519 (misccfg == 0x4000 || misccfg == 0x8000)) || 3520 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3521 pci_get_vendor(dev) == BCOM_VENDORID && 3522 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3523 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3524 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3525 (pci_get_vendor(dev) == BCOM_VENDORID && 3526 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3527 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3528 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3529 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3530 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || 3531 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || 3532 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3533 /* These chips are 10/100 only. */ 3534 capmask &= ~BMSR_EXTSTAT; 3535 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3536 } 3537 3538 /* 3539 * Some controllers seem to require a special firmware to use 3540 * TSO. But the firmware is not available to FreeBSD and Linux 3541 * claims that the TSO performed by the firmware is slower than 3542 * hardware based TSO. Moreover the firmware based TSO has one 3543 * known bug which can't handle TSO if Ethernet header + IP/TCP 3544 * header is greater than 80 bytes. A workaround for the TSO 3545 * bug exist but it seems it's too expensive than not using 3546 * TSO at all. Some hardwares also have the TSO bug so limit 3547 * the TSO to the controllers that are not affected TSO issues 3548 * (e.g. 5755 or higher). 3549 */ 3550 if (BGE_IS_5717_PLUS(sc)) { 3551 /* BCM5717 requires different TSO configuration. */ 3552 sc->bge_flags |= BGE_FLAG_TSO3; 3553 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3554 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3555 /* TSO on BCM5719 A0 does not work. */ 3556 sc->bge_flags &= ~BGE_FLAG_TSO3; 3557 } 3558 } else if (BGE_IS_5755_PLUS(sc)) { 3559 /* 3560 * BCM5754 and BCM5787 shares the same ASIC id so 3561 * explicit device id check is required. 3562 * Due to unknown reason TSO does not work on BCM5755M. 3563 */ 3564 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3565 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3566 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3567 sc->bge_flags |= BGE_FLAG_TSO; 3568 } 3569 3570 /* 3571 * Check if this is a PCI-X or PCI Express device. 3572 */ 3573 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3574 /* 3575 * Found a PCI Express capabilities register, this 3576 * must be a PCI Express device. 3577 */ 3578 sc->bge_flags |= BGE_FLAG_PCIE; 3579 sc->bge_expcap = reg; 3580 /* Extract supported maximum payload size. */ 3581 sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 3582 PCIER_DEVICE_CAP, 2); 3583 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 3584 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3585 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3586 sc->bge_expmrq = 2048; 3587 else 3588 sc->bge_expmrq = 4096; 3589 pci_set_max_read_req(dev, sc->bge_expmrq); 3590 } else { 3591 /* 3592 * Check if the device is in PCI-X Mode. 3593 * (This bit is not valid on PCI Express controllers.) 3594 */ 3595 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3596 sc->bge_pcixcap = reg; 3597 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3598 BGE_PCISTATE_PCI_BUSMODE) == 0) 3599 sc->bge_flags |= BGE_FLAG_PCIX; 3600 } 3601 3602 /* 3603 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3604 * not actually a MAC controller bug but an issue with the embedded 3605 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3606 */ 3607 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3608 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3609 /* 3610 * Some PCI-X bridges are known to trigger write reordering to 3611 * the mailbox registers. Typical phenomena is watchdog timeouts 3612 * caused by out-of-order TX completions. Enable workaround for 3613 * PCI-X devices that live behind these bridges. 3614 * Note, PCI-X controllers can run in PCI mode so we can't use 3615 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3616 */ 3617 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3618 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3619 /* 3620 * Allocate the interrupt, using MSI if possible. These devices 3621 * support 8 MSI messages, but only the first one is used in 3622 * normal operation. 3623 */ 3624 rid = 0; 3625 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3626 sc->bge_msicap = reg; 3627 reg = 1; 3628 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) { 3629 rid = 1; 3630 sc->bge_flags |= BGE_FLAG_MSI; 3631 } 3632 } 3633 3634 /* 3635 * All controllers except BCM5700 supports tagged status but 3636 * we use tagged status only for MSI case on BCM5717. Otherwise 3637 * MSI on BCM5717 does not work. 3638 */ 3639#ifndef DEVICE_POLLING 3640 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3641 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3642#endif 3643 3644 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3645 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 3646 3647 if (sc->bge_irq == NULL) { 3648 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3649 error = ENXIO; 3650 goto fail; 3651 } 3652 3653 bge_devinfo(sc); 3654 3655 sc->bge_asf_mode = 0; 3656 /* No ASF if APE present. */ 3657 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3658 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3659 BGE_SRAM_DATA_SIG_MAGIC)) { 3660 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3661 BGE_HWCFG_ASF) { 3662 sc->bge_asf_mode |= ASF_ENABLE; 3663 sc->bge_asf_mode |= ASF_STACKUP; 3664 if (BGE_IS_575X_PLUS(sc)) 3665 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3666 } 3667 } 3668 } 3669 3670 bge_stop_fw(sc); 3671 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3672 if (bge_reset(sc)) { 3673 device_printf(sc->bge_dev, "chip reset failed\n"); 3674 error = ENXIO; 3675 goto fail; 3676 } 3677 3678 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3679 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3680 3681 if (bge_chipinit(sc)) { 3682 device_printf(sc->bge_dev, "chip initialization failed\n"); 3683 error = ENXIO; 3684 goto fail; 3685 } 3686 3687 error = bge_get_eaddr(sc, eaddr); 3688 if (error) { 3689 device_printf(sc->bge_dev, 3690 "failed to read station address\n"); 3691 error = ENXIO; 3692 goto fail; 3693 } 3694 3695 /* 5705 limits RX return ring to 512 entries. */ 3696 if (BGE_IS_5717_PLUS(sc)) 3697 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3698 else if (BGE_IS_5705_PLUS(sc)) 3699 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3700 else 3701 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3702 3703 if (bge_dma_alloc(sc)) { 3704 device_printf(sc->bge_dev, 3705 "failed to allocate DMA resources\n"); 3706 error = ENXIO; 3707 goto fail; 3708 } 3709 3710 /* Set default tuneable values. */ 3711 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3712 sc->bge_rx_coal_ticks = 150; 3713 sc->bge_tx_coal_ticks = 150; 3714 sc->bge_rx_max_coal_bds = 10; 3715 sc->bge_tx_max_coal_bds = 10; 3716 3717 /* Initialize checksum features to use. */ 3718 sc->bge_csum_features = BGE_CSUM_FEATURES; 3719 if (sc->bge_forced_udpcsum != 0) 3720 sc->bge_csum_features |= CSUM_UDP; 3721 3722 /* Set up ifnet structure */ 3723 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3724 if (ifp == NULL) { 3725 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3726 error = ENXIO; 3727 goto fail; 3728 } 3729 ifp->if_softc = sc; 3730 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3731 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3732 ifp->if_ioctl = bge_ioctl; 3733 ifp->if_start = bge_start; 3734 ifp->if_init = bge_init; 3735 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 3736 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 3737 IFQ_SET_READY(&ifp->if_snd); 3738 ifp->if_hwassist = sc->bge_csum_features; 3739 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3740 IFCAP_VLAN_MTU; 3741 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3742 ifp->if_hwassist |= CSUM_TSO; 3743 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 3744 } 3745#ifdef IFCAP_VLAN_HWCSUM 3746 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 3747#endif 3748 ifp->if_capenable = ifp->if_capabilities; 3749#ifdef DEVICE_POLLING 3750 ifp->if_capabilities |= IFCAP_POLLING; 3751#endif 3752 3753 /* 3754 * 5700 B0 chips do not support checksumming correctly due 3755 * to hardware bugs. 3756 */ 3757 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3758 ifp->if_capabilities &= ~IFCAP_HWCSUM; 3759 ifp->if_capenable &= ~IFCAP_HWCSUM; 3760 ifp->if_hwassist = 0; 3761 } 3762 3763 /* 3764 * Figure out what sort of media we have by checking the 3765 * hardware config word in the first 32k of NIC internal memory, 3766 * or fall back to examining the EEPROM if necessary. 3767 * Note: on some BCM5700 cards, this value appears to be unset. 3768 * If that's the case, we have to rely on identifying the NIC 3769 * by its PCI subsystem ID, as we do below for the SysKonnect 3770 * SK-9D41. 3771 */ 3772 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3773 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3774 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3775 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3776 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3777 sizeof(hwcfg))) { 3778 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3779 error = ENXIO; 3780 goto fail; 3781 } 3782 hwcfg = ntohl(hwcfg); 3783 } 3784 3785 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3786 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3787 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3788 if (BGE_IS_5705_PLUS(sc)) { 3789 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3790 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3791 } else 3792 sc->bge_flags |= BGE_FLAG_TBI; 3793 } 3794 3795 /* Set various PHY bug flags. */ 3796 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3797 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3798 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3799 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3800 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3801 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3802 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3803 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3804 if (pci_get_subvendor(dev) == DELL_VENDORID) 3805 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3806 if ((BGE_IS_5705_PLUS(sc)) && 3807 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3808 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3809 sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3810 !BGE_IS_5717_PLUS(sc)) { 3811 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3812 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3813 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3814 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3815 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3816 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3817 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3818 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3819 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3820 } else 3821 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3822 } 3823 3824 /* 3825 * Don't enable Ethernet@WireSpeed for the 5700 or the 3826 * 5705 A0 and A1 chips. 3827 */ 3828 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3829 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3830 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3831 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3832 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3833 3834 if (sc->bge_flags & BGE_FLAG_TBI) { 3835 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3836 bge_ifmedia_sts); 3837 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3838 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3839 0, NULL); 3840 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3841 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3842 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3843 } else { 3844 /* 3845 * Do transceiver setup and tell the firmware the 3846 * driver is down so we can try to get access the 3847 * probe if ASF is running. Retry a couple of times 3848 * if we get a conflict with the ASF firmware accessing 3849 * the PHY. 3850 */ 3851 trys = 0; 3852 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3853again: 3854 bge_asf_driver_up(sc); 3855 3856 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, 3857 bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY, 3858 MIIF_DOPAUSE); 3859 if (error != 0) { 3860 if (trys++ < 4) { 3861 device_printf(sc->bge_dev, "Try again\n"); 3862 bge_miibus_writereg(sc->bge_dev, 3863 sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 3864 goto again; 3865 } 3866 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3867 goto fail; 3868 } 3869 3870 /* 3871 * Now tell the firmware we are going up after probing the PHY 3872 */ 3873 if (sc->bge_asf_mode & ASF_STACKUP) 3874 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3875 } 3876 3877 /* 3878 * When using the BCM5701 in PCI-X mode, data corruption has 3879 * been observed in the first few bytes of some received packets. 3880 * Aligning the packet buffer in memory eliminates the corruption. 3881 * Unfortunately, this misaligns the packet payloads. On platforms 3882 * which do not support unaligned accesses, we will realign the 3883 * payloads by copying the received packets. 3884 */ 3885 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3886 sc->bge_flags & BGE_FLAG_PCIX) 3887 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3888 3889 /* 3890 * Call MI attach routine. 3891 */ 3892 ether_ifattach(ifp, eaddr); 3893 3894 /* Tell upper layer we support long frames. */ 3895 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3896 3897 /* 3898 * Hookup IRQ last. 3899 */ 3900 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3901 /* Take advantage of single-shot MSI. */ 3902 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3903 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3904 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3905 taskqueue_thread_enqueue, &sc->bge_tq); 3906 if (sc->bge_tq == NULL) { 3907 device_printf(dev, "could not create taskqueue.\n"); 3908 ether_ifdetach(ifp); 3909 error = ENOMEM; 3910 goto fail; 3911 } 3912 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, 3913 "%s taskq", device_get_nameunit(sc->bge_dev)); 3914 if (error != 0) { 3915 device_printf(dev, "could not start threads.\n"); 3916 ether_ifdetach(ifp); 3917 goto fail; 3918 } 3919 error = bus_setup_intr(dev, sc->bge_irq, 3920 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3921 &sc->bge_intrhand); 3922 } else 3923 error = bus_setup_intr(dev, sc->bge_irq, 3924 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3925 &sc->bge_intrhand); 3926 3927 if (error) { 3928 ether_ifdetach(ifp); 3929 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3930 } 3931 3932fail: 3933 if (error) 3934 bge_detach(dev); 3935 return (error); 3936} 3937 3938static int 3939bge_detach(device_t dev) 3940{ 3941 struct bge_softc *sc; 3942 struct ifnet *ifp; 3943 3944 sc = device_get_softc(dev); 3945 ifp = sc->bge_ifp; 3946 3947#ifdef DEVICE_POLLING 3948 if (ifp->if_capenable & IFCAP_POLLING) 3949 ether_poll_deregister(ifp); 3950#endif 3951 3952 if (device_is_attached(dev)) { 3953 ether_ifdetach(ifp); 3954 BGE_LOCK(sc); 3955 bge_stop(sc); 3956 BGE_UNLOCK(sc); 3957 callout_drain(&sc->bge_stat_ch); 3958 } 3959 3960 if (sc->bge_tq) 3961 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3962 3963 if (sc->bge_flags & BGE_FLAG_TBI) 3964 ifmedia_removeall(&sc->bge_ifmedia); 3965 else if (sc->bge_miibus != NULL) { 3966 bus_generic_detach(dev); 3967 device_delete_child(dev, sc->bge_miibus); 3968 } 3969 3970 bge_release_resources(sc); 3971 3972 return (0); 3973} 3974 3975static void 3976bge_release_resources(struct bge_softc *sc) 3977{ 3978 device_t dev; 3979 3980 dev = sc->bge_dev; 3981 3982 if (sc->bge_tq != NULL) 3983 taskqueue_free(sc->bge_tq); 3984 3985 if (sc->bge_intrhand != NULL) 3986 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3987 3988 if (sc->bge_irq != NULL) { 3989 bus_release_resource(dev, SYS_RES_IRQ, 3990 rman_get_rid(sc->bge_irq), sc->bge_irq); 3991 pci_release_msi(dev); 3992 } 3993 3994 if (sc->bge_res != NULL) 3995 bus_release_resource(dev, SYS_RES_MEMORY, 3996 rman_get_rid(sc->bge_res), sc->bge_res); 3997 3998 if (sc->bge_res2 != NULL) 3999 bus_release_resource(dev, SYS_RES_MEMORY, 4000 rman_get_rid(sc->bge_res2), sc->bge_res2); 4001 4002 if (sc->bge_ifp != NULL) 4003 if_free(sc->bge_ifp); 4004 4005 bge_dma_free(sc); 4006 4007 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 4008 BGE_LOCK_DESTROY(sc); 4009} 4010 4011static int 4012bge_reset(struct bge_softc *sc) 4013{ 4014 device_t dev; 4015 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 4016 void (*write_op)(struct bge_softc *, int, int); 4017 uint16_t devctl; 4018 int i; 4019 4020 dev = sc->bge_dev; 4021 4022 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4023 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4024 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4025 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4026 4027 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4028 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 4029 if (sc->bge_flags & BGE_FLAG_PCIE) 4030 write_op = bge_writemem_direct; 4031 else 4032 write_op = bge_writemem_ind; 4033 } else 4034 write_op = bge_writereg_ind; 4035 4036 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 4037 sc->bge_asicrev != BGE_ASICREV_BCM5701) { 4038 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4039 for (i = 0; i < 8000; i++) { 4040 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4041 BGE_NVRAMSWARB_GNT1) 4042 break; 4043 DELAY(20); 4044 } 4045 if (i == 8000) { 4046 if (bootverbose) 4047 device_printf(dev, "NVRAM lock timedout!\n"); 4048 } 4049 } 4050 /* Take APE lock when performing reset. */ 4051 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4052 4053 /* Save some important PCI state. */ 4054 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 4055 command = pci_read_config(dev, BGE_PCI_CMD, 4); 4056 4057 pci_write_config(dev, BGE_PCI_MISC_CTL, 4058 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4059 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4060 4061 /* Disable fastboot on controllers that support it. */ 4062 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 4063 BGE_IS_5755_PLUS(sc)) { 4064 if (bootverbose) 4065 device_printf(dev, "Disabling fastboot\n"); 4066 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 4067 } 4068 4069 /* 4070 * Write the magic number to SRAM at offset 0xB50. 4071 * When firmware finishes its initialization it will 4072 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 4073 */ 4074 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4075 4076 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4077 4078 /* XXX: Broadcom Linux driver. */ 4079 if (sc->bge_flags & BGE_FLAG_PCIE) { 4080 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 4081 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 4082 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 4083 CSR_WRITE_4(sc, 0x7E2C, 0x20); 4084 } 4085 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4086 /* Prevent PCIE link training during global reset */ 4087 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4088 reset |= 1 << 29; 4089 } 4090 } 4091 4092 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4093 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4094 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4095 val | BGE_VCPU_STATUS_DRV_RESET); 4096 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4097 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4098 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4099 } 4100 4101 /* 4102 * Set GPHY Power Down Override to leave GPHY 4103 * powered up in D0 uninitialized. 4104 */ 4105 if (BGE_IS_5705_PLUS(sc) && 4106 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4107 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4108 4109 /* Issue global reset */ 4110 write_op(sc, BGE_MISC_CFG, reset); 4111 4112 if (sc->bge_flags & BGE_FLAG_PCIE) 4113 DELAY(100 * 1000); 4114 else 4115 DELAY(1000); 4116 4117 /* XXX: Broadcom Linux driver. */ 4118 if (sc->bge_flags & BGE_FLAG_PCIE) { 4119 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4120 DELAY(500000); /* wait for link training to complete */ 4121 val = pci_read_config(dev, 0xC4, 4); 4122 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4123 } 4124 devctl = pci_read_config(dev, 4125 sc->bge_expcap + PCIER_DEVICE_CTL, 2); 4126 /* Clear enable no snoop and disable relaxed ordering. */ 4127 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4128 PCIEM_CTL_NOSNOOP_ENABLE); 4129 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 4130 devctl, 2); 4131 pci_set_max_read_req(dev, sc->bge_expmrq); 4132 /* Clear error status. */ 4133 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4134 PCIEM_STA_CORRECTABLE_ERROR | 4135 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4136 PCIEM_STA_UNSUPPORTED_REQ, 2); 4137 } 4138 4139 /* Reset some of the PCI state that got zapped by reset. */ 4140 pci_write_config(dev, BGE_PCI_MISC_CTL, 4141 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4142 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4143 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4144 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4145 (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4146 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4147 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4148 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4149 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4150 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4151 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 4152 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 4153 pci_write_config(dev, BGE_PCI_CMD, command, 4); 4154 /* 4155 * Disable PCI-X relaxed ordering to ensure status block update 4156 * comes first then packet buffer DMA. Otherwise driver may 4157 * read stale status block. 4158 */ 4159 if (sc->bge_flags & BGE_FLAG_PCIX) { 4160 devctl = pci_read_config(dev, 4161 sc->bge_pcixcap + PCIXR_COMMAND, 2); 4162 devctl &= ~PCIXM_COMMAND_ERO; 4163 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4164 devctl &= ~PCIXM_COMMAND_MAX_READ; 4165 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4166 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4167 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4168 PCIXM_COMMAND_MAX_READ); 4169 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4170 } 4171 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4172 devctl, 2); 4173 } 4174 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 4175 if (BGE_IS_5714_FAMILY(sc)) { 4176 /* This chip disables MSI on reset. */ 4177 if (sc->bge_flags & BGE_FLAG_MSI) { 4178 val = pci_read_config(dev, 4179 sc->bge_msicap + PCIR_MSI_CTRL, 2); 4180 pci_write_config(dev, 4181 sc->bge_msicap + PCIR_MSI_CTRL, 4182 val | PCIM_MSICTRL_MSI_ENABLE, 2); 4183 val = CSR_READ_4(sc, BGE_MSI_MODE); 4184 CSR_WRITE_4(sc, BGE_MSI_MODE, 4185 val | BGE_MSIMODE_ENABLE); 4186 } 4187 val = CSR_READ_4(sc, BGE_MARB_MODE); 4188 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4189 } else 4190 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4191 4192 /* Fix up byte swapping. */ 4193 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4194 4195 val = CSR_READ_4(sc, BGE_MAC_MODE); 4196 val = (val & ~mac_mode_mask) | mac_mode; 4197 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4198 DELAY(40); 4199 4200 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4201 4202 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4203 for (i = 0; i < BGE_TIMEOUT; i++) { 4204 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4205 if (val & BGE_VCPU_STATUS_INIT_DONE) 4206 break; 4207 DELAY(100); 4208 } 4209 if (i == BGE_TIMEOUT) { 4210 device_printf(dev, "reset timed out\n"); 4211 return (1); 4212 } 4213 } else { 4214 /* 4215 * Poll until we see the 1's complement of the magic number. 4216 * This indicates that the firmware initialization is complete. 4217 * We expect this to fail if no chip containing the Ethernet 4218 * address is fitted though. 4219 */ 4220 for (i = 0; i < BGE_TIMEOUT; i++) { 4221 DELAY(10); 4222 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4223 if (val == ~BGE_SRAM_FW_MB_MAGIC) 4224 break; 4225 } 4226 4227 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4228 device_printf(dev, 4229 "firmware handshake timed out, found 0x%08x\n", 4230 val); 4231 /* BCM57765 A0 needs additional time before accessing. */ 4232 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4233 DELAY(10 * 1000); /* XXX */ 4234 } 4235 4236 /* 4237 * The 5704 in TBI mode apparently needs some special 4238 * adjustment to insure the SERDES drive level is set 4239 * to 1.2V. 4240 */ 4241 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4242 sc->bge_flags & BGE_FLAG_TBI) { 4243 val = CSR_READ_4(sc, BGE_SERDES_CFG); 4244 val = (val & ~0xFFF) | 0x880; 4245 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4246 } 4247 4248 /* XXX: Broadcom Linux driver. */ 4249 if (sc->bge_flags & BGE_FLAG_PCIE && 4250 !BGE_IS_5717_PLUS(sc) && 4251 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4252 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4253 /* Enable Data FIFO protection. */ 4254 val = CSR_READ_4(sc, 0x7C00); 4255 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4256 } 4257 4258 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 4259 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4260 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4261 4262 return (0); 4263} 4264 4265static __inline void 4266bge_rxreuse_std(struct bge_softc *sc, int i) 4267{ 4268 struct bge_rx_bd *r; 4269 4270 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4271 r->bge_flags = BGE_RXBDFLAG_END; 4272 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4273 r->bge_idx = i; 4274 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4275} 4276 4277static __inline void 4278bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4279{ 4280 struct bge_extrx_bd *r; 4281 4282 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4283 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4284 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4285 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4286 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4287 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4288 r->bge_idx = i; 4289 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4290} 4291 4292/* 4293 * Frame reception handling. This is called if there's a frame 4294 * on the receive return list. 4295 * 4296 * Note: we have to be able to handle two possibilities here: 4297 * 1) the frame is from the jumbo receive ring 4298 * 2) the frame is from the standard receive ring 4299 */ 4300 4301static int 4302bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 4303{ 4304 struct ifnet *ifp; 4305 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4306 uint16_t rx_cons; 4307 4308 rx_cons = sc->bge_rx_saved_considx; 4309 4310 /* Nothing to do. */ 4311 if (rx_cons == rx_prod) 4312 return (rx_npkts); 4313 4314 ifp = sc->bge_ifp; 4315 4316 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4317 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4318 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4319 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4320 if (BGE_IS_JUMBO_CAPABLE(sc) && 4321 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4322 (MCLBYTES - ETHER_ALIGN)) 4323 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4324 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4325 4326 while (rx_cons != rx_prod) { 4327 struct bge_rx_bd *cur_rx; 4328 uint32_t rxidx; 4329 struct mbuf *m = NULL; 4330 uint16_t vlan_tag = 0; 4331 int have_tag = 0; 4332 4333#ifdef DEVICE_POLLING 4334 if (ifp->if_capenable & IFCAP_POLLING) { 4335 if (sc->rxcycles <= 0) 4336 break; 4337 sc->rxcycles--; 4338 } 4339#endif 4340 4341 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 4342 4343 rxidx = cur_rx->bge_idx; 4344 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4345 4346 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 4347 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4348 have_tag = 1; 4349 vlan_tag = cur_rx->bge_vlan_tag; 4350 } 4351 4352 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4353 jumbocnt++; 4354 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4355 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4356 bge_rxreuse_jumbo(sc, rxidx); 4357 continue; 4358 } 4359 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4360 bge_rxreuse_jumbo(sc, rxidx); 4361 ifp->if_iqdrops++; 4362 continue; 4363 } 4364 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4365 } else { 4366 stdcnt++; 4367 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4368 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4369 bge_rxreuse_std(sc, rxidx); 4370 continue; 4371 } 4372 if (bge_newbuf_std(sc, rxidx) != 0) { 4373 bge_rxreuse_std(sc, rxidx); 4374 ifp->if_iqdrops++; 4375 continue; 4376 } 4377 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4378 } 4379 4380 ifp->if_ipackets++; 4381#ifndef __NO_STRICT_ALIGNMENT 4382 /* 4383 * For architectures with strict alignment we must make sure 4384 * the payload is aligned. 4385 */ 4386 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4387 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4388 cur_rx->bge_len); 4389 m->m_data += ETHER_ALIGN; 4390 } 4391#endif 4392 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4393 m->m_pkthdr.rcvif = ifp; 4394 4395 if (ifp->if_capenable & IFCAP_RXCSUM) 4396 bge_rxcsum(sc, cur_rx, m); 4397 4398 /* 4399 * If we received a packet with a vlan tag, 4400 * attach that information to the packet. 4401 */ 4402 if (have_tag) { 4403 m->m_pkthdr.ether_vtag = vlan_tag; 4404 m->m_flags |= M_VLANTAG; 4405 } 4406 4407 if (holdlck != 0) { 4408 BGE_UNLOCK(sc); 4409 (*ifp->if_input)(ifp, m); 4410 BGE_LOCK(sc); 4411 } else 4412 (*ifp->if_input)(ifp, m); 4413 rx_npkts++; 4414 4415 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 4416 return (rx_npkts); 4417 } 4418 4419 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4420 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4421 if (stdcnt > 0) 4422 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4423 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 4424 4425 if (jumbocnt > 0) 4426 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4427 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4428 4429 sc->bge_rx_saved_considx = rx_cons; 4430 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4431 if (stdcnt) 4432 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4433 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 4434 if (jumbocnt) 4435 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4436 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4437#ifdef notyet 4438 /* 4439 * This register wraps very quickly under heavy packet drops. 4440 * If you need correct statistics, you can enable this check. 4441 */ 4442 if (BGE_IS_5705_PLUS(sc)) 4443 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4444#endif 4445 return (rx_npkts); 4446} 4447 4448static void 4449bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4450{ 4451 4452 if (BGE_IS_5717_PLUS(sc)) { 4453 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4454 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4455 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4456 if ((cur_rx->bge_error_flag & 4457 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4458 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4459 } 4460 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4461 m->m_pkthdr.csum_data = 4462 cur_rx->bge_tcp_udp_csum; 4463 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4464 CSUM_PSEUDO_HDR; 4465 } 4466 } 4467 } else { 4468 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4469 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4470 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4471 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4472 } 4473 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4474 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4475 m->m_pkthdr.csum_data = 4476 cur_rx->bge_tcp_udp_csum; 4477 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4478 CSUM_PSEUDO_HDR; 4479 } 4480 } 4481} 4482 4483static void 4484bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4485{ 4486 struct bge_tx_bd *cur_tx; 4487 struct ifnet *ifp; 4488 4489 BGE_LOCK_ASSERT(sc); 4490 4491 /* Nothing to do. */ 4492 if (sc->bge_tx_saved_considx == tx_cons) 4493 return; 4494 4495 ifp = sc->bge_ifp; 4496 4497 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4498 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4499 /* 4500 * Go through our tx ring and free mbufs for those 4501 * frames that have been sent. 4502 */ 4503 while (sc->bge_tx_saved_considx != tx_cons) { 4504 uint32_t idx; 4505 4506 idx = sc->bge_tx_saved_considx; 4507 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4508 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4509 ifp->if_opackets++; 4510 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4511 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4512 sc->bge_cdata.bge_tx_dmamap[idx], 4513 BUS_DMASYNC_POSTWRITE); 4514 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4515 sc->bge_cdata.bge_tx_dmamap[idx]); 4516 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4517 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4518 } 4519 sc->bge_txcnt--; 4520 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4521 } 4522 4523 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4524 if (sc->bge_txcnt == 0) 4525 sc->bge_timer = 0; 4526} 4527 4528#ifdef DEVICE_POLLING 4529static int 4530bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 4531{ 4532 struct bge_softc *sc = ifp->if_softc; 4533 uint16_t rx_prod, tx_cons; 4534 uint32_t statusword; 4535 int rx_npkts = 0; 4536 4537 BGE_LOCK(sc); 4538 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4539 BGE_UNLOCK(sc); 4540 return (rx_npkts); 4541 } 4542 4543 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4544 sc->bge_cdata.bge_status_map, 4545 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4546 /* Fetch updates from the status block. */ 4547 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4548 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4549 4550 statusword = sc->bge_ldata.bge_status_block->bge_status; 4551 /* Clear the status so the next pass only sees the changes. */ 4552 sc->bge_ldata.bge_status_block->bge_status = 0; 4553 4554 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4555 sc->bge_cdata.bge_status_map, 4556 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4557 4558 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4559 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4560 sc->bge_link_evt++; 4561 4562 if (cmd == POLL_AND_CHECK_STATUS) 4563 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4564 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4565 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4566 bge_link_upd(sc); 4567 4568 sc->rxcycles = count; 4569 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4570 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4571 BGE_UNLOCK(sc); 4572 return (rx_npkts); 4573 } 4574 bge_txeof(sc, tx_cons); 4575 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4576 bge_start_locked(ifp); 4577 4578 BGE_UNLOCK(sc); 4579 return (rx_npkts); 4580} 4581#endif /* DEVICE_POLLING */ 4582 4583static int 4584bge_msi_intr(void *arg) 4585{ 4586 struct bge_softc *sc; 4587 4588 sc = (struct bge_softc *)arg; 4589 /* 4590 * This interrupt is not shared and controller already 4591 * disabled further interrupt. 4592 */ 4593 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4594 return (FILTER_HANDLED); 4595} 4596 4597static void 4598bge_intr_task(void *arg, int pending) 4599{ 4600 struct bge_softc *sc; 4601 struct ifnet *ifp; 4602 uint32_t status, status_tag; 4603 uint16_t rx_prod, tx_cons; 4604 4605 sc = (struct bge_softc *)arg; 4606 ifp = sc->bge_ifp; 4607 4608 BGE_LOCK(sc); 4609 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4610 BGE_UNLOCK(sc); 4611 return; 4612 } 4613 4614 /* Get updated status block. */ 4615 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4616 sc->bge_cdata.bge_status_map, 4617 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4618 4619 /* Save producer/consumer indices. */ 4620 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4621 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4622 status = sc->bge_ldata.bge_status_block->bge_status; 4623 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4624 /* Dirty the status flag. */ 4625 sc->bge_ldata.bge_status_block->bge_status = 0; 4626 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4627 sc->bge_cdata.bge_status_map, 4628 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4629 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4630 status_tag = 0; 4631 4632 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4633 bge_link_upd(sc); 4634 4635 /* Let controller work. */ 4636 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4637 4638 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4639 sc->bge_rx_saved_considx != rx_prod) { 4640 /* Check RX return ring producer/consumer. */ 4641 BGE_UNLOCK(sc); 4642 bge_rxeof(sc, rx_prod, 0); 4643 BGE_LOCK(sc); 4644 } 4645 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4646 /* Check TX ring producer/consumer. */ 4647 bge_txeof(sc, tx_cons); 4648 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4649 bge_start_locked(ifp); 4650 } 4651 BGE_UNLOCK(sc); 4652} 4653 4654static void 4655bge_intr(void *xsc) 4656{ 4657 struct bge_softc *sc; 4658 struct ifnet *ifp; 4659 uint32_t statusword; 4660 uint16_t rx_prod, tx_cons; 4661 4662 sc = xsc; 4663 4664 BGE_LOCK(sc); 4665 4666 ifp = sc->bge_ifp; 4667 4668#ifdef DEVICE_POLLING 4669 if (ifp->if_capenable & IFCAP_POLLING) { 4670 BGE_UNLOCK(sc); 4671 return; 4672 } 4673#endif 4674 4675 /* 4676 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4677 * disable interrupts by writing nonzero like we used to, since with 4678 * our current organization this just gives complications and 4679 * pessimizations for re-enabling interrupts. We used to have races 4680 * instead of the necessary complications. Disabling interrupts 4681 * would just reduce the chance of a status update while we are 4682 * running (by switching to the interrupt-mode coalescence 4683 * parameters), but this chance is already very low so it is more 4684 * efficient to get another interrupt than prevent it. 4685 * 4686 * We do the ack first to ensure another interrupt if there is a 4687 * status update after the ack. We don't check for the status 4688 * changing later because it is more efficient to get another 4689 * interrupt than prevent it, not quite as above (not checking is 4690 * a smaller optimization than not toggling the interrupt enable, 4691 * since checking doesn't involve PCI accesses and toggling require 4692 * the status check). So toggling would probably be a pessimization 4693 * even with MSI. It would only be needed for using a task queue. 4694 */ 4695 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4696 4697 /* 4698 * Do the mandatory PCI flush as well as get the link status. 4699 */ 4700 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4701 4702 /* Make sure the descriptor ring indexes are coherent. */ 4703 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4704 sc->bge_cdata.bge_status_map, 4705 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4706 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4707 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4708 sc->bge_ldata.bge_status_block->bge_status = 0; 4709 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4710 sc->bge_cdata.bge_status_map, 4711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4712 4713 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4714 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4715 statusword || sc->bge_link_evt) 4716 bge_link_upd(sc); 4717 4718 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4719 /* Check RX return ring producer/consumer. */ 4720 bge_rxeof(sc, rx_prod, 1); 4721 } 4722 4723 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4724 /* Check TX ring producer/consumer. */ 4725 bge_txeof(sc, tx_cons); 4726 } 4727 4728 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4729 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4730 bge_start_locked(ifp); 4731 4732 BGE_UNLOCK(sc); 4733} 4734 4735static void 4736bge_asf_driver_up(struct bge_softc *sc) 4737{ 4738 if (sc->bge_asf_mode & ASF_STACKUP) { 4739 /* Send ASF heartbeat aprox. every 2s */ 4740 if (sc->bge_asf_count) 4741 sc->bge_asf_count --; 4742 else { 4743 sc->bge_asf_count = 2; 4744 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4745 BGE_FW_CMD_DRV_ALIVE); 4746 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4747 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4748 BGE_FW_HB_TIMEOUT_SEC); 4749 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4750 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4751 BGE_RX_CPU_DRV_EVENT); 4752 } 4753 } 4754} 4755 4756static void 4757bge_tick(void *xsc) 4758{ 4759 struct bge_softc *sc = xsc; 4760 struct mii_data *mii = NULL; 4761 4762 BGE_LOCK_ASSERT(sc); 4763 4764 /* Synchronize with possible callout reset/stop. */ 4765 if (callout_pending(&sc->bge_stat_ch) || 4766 !callout_active(&sc->bge_stat_ch)) 4767 return; 4768 4769 if (BGE_IS_5705_PLUS(sc)) 4770 bge_stats_update_regs(sc); 4771 else 4772 bge_stats_update(sc); 4773 4774 /* XXX Add APE heartbeat check here? */ 4775 4776 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4777 mii = device_get_softc(sc->bge_miibus); 4778 /* 4779 * Do not touch PHY if we have link up. This could break 4780 * IPMI/ASF mode or produce extra input errors 4781 * (extra errors was reported for bcm5701 & bcm5704). 4782 */ 4783 if (!sc->bge_link) 4784 mii_tick(mii); 4785 } else { 4786 /* 4787 * Since in TBI mode auto-polling can't be used we should poll 4788 * link status manually. Here we register pending link event 4789 * and trigger interrupt. 4790 */ 4791#ifdef DEVICE_POLLING 4792 /* In polling mode we poll link state in bge_poll(). */ 4793 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 4794#endif 4795 { 4796 sc->bge_link_evt++; 4797 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4798 sc->bge_flags & BGE_FLAG_5788) 4799 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4800 else 4801 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4802 } 4803 } 4804 4805 bge_asf_driver_up(sc); 4806 bge_watchdog(sc); 4807 4808 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4809} 4810 4811static void 4812bge_stats_update_regs(struct bge_softc *sc) 4813{ 4814 struct ifnet *ifp; 4815 struct bge_mac_stats *stats; 4816 uint32_t val; 4817 4818 ifp = sc->bge_ifp; 4819 stats = &sc->bge_mac_stats; 4820 4821 stats->ifHCOutOctets += 4822 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4823 stats->etherStatsCollisions += 4824 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4825 stats->outXonSent += 4826 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4827 stats->outXoffSent += 4828 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4829 stats->dot3StatsInternalMacTransmitErrors += 4830 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4831 stats->dot3StatsSingleCollisionFrames += 4832 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4833 stats->dot3StatsMultipleCollisionFrames += 4834 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4835 stats->dot3StatsDeferredTransmissions += 4836 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4837 stats->dot3StatsExcessiveCollisions += 4838 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4839 stats->dot3StatsLateCollisions += 4840 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4841 stats->ifHCOutUcastPkts += 4842 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4843 stats->ifHCOutMulticastPkts += 4844 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4845 stats->ifHCOutBroadcastPkts += 4846 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4847 4848 stats->ifHCInOctets += 4849 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4850 stats->etherStatsFragments += 4851 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4852 stats->ifHCInUcastPkts += 4853 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4854 stats->ifHCInMulticastPkts += 4855 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4856 stats->ifHCInBroadcastPkts += 4857 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4858 stats->dot3StatsFCSErrors += 4859 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4860 stats->dot3StatsAlignmentErrors += 4861 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4862 stats->xonPauseFramesReceived += 4863 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4864 stats->xoffPauseFramesReceived += 4865 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4866 stats->macControlFramesReceived += 4867 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4868 stats->xoffStateEntered += 4869 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4870 stats->dot3StatsFramesTooLong += 4871 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4872 stats->etherStatsJabbers += 4873 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4874 stats->etherStatsUndersizePkts += 4875 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4876 4877 stats->FramesDroppedDueToFilters += 4878 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4879 stats->DmaWriteQueueFull += 4880 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4881 stats->DmaWriteHighPriQueueFull += 4882 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4883 stats->NoMoreRxBDs += 4884 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4885 /* 4886 * XXX 4887 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4888 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4889 * includes number of unwanted multicast frames. This comes 4890 * from silicon bug and known workaround to get rough(not 4891 * exact) counter is to enable interrupt on MBUF low water 4892 * attention. This can be accomplished by setting 4893 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4894 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4895 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4896 * However that change would generate more interrupts and 4897 * there are still possibilities of losing multiple frames 4898 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4899 * Given that the workaround still would not get correct 4900 * counter I don't think it's worth to implement it. So 4901 * ignore reading the counter on controllers that have the 4902 * silicon bug. 4903 */ 4904 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4905 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4906 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4907 stats->InputDiscards += 4908 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4909 stats->InputErrors += 4910 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4911 stats->RecvThresholdHit += 4912 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4913 4914 ifp->if_collisions = (u_long)stats->etherStatsCollisions; 4915 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4916 stats->InputErrors); 4917 4918 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 4919 /* 4920 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4921 * frames, it's safe to disable workaround for DMA engine's 4922 * miscalculation of TXMBUF space. 4923 */ 4924 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts + 4925 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) { 4926 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4927 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 4928 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4929 else 4930 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4931 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4932 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG; 4933 } 4934 } 4935} 4936 4937static void 4938bge_stats_clear_regs(struct bge_softc *sc) 4939{ 4940 4941 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4942 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4943 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4944 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4945 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4946 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4947 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4948 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4949 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4950 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4951 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4952 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4953 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4954 4955 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4956 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4957 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4958 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4959 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4960 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4961 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4962 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4963 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4964 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4965 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4966 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4967 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4968 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4969 4970 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4971 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4972 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4973 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4974 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4975 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4976 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4977} 4978 4979static void 4980bge_stats_update(struct bge_softc *sc) 4981{ 4982 struct ifnet *ifp; 4983 bus_size_t stats; 4984 uint32_t cnt; /* current register value */ 4985 4986 ifp = sc->bge_ifp; 4987 4988 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4989 4990#define READ_STAT(sc, stats, stat) \ 4991 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4992 4993 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4994 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 4995 sc->bge_tx_collisions = cnt; 4996 4997 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 4998 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds); 4999 sc->bge_rx_nobds = cnt; 5000 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 5001 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs); 5002 sc->bge_rx_inerrs = cnt; 5003 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 5004 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 5005 sc->bge_rx_discards = cnt; 5006 5007 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 5008 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 5009 sc->bge_tx_discards = cnt; 5010 5011#undef READ_STAT 5012} 5013 5014/* 5015 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5016 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5017 * but when such padded frames employ the bge IP/TCP checksum offload, 5018 * the hardware checksum assist gives incorrect results (possibly 5019 * from incorporating its own padding into the UDP/TCP checksum; who knows). 5020 * If we pad such runts with zeros, the onboard checksum comes out correct. 5021 */ 5022static __inline int 5023bge_cksum_pad(struct mbuf *m) 5024{ 5025 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 5026 struct mbuf *last; 5027 5028 /* If there's only the packet-header and we can pad there, use it. */ 5029 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 5030 M_TRAILINGSPACE(m) >= padlen) { 5031 last = m; 5032 } else { 5033 /* 5034 * Walk packet chain to find last mbuf. We will either 5035 * pad there, or append a new mbuf and pad it. 5036 */ 5037 for (last = m; last->m_next != NULL; last = last->m_next); 5038 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 5039 /* Allocate new empty mbuf, pad it. Compact later. */ 5040 struct mbuf *n; 5041 5042 MGET(n, M_NOWAIT, MT_DATA); 5043 if (n == NULL) 5044 return (ENOBUFS); 5045 n->m_len = 0; 5046 last->m_next = n; 5047 last = n; 5048 } 5049 } 5050 5051 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 5052 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 5053 last->m_len += padlen; 5054 m->m_pkthdr.len += padlen; 5055 5056 return (0); 5057} 5058 5059static struct mbuf * 5060bge_check_short_dma(struct mbuf *m) 5061{ 5062 struct mbuf *n; 5063 int found; 5064 5065 /* 5066 * If device receive two back-to-back send BDs with less than 5067 * or equal to 8 total bytes then the device may hang. The two 5068 * back-to-back send BDs must in the same frame for this failure 5069 * to occur. Scan mbuf chains and see whether two back-to-back 5070 * send BDs are there. If this is the case, allocate new mbuf 5071 * and copy the frame to workaround the silicon bug. 5072 */ 5073 for (n = m, found = 0; n != NULL; n = n->m_next) { 5074 if (n->m_len < 8) { 5075 found++; 5076 if (found > 1) 5077 break; 5078 continue; 5079 } 5080 found = 0; 5081 } 5082 5083 if (found > 1) { 5084 n = m_defrag(m, M_NOWAIT); 5085 if (n == NULL) 5086 m_freem(m); 5087 } else 5088 n = m; 5089 return (n); 5090} 5091 5092static struct mbuf * 5093bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 5094 uint16_t *flags) 5095{ 5096 struct ip *ip; 5097 struct tcphdr *tcp; 5098 struct mbuf *n; 5099 uint16_t hlen; 5100 uint32_t poff; 5101 5102 if (M_WRITABLE(m) == 0) { 5103 /* Get a writable copy. */ 5104 n = m_dup(m, M_NOWAIT); 5105 m_freem(m); 5106 if (n == NULL) 5107 return (NULL); 5108 m = n; 5109 } 5110 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5111 if (m == NULL) 5112 return (NULL); 5113 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5114 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5115 m = m_pullup(m, poff + sizeof(struct tcphdr)); 5116 if (m == NULL) 5117 return (NULL); 5118 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5119 m = m_pullup(m, poff + (tcp->th_off << 2)); 5120 if (m == NULL) 5121 return (NULL); 5122 /* 5123 * It seems controller doesn't modify IP length and TCP pseudo 5124 * checksum. These checksum computed by upper stack should be 0. 5125 */ 5126 *mss = m->m_pkthdr.tso_segsz; 5127 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5128 ip->ip_sum = 0; 5129 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5130 /* Clear pseudo checksum computed by TCP stack. */ 5131 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5132 tcp->th_sum = 0; 5133 /* 5134 * Broadcom controllers uses different descriptor format for 5135 * TSO depending on ASIC revision. Due to TSO-capable firmware 5136 * license issue and lower performance of firmware based TSO 5137 * we only support hardware based TSO. 5138 */ 5139 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5140 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 5141 if (sc->bge_flags & BGE_FLAG_TSO3) { 5142 /* 5143 * For BCM5717 and newer controllers, hardware based TSO 5144 * uses the 14 lower bits of the bge_mss field to store the 5145 * MSS and the upper 2 bits to store the lowest 2 bits of 5146 * the IP/TCP header length. The upper 6 bits of the header 5147 * length are stored in the bge_flags[14:10,4] field. Jumbo 5148 * frames are supported. 5149 */ 5150 *mss |= ((hlen & 0x3) << 14); 5151 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 5152 } else { 5153 /* 5154 * For BCM5755 and newer controllers, hardware based TSO uses 5155 * the lower 11 bits to store the MSS and the upper 5 bits to 5156 * store the IP/TCP header length. Jumbo frames are not 5157 * supported. 5158 */ 5159 *mss |= (hlen << 11); 5160 } 5161 return (m); 5162} 5163 5164/* 5165 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5166 * pointers to descriptors. 5167 */ 5168static int 5169bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 5170{ 5171 bus_dma_segment_t segs[BGE_NSEG_NEW]; 5172 bus_dmamap_t map; 5173 struct bge_tx_bd *d; 5174 struct mbuf *m = *m_head; 5175 uint32_t idx = *txidx; 5176 uint16_t csum_flags, mss, vlan_tag; 5177 int nsegs, i, error; 5178 5179 csum_flags = 0; 5180 mss = 0; 5181 vlan_tag = 0; 5182 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5183 m->m_next != NULL) { 5184 *m_head = bge_check_short_dma(m); 5185 if (*m_head == NULL) 5186 return (ENOBUFS); 5187 m = *m_head; 5188 } 5189 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5190 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5191 if (*m_head == NULL) 5192 return (ENOBUFS); 5193 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5194 BGE_TXBDFLAG_CPU_POST_DMA; 5195 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 5196 if (m->m_pkthdr.csum_flags & CSUM_IP) 5197 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5198 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 5199 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5200 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 5201 (error = bge_cksum_pad(m)) != 0) { 5202 m_freem(m); 5203 *m_head = NULL; 5204 return (error); 5205 } 5206 } 5207 } 5208 5209 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 5210 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 5211 m->m_pkthdr.len > ETHER_MAX_LEN) 5212 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 5213 if (sc->bge_forced_collapse > 0 && 5214 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5215 /* 5216 * Forcedly collapse mbuf chains to overcome hardware 5217 * limitation which only support a single outstanding 5218 * DMA read operation. 5219 */ 5220 if (sc->bge_forced_collapse == 1) 5221 m = m_defrag(m, M_NOWAIT); 5222 else 5223 m = m_collapse(m, M_NOWAIT, 5224 sc->bge_forced_collapse); 5225 if (m == NULL) 5226 m = *m_head; 5227 *m_head = m; 5228 } 5229 } 5230 5231 map = sc->bge_cdata.bge_tx_dmamap[idx]; 5232 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5233 &nsegs, BUS_DMA_NOWAIT); 5234 if (error == EFBIG) { 5235 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5236 if (m == NULL) { 5237 m_freem(*m_head); 5238 *m_head = NULL; 5239 return (ENOBUFS); 5240 } 5241 *m_head = m; 5242 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 5243 m, segs, &nsegs, BUS_DMA_NOWAIT); 5244 if (error) { 5245 m_freem(m); 5246 *m_head = NULL; 5247 return (error); 5248 } 5249 } else if (error != 0) 5250 return (error); 5251 5252 /* Check if we have enough free send BDs. */ 5253 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 5254 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5255 return (ENOBUFS); 5256 } 5257 5258 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5259 5260 if (m->m_flags & M_VLANTAG) { 5261 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5262 vlan_tag = m->m_pkthdr.ether_vtag; 5263 } 5264 5265 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 && 5266 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5267 /* 5268 * 5725 family of devices corrupts TSO packets when TSO DMA 5269 * buffers cross into regions which are within MSS bytes of 5270 * a 4GB boundary. If we encounter the condition, drop the 5271 * packet. 5272 */ 5273 for (i = 0; ; i++) { 5274 d = &sc->bge_ldata.bge_tx_ring[idx]; 5275 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5276 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5277 d->bge_len = segs[i].ds_len; 5278 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss < 5279 d->bge_addr.bge_addr_lo) 5280 break; 5281 d->bge_flags = csum_flags; 5282 d->bge_vlan_tag = vlan_tag; 5283 d->bge_mss = mss; 5284 if (i == nsegs - 1) 5285 break; 5286 BGE_INC(idx, BGE_TX_RING_CNT); 5287 } 5288 if (i != nsegs - 1) { 5289 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, 5290 BUS_DMASYNC_POSTWRITE); 5291 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5292 m_freem(*m_head); 5293 *m_head = NULL; 5294 return (EIO); 5295 } 5296 } else { 5297 for (i = 0; ; i++) { 5298 d = &sc->bge_ldata.bge_tx_ring[idx]; 5299 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5300 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5301 d->bge_len = segs[i].ds_len; 5302 d->bge_flags = csum_flags; 5303 d->bge_vlan_tag = vlan_tag; 5304 d->bge_mss = mss; 5305 if (i == nsegs - 1) 5306 break; 5307 BGE_INC(idx, BGE_TX_RING_CNT); 5308 } 5309 } 5310 5311 /* Mark the last segment as end of packet... */ 5312 d->bge_flags |= BGE_TXBDFLAG_END; 5313 5314 /* 5315 * Insure that the map for this transmission 5316 * is placed at the array index of the last descriptor 5317 * in this chain. 5318 */ 5319 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 5320 sc->bge_cdata.bge_tx_dmamap[idx] = map; 5321 sc->bge_cdata.bge_tx_chain[idx] = m; 5322 sc->bge_txcnt += nsegs; 5323 5324 BGE_INC(idx, BGE_TX_RING_CNT); 5325 *txidx = idx; 5326 5327 return (0); 5328} 5329 5330/* 5331 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5332 * to the mbuf data regions directly in the transmit descriptors. 5333 */ 5334static void 5335bge_start_locked(struct ifnet *ifp) 5336{ 5337 struct bge_softc *sc; 5338 struct mbuf *m_head; 5339 uint32_t prodidx; 5340 int count; 5341 5342 sc = ifp->if_softc; 5343 BGE_LOCK_ASSERT(sc); 5344 5345 if (!sc->bge_link || 5346 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5347 IFF_DRV_RUNNING) 5348 return; 5349 5350 prodidx = sc->bge_tx_prodidx; 5351 5352 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 5353 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5354 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5355 break; 5356 } 5357 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 5358 if (m_head == NULL) 5359 break; 5360 5361 /* 5362 * Pack the data into the transmit ring. If we 5363 * don't have room, set the OACTIVE flag and wait 5364 * for the NIC to drain the ring. 5365 */ 5366 if (bge_encap(sc, &m_head, &prodidx)) { 5367 if (m_head == NULL) 5368 break; 5369 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 5370 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5371 break; 5372 } 5373 ++count; 5374 5375 /* 5376 * If there's a BPF listener, bounce a copy of this frame 5377 * to him. 5378 */ 5379#ifdef ETHER_BPF_MTAP 5380 ETHER_BPF_MTAP(ifp, m_head); 5381#else 5382 BPF_MTAP(ifp, m_head); 5383#endif 5384 } 5385 5386 if (count > 0) { 5387 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 5388 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 5389 /* Transmit. */ 5390 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5391 /* 5700 b2 errata */ 5392 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 5393 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5394 5395 sc->bge_tx_prodidx = prodidx; 5396 5397 /* 5398 * Set a timeout in case the chip goes out to lunch. 5399 */ 5400 sc->bge_timer = BGE_TX_TIMEOUT; 5401 } 5402} 5403 5404/* 5405 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5406 * to the mbuf data regions directly in the transmit descriptors. 5407 */ 5408static void 5409bge_start(struct ifnet *ifp) 5410{ 5411 struct bge_softc *sc; 5412 5413 sc = ifp->if_softc; 5414 BGE_LOCK(sc); 5415 bge_start_locked(ifp); 5416 BGE_UNLOCK(sc); 5417} 5418 5419static void 5420bge_init_locked(struct bge_softc *sc) 5421{ 5422 struct ifnet *ifp; 5423 uint16_t *m; 5424 uint32_t mode; 5425 5426 BGE_LOCK_ASSERT(sc); 5427 5428 ifp = sc->bge_ifp; 5429 5430 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5431 return; 5432 5433 /* Cancel pending I/O and flush buffers. */ 5434 bge_stop(sc); 5435 5436 bge_stop_fw(sc); 5437 bge_sig_pre_reset(sc, BGE_RESET_START); 5438 bge_reset(sc); 5439 bge_sig_legacy(sc, BGE_RESET_START); 5440 bge_sig_post_reset(sc, BGE_RESET_START); 5441 5442 bge_chipinit(sc); 5443 5444 /* 5445 * Init the various state machines, ring 5446 * control blocks and firmware. 5447 */ 5448 if (bge_blockinit(sc)) { 5449 device_printf(sc->bge_dev, "initialization failure\n"); 5450 return; 5451 } 5452 5453 ifp = sc->bge_ifp; 5454 5455 /* Specify MTU. */ 5456 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5457 ETHER_HDR_LEN + ETHER_CRC_LEN + 5458 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 5459 5460 /* Load our MAC address. */ 5461 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 5462 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5463 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5464 5465 /* Program promiscuous mode. */ 5466 bge_setpromisc(sc); 5467 5468 /* Program multicast filter. */ 5469 bge_setmulti(sc); 5470 5471 /* Program VLAN tag stripping. */ 5472 bge_setvlan(sc); 5473 5474 /* Override UDP checksum offloading. */ 5475 if (sc->bge_forced_udpcsum == 0) 5476 sc->bge_csum_features &= ~CSUM_UDP; 5477 else 5478 sc->bge_csum_features |= CSUM_UDP; 5479 if (ifp->if_capabilities & IFCAP_TXCSUM && 5480 ifp->if_capenable & IFCAP_TXCSUM) { 5481 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 5482 ifp->if_hwassist |= sc->bge_csum_features; 5483 } 5484 5485 /* Init RX ring. */ 5486 if (bge_init_rx_ring_std(sc) != 0) { 5487 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5488 bge_stop(sc); 5489 return; 5490 } 5491 5492 /* 5493 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5494 * memory to insure that the chip has in fact read the first 5495 * entry of the ring. 5496 */ 5497 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5498 uint32_t v, i; 5499 for (i = 0; i < 10; i++) { 5500 DELAY(20); 5501 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5502 if (v == (MCLBYTES - ETHER_ALIGN)) 5503 break; 5504 } 5505 if (i == 10) 5506 device_printf (sc->bge_dev, 5507 "5705 A0 chip failed to load RX ring\n"); 5508 } 5509 5510 /* Init jumbo RX ring. */ 5511 if (BGE_IS_JUMBO_CAPABLE(sc) && 5512 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 5513 (MCLBYTES - ETHER_ALIGN)) { 5514 if (bge_init_rx_ring_jumbo(sc) != 0) { 5515 device_printf(sc->bge_dev, 5516 "no memory for jumbo Rx buffers.\n"); 5517 bge_stop(sc); 5518 return; 5519 } 5520 } 5521 5522 /* Init our RX return ring index. */ 5523 sc->bge_rx_saved_considx = 0; 5524 5525 /* Init our RX/TX stat counters. */ 5526 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5527 5528 /* Init TX ring. */ 5529 bge_init_tx_ring(sc); 5530 5531 /* Enable TX MAC state machine lockup fix. */ 5532 mode = CSR_READ_4(sc, BGE_TX_MODE); 5533 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5534 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5535 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 5536 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 5537 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5538 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5539 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5540 } 5541 /* Turn on transmitter. */ 5542 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5543 DELAY(100); 5544 5545 /* Turn on receiver. */ 5546 mode = CSR_READ_4(sc, BGE_RX_MODE); 5547 if (BGE_IS_5755_PLUS(sc)) 5548 mode |= BGE_RXMODE_IPV6_ENABLE; 5549 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 5550 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5551 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5552 DELAY(10); 5553 5554 /* 5555 * Set the number of good frames to receive after RX MBUF 5556 * Low Watermark has been reached. After the RX MAC receives 5557 * this number of frames, it will drop subsequent incoming 5558 * frames until the MBUF High Watermark is reached. 5559 */ 5560 if (BGE_IS_57765_PLUS(sc)) 5561 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5562 else 5563 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5564 5565 /* Clear MAC statistics. */ 5566 if (BGE_IS_5705_PLUS(sc)) 5567 bge_stats_clear_regs(sc); 5568 5569 /* Tell firmware we're alive. */ 5570 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5571 5572#ifdef DEVICE_POLLING 5573 /* Disable interrupts if we are polling. */ 5574 if (ifp->if_capenable & IFCAP_POLLING) { 5575 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5576 BGE_PCIMISCCTL_MASK_PCI_INTR); 5577 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5578 } else 5579#endif 5580 5581 /* Enable host interrupts. */ 5582 { 5583 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5584 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5585 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5586 } 5587 5588 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5589 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5590 5591 bge_ifmedia_upd_locked(ifp); 5592 5593 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5594} 5595 5596static void 5597bge_init(void *xsc) 5598{ 5599 struct bge_softc *sc = xsc; 5600 5601 BGE_LOCK(sc); 5602 bge_init_locked(sc); 5603 BGE_UNLOCK(sc); 5604} 5605 5606/* 5607 * Set media options. 5608 */ 5609static int 5610bge_ifmedia_upd(struct ifnet *ifp) 5611{ 5612 struct bge_softc *sc = ifp->if_softc; 5613 int res; 5614 5615 BGE_LOCK(sc); 5616 res = bge_ifmedia_upd_locked(ifp); 5617 BGE_UNLOCK(sc); 5618 5619 return (res); 5620} 5621 5622static int 5623bge_ifmedia_upd_locked(struct ifnet *ifp) 5624{ 5625 struct bge_softc *sc = ifp->if_softc; 5626 struct mii_data *mii; 5627 struct mii_softc *miisc; 5628 struct ifmedia *ifm; 5629 5630 BGE_LOCK_ASSERT(sc); 5631 5632 ifm = &sc->bge_ifmedia; 5633 5634 /* If this is a 1000baseX NIC, enable the TBI port. */ 5635 if (sc->bge_flags & BGE_FLAG_TBI) { 5636 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5637 return (EINVAL); 5638 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5639 case IFM_AUTO: 5640 /* 5641 * The BCM5704 ASIC appears to have a special 5642 * mechanism for programming the autoneg 5643 * advertisement registers in TBI mode. 5644 */ 5645 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5646 uint32_t sgdig; 5647 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5648 if (sgdig & BGE_SGDIGSTS_DONE) { 5649 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5650 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5651 sgdig |= BGE_SGDIGCFG_AUTO | 5652 BGE_SGDIGCFG_PAUSE_CAP | 5653 BGE_SGDIGCFG_ASYM_PAUSE; 5654 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5655 sgdig | BGE_SGDIGCFG_SEND); 5656 DELAY(5); 5657 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5658 } 5659 } 5660 break; 5661 case IFM_1000_SX: 5662 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5663 BGE_CLRBIT(sc, BGE_MAC_MODE, 5664 BGE_MACMODE_HALF_DUPLEX); 5665 } else { 5666 BGE_SETBIT(sc, BGE_MAC_MODE, 5667 BGE_MACMODE_HALF_DUPLEX); 5668 } 5669 DELAY(40); 5670 break; 5671 default: 5672 return (EINVAL); 5673 } 5674 return (0); 5675 } 5676 5677 sc->bge_link_evt++; 5678 mii = device_get_softc(sc->bge_miibus); 5679 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5680 PHY_RESET(miisc); 5681 mii_mediachg(mii); 5682 5683 /* 5684 * Force an interrupt so that we will call bge_link_upd 5685 * if needed and clear any pending link state attention. 5686 * Without this we are not getting any further interrupts 5687 * for link state changes and thus will not UP the link and 5688 * not be able to send in bge_start_locked. The only 5689 * way to get things working was to receive a packet and 5690 * get an RX intr. 5691 * bge_tick should help for fiber cards and we might not 5692 * need to do this here if BGE_FLAG_TBI is set but as 5693 * we poll for fiber anyway it should not harm. 5694 */ 5695 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5696 sc->bge_flags & BGE_FLAG_5788) 5697 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5698 else 5699 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5700 5701 return (0); 5702} 5703 5704/* 5705 * Report current media status. 5706 */ 5707static void 5708bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5709{ 5710 struct bge_softc *sc = ifp->if_softc; 5711 struct mii_data *mii; 5712 5713 BGE_LOCK(sc); 5714 5715 if ((ifp->if_flags & IFF_UP) == 0) { 5716 BGE_UNLOCK(sc); 5717 return; 5718 } 5719 if (sc->bge_flags & BGE_FLAG_TBI) { 5720 ifmr->ifm_status = IFM_AVALID; 5721 ifmr->ifm_active = IFM_ETHER; 5722 if (CSR_READ_4(sc, BGE_MAC_STS) & 5723 BGE_MACSTAT_TBI_PCS_SYNCHED) 5724 ifmr->ifm_status |= IFM_ACTIVE; 5725 else { 5726 ifmr->ifm_active |= IFM_NONE; 5727 BGE_UNLOCK(sc); 5728 return; 5729 } 5730 ifmr->ifm_active |= IFM_1000_SX; 5731 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5732 ifmr->ifm_active |= IFM_HDX; 5733 else 5734 ifmr->ifm_active |= IFM_FDX; 5735 BGE_UNLOCK(sc); 5736 return; 5737 } 5738 5739 mii = device_get_softc(sc->bge_miibus); 5740 mii_pollstat(mii); 5741 ifmr->ifm_active = mii->mii_media_active; 5742 ifmr->ifm_status = mii->mii_media_status; 5743 5744 BGE_UNLOCK(sc); 5745} 5746 5747static int 5748bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 5749{ 5750 struct bge_softc *sc = ifp->if_softc; 5751 struct ifreq *ifr = (struct ifreq *) data; 5752 struct mii_data *mii; 5753 int flags, mask, error = 0; 5754 5755 switch (command) { 5756 case SIOCSIFMTU: 5757 if (BGE_IS_JUMBO_CAPABLE(sc) || 5758 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5759 if (ifr->ifr_mtu < ETHERMIN || 5760 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5761 error = EINVAL; 5762 break; 5763 } 5764 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5765 error = EINVAL; 5766 break; 5767 } 5768 BGE_LOCK(sc); 5769 if (ifp->if_mtu != ifr->ifr_mtu) { 5770 ifp->if_mtu = ifr->ifr_mtu; 5771 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5772 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5773 bge_init_locked(sc); 5774 } 5775 } 5776 BGE_UNLOCK(sc); 5777 break; 5778 case SIOCSIFFLAGS: 5779 BGE_LOCK(sc); 5780 if (ifp->if_flags & IFF_UP) { 5781 /* 5782 * If only the state of the PROMISC flag changed, 5783 * then just use the 'set promisc mode' command 5784 * instead of reinitializing the entire NIC. Doing 5785 * a full re-init means reloading the firmware and 5786 * waiting for it to start up, which may take a 5787 * second or two. Similarly for ALLMULTI. 5788 */ 5789 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5790 flags = ifp->if_flags ^ sc->bge_if_flags; 5791 if (flags & IFF_PROMISC) 5792 bge_setpromisc(sc); 5793 if (flags & IFF_ALLMULTI) 5794 bge_setmulti(sc); 5795 } else 5796 bge_init_locked(sc); 5797 } else { 5798 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5799 bge_stop(sc); 5800 } 5801 } 5802 sc->bge_if_flags = ifp->if_flags; 5803 BGE_UNLOCK(sc); 5804 error = 0; 5805 break; 5806 case SIOCADDMULTI: 5807 case SIOCDELMULTI: 5808 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5809 BGE_LOCK(sc); 5810 bge_setmulti(sc); 5811 BGE_UNLOCK(sc); 5812 error = 0; 5813 } 5814 break; 5815 case SIOCSIFMEDIA: 5816 case SIOCGIFMEDIA: 5817 if (sc->bge_flags & BGE_FLAG_TBI) { 5818 error = ifmedia_ioctl(ifp, ifr, 5819 &sc->bge_ifmedia, command); 5820 } else { 5821 mii = device_get_softc(sc->bge_miibus); 5822 error = ifmedia_ioctl(ifp, ifr, 5823 &mii->mii_media, command); 5824 } 5825 break; 5826 case SIOCSIFCAP: 5827 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5828#ifdef DEVICE_POLLING 5829 if (mask & IFCAP_POLLING) { 5830 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5831 error = ether_poll_register(bge_poll, ifp); 5832 if (error) 5833 return (error); 5834 BGE_LOCK(sc); 5835 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5836 BGE_PCIMISCCTL_MASK_PCI_INTR); 5837 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5838 ifp->if_capenable |= IFCAP_POLLING; 5839 BGE_UNLOCK(sc); 5840 } else { 5841 error = ether_poll_deregister(ifp); 5842 /* Enable interrupt even in error case */ 5843 BGE_LOCK(sc); 5844 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5845 BGE_PCIMISCCTL_MASK_PCI_INTR); 5846 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5847 ifp->if_capenable &= ~IFCAP_POLLING; 5848 BGE_UNLOCK(sc); 5849 } 5850 } 5851#endif 5852 if ((mask & IFCAP_TXCSUM) != 0 && 5853 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 5854 ifp->if_capenable ^= IFCAP_TXCSUM; 5855 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 5856 ifp->if_hwassist |= sc->bge_csum_features; 5857 else 5858 ifp->if_hwassist &= ~sc->bge_csum_features; 5859 } 5860 5861 if ((mask & IFCAP_RXCSUM) != 0 && 5862 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 5863 ifp->if_capenable ^= IFCAP_RXCSUM; 5864 5865 if ((mask & IFCAP_TSO4) != 0 && 5866 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 5867 ifp->if_capenable ^= IFCAP_TSO4; 5868 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 5869 ifp->if_hwassist |= CSUM_TSO; 5870 else 5871 ifp->if_hwassist &= ~CSUM_TSO; 5872 } 5873 5874 if (mask & IFCAP_VLAN_MTU) { 5875 ifp->if_capenable ^= IFCAP_VLAN_MTU; 5876 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5877 bge_init(sc); 5878 } 5879 5880 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5881 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 5882 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 5883 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5884 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 5885 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 5886 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 5887 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 5888 BGE_LOCK(sc); 5889 bge_setvlan(sc); 5890 BGE_UNLOCK(sc); 5891 } 5892#ifdef VLAN_CAPABILITIES 5893 VLAN_CAPABILITIES(ifp); 5894#endif 5895 break; 5896 default: 5897 error = ether_ioctl(ifp, command, data); 5898 break; 5899 } 5900 5901 return (error); 5902} 5903 5904static void 5905bge_watchdog(struct bge_softc *sc) 5906{ 5907 struct ifnet *ifp; 5908 uint32_t status; 5909 5910 BGE_LOCK_ASSERT(sc); 5911 5912 if (sc->bge_timer == 0 || --sc->bge_timer) 5913 return; 5914 5915 /* If pause frames are active then don't reset the hardware. */ 5916 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5917 status = CSR_READ_4(sc, BGE_RX_STS); 5918 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5919 /* 5920 * If link partner has us in XOFF state then wait for 5921 * the condition to clear. 5922 */ 5923 CSR_WRITE_4(sc, BGE_RX_STS, status); 5924 sc->bge_timer = BGE_TX_TIMEOUT; 5925 return; 5926 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5927 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5928 /* 5929 * If link partner has us in XOFF state then wait for 5930 * the condition to clear. 5931 */ 5932 CSR_WRITE_4(sc, BGE_RX_STS, status); 5933 sc->bge_timer = BGE_TX_TIMEOUT; 5934 return; 5935 } 5936 /* 5937 * Any other condition is unexpected and the controller 5938 * should be reset. 5939 */ 5940 } 5941 5942 ifp = sc->bge_ifp; 5943 5944 if_printf(ifp, "watchdog timeout -- resetting\n"); 5945 5946 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5947 bge_init_locked(sc); 5948 5949 ifp->if_oerrors++; 5950} 5951 5952static void 5953bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5954{ 5955 int i; 5956 5957 BGE_CLRBIT(sc, reg, bit); 5958 5959 for (i = 0; i < BGE_TIMEOUT; i++) { 5960 if ((CSR_READ_4(sc, reg) & bit) == 0) 5961 return; 5962 DELAY(100); 5963 } 5964} 5965 5966/* 5967 * Stop the adapter and free any mbufs allocated to the 5968 * RX and TX lists. 5969 */ 5970static void 5971bge_stop(struct bge_softc *sc) 5972{ 5973 struct ifnet *ifp; 5974 5975 BGE_LOCK_ASSERT(sc); 5976 5977 ifp = sc->bge_ifp; 5978 5979 callout_stop(&sc->bge_stat_ch); 5980 5981 /* Disable host interrupts. */ 5982 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5983 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5984 5985 /* 5986 * Tell firmware we're shutting down. 5987 */ 5988 bge_stop_fw(sc); 5989 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5990 5991 /* 5992 * Disable all of the receiver blocks. 5993 */ 5994 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5995 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5996 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5997 if (BGE_IS_5700_FAMILY(sc)) 5998 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5999 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 6000 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6001 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6002 6003 /* 6004 * Disable all of the transmit blocks. 6005 */ 6006 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6007 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6008 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6009 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6010 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6011 if (BGE_IS_5700_FAMILY(sc)) 6012 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6013 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6014 6015 /* 6016 * Shut down all of the memory managers and related 6017 * state machines. 6018 */ 6019 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6020 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6021 if (BGE_IS_5700_FAMILY(sc)) 6022 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6023 6024 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6025 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6026 if (!(BGE_IS_5705_PLUS(sc))) { 6027 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6028 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6029 } 6030 /* Update MAC statistics. */ 6031 if (BGE_IS_5705_PLUS(sc)) 6032 bge_stats_update_regs(sc); 6033 6034 bge_reset(sc); 6035 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6036 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6037 6038 /* 6039 * Keep the ASF firmware running if up. 6040 */ 6041 if (sc->bge_asf_mode & ASF_STACKUP) 6042 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6043 else 6044 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6045 6046 /* Free the RX lists. */ 6047 bge_free_rx_ring_std(sc); 6048 6049 /* Free jumbo RX list. */ 6050 if (BGE_IS_JUMBO_CAPABLE(sc)) 6051 bge_free_rx_ring_jumbo(sc); 6052 6053 /* Free TX buffers. */ 6054 bge_free_tx_ring(sc); 6055 6056 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6057 6058 /* Clear MAC's link state (PHY may still have link UP). */ 6059 if (bootverbose && sc->bge_link) 6060 if_printf(sc->bge_ifp, "link DOWN\n"); 6061 sc->bge_link = 0; 6062 6063 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6064} 6065 6066/* 6067 * Stop all chip I/O so that the kernel's probe routines don't 6068 * get confused by errant DMAs when rebooting. 6069 */ 6070static int 6071bge_shutdown(device_t dev) 6072{ 6073 struct bge_softc *sc; 6074 6075 sc = device_get_softc(dev); 6076 BGE_LOCK(sc); 6077 bge_stop(sc); 6078 BGE_UNLOCK(sc); 6079 6080 return (0); 6081} 6082 6083static int 6084bge_suspend(device_t dev) 6085{ 6086 struct bge_softc *sc; 6087 6088 sc = device_get_softc(dev); 6089 BGE_LOCK(sc); 6090 bge_stop(sc); 6091 BGE_UNLOCK(sc); 6092 6093 return (0); 6094} 6095 6096static int 6097bge_resume(device_t dev) 6098{ 6099 struct bge_softc *sc; 6100 struct ifnet *ifp; 6101 6102 sc = device_get_softc(dev); 6103 BGE_LOCK(sc); 6104 ifp = sc->bge_ifp; 6105 if (ifp->if_flags & IFF_UP) { 6106 bge_init_locked(sc); 6107 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6108 bge_start_locked(ifp); 6109 } 6110 BGE_UNLOCK(sc); 6111 6112 return (0); 6113} 6114 6115static void 6116bge_link_upd(struct bge_softc *sc) 6117{ 6118 struct mii_data *mii; 6119 uint32_t link, status; 6120 6121 BGE_LOCK_ASSERT(sc); 6122 6123 /* Clear 'pending link event' flag. */ 6124 sc->bge_link_evt = 0; 6125 6126 /* 6127 * Process link state changes. 6128 * Grrr. The link status word in the status block does 6129 * not work correctly on the BCM5700 rev AX and BX chips, 6130 * according to all available information. Hence, we have 6131 * to enable MII interrupts in order to properly obtain 6132 * async link changes. Unfortunately, this also means that 6133 * we have to read the MAC status register to detect link 6134 * changes, thereby adding an additional register access to 6135 * the interrupt handler. 6136 * 6137 * XXX: perhaps link state detection procedure used for 6138 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 6139 */ 6140 6141 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6142 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 6143 status = CSR_READ_4(sc, BGE_MAC_STS); 6144 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6145 mii = device_get_softc(sc->bge_miibus); 6146 mii_pollstat(mii); 6147 if (!sc->bge_link && 6148 mii->mii_media_status & IFM_ACTIVE && 6149 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6150 sc->bge_link++; 6151 if (bootverbose) 6152 if_printf(sc->bge_ifp, "link UP\n"); 6153 } else if (sc->bge_link && 6154 (!(mii->mii_media_status & IFM_ACTIVE) || 6155 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6156 sc->bge_link = 0; 6157 if (bootverbose) 6158 if_printf(sc->bge_ifp, "link DOWN\n"); 6159 } 6160 6161 /* Clear the interrupt. */ 6162 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6163 BGE_EVTENB_MI_INTERRUPT); 6164 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6165 BRGPHY_MII_ISR); 6166 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6167 BRGPHY_MII_IMR, BRGPHY_INTRS); 6168 } 6169 return; 6170 } 6171 6172 if (sc->bge_flags & BGE_FLAG_TBI) { 6173 status = CSR_READ_4(sc, BGE_MAC_STS); 6174 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6175 if (!sc->bge_link) { 6176 sc->bge_link++; 6177 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 6178 BGE_CLRBIT(sc, BGE_MAC_MODE, 6179 BGE_MACMODE_TBI_SEND_CFGS); 6180 DELAY(40); 6181 } 6182 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6183 if (bootverbose) 6184 if_printf(sc->bge_ifp, "link UP\n"); 6185 if_link_state_change(sc->bge_ifp, 6186 LINK_STATE_UP); 6187 } 6188 } else if (sc->bge_link) { 6189 sc->bge_link = 0; 6190 if (bootverbose) 6191 if_printf(sc->bge_ifp, "link DOWN\n"); 6192 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 6193 } 6194 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 6195 /* 6196 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 6197 * in status word always set. Workaround this bug by reading 6198 * PHY link status directly. 6199 */ 6200 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 6201 6202 if (link != sc->bge_link || 6203 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 6204 mii = device_get_softc(sc->bge_miibus); 6205 mii_pollstat(mii); 6206 if (!sc->bge_link && 6207 mii->mii_media_status & IFM_ACTIVE && 6208 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6209 sc->bge_link++; 6210 if (bootverbose) 6211 if_printf(sc->bge_ifp, "link UP\n"); 6212 } else if (sc->bge_link && 6213 (!(mii->mii_media_status & IFM_ACTIVE) || 6214 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6215 sc->bge_link = 0; 6216 if (bootverbose) 6217 if_printf(sc->bge_ifp, "link DOWN\n"); 6218 } 6219 } 6220 } else { 6221 /* 6222 * For controllers that call mii_tick, we have to poll 6223 * link status. 6224 */ 6225 mii = device_get_softc(sc->bge_miibus); 6226 mii_pollstat(mii); 6227 bge_miibus_statchg(sc->bge_dev); 6228 } 6229 6230 /* Disable MAC attention when link is up. */ 6231 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6232 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6233 BGE_MACSTAT_LINK_CHANGED); 6234} 6235 6236static void 6237bge_add_sysctls(struct bge_softc *sc) 6238{ 6239 struct sysctl_ctx_list *ctx; 6240 struct sysctl_oid_list *children; 6241 char tn[32]; 6242 int unit; 6243 6244 ctx = device_get_sysctl_ctx(sc->bge_dev); 6245 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 6246 6247#ifdef BGE_REGISTER_DEBUG 6248 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 6249 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 6250 "Debug Information"); 6251 6252 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 6253 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 6254 "MAC Register Read"); 6255 6256 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6257 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I", 6258 "APE Register Read"); 6259 6260 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 6261 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 6262 "Memory Read"); 6263 6264#endif 6265 6266 unit = device_get_unit(sc->bge_dev); 6267 /* 6268 * A common design characteristic for many Broadcom client controllers 6269 * is that they only support a single outstanding DMA read operation 6270 * on the PCIe bus. This means that it will take twice as long to fetch 6271 * a TX frame that is split into header and payload buffers as it does 6272 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6273 * these controllers, coalescing buffers to reduce the number of memory 6274 * reads is effective way to get maximum performance(about 940Mbps). 6275 * Without collapsing TX buffers the maximum TCP bulk transfer 6276 * performance is about 850Mbps. However forcing coalescing mbufs 6277 * consumes a lot of CPU cycles, so leave it off by default. 6278 */ 6279 sc->bge_forced_collapse = 0; 6280 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 6281 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 6282 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6283 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 6284 "Number of fragmented TX buffers of a frame allowed before " 6285 "forced collapsing"); 6286 6287 sc->bge_msi = 1; 6288 snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit); 6289 TUNABLE_INT_FETCH(tn, &sc->bge_msi); 6290 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6291 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI"); 6292 6293 /* 6294 * It seems all Broadcom controllers have a bug that can generate UDP 6295 * datagrams with checksum value 0 when TX UDP checksum offloading is 6296 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 6297 * Even though the probability of generating such UDP datagrams is 6298 * low, I don't want to see FreeBSD boxes to inject such datagrams 6299 * into network so disable UDP checksum offloading by default. Users 6300 * still override this behavior by setting a sysctl variable, 6301 * dev.bge.0.forced_udpcsum. 6302 */ 6303 sc->bge_forced_udpcsum = 0; 6304 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 6305 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 6306 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6307 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 6308 "Enable UDP checksum offloading even if controller can " 6309 "generate UDP checksum value 0"); 6310 6311 if (BGE_IS_5705_PLUS(sc)) 6312 bge_add_sysctl_stats_regs(sc, ctx, children); 6313 else 6314 bge_add_sysctl_stats(sc, ctx, children); 6315} 6316 6317#define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 6318 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 6319 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 6320 desc) 6321 6322static void 6323bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6324 struct sysctl_oid_list *parent) 6325{ 6326 struct sysctl_oid *tree; 6327 struct sysctl_oid_list *children, *schildren; 6328 6329 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6330 NULL, "BGE Statistics"); 6331 schildren = children = SYSCTL_CHILDREN(tree); 6332 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6333 children, COSFramesDroppedDueToFilters, 6334 "FramesDroppedDueToFilters"); 6335 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6336 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6337 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6338 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6339 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6340 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 6341 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 6342 children, ifInDiscards, "InputDiscards"); 6343 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 6344 children, ifInErrors, "InputErrors"); 6345 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6346 children, nicRecvThresholdHit, "RecvThresholdHit"); 6347 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6348 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6349 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6350 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6351 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6352 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6353 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6354 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6355 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6356 children, nicRingStatusUpdate, "RingStatusUpdate"); 6357 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6358 children, nicInterrupts, "Interrupts"); 6359 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6360 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6361 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6362 children, nicSendThresholdHit, "SendThresholdHit"); 6363 6364 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 6365 NULL, "BGE RX Statistics"); 6366 children = SYSCTL_CHILDREN(tree); 6367 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 6368 children, rxstats.ifHCInOctets, "ifHCInOctets"); 6369 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6370 children, rxstats.etherStatsFragments, "Fragments"); 6371 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 6372 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6373 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6374 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6375 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6376 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6377 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6378 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6379 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6380 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6381 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6382 children, rxstats.xoffPauseFramesReceived, 6383 "xoffPauseFramesReceived"); 6384 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6385 children, rxstats.macControlFramesReceived, 6386 "ControlFramesReceived"); 6387 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6388 children, rxstats.xoffStateEntered, "xoffStateEntered"); 6389 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6390 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6391 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6392 children, rxstats.etherStatsJabbers, "Jabbers"); 6393 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6394 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6395 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 6396 children, rxstats.inRangeLengthError, "inRangeLengthError"); 6397 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 6398 children, rxstats.outRangeLengthError, "outRangeLengthError"); 6399 6400 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 6401 NULL, "BGE TX Statistics"); 6402 children = SYSCTL_CHILDREN(tree); 6403 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 6404 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6405 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6406 children, txstats.etherStatsCollisions, "Collisions"); 6407 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6408 children, txstats.outXonSent, "XonSent"); 6409 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6410 children, txstats.outXoffSent, "XoffSent"); 6411 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6412 children, txstats.flowControlDone, "flowControlDone"); 6413 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6414 children, txstats.dot3StatsInternalMacTransmitErrors, 6415 "InternalMacTransmitErrors"); 6416 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6417 children, txstats.dot3StatsSingleCollisionFrames, 6418 "SingleCollisionFrames"); 6419 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6420 children, txstats.dot3StatsMultipleCollisionFrames, 6421 "MultipleCollisionFrames"); 6422 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6423 children, txstats.dot3StatsDeferredTransmissions, 6424 "DeferredTransmissions"); 6425 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6426 children, txstats.dot3StatsExcessiveCollisions, 6427 "ExcessiveCollisions"); 6428 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 6429 children, txstats.dot3StatsLateCollisions, 6430 "LateCollisions"); 6431 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 6432 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6433 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6434 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6435 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6436 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6437 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6438 children, txstats.dot3StatsCarrierSenseErrors, 6439 "CarrierSenseErrors"); 6440 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6441 children, txstats.ifOutDiscards, "Discards"); 6442 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6443 children, txstats.ifOutErrors, "Errors"); 6444} 6445 6446#undef BGE_SYSCTL_STAT 6447 6448#define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 6449 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 6450 6451static void 6452bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6453 struct sysctl_oid_list *parent) 6454{ 6455 struct sysctl_oid *tree; 6456 struct sysctl_oid_list *child, *schild; 6457 struct bge_mac_stats *stats; 6458 6459 stats = &sc->bge_mac_stats; 6460 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6461 NULL, "BGE Statistics"); 6462 schild = child = SYSCTL_CHILDREN(tree); 6463 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 6464 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 6465 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 6466 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 6467 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 6468 &stats->DmaWriteHighPriQueueFull, 6469 "NIC DMA Write High Priority Queue Full"); 6470 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 6471 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 6472 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 6473 &stats->InputDiscards, "Discarded Input Frames"); 6474 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 6475 &stats->InputErrors, "Input Errors"); 6476 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 6477 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 6478 6479 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 6480 NULL, "BGE RX Statistics"); 6481 child = SYSCTL_CHILDREN(tree); 6482 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 6483 &stats->ifHCInOctets, "Inbound Octets"); 6484 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 6485 &stats->etherStatsFragments, "Fragments"); 6486 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6487 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 6488 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6489 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 6490 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6491 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 6492 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 6493 &stats->dot3StatsFCSErrors, "FCS Errors"); 6494 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 6495 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 6496 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 6497 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 6498 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 6499 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 6500 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 6501 &stats->macControlFramesReceived, "MAC Control Frames Received"); 6502 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 6503 &stats->xoffStateEntered, "XOFF State Entered"); 6504 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 6505 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 6506 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 6507 &stats->etherStatsJabbers, "Jabbers"); 6508 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 6509 &stats->etherStatsUndersizePkts, "Undersized Packets"); 6510 6511 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 6512 NULL, "BGE TX Statistics"); 6513 child = SYSCTL_CHILDREN(tree); 6514 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 6515 &stats->ifHCOutOctets, "Outbound Octets"); 6516 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 6517 &stats->etherStatsCollisions, "TX Collisions"); 6518 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 6519 &stats->outXonSent, "XON Sent"); 6520 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 6521 &stats->outXoffSent, "XOFF Sent"); 6522 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 6523 &stats->dot3StatsInternalMacTransmitErrors, 6524 "Internal MAC TX Errors"); 6525 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 6526 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 6527 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 6528 &stats->dot3StatsMultipleCollisionFrames, 6529 "Multiple Collision Frames"); 6530 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6531 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6532 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6533 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6534 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6535 &stats->dot3StatsLateCollisions, "Late Collisions"); 6536 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6537 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6538 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6539 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6540 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6541 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6542} 6543 6544#undef BGE_SYSCTL_STAT_ADD64 6545 6546static int 6547bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6548{ 6549 struct bge_softc *sc; 6550 uint32_t result; 6551 int offset; 6552 6553 sc = (struct bge_softc *)arg1; 6554 offset = arg2; 6555 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6556 offsetof(bge_hostaddr, bge_addr_lo)); 6557 return (sysctl_handle_int(oidp, &result, 0, req)); 6558} 6559 6560#ifdef BGE_REGISTER_DEBUG 6561static int 6562bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6563{ 6564 struct bge_softc *sc; 6565 uint16_t *sbdata; 6566 int error, result, sbsz; 6567 int i, j; 6568 6569 result = -1; 6570 error = sysctl_handle_int(oidp, &result, 0, req); 6571 if (error || (req->newptr == NULL)) 6572 return (error); 6573 6574 if (result == 1) { 6575 sc = (struct bge_softc *)arg1; 6576 6577 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6578 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6579 sbsz = BGE_STATUS_BLK_SZ; 6580 else 6581 sbsz = 32; 6582 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6583 printf("Status Block:\n"); 6584 BGE_LOCK(sc); 6585 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6586 sc->bge_cdata.bge_status_map, 6587 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6588 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6589 printf("%06x:", i); 6590 for (j = 0; j < 8; j++) 6591 printf(" %04x", sbdata[i++]); 6592 printf("\n"); 6593 } 6594 6595 printf("Registers:\n"); 6596 for (i = 0x800; i < 0xA00; ) { 6597 printf("%06x:", i); 6598 for (j = 0; j < 8; j++) { 6599 printf(" %08x", CSR_READ_4(sc, i)); 6600 i += 4; 6601 } 6602 printf("\n"); 6603 } 6604 BGE_UNLOCK(sc); 6605 6606 printf("Hardware Flags:\n"); 6607 if (BGE_IS_5717_PLUS(sc)) 6608 printf(" - 5717 Plus\n"); 6609 if (BGE_IS_5755_PLUS(sc)) 6610 printf(" - 5755 Plus\n"); 6611 if (BGE_IS_575X_PLUS(sc)) 6612 printf(" - 575X Plus\n"); 6613 if (BGE_IS_5705_PLUS(sc)) 6614 printf(" - 5705 Plus\n"); 6615 if (BGE_IS_5714_FAMILY(sc)) 6616 printf(" - 5714 Family\n"); 6617 if (BGE_IS_5700_FAMILY(sc)) 6618 printf(" - 5700 Family\n"); 6619 if (sc->bge_flags & BGE_FLAG_JUMBO) 6620 printf(" - Supports Jumbo Frames\n"); 6621 if (sc->bge_flags & BGE_FLAG_PCIX) 6622 printf(" - PCI-X Bus\n"); 6623 if (sc->bge_flags & BGE_FLAG_PCIE) 6624 printf(" - PCI Express Bus\n"); 6625 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6626 printf(" - No 3 LEDs\n"); 6627 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6628 printf(" - RX Alignment Bug\n"); 6629 } 6630 6631 return (error); 6632} 6633 6634static int 6635bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6636{ 6637 struct bge_softc *sc; 6638 int error; 6639 uint16_t result; 6640 uint32_t val; 6641 6642 result = -1; 6643 error = sysctl_handle_int(oidp, &result, 0, req); 6644 if (error || (req->newptr == NULL)) 6645 return (error); 6646 6647 if (result < 0x8000) { 6648 sc = (struct bge_softc *)arg1; 6649 val = CSR_READ_4(sc, result); 6650 printf("reg 0x%06X = 0x%08X\n", result, val); 6651 } 6652 6653 return (error); 6654} 6655 6656static int 6657bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6658{ 6659 struct bge_softc *sc; 6660 int error; 6661 uint16_t result; 6662 uint32_t val; 6663 6664 result = -1; 6665 error = sysctl_handle_int(oidp, &result, 0, req); 6666 if (error || (req->newptr == NULL)) 6667 return (error); 6668 6669 if (result < 0x8000) { 6670 sc = (struct bge_softc *)arg1; 6671 val = APE_READ_4(sc, result); 6672 printf("reg 0x%06X = 0x%08X\n", result, val); 6673 } 6674 6675 return (error); 6676} 6677 6678static int 6679bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6680{ 6681 struct bge_softc *sc; 6682 int error; 6683 uint16_t result; 6684 uint32_t val; 6685 6686 result = -1; 6687 error = sysctl_handle_int(oidp, &result, 0, req); 6688 if (error || (req->newptr == NULL)) 6689 return (error); 6690 6691 if (result < 0x8000) { 6692 sc = (struct bge_softc *)arg1; 6693 val = bge_readmem_ind(sc, result); 6694 printf("mem 0x%06X = 0x%08X\n", result, val); 6695 } 6696 6697 return (error); 6698} 6699#endif 6700 6701static int 6702bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6703{ 6704 6705 if (sc->bge_flags & BGE_FLAG_EADDR) 6706 return (1); 6707 6708#ifdef __sparc64__ 6709 OF_getetheraddr(sc->bge_dev, ether_addr); 6710 return (0); 6711#endif 6712 return (1); 6713} 6714 6715static int 6716bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6717{ 6718 uint32_t mac_addr; 6719 6720 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6721 if ((mac_addr >> 16) == 0x484b) { 6722 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6723 ether_addr[1] = (uint8_t)mac_addr; 6724 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6725 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6726 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6727 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6728 ether_addr[5] = (uint8_t)mac_addr; 6729 return (0); 6730 } 6731 return (1); 6732} 6733 6734static int 6735bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6736{ 6737 int mac_offset = BGE_EE_MAC_OFFSET; 6738 6739 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6740 mac_offset = BGE_EE_MAC_OFFSET_5906; 6741 6742 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6743 ETHER_ADDR_LEN)); 6744} 6745 6746static int 6747bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6748{ 6749 6750 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6751 return (1); 6752 6753 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6754 ETHER_ADDR_LEN)); 6755} 6756 6757static int 6758bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6759{ 6760 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6761 /* NOTE: Order is critical */ 6762 bge_get_eaddr_fw, 6763 bge_get_eaddr_mem, 6764 bge_get_eaddr_nvram, 6765 bge_get_eaddr_eeprom, 6766 NULL 6767 }; 6768 const bge_eaddr_fcn_t *func; 6769 6770 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6771 if ((*func)(sc, eaddr) == 0) 6772 break; 6773 } 6774 return (*func == NULL ? ENXIO : 0); 6775} 6776