if_bfe.c revision 158651
1/*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 158651 2006-05-16 14:37:58Z phk $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/sockio.h> 34#include <sys/mbuf.h> 35#include <sys/malloc.h> 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/socket.h> 39#include <sys/queue.h> 40 41#include <net/if.h> 42#include <net/if_arp.h> 43#include <net/ethernet.h> 44#include <net/if_dl.h> 45#include <net/if_media.h> 46 47#include <net/bpf.h> 48 49#include <net/if_types.h> 50#include <net/if_vlan_var.h> 51 52#include <netinet/in_systm.h> 53#include <netinet/in.h> 54#include <netinet/ip.h> 55 56#include <machine/bus.h> 57#include <machine/resource.h> 58#include <sys/bus.h> 59#include <sys/rman.h> 60 61#include <dev/mii/mii.h> 62#include <dev/mii/miivar.h> 63#include "miidevs.h" 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68#include <dev/bfe/if_bfereg.h> 69 70MODULE_DEPEND(bfe, pci, 1, 1, 1); 71MODULE_DEPEND(bfe, ether, 1, 1, 1); 72MODULE_DEPEND(bfe, miibus, 1, 1, 1); 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 78 79static struct bfe_type bfe_devs[] = { 80 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 81 "Broadcom BCM4401 Fast Ethernet" }, 82 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 83 "Broadcom BCM4401-B0 Fast Ethernet" }, 84 { 0, 0, NULL } 85}; 86 87static int bfe_probe (device_t); 88static int bfe_attach (device_t); 89static int bfe_detach (device_t); 90static void bfe_release_resources (struct bfe_softc *); 91static void bfe_intr (void *); 92static void bfe_start (struct ifnet *); 93static void bfe_start_locked (struct ifnet *); 94static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 95static void bfe_init (void *); 96static void bfe_init_locked (void *); 97static void bfe_stop (struct bfe_softc *); 98static void bfe_watchdog (struct ifnet *); 99static void bfe_shutdown (device_t); 100static void bfe_tick (void *); 101static void bfe_txeof (struct bfe_softc *); 102static void bfe_rxeof (struct bfe_softc *); 103static void bfe_set_rx_mode (struct bfe_softc *); 104static int bfe_list_rx_init (struct bfe_softc *); 105static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 106static void bfe_rx_ring_free (struct bfe_softc *); 107 108static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 109static int bfe_ifmedia_upd (struct ifnet *); 110static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111static int bfe_miibus_readreg (device_t, int, int); 112static int bfe_miibus_writereg (device_t, int, int, int); 113static void bfe_miibus_statchg (device_t); 114static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 115 u_long, const int); 116static void bfe_get_config (struct bfe_softc *sc); 117static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 118static void bfe_stats_update (struct bfe_softc *); 119static void bfe_clear_stats (struct bfe_softc *); 120static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 121static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 122static int bfe_resetphy (struct bfe_softc *); 123static int bfe_setupphy (struct bfe_softc *); 124static void bfe_chip_reset (struct bfe_softc *); 125static void bfe_chip_halt (struct bfe_softc *); 126static void bfe_core_reset (struct bfe_softc *); 127static void bfe_core_disable (struct bfe_softc *); 128static int bfe_dma_alloc (device_t); 129static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 130static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 131static void bfe_cam_write (struct bfe_softc *, u_char *, int); 132 133static device_method_t bfe_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, bfe_probe), 136 DEVMETHOD(device_attach, bfe_attach), 137 DEVMETHOD(device_detach, bfe_detach), 138 DEVMETHOD(device_shutdown, bfe_shutdown), 139 140 /* bus interface */ 141 DEVMETHOD(bus_print_child, bus_generic_print_child), 142 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143 144 /* MII interface */ 145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 148 149 { 0, 0 } 150}; 151 152static driver_t bfe_driver = { 153 "bfe", 154 bfe_methods, 155 sizeof(struct bfe_softc) 156}; 157 158static devclass_t bfe_devclass; 159 160DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 161DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 162 163/* 164 * Probe for a Broadcom 4401 chip. 165 */ 166static int 167bfe_probe(device_t dev) 168{ 169 struct bfe_type *t; 170 struct bfe_softc *sc; 171 172 t = bfe_devs; 173 174 sc = device_get_softc(dev); 175 bzero(sc, sizeof(struct bfe_softc)); 176 sc->bfe_unit = device_get_unit(dev); 177 sc->bfe_dev = dev; 178 179 while(t->bfe_name != NULL) { 180 if ((pci_get_vendor(dev) == t->bfe_vid) && 181 (pci_get_device(dev) == t->bfe_did)) { 182 device_set_desc_copy(dev, t->bfe_name); 183 return (BUS_PROBE_DEFAULT); 184 } 185 t++; 186 } 187 188 return (ENXIO); 189} 190 191static int 192bfe_dma_alloc(device_t dev) 193{ 194 struct bfe_softc *sc; 195 int error, i; 196 197 sc = device_get_softc(dev); 198 199 /* 200 * parent tag. Apparently the chip cannot handle any DMA address 201 * greater than 1GB. 202 */ 203 error = bus_dma_tag_create(NULL, /* parent */ 204 PAGE_SIZE, 0, /* alignment, boundary */ 205 0x3FFFFFFF, /* lowaddr */ 206 BUS_SPACE_MAXADDR, /* highaddr */ 207 NULL, NULL, /* filter, filterarg */ 208 MAXBSIZE, /* maxsize */ 209 BUS_SPACE_UNRESTRICTED, /* num of segments */ 210 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 211 0, /* flags */ 212 NULL, NULL, /* lockfunc, lockarg */ 213 &sc->bfe_parent_tag); 214 215 /* tag for TX ring */ 216 error = bus_dma_tag_create(sc->bfe_parent_tag, 217 1, 0, 218 BUS_SPACE_MAXADDR, 219 BUS_SPACE_MAXADDR, 220 NULL, NULL, 221 BFE_TX_LIST_SIZE, 222 1, 223 BUS_SPACE_MAXSIZE_32BIT, 224 0, 225 NULL, NULL, 226 &sc->bfe_tx_tag); 227 228 if (error) { 229 device_printf(dev, "could not allocate dma tag\n"); 230 return (ENOMEM); 231 } 232 233 /* tag for RX ring */ 234 error = bus_dma_tag_create(sc->bfe_parent_tag, 235 1, 0, 236 BUS_SPACE_MAXADDR, 237 BUS_SPACE_MAXADDR, 238 NULL, NULL, 239 BFE_RX_LIST_SIZE, 240 1, 241 BUS_SPACE_MAXSIZE_32BIT, 242 0, 243 NULL, NULL, 244 &sc->bfe_rx_tag); 245 246 if (error) { 247 device_printf(dev, "could not allocate dma tag\n"); 248 return (ENOMEM); 249 } 250 251 /* tag for mbufs */ 252 error = bus_dma_tag_create(sc->bfe_parent_tag, 253 ETHER_ALIGN, 0, 254 BUS_SPACE_MAXADDR, 255 BUS_SPACE_MAXADDR, 256 NULL, NULL, 257 MCLBYTES, 258 1, 259 BUS_SPACE_MAXSIZE_32BIT, 260 BUS_DMA_ALLOCNOW, 261 NULL, NULL, 262 &sc->bfe_tag); 263 264 if (error) { 265 device_printf(dev, "could not allocate dma tag\n"); 266 return (ENOMEM); 267 } 268 269 /* pre allocate dmamaps for RX list */ 270 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 271 error = bus_dmamap_create(sc->bfe_tag, 0, 272 &sc->bfe_rx_ring[i].bfe_map); 273 if (error) { 274 device_printf(dev, "cannot create DMA map for RX\n"); 275 return (ENOMEM); 276 } 277 } 278 279 /* pre allocate dmamaps for TX list */ 280 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 281 error = bus_dmamap_create(sc->bfe_tag, 0, 282 &sc->bfe_tx_ring[i].bfe_map); 283 if (error) { 284 device_printf(dev, "cannot create DMA map for TX\n"); 285 return (ENOMEM); 286 } 287 } 288 289 /* Alloc dma for rx ring */ 290 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 291 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 292 293 if(error) 294 return (ENOMEM); 295 296 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 297 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 298 sc->bfe_rx_list, sizeof(struct bfe_desc), 299 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_NOWAIT); 300 301 if(error) 302 return (ENOMEM); 303 304 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 305 306 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 307 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 308 if (error) 309 return (ENOMEM); 310 311 312 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 313 sc->bfe_tx_list, sizeof(struct bfe_desc), 314 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_NOWAIT); 315 if(error) 316 return (ENOMEM); 317 318 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 319 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 320 321 return (0); 322} 323 324static int 325bfe_attach(device_t dev) 326{ 327 struct ifnet *ifp = NULL; 328 struct bfe_softc *sc; 329 int unit, error = 0, rid; 330 331 sc = device_get_softc(dev); 332 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 333 MTX_DEF); 334 335 unit = device_get_unit(dev); 336 sc->bfe_dev = dev; 337 sc->bfe_unit = unit; 338 339 /* 340 * Map control/status registers. 341 */ 342 pci_enable_busmaster(dev); 343 344 rid = BFE_PCI_MEMLO; 345 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 346 RF_ACTIVE); 347 if (sc->bfe_res == NULL) { 348 printf ("bfe%d: couldn't map memory\n", unit); 349 error = ENXIO; 350 goto fail; 351 } 352 353 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 354 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 355 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 356 357 /* Allocate interrupt */ 358 rid = 0; 359 360 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 361 RF_SHAREABLE | RF_ACTIVE); 362 if (sc->bfe_irq == NULL) { 363 printf("bfe%d: couldn't map interrupt\n", unit); 364 error = ENXIO; 365 goto fail; 366 } 367 368 if (bfe_dma_alloc(dev)) { 369 printf("bfe%d: failed to allocate DMA resources\n", 370 sc->bfe_unit); 371 error = ENXIO; 372 goto fail; 373 } 374 375 /* Set up ifnet structure */ 376 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 377 if (ifp == NULL) { 378 printf("bfe%d: failed to if_alloc()\n", sc->bfe_unit); 379 error = ENOSPC; 380 goto fail; 381 } 382 ifp->if_softc = sc; 383 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 384 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 385 ifp->if_ioctl = bfe_ioctl; 386 ifp->if_start = bfe_start; 387 ifp->if_watchdog = bfe_watchdog; 388 ifp->if_init = bfe_init; 389 ifp->if_mtu = ETHERMTU; 390 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 391 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 392 IFQ_SET_READY(&ifp->if_snd); 393 394 bfe_get_config(sc); 395 396 /* Reset the chip and turn on the PHY */ 397 BFE_LOCK(sc); 398 bfe_chip_reset(sc); 399 BFE_UNLOCK(sc); 400 401 if (mii_phy_probe(dev, &sc->bfe_miibus, 402 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 403 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 404 error = ENXIO; 405 goto fail; 406 } 407 408 ether_ifattach(ifp, sc->bfe_enaddr); 409 callout_handle_init(&sc->bfe_stat_ch); 410 411 /* 412 * Tell the upper layer(s) we support long frames. 413 */ 414 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 415 ifp->if_capabilities |= IFCAP_VLAN_MTU; 416 ifp->if_capenable |= IFCAP_VLAN_MTU; 417 418 /* 419 * Hook interrupt last to avoid having to lock softc 420 */ 421 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 422 bfe_intr, sc, &sc->bfe_intrhand); 423 424 if (error) { 425 printf("bfe%d: couldn't set up irq\n", unit); 426 goto fail; 427 } 428fail: 429 if (error) 430 bfe_release_resources(sc); 431 return (error); 432} 433 434static int 435bfe_detach(device_t dev) 436{ 437 struct bfe_softc *sc; 438 struct ifnet *ifp; 439 440 sc = device_get_softc(dev); 441 442 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 443 BFE_LOCK(sc); 444 445 ifp = sc->bfe_ifp; 446 447 if (device_is_attached(dev)) { 448 bfe_stop(sc); 449 ether_ifdetach(ifp); 450 } 451 452 bfe_chip_reset(sc); 453 454 bus_generic_detach(dev); 455 if(sc->bfe_miibus != NULL) 456 device_delete_child(dev, sc->bfe_miibus); 457 458 bfe_release_resources(sc); 459 BFE_UNLOCK(sc); 460 mtx_destroy(&sc->bfe_mtx); 461 462 return (0); 463} 464 465/* 466 * Stop all chip I/O so that the kernel's probe routines don't 467 * get confused by errant DMAs when rebooting. 468 */ 469static void 470bfe_shutdown(device_t dev) 471{ 472 struct bfe_softc *sc; 473 474 sc = device_get_softc(dev); 475 BFE_LOCK(sc); 476 bfe_stop(sc); 477 478 BFE_UNLOCK(sc); 479 return; 480} 481 482static int 483bfe_miibus_readreg(device_t dev, int phy, int reg) 484{ 485 struct bfe_softc *sc; 486 u_int32_t ret; 487 488 sc = device_get_softc(dev); 489 if(phy != sc->bfe_phyaddr) 490 return (0); 491 bfe_readphy(sc, reg, &ret); 492 493 return (ret); 494} 495 496static int 497bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 498{ 499 struct bfe_softc *sc; 500 501 sc = device_get_softc(dev); 502 if(phy != sc->bfe_phyaddr) 503 return (0); 504 bfe_writephy(sc, reg, val); 505 506 return (0); 507} 508 509static void 510bfe_miibus_statchg(device_t dev) 511{ 512 return; 513} 514 515static void 516bfe_tx_ring_free(struct bfe_softc *sc) 517{ 518 int i; 519 520 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 521 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 522 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 523 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 524 bus_dmamap_unload(sc->bfe_tag, 525 sc->bfe_tx_ring[i].bfe_map); 526 } 527 } 528 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 529 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 530} 531 532static void 533bfe_rx_ring_free(struct bfe_softc *sc) 534{ 535 int i; 536 537 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 538 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 539 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 540 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 541 bus_dmamap_unload(sc->bfe_tag, 542 sc->bfe_rx_ring[i].bfe_map); 543 } 544 } 545 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 546 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 547} 548 549static int 550bfe_list_rx_init(struct bfe_softc *sc) 551{ 552 int i; 553 554 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 555 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 556 return (ENOBUFS); 557 } 558 559 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 560 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 561 562 sc->bfe_rx_cons = 0; 563 564 return (0); 565} 566 567static int 568bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 569{ 570 struct bfe_rxheader *rx_header; 571 struct bfe_desc *d; 572 struct bfe_data *r; 573 u_int32_t ctrl; 574 int error; 575 576 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 577 return (EINVAL); 578 579 if(m == NULL) { 580 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 581 if(m == NULL) 582 return (ENOBUFS); 583 m->m_len = m->m_pkthdr.len = MCLBYTES; 584 } 585 else 586 m->m_data = m->m_ext.ext_buf; 587 588 rx_header = mtod(m, struct bfe_rxheader *); 589 rx_header->len = 0; 590 rx_header->flags = 0; 591 592 /* Map the mbuf into DMA */ 593 sc->bfe_rx_cnt = c; 594 d = &sc->bfe_rx_list[c]; 595 r = &sc->bfe_rx_ring[c]; 596 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 597 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 598 if (error) 599 printf("Serious error: bfe failed to map RX buffer\n"); 600 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 601 602 ctrl = ETHER_MAX_LEN + 32; 603 604 if(c == BFE_RX_LIST_CNT - 1) 605 ctrl |= BFE_DESC_EOT; 606 607 d->bfe_ctrl = ctrl; 608 r->bfe_mbuf = m; 609 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 610 return (0); 611} 612 613static void 614bfe_get_config(struct bfe_softc *sc) 615{ 616 u_int8_t eeprom[128]; 617 618 bfe_read_eeprom(sc, eeprom); 619 620 sc->bfe_enaddr[0] = eeprom[79]; 621 sc->bfe_enaddr[1] = eeprom[78]; 622 sc->bfe_enaddr[2] = eeprom[81]; 623 sc->bfe_enaddr[3] = eeprom[80]; 624 sc->bfe_enaddr[4] = eeprom[83]; 625 sc->bfe_enaddr[5] = eeprom[82]; 626 627 sc->bfe_phyaddr = eeprom[90] & 0x1f; 628 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 629 630 sc->bfe_core_unit = 0; 631 sc->bfe_dma_offset = BFE_PCI_DMA; 632} 633 634static void 635bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 636{ 637 u_int32_t bar_orig, pci_rev, val; 638 639 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 640 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 641 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 642 643 val = CSR_READ_4(sc, BFE_SBINTVEC); 644 val |= cores; 645 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 646 647 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 648 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 649 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 650 651 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 652} 653 654static void 655bfe_clear_stats(struct bfe_softc *sc) 656{ 657 u_long reg; 658 659 BFE_LOCK_ASSERT(sc); 660 661 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 662 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 663 CSR_READ_4(sc, reg); 664 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 665 CSR_READ_4(sc, reg); 666} 667 668static int 669bfe_resetphy(struct bfe_softc *sc) 670{ 671 u_int32_t val; 672 673 bfe_writephy(sc, 0, BMCR_RESET); 674 DELAY(100); 675 bfe_readphy(sc, 0, &val); 676 if (val & BMCR_RESET) { 677 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 678 return (ENXIO); 679 } 680 return (0); 681} 682 683static void 684bfe_chip_halt(struct bfe_softc *sc) 685{ 686 BFE_LOCK_ASSERT(sc); 687 /* disable interrupts - not that it actually does..*/ 688 CSR_WRITE_4(sc, BFE_IMASK, 0); 689 CSR_READ_4(sc, BFE_IMASK); 690 691 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 692 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 693 694 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 695 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 696 DELAY(10); 697} 698 699static void 700bfe_chip_reset(struct bfe_softc *sc) 701{ 702 u_int32_t val; 703 704 BFE_LOCK_ASSERT(sc); 705 706 /* Set the interrupt vector for the enet core */ 707 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 708 709 /* is core up? */ 710 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 711 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 712 if (val == BFE_CLOCK) { 713 /* It is, so shut it down */ 714 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 715 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 716 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 717 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 718 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 719 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 720 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 721 100, 0); 722 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 723 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 724 } 725 726 bfe_core_reset(sc); 727 bfe_clear_stats(sc); 728 729 /* 730 * We want the phy registers to be accessible even when 731 * the driver is "downed" so initialize MDC preamble, frequency, 732 * and whether internal or external phy here. 733 */ 734 735 /* 4402 has 62.5Mhz SB clock and internal phy */ 736 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 737 738 /* Internal or external PHY? */ 739 val = CSR_READ_4(sc, BFE_DEVCTRL); 740 if(!(val & BFE_IPP)) 741 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 742 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 743 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 744 DELAY(100); 745 } 746 747 /* Enable CRC32 generation and set proper LED modes */ 748 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 749 750 /* Reset or clear powerdown control bit */ 751 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 752 753 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 754 BFE_LAZY_FC_MASK)); 755 756 /* 757 * We don't want lazy interrupts, so just send them at 758 * the end of a frame, please 759 */ 760 BFE_OR(sc, BFE_RCV_LAZY, 0); 761 762 /* Set max lengths, accounting for VLAN tags */ 763 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 764 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 765 766 /* Set watermark XXX - magic */ 767 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 768 769 /* 770 * Initialise DMA channels 771 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 772 */ 773 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 774 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 775 776 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 777 BFE_RX_CTRL_ENABLE); 778 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 779 780 bfe_resetphy(sc); 781 bfe_setupphy(sc); 782} 783 784static void 785bfe_core_disable(struct bfe_softc *sc) 786{ 787 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 788 return; 789 790 /* 791 * Set reject, wait for it set, then wait for the core to stop 792 * being busy, then set reset and reject and enable the clocks. 793 */ 794 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 795 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 796 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 797 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 798 BFE_RESET)); 799 CSR_READ_4(sc, BFE_SBTMSLOW); 800 DELAY(10); 801 /* Leave reset and reject set */ 802 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 803 DELAY(10); 804} 805 806static void 807bfe_core_reset(struct bfe_softc *sc) 808{ 809 u_int32_t val; 810 811 /* Disable the core */ 812 bfe_core_disable(sc); 813 814 /* and bring it back up */ 815 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 816 CSR_READ_4(sc, BFE_SBTMSLOW); 817 DELAY(10); 818 819 /* Chip bug, clear SERR, IB and TO if they are set. */ 820 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 821 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 822 val = CSR_READ_4(sc, BFE_SBIMSTATE); 823 if (val & (BFE_IBE | BFE_TO)) 824 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 825 826 /* Clear reset and allow it to move through the core */ 827 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 828 CSR_READ_4(sc, BFE_SBTMSLOW); 829 DELAY(10); 830 831 /* Leave the clock set */ 832 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 833 CSR_READ_4(sc, BFE_SBTMSLOW); 834 DELAY(10); 835} 836 837static void 838bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 839{ 840 u_int32_t val; 841 842 val = ((u_int32_t) data[2]) << 24; 843 val |= ((u_int32_t) data[3]) << 16; 844 val |= ((u_int32_t) data[4]) << 8; 845 val |= ((u_int32_t) data[5]); 846 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 847 val = (BFE_CAM_HI_VALID | 848 (((u_int32_t) data[0]) << 8) | 849 (((u_int32_t) data[1]))); 850 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 851 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 852 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 853 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 854} 855 856static void 857bfe_set_rx_mode(struct bfe_softc *sc) 858{ 859 struct ifnet *ifp = sc->bfe_ifp; 860 struct ifmultiaddr *ifma; 861 u_int32_t val; 862 int i = 0; 863 864 val = CSR_READ_4(sc, BFE_RXCONF); 865 866 if (ifp->if_flags & IFF_PROMISC) 867 val |= BFE_RXCONF_PROMISC; 868 else 869 val &= ~BFE_RXCONF_PROMISC; 870 871 if (ifp->if_flags & IFF_BROADCAST) 872 val &= ~BFE_RXCONF_DBCAST; 873 else 874 val |= BFE_RXCONF_DBCAST; 875 876 877 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 878 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 879 880 if (ifp->if_flags & IFF_ALLMULTI) 881 val |= BFE_RXCONF_ALLMULTI; 882 else { 883 val &= ~BFE_RXCONF_ALLMULTI; 884 IF_ADDR_LOCK(ifp); 885 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 886 if (ifma->ifma_addr->sa_family != AF_LINK) 887 continue; 888 bfe_cam_write(sc, 889 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 890 } 891 IF_ADDR_UNLOCK(ifp); 892 } 893 894 CSR_WRITE_4(sc, BFE_RXCONF, val); 895 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 896} 897 898static void 899bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 900{ 901 u_int32_t *ptr; 902 903 ptr = arg; 904 *ptr = segs->ds_addr; 905} 906 907static void 908bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 909{ 910 struct bfe_desc *d; 911 912 d = arg; 913 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 914 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 915} 916 917static void 918bfe_release_resources(struct bfe_softc *sc) 919{ 920 device_t dev; 921 int i; 922 923 dev = sc->bfe_dev; 924 925 if (sc->bfe_vpd_prodname != NULL) 926 free(sc->bfe_vpd_prodname, M_DEVBUF); 927 928 if (sc->bfe_vpd_readonly != NULL) 929 free(sc->bfe_vpd_readonly, M_DEVBUF); 930 931 if (sc->bfe_intrhand != NULL) 932 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 933 934 if (sc->bfe_irq != NULL) 935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 936 937 if (sc->bfe_res != NULL) 938 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 939 940 if (sc->bfe_ifp != NULL) 941 if_free(sc->bfe_ifp); 942 943 if(sc->bfe_tx_tag != NULL) { 944 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 945 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 946 sc->bfe_tx_map); 947 bus_dma_tag_destroy(sc->bfe_tx_tag); 948 sc->bfe_tx_tag = NULL; 949 } 950 951 if(sc->bfe_rx_tag != NULL) { 952 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 953 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 954 sc->bfe_rx_map); 955 bus_dma_tag_destroy(sc->bfe_rx_tag); 956 sc->bfe_rx_tag = NULL; 957 } 958 959 if(sc->bfe_tag != NULL) { 960 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 961 bus_dmamap_destroy(sc->bfe_tag, 962 sc->bfe_tx_ring[i].bfe_map); 963 } 964 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 965 bus_dmamap_destroy(sc->bfe_tag, 966 sc->bfe_rx_ring[i].bfe_map); 967 } 968 bus_dma_tag_destroy(sc->bfe_tag); 969 sc->bfe_tag = NULL; 970 } 971 972 if(sc->bfe_parent_tag != NULL) 973 bus_dma_tag_destroy(sc->bfe_parent_tag); 974 975 return; 976} 977 978static void 979bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 980{ 981 long i; 982 u_int16_t *ptr = (u_int16_t *)data; 983 984 for(i = 0; i < 128; i += 2) 985 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 986} 987 988static int 989bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 990 u_long timeout, const int clear) 991{ 992 u_long i; 993 994 for (i = 0; i < timeout; i++) { 995 u_int32_t val = CSR_READ_4(sc, reg); 996 997 if (clear && !(val & bit)) 998 break; 999 if (!clear && (val & bit)) 1000 break; 1001 DELAY(10); 1002 } 1003 if (i == timeout) { 1004 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1005 "%x to %s.\n", sc->bfe_unit, bit, reg, 1006 (clear ? "clear" : "set")); 1007 return (-1); 1008 } 1009 return (0); 1010} 1011 1012static int 1013bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1014{ 1015 int err; 1016 1017 /* Clear MII ISR */ 1018 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1019 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1020 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1021 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1022 (reg << BFE_MDIO_RA_SHIFT) | 1023 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1024 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1025 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1026 1027 return (err); 1028} 1029 1030static int 1031bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1032{ 1033 int status; 1034 1035 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1036 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1037 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1038 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1039 (reg << BFE_MDIO_RA_SHIFT) | 1040 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1041 (val & BFE_MDIO_DATA_DATA))); 1042 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1043 1044 return (status); 1045} 1046 1047/* 1048 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1049 * twice 1050 */ 1051static int 1052bfe_setupphy(struct bfe_softc *sc) 1053{ 1054 u_int32_t val; 1055 1056 /* Enable activity LED */ 1057 bfe_readphy(sc, 26, &val); 1058 bfe_writephy(sc, 26, val & 0x7fff); 1059 bfe_readphy(sc, 26, &val); 1060 1061 /* Enable traffic meter LED mode */ 1062 bfe_readphy(sc, 27, &val); 1063 bfe_writephy(sc, 27, val | (1 << 6)); 1064 1065 return (0); 1066} 1067 1068static void 1069bfe_stats_update(struct bfe_softc *sc) 1070{ 1071 u_long reg; 1072 u_int32_t *val; 1073 1074 val = &sc->bfe_hwstats.tx_good_octets; 1075 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1076 *val++ += CSR_READ_4(sc, reg); 1077 } 1078 val = &sc->bfe_hwstats.rx_good_octets; 1079 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1080 *val++ += CSR_READ_4(sc, reg); 1081 } 1082} 1083 1084static void 1085bfe_txeof(struct bfe_softc *sc) 1086{ 1087 struct ifnet *ifp; 1088 int i, chipidx; 1089 1090 BFE_LOCK_ASSERT(sc); 1091 1092 ifp = sc->bfe_ifp; 1093 1094 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1095 chipidx /= sizeof(struct bfe_desc); 1096 1097 i = sc->bfe_tx_cons; 1098 /* Go through the mbufs and free those that have been transmitted */ 1099 while(i != chipidx) { 1100 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1101 if(r->bfe_mbuf != NULL) { 1102 ifp->if_opackets++; 1103 m_freem(r->bfe_mbuf); 1104 r->bfe_mbuf = NULL; 1105 } 1106 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1107 sc->bfe_tx_cnt--; 1108 BFE_INC(i, BFE_TX_LIST_CNT); 1109 } 1110 1111 if(i != sc->bfe_tx_cons) { 1112 /* we freed up some mbufs */ 1113 sc->bfe_tx_cons = i; 1114 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1115 } 1116 if(sc->bfe_tx_cnt == 0) 1117 ifp->if_timer = 0; 1118 else 1119 ifp->if_timer = 5; 1120} 1121 1122/* Pass a received packet up the stack */ 1123static void 1124bfe_rxeof(struct bfe_softc *sc) 1125{ 1126 struct mbuf *m; 1127 struct ifnet *ifp; 1128 struct bfe_rxheader *rxheader; 1129 struct bfe_data *r; 1130 int cons; 1131 u_int32_t status, current, len, flags; 1132 1133 BFE_LOCK_ASSERT(sc); 1134 cons = sc->bfe_rx_cons; 1135 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1136 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1137 1138 ifp = sc->bfe_ifp; 1139 1140 while(current != cons) { 1141 r = &sc->bfe_rx_ring[cons]; 1142 m = r->bfe_mbuf; 1143 rxheader = mtod(m, struct bfe_rxheader*); 1144 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1145 len = rxheader->len; 1146 r->bfe_mbuf = NULL; 1147 1148 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1149 flags = rxheader->flags; 1150 1151 len -= ETHER_CRC_LEN; 1152 1153 /* flag an error and try again */ 1154 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1155 ifp->if_ierrors++; 1156 if (flags & BFE_RX_FLAG_SERR) 1157 ifp->if_collisions++; 1158 bfe_list_newbuf(sc, cons, m); 1159 BFE_INC(cons, BFE_RX_LIST_CNT); 1160 continue; 1161 } 1162 1163 /* Go past the rx header */ 1164 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1165 m_adj(m, BFE_RX_OFFSET); 1166 m->m_len = m->m_pkthdr.len = len; 1167 } else { 1168 bfe_list_newbuf(sc, cons, m); 1169 ifp->if_ierrors++; 1170 BFE_INC(cons, BFE_RX_LIST_CNT); 1171 continue; 1172 } 1173 1174 ifp->if_ipackets++; 1175 m->m_pkthdr.rcvif = ifp; 1176 BFE_UNLOCK(sc); 1177 (*ifp->if_input)(ifp, m); 1178 BFE_LOCK(sc); 1179 1180 BFE_INC(cons, BFE_RX_LIST_CNT); 1181 } 1182 sc->bfe_rx_cons = cons; 1183} 1184 1185static void 1186bfe_intr(void *xsc) 1187{ 1188 struct bfe_softc *sc = xsc; 1189 struct ifnet *ifp; 1190 u_int32_t istat, imask, flag; 1191 1192 ifp = sc->bfe_ifp; 1193 1194 BFE_LOCK(sc); 1195 1196 istat = CSR_READ_4(sc, BFE_ISTAT); 1197 imask = CSR_READ_4(sc, BFE_IMASK); 1198 1199 /* 1200 * Defer unsolicited interrupts - This is necessary because setting the 1201 * chips interrupt mask register to 0 doesn't actually stop the 1202 * interrupts 1203 */ 1204 istat &= imask; 1205 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1206 CSR_READ_4(sc, BFE_ISTAT); 1207 1208 /* not expecting this interrupt, disregard it */ 1209 if(istat == 0) { 1210 BFE_UNLOCK(sc); 1211 return; 1212 } 1213 1214 if(istat & BFE_ISTAT_ERRORS) { 1215 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1216 if(flag & BFE_STAT_EMASK) 1217 ifp->if_oerrors++; 1218 1219 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1220 if(flag & BFE_RX_FLAG_ERRORS) 1221 ifp->if_ierrors++; 1222 1223 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1224 bfe_init_locked(sc); 1225 } 1226 1227 /* A packet was received */ 1228 if(istat & BFE_ISTAT_RX) 1229 bfe_rxeof(sc); 1230 1231 /* A packet was sent */ 1232 if(istat & BFE_ISTAT_TX) 1233 bfe_txeof(sc); 1234 1235 /* We have packets pending, fire them out */ 1236 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1237 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1238 bfe_start_locked(ifp); 1239 1240 BFE_UNLOCK(sc); 1241} 1242 1243static int 1244bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, u_int32_t *txidx) 1245{ 1246 struct bfe_desc *d = NULL; 1247 struct bfe_data *r = NULL; 1248 struct mbuf *m; 1249 u_int32_t frag, cur, cnt = 0; 1250 int chainlen = 0; 1251 int error; 1252 1253 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1254 return (ENOBUFS); 1255 1256 /* 1257 * Count the number of frags in this chain to see if 1258 * we need to m_defrag. Since the descriptor list is shared 1259 * by all packets, we'll m_defrag long chains so that they 1260 * do not use up the entire list, even if they would fit. 1261 */ 1262 for(m = *m_head; m != NULL; m = m->m_next) 1263 chainlen++; 1264 1265 1266 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1267 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1268 m = m_defrag(*m_head, M_DONTWAIT); 1269 if (m == NULL) 1270 return (ENOBUFS); 1271 *m_head = m; 1272 } 1273 1274 /* 1275 * Start packing the mbufs in this chain into 1276 * the fragment pointers. Stop when we run out 1277 * of fragments or hit the end of the mbuf chain. 1278 */ 1279 cur = frag = *txidx; 1280 cnt = 0; 1281 1282 for(m = *m_head; m != NULL; m = m->m_next) { 1283 if(m->m_len != 0) { 1284 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1285 return (ENOBUFS); 1286 1287 d = &sc->bfe_tx_list[cur]; 1288 r = &sc->bfe_tx_ring[cur]; 1289 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1290 /* always intterupt on completion */ 1291 d->bfe_ctrl |= BFE_DESC_IOC; 1292 if(cnt == 0) 1293 /* Set start of frame */ 1294 d->bfe_ctrl |= BFE_DESC_SOF; 1295 if(cur == BFE_TX_LIST_CNT - 1) 1296 /* 1297 * Tell the chip to wrap to the start of 1298 * the descriptor list 1299 */ 1300 d->bfe_ctrl |= BFE_DESC_EOT; 1301 1302 error = bus_dmamap_load(sc->bfe_tag, 1303 r->bfe_map, mtod(m, void*), m->m_len, 1304 bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 1305 if (error) 1306 return (ENOBUFS); 1307 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1308 BUS_DMASYNC_PREWRITE); 1309 1310 frag = cur; 1311 BFE_INC(cur, BFE_TX_LIST_CNT); 1312 cnt++; 1313 } 1314 } 1315 1316 if (m != NULL) 1317 return (ENOBUFS); 1318 1319 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1320 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1321 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1322 1323 *txidx = cur; 1324 sc->bfe_tx_cnt += cnt; 1325 return (0); 1326} 1327 1328/* 1329 * Set up to transmit a packet. 1330 */ 1331static void 1332bfe_start(struct ifnet *ifp) 1333{ 1334 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1335 bfe_start_locked(ifp); 1336 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1337} 1338 1339/* 1340 * Set up to transmit a packet. The softc is already locked. 1341 */ 1342static void 1343bfe_start_locked(struct ifnet *ifp) 1344{ 1345 struct bfe_softc *sc; 1346 struct mbuf *m_head = NULL; 1347 int idx, queued = 0; 1348 1349 sc = ifp->if_softc; 1350 idx = sc->bfe_tx_prod; 1351 1352 BFE_LOCK_ASSERT(sc); 1353 1354 /* 1355 * Not much point trying to send if the link is down 1356 * or we have nothing to send. 1357 */ 1358 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1359 return; 1360 1361 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1362 return; 1363 1364 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1365 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1366 if(m_head == NULL) 1367 break; 1368 1369 /* 1370 * Pack the data into the tx ring. If we dont have 1371 * enough room, let the chip drain the ring. 1372 */ 1373 if(bfe_encap(sc, &m_head, &idx)) { 1374 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1375 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1376 break; 1377 } 1378 1379 queued++; 1380 1381 /* 1382 * If there's a BPF listener, bounce a copy of this frame 1383 * to him. 1384 */ 1385 BPF_MTAP(ifp, m_head); 1386 } 1387 1388 if (queued) { 1389 sc->bfe_tx_prod = idx; 1390 /* Transmit - twice due to apparent hardware bug */ 1391 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1392 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1393 1394 /* 1395 * Set a timeout in case the chip goes out to lunch. 1396 */ 1397 ifp->if_timer = 5; 1398 } 1399} 1400 1401static void 1402bfe_init(void *xsc) 1403{ 1404 BFE_LOCK((struct bfe_softc *)xsc); 1405 bfe_init_locked(xsc); 1406 BFE_UNLOCK((struct bfe_softc *)xsc); 1407} 1408 1409static void 1410bfe_init_locked(void *xsc) 1411{ 1412 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1413 struct ifnet *ifp = sc->bfe_ifp; 1414 1415 BFE_LOCK_ASSERT(sc); 1416 1417 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1418 return; 1419 1420 bfe_stop(sc); 1421 bfe_chip_reset(sc); 1422 1423 if (bfe_list_rx_init(sc) == ENOBUFS) { 1424 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1425 sc->bfe_unit); 1426 bfe_stop(sc); 1427 return; 1428 } 1429 1430 bfe_set_rx_mode(sc); 1431 1432 /* Enable the chip and core */ 1433 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1434 /* Enable interrupts */ 1435 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1436 1437 bfe_ifmedia_upd(ifp); 1438 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1439 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1440 1441 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1442} 1443 1444/* 1445 * Set media options. 1446 */ 1447static int 1448bfe_ifmedia_upd(struct ifnet *ifp) 1449{ 1450 struct bfe_softc *sc; 1451 struct mii_data *mii; 1452 1453 sc = ifp->if_softc; 1454 1455 mii = device_get_softc(sc->bfe_miibus); 1456 sc->bfe_link = 0; 1457 if (mii->mii_instance) { 1458 struct mii_softc *miisc; 1459 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1460 miisc = LIST_NEXT(miisc, mii_list)) 1461 mii_phy_reset(miisc); 1462 } 1463 mii_mediachg(mii); 1464 1465 return (0); 1466} 1467 1468/* 1469 * Report current media status. 1470 */ 1471static void 1472bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1473{ 1474 struct bfe_softc *sc = ifp->if_softc; 1475 struct mii_data *mii; 1476 1477 mii = device_get_softc(sc->bfe_miibus); 1478 mii_pollstat(mii); 1479 ifmr->ifm_active = mii->mii_media_active; 1480 ifmr->ifm_status = mii->mii_media_status; 1481} 1482 1483static int 1484bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1485{ 1486 struct bfe_softc *sc = ifp->if_softc; 1487 struct ifreq *ifr = (struct ifreq *) data; 1488 struct mii_data *mii; 1489 int error = 0; 1490 1491 switch(command) { 1492 case SIOCSIFFLAGS: 1493 BFE_LOCK(sc); 1494 if(ifp->if_flags & IFF_UP) 1495 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1496 bfe_set_rx_mode(sc); 1497 else 1498 bfe_init_locked(sc); 1499 else if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1500 bfe_stop(sc); 1501 BFE_UNLOCK(sc); 1502 break; 1503 case SIOCADDMULTI: 1504 case SIOCDELMULTI: 1505 BFE_LOCK(sc); 1506 if(ifp->if_drv_flags & IFF_DRV_RUNNING) 1507 bfe_set_rx_mode(sc); 1508 BFE_UNLOCK(sc); 1509 break; 1510 case SIOCGIFMEDIA: 1511 case SIOCSIFMEDIA: 1512 mii = device_get_softc(sc->bfe_miibus); 1513 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1514 command); 1515 break; 1516 default: 1517 error = ether_ioctl(ifp, command, data); 1518 break; 1519 } 1520 1521 return (error); 1522} 1523 1524static void 1525bfe_watchdog(struct ifnet *ifp) 1526{ 1527 struct bfe_softc *sc; 1528 1529 sc = ifp->if_softc; 1530 1531 BFE_LOCK(sc); 1532 1533 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1534 1535 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1536 bfe_init_locked(sc); 1537 1538 ifp->if_oerrors++; 1539 1540 BFE_UNLOCK(sc); 1541} 1542 1543static void 1544bfe_tick(void *xsc) 1545{ 1546 struct bfe_softc *sc = xsc; 1547 struct mii_data *mii; 1548 1549 if (sc == NULL) 1550 return; 1551 1552 BFE_LOCK(sc); 1553 1554 mii = device_get_softc(sc->bfe_miibus); 1555 1556 bfe_stats_update(sc); 1557 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1558 1559 if(sc->bfe_link) { 1560 BFE_UNLOCK(sc); 1561 return; 1562 } 1563 1564 mii_tick(mii); 1565 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1566 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1567 sc->bfe_link++; 1568 1569 BFE_UNLOCK(sc); 1570} 1571 1572/* 1573 * Stop the adapter and free any mbufs allocated to the 1574 * RX and TX lists. 1575 */ 1576static void 1577bfe_stop(struct bfe_softc *sc) 1578{ 1579 struct ifnet *ifp; 1580 1581 BFE_LOCK_ASSERT(sc); 1582 1583 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1584 1585 ifp = sc->bfe_ifp; 1586 1587 bfe_chip_halt(sc); 1588 bfe_tx_ring_free(sc); 1589 bfe_rx_ring_free(sc); 1590 1591 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1592} 1593