if_bfe.c revision 139944
1/*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 139944 2005-01-09 19:57:55Z sam $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/sockio.h> 34#include <sys/mbuf.h> 35#include <sys/malloc.h> 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/socket.h> 39#include <sys/queue.h> 40 41#include <net/if.h> 42#include <net/if_arp.h> 43#include <net/ethernet.h> 44#include <net/if_dl.h> 45#include <net/if_media.h> 46 47#include <net/bpf.h> 48 49#include <net/if_types.h> 50#include <net/if_vlan_var.h> 51 52#include <netinet/in_systm.h> 53#include <netinet/in.h> 54#include <netinet/ip.h> 55 56#include <machine/clock.h> /* for DELAY */ 57#include <machine/bus_memio.h> 58#include <machine/bus.h> 59#include <machine/resource.h> 60#include <sys/bus.h> 61#include <sys/rman.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65#include "miidevs.h" 66 67#include <dev/pci/pcireg.h> 68#include <dev/pci/pcivar.h> 69 70#include <dev/bfe/if_bfereg.h> 71 72MODULE_DEPEND(bfe, pci, 1, 1, 1); 73MODULE_DEPEND(bfe, ether, 1, 1, 1); 74MODULE_DEPEND(bfe, miibus, 1, 1, 1); 75 76/* "controller miibus0" required. See GENERIC if you get errors here. */ 77#include "miibus_if.h" 78 79#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 80 81static struct bfe_type bfe_devs[] = { 82 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 83 "Broadcom BCM4401 Fast Ethernet" }, 84 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 85 "Broadcom BCM4401-B0 Fast Ethernet" }, 86 { 0, 0, NULL } 87}; 88 89static int bfe_probe (device_t); 90static int bfe_attach (device_t); 91static int bfe_detach (device_t); 92static void bfe_release_resources (struct bfe_softc *); 93static void bfe_intr (void *); 94static void bfe_start (struct ifnet *); 95static void bfe_start_locked (struct ifnet *); 96static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 97static void bfe_init (void *); 98static void bfe_init_locked (void *); 99static void bfe_stop (struct bfe_softc *); 100static void bfe_watchdog (struct ifnet *); 101static void bfe_shutdown (device_t); 102static void bfe_tick (void *); 103static void bfe_txeof (struct bfe_softc *); 104static void bfe_rxeof (struct bfe_softc *); 105static void bfe_set_rx_mode (struct bfe_softc *); 106static int bfe_list_rx_init (struct bfe_softc *); 107static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 108static void bfe_rx_ring_free (struct bfe_softc *); 109 110static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 111static int bfe_ifmedia_upd (struct ifnet *); 112static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 113static int bfe_miibus_readreg (device_t, int, int); 114static int bfe_miibus_writereg (device_t, int, int, int); 115static void bfe_miibus_statchg (device_t); 116static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 117 u_long, const int); 118static void bfe_get_config (struct bfe_softc *sc); 119static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 120static void bfe_stats_update (struct bfe_softc *); 121static void bfe_clear_stats (struct bfe_softc *); 122static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 123static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 124static int bfe_resetphy (struct bfe_softc *); 125static int bfe_setupphy (struct bfe_softc *); 126static void bfe_chip_reset (struct bfe_softc *); 127static void bfe_chip_halt (struct bfe_softc *); 128static void bfe_core_reset (struct bfe_softc *); 129static void bfe_core_disable (struct bfe_softc *); 130static int bfe_dma_alloc (device_t); 131static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 132static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 133static void bfe_cam_write (struct bfe_softc *, u_char *, int); 134 135static device_method_t bfe_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, bfe_probe), 138 DEVMETHOD(device_attach, bfe_attach), 139 DEVMETHOD(device_detach, bfe_detach), 140 DEVMETHOD(device_shutdown, bfe_shutdown), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 148 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 149 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 150 151 { 0, 0 } 152}; 153 154static driver_t bfe_driver = { 155 "bfe", 156 bfe_methods, 157 sizeof(struct bfe_softc) 158}; 159 160static devclass_t bfe_devclass; 161 162DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 163DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 164 165/* 166 * Probe for a Broadcom 4401 chip. 167 */ 168static int 169bfe_probe(device_t dev) 170{ 171 struct bfe_type *t; 172 struct bfe_softc *sc; 173 174 t = bfe_devs; 175 176 sc = device_get_softc(dev); 177 bzero(sc, sizeof(struct bfe_softc)); 178 sc->bfe_unit = device_get_unit(dev); 179 sc->bfe_dev = dev; 180 181 while(t->bfe_name != NULL) { 182 if ((pci_get_vendor(dev) == t->bfe_vid) && 183 (pci_get_device(dev) == t->bfe_did)) { 184 device_set_desc_copy(dev, t->bfe_name); 185 return (0); 186 } 187 t++; 188 } 189 190 return (ENXIO); 191} 192 193static int 194bfe_dma_alloc(device_t dev) 195{ 196 struct bfe_softc *sc; 197 int error, i; 198 199 sc = device_get_softc(dev); 200 201 /* parent tag */ 202 error = bus_dma_tag_create(NULL, /* parent */ 203 PAGE_SIZE, 0, /* alignment, boundary */ 204 BUS_SPACE_MAXADDR, /* lowaddr */ 205 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 206 NULL, NULL, /* filter, filterarg */ 207 MAXBSIZE, /* maxsize */ 208 BUS_SPACE_UNRESTRICTED, /* num of segments */ 209 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 210 BUS_DMA_ALLOCNOW, /* flags */ 211 NULL, NULL, /* lockfunc, lockarg */ 212 &sc->bfe_parent_tag); 213 214 /* tag for TX ring */ 215 error = bus_dma_tag_create(sc->bfe_parent_tag, 216 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 217 BUS_SPACE_MAXADDR, 218 BUS_SPACE_MAXADDR, 219 NULL, NULL, 220 BFE_TX_LIST_SIZE, 221 1, 222 BUS_SPACE_MAXSIZE_32BIT, 223 0, 224 NULL, NULL, 225 &sc->bfe_tx_tag); 226 227 if (error) { 228 device_printf(dev, "could not allocate dma tag\n"); 229 return (ENOMEM); 230 } 231 232 /* tag for RX ring */ 233 error = bus_dma_tag_create(sc->bfe_parent_tag, 234 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 235 BUS_SPACE_MAXADDR, 236 BUS_SPACE_MAXADDR, 237 NULL, NULL, 238 BFE_RX_LIST_SIZE, 239 1, 240 BUS_SPACE_MAXSIZE_32BIT, 241 0, 242 NULL, NULL, 243 &sc->bfe_rx_tag); 244 245 if (error) { 246 device_printf(dev, "could not allocate dma tag\n"); 247 return (ENOMEM); 248 } 249 250 /* tag for mbufs */ 251 error = bus_dma_tag_create(sc->bfe_parent_tag, 252 ETHER_ALIGN, 0, 253 BUS_SPACE_MAXADDR, 254 BUS_SPACE_MAXADDR, 255 NULL, NULL, 256 MCLBYTES, 257 1, 258 BUS_SPACE_MAXSIZE_32BIT, 259 0, 260 NULL, NULL, 261 &sc->bfe_tag); 262 263 if (error) { 264 device_printf(dev, "could not allocate dma tag\n"); 265 return (ENOMEM); 266 } 267 268 /* pre allocate dmamaps for RX list */ 269 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 270 error = bus_dmamap_create(sc->bfe_tag, 0, 271 &sc->bfe_rx_ring[i].bfe_map); 272 if (error) { 273 device_printf(dev, "cannot create DMA map for RX\n"); 274 return (ENOMEM); 275 } 276 } 277 278 /* pre allocate dmamaps for TX list */ 279 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 280 error = bus_dmamap_create(sc->bfe_tag, 0, 281 &sc->bfe_tx_ring[i].bfe_map); 282 if (error) { 283 device_printf(dev, "cannot create DMA map for TX\n"); 284 return (ENOMEM); 285 } 286 } 287 288 /* Alloc dma for rx ring */ 289 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 290 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 291 292 if(error) 293 return (ENOMEM); 294 295 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 296 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 297 sc->bfe_rx_list, sizeof(struct bfe_desc), 298 bfe_dma_map, &sc->bfe_rx_dma, 0); 299 300 if(error) 301 return (ENOMEM); 302 303 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 304 305 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 306 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 307 if (error) 308 return (ENOMEM); 309 310 311 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 312 sc->bfe_tx_list, sizeof(struct bfe_desc), 313 bfe_dma_map, &sc->bfe_tx_dma, 0); 314 if(error) 315 return (ENOMEM); 316 317 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 318 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 319 320 return (0); 321} 322 323static int 324bfe_attach(device_t dev) 325{ 326 struct ifnet *ifp; 327 struct bfe_softc *sc; 328 int unit, error = 0, rid; 329 330 sc = device_get_softc(dev); 331 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 332 MTX_DEF); 333 334 unit = device_get_unit(dev); 335 sc->bfe_dev = dev; 336 sc->bfe_unit = unit; 337 338 /* 339 * Handle power management nonsense. 340 */ 341 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 342 u_int32_t membase, irq; 343 344 /* Save important PCI config data. */ 345 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 346 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 347 348 /* Reset the power state. */ 349 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 350 sc->bfe_unit, pci_get_powerstate(dev)); 351 352 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 353 354 /* Restore PCI config data. */ 355 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 356 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 357 } 358 359 /* 360 * Map control/status registers. 361 */ 362 pci_enable_busmaster(dev); 363 364 rid = BFE_PCI_MEMLO; 365 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 366 RF_ACTIVE); 367 if (sc->bfe_res == NULL) { 368 printf ("bfe%d: couldn't map memory\n", unit); 369 error = ENXIO; 370 goto fail; 371 } 372 373 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 374 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 375 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 376 377 /* Allocate interrupt */ 378 rid = 0; 379 380 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 381 RF_SHAREABLE | RF_ACTIVE); 382 if (sc->bfe_irq == NULL) { 383 printf("bfe%d: couldn't map interrupt\n", unit); 384 error = ENXIO; 385 goto fail; 386 } 387 388 if (bfe_dma_alloc(dev)) { 389 printf("bfe%d: failed to allocate DMA resources\n", 390 sc->bfe_unit); 391 bfe_release_resources(sc); 392 error = ENXIO; 393 goto fail; 394 } 395 396 /* Set up ifnet structure */ 397 ifp = &sc->arpcom.ac_if; 398 ifp->if_softc = sc; 399 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 400 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 401 ifp->if_ioctl = bfe_ioctl; 402 ifp->if_start = bfe_start; 403 ifp->if_watchdog = bfe_watchdog; 404 ifp->if_init = bfe_init; 405 ifp->if_mtu = ETHERMTU; 406 ifp->if_baudrate = 100000000; 407 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 408 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 409 IFQ_SET_READY(&ifp->if_snd); 410 411 bfe_get_config(sc); 412 413 /* Reset the chip and turn on the PHY */ 414 BFE_LOCK(sc); 415 bfe_chip_reset(sc); 416 BFE_UNLOCK(sc); 417 418 if (mii_phy_probe(dev, &sc->bfe_miibus, 419 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 420 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 421 error = ENXIO; 422 goto fail; 423 } 424 425 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 426 callout_handle_init(&sc->bfe_stat_ch); 427 428 /* 429 * Tell the upper layer(s) we support long frames. 430 */ 431 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 432 ifp->if_capabilities |= IFCAP_VLAN_MTU; 433 ifp->if_capenable |= IFCAP_VLAN_MTU; 434 435 /* 436 * Hook interrupt last to avoid having to lock softc 437 */ 438 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 439 bfe_intr, sc, &sc->bfe_intrhand); 440 441 if (error) { 442 bfe_release_resources(sc); 443 printf("bfe%d: couldn't set up irq\n", unit); 444 goto fail; 445 } 446fail: 447 if(error) 448 bfe_release_resources(sc); 449 return (error); 450} 451 452static int 453bfe_detach(device_t dev) 454{ 455 struct bfe_softc *sc; 456 struct ifnet *ifp; 457 458 sc = device_get_softc(dev); 459 460 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 461 BFE_LOCK(sc); 462 463 ifp = &sc->arpcom.ac_if; 464 465 if (device_is_attached(dev)) { 466 bfe_stop(sc); 467 ether_ifdetach(ifp); 468 } 469 470 bfe_chip_reset(sc); 471 472 bus_generic_detach(dev); 473 if(sc->bfe_miibus != NULL) 474 device_delete_child(dev, sc->bfe_miibus); 475 476 bfe_release_resources(sc); 477 BFE_UNLOCK(sc); 478 mtx_destroy(&sc->bfe_mtx); 479 480 return (0); 481} 482 483/* 484 * Stop all chip I/O so that the kernel's probe routines don't 485 * get confused by errant DMAs when rebooting. 486 */ 487static void 488bfe_shutdown(device_t dev) 489{ 490 struct bfe_softc *sc; 491 492 sc = device_get_softc(dev); 493 BFE_LOCK(sc); 494 bfe_stop(sc); 495 496 BFE_UNLOCK(sc); 497 return; 498} 499 500static int 501bfe_miibus_readreg(device_t dev, int phy, int reg) 502{ 503 struct bfe_softc *sc; 504 u_int32_t ret; 505 506 sc = device_get_softc(dev); 507 if(phy != sc->bfe_phyaddr) 508 return (0); 509 bfe_readphy(sc, reg, &ret); 510 511 return (ret); 512} 513 514static int 515bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 516{ 517 struct bfe_softc *sc; 518 519 sc = device_get_softc(dev); 520 if(phy != sc->bfe_phyaddr) 521 return (0); 522 bfe_writephy(sc, reg, val); 523 524 return (0); 525} 526 527static void 528bfe_miibus_statchg(device_t dev) 529{ 530 return; 531} 532 533static void 534bfe_tx_ring_free(struct bfe_softc *sc) 535{ 536 int i; 537 538 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 539 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 540 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 541 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 542 bus_dmamap_unload(sc->bfe_tag, 543 sc->bfe_tx_ring[i].bfe_map); 544 bus_dmamap_destroy(sc->bfe_tag, 545 sc->bfe_tx_ring[i].bfe_map); 546 } 547 } 548 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 549 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 550} 551 552static void 553bfe_rx_ring_free(struct bfe_softc *sc) 554{ 555 int i; 556 557 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 558 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 559 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 560 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 561 bus_dmamap_unload(sc->bfe_tag, 562 sc->bfe_rx_ring[i].bfe_map); 563 bus_dmamap_destroy(sc->bfe_tag, 564 sc->bfe_rx_ring[i].bfe_map); 565 } 566 } 567 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 568 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 569} 570 571 572static int 573bfe_list_rx_init(struct bfe_softc *sc) 574{ 575 int i; 576 577 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 578 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 579 return (ENOBUFS); 580 } 581 582 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 583 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 584 585 sc->bfe_rx_cons = 0; 586 587 return (0); 588} 589 590static int 591bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 592{ 593 struct bfe_rxheader *rx_header; 594 struct bfe_desc *d; 595 struct bfe_data *r; 596 u_int32_t ctrl; 597 598 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 599 return (EINVAL); 600 601 if(m == NULL) { 602 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 603 if(m == NULL) 604 return (ENOBUFS); 605 m->m_len = m->m_pkthdr.len = MCLBYTES; 606 } 607 else 608 m->m_data = m->m_ext.ext_buf; 609 610 rx_header = mtod(m, struct bfe_rxheader *); 611 rx_header->len = 0; 612 rx_header->flags = 0; 613 614 /* Map the mbuf into DMA */ 615 sc->bfe_rx_cnt = c; 616 d = &sc->bfe_rx_list[c]; 617 r = &sc->bfe_rx_ring[c]; 618 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 619 MCLBYTES, bfe_dma_map_desc, d, 0); 620 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 621 622 ctrl = ETHER_MAX_LEN + 32; 623 624 if(c == BFE_RX_LIST_CNT - 1) 625 ctrl |= BFE_DESC_EOT; 626 627 d->bfe_ctrl = ctrl; 628 r->bfe_mbuf = m; 629 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 630 return (0); 631} 632 633static void 634bfe_get_config(struct bfe_softc *sc) 635{ 636 u_int8_t eeprom[128]; 637 638 bfe_read_eeprom(sc, eeprom); 639 640 sc->arpcom.ac_enaddr[0] = eeprom[79]; 641 sc->arpcom.ac_enaddr[1] = eeprom[78]; 642 sc->arpcom.ac_enaddr[2] = eeprom[81]; 643 sc->arpcom.ac_enaddr[3] = eeprom[80]; 644 sc->arpcom.ac_enaddr[4] = eeprom[83]; 645 sc->arpcom.ac_enaddr[5] = eeprom[82]; 646 647 sc->bfe_phyaddr = eeprom[90] & 0x1f; 648 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 649 650 sc->bfe_core_unit = 0; 651 sc->bfe_dma_offset = BFE_PCI_DMA; 652} 653 654static void 655bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 656{ 657 u_int32_t bar_orig, pci_rev, val; 658 659 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 660 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 661 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 662 663 val = CSR_READ_4(sc, BFE_SBINTVEC); 664 val |= cores; 665 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 666 667 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 668 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 669 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 670 671 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 672} 673 674static void 675bfe_clear_stats(struct bfe_softc *sc) 676{ 677 u_long reg; 678 679 BFE_LOCK_ASSERT(sc); 680 681 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 682 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 683 CSR_READ_4(sc, reg); 684 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 685 CSR_READ_4(sc, reg); 686} 687 688static int 689bfe_resetphy(struct bfe_softc *sc) 690{ 691 u_int32_t val; 692 693 bfe_writephy(sc, 0, BMCR_RESET); 694 DELAY(100); 695 bfe_readphy(sc, 0, &val); 696 if (val & BMCR_RESET) { 697 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 698 return (ENXIO); 699 } 700 return (0); 701} 702 703static void 704bfe_chip_halt(struct bfe_softc *sc) 705{ 706 BFE_LOCK_ASSERT(sc); 707 /* disable interrupts - not that it actually does..*/ 708 CSR_WRITE_4(sc, BFE_IMASK, 0); 709 CSR_READ_4(sc, BFE_IMASK); 710 711 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 712 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 713 714 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 715 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 716 DELAY(10); 717} 718 719static void 720bfe_chip_reset(struct bfe_softc *sc) 721{ 722 u_int32_t val; 723 724 BFE_LOCK_ASSERT(sc); 725 726 /* Set the interrupt vector for the enet core */ 727 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 728 729 /* is core up? */ 730 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 731 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 732 if (val == BFE_CLOCK) { 733 /* It is, so shut it down */ 734 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 735 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 736 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 737 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 738 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 739 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 740 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 741 100, 0); 742 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 743 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 744 } 745 746 bfe_core_reset(sc); 747 bfe_clear_stats(sc); 748 749 /* 750 * We want the phy registers to be accessible even when 751 * the driver is "downed" so initialize MDC preamble, frequency, 752 * and whether internal or external phy here. 753 */ 754 755 /* 4402 has 62.5Mhz SB clock and internal phy */ 756 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 757 758 /* Internal or external PHY? */ 759 val = CSR_READ_4(sc, BFE_DEVCTRL); 760 if(!(val & BFE_IPP)) 761 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 762 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 763 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 764 DELAY(100); 765 } 766 767 /* Enable CRC32 generation and set proper LED modes */ 768 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 769 770 /* Reset or clear powerdown control bit */ 771 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 772 773 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 774 BFE_LAZY_FC_MASK)); 775 776 /* 777 * We don't want lazy interrupts, so just send them at 778 * the end of a frame, please 779 */ 780 BFE_OR(sc, BFE_RCV_LAZY, 0); 781 782 /* Set max lengths, accounting for VLAN tags */ 783 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 784 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 785 786 /* Set watermark XXX - magic */ 787 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 788 789 /* 790 * Initialise DMA channels 791 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 792 */ 793 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 794 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 795 796 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 797 BFE_RX_CTRL_ENABLE); 798 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 799 800 bfe_resetphy(sc); 801 bfe_setupphy(sc); 802} 803 804static void 805bfe_core_disable(struct bfe_softc *sc) 806{ 807 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 808 return; 809 810 /* 811 * Set reject, wait for it set, then wait for the core to stop 812 * being busy, then set reset and reject and enable the clocks. 813 */ 814 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 815 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 816 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 818 BFE_RESET)); 819 CSR_READ_4(sc, BFE_SBTMSLOW); 820 DELAY(10); 821 /* Leave reset and reject set */ 822 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 823 DELAY(10); 824} 825 826static void 827bfe_core_reset(struct bfe_softc *sc) 828{ 829 u_int32_t val; 830 831 /* Disable the core */ 832 bfe_core_disable(sc); 833 834 /* and bring it back up */ 835 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 836 CSR_READ_4(sc, BFE_SBTMSLOW); 837 DELAY(10); 838 839 /* Chip bug, clear SERR, IB and TO if they are set. */ 840 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 841 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 842 val = CSR_READ_4(sc, BFE_SBIMSTATE); 843 if (val & (BFE_IBE | BFE_TO)) 844 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 845 846 /* Clear reset and allow it to move through the core */ 847 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 848 CSR_READ_4(sc, BFE_SBTMSLOW); 849 DELAY(10); 850 851 /* Leave the clock set */ 852 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 853 CSR_READ_4(sc, BFE_SBTMSLOW); 854 DELAY(10); 855} 856 857static void 858bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 859{ 860 u_int32_t val; 861 862 val = ((u_int32_t) data[2]) << 24; 863 val |= ((u_int32_t) data[3]) << 16; 864 val |= ((u_int32_t) data[4]) << 8; 865 val |= ((u_int32_t) data[5]); 866 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 867 val = (BFE_CAM_HI_VALID | 868 (((u_int32_t) data[0]) << 8) | 869 (((u_int32_t) data[1]))); 870 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 871 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 872 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 873 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 874} 875 876static void 877bfe_set_rx_mode(struct bfe_softc *sc) 878{ 879 struct ifnet *ifp = &sc->arpcom.ac_if; 880 struct ifmultiaddr *ifma; 881 u_int32_t val; 882 int i = 0; 883 884 val = CSR_READ_4(sc, BFE_RXCONF); 885 886 if (ifp->if_flags & IFF_PROMISC) 887 val |= BFE_RXCONF_PROMISC; 888 else 889 val &= ~BFE_RXCONF_PROMISC; 890 891 if (ifp->if_flags & IFF_BROADCAST) 892 val &= ~BFE_RXCONF_DBCAST; 893 else 894 val |= BFE_RXCONF_DBCAST; 895 896 897 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 898 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 899 900 if (ifp->if_flags & IFF_ALLMULTI) 901 val |= BFE_RXCONF_ALLMULTI; 902 else { 903 val &= ~BFE_RXCONF_ALLMULTI; 904 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 905 if (ifma->ifma_addr->sa_family != AF_LINK) 906 continue; 907 bfe_cam_write(sc, 908 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 909 } 910 } 911 912 CSR_WRITE_4(sc, BFE_RXCONF, val); 913 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 914} 915 916static void 917bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 918{ 919 u_int32_t *ptr; 920 921 ptr = arg; 922 *ptr = segs->ds_addr; 923} 924 925static void 926bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 927{ 928 struct bfe_desc *d; 929 930 d = arg; 931 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 932 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 933} 934 935static void 936bfe_release_resources(struct bfe_softc *sc) 937{ 938 device_t dev; 939 int i; 940 941 dev = sc->bfe_dev; 942 943 if (sc->bfe_vpd_prodname != NULL) 944 free(sc->bfe_vpd_prodname, M_DEVBUF); 945 946 if (sc->bfe_vpd_readonly != NULL) 947 free(sc->bfe_vpd_readonly, M_DEVBUF); 948 949 if (sc->bfe_intrhand != NULL) 950 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 951 952 if (sc->bfe_irq != NULL) 953 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 954 955 if (sc->bfe_res != NULL) 956 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 957 958 if(sc->bfe_tx_tag != NULL) { 959 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 960 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 961 sc->bfe_tx_map); 962 bus_dma_tag_destroy(sc->bfe_tx_tag); 963 sc->bfe_tx_tag = NULL; 964 } 965 966 if(sc->bfe_rx_tag != NULL) { 967 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 968 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 969 sc->bfe_rx_map); 970 bus_dma_tag_destroy(sc->bfe_rx_tag); 971 sc->bfe_rx_tag = NULL; 972 } 973 974 if(sc->bfe_tag != NULL) { 975 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 976 bus_dmamap_destroy(sc->bfe_tag, 977 sc->bfe_tx_ring[i].bfe_map); 978 } 979 bus_dma_tag_destroy(sc->bfe_tag); 980 sc->bfe_tag = NULL; 981 } 982 983 if(sc->bfe_parent_tag != NULL) 984 bus_dma_tag_destroy(sc->bfe_parent_tag); 985 986 return; 987} 988 989static void 990bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 991{ 992 long i; 993 u_int16_t *ptr = (u_int16_t *)data; 994 995 for(i = 0; i < 128; i += 2) 996 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 997} 998 999static int 1000bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1001 u_long timeout, const int clear) 1002{ 1003 u_long i; 1004 1005 for (i = 0; i < timeout; i++) { 1006 u_int32_t val = CSR_READ_4(sc, reg); 1007 1008 if (clear && !(val & bit)) 1009 break; 1010 if (!clear && (val & bit)) 1011 break; 1012 DELAY(10); 1013 } 1014 if (i == timeout) { 1015 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1016 "%x to %s.\n", sc->bfe_unit, bit, reg, 1017 (clear ? "clear" : "set")); 1018 return (-1); 1019 } 1020 return (0); 1021} 1022 1023static int 1024bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1025{ 1026 int err; 1027 1028 /* Clear MII ISR */ 1029 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1030 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1031 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1032 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1033 (reg << BFE_MDIO_RA_SHIFT) | 1034 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1035 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1036 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1037 1038 return (err); 1039} 1040 1041static int 1042bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1043{ 1044 int status; 1045 1046 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1047 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1048 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1049 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1050 (reg << BFE_MDIO_RA_SHIFT) | 1051 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1052 (val & BFE_MDIO_DATA_DATA))); 1053 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1054 1055 return (status); 1056} 1057 1058/* 1059 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1060 * twice 1061 */ 1062static int 1063bfe_setupphy(struct bfe_softc *sc) 1064{ 1065 u_int32_t val; 1066 1067 /* Enable activity LED */ 1068 bfe_readphy(sc, 26, &val); 1069 bfe_writephy(sc, 26, val & 0x7fff); 1070 bfe_readphy(sc, 26, &val); 1071 1072 /* Enable traffic meter LED mode */ 1073 bfe_readphy(sc, 27, &val); 1074 bfe_writephy(sc, 27, val | (1 << 6)); 1075 1076 return (0); 1077} 1078 1079static void 1080bfe_stats_update(struct bfe_softc *sc) 1081{ 1082 u_long reg; 1083 u_int32_t *val; 1084 1085 val = &sc->bfe_hwstats.tx_good_octets; 1086 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1087 *val++ += CSR_READ_4(sc, reg); 1088 } 1089 val = &sc->bfe_hwstats.rx_good_octets; 1090 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1091 *val++ += CSR_READ_4(sc, reg); 1092 } 1093} 1094 1095static void 1096bfe_txeof(struct bfe_softc *sc) 1097{ 1098 struct ifnet *ifp; 1099 int i, chipidx; 1100 1101 BFE_LOCK_ASSERT(sc); 1102 1103 ifp = &sc->arpcom.ac_if; 1104 1105 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1106 chipidx /= sizeof(struct bfe_desc); 1107 1108 i = sc->bfe_tx_cons; 1109 /* Go through the mbufs and free those that have been transmitted */ 1110 while(i != chipidx) { 1111 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1112 if(r->bfe_mbuf != NULL) { 1113 ifp->if_opackets++; 1114 m_freem(r->bfe_mbuf); 1115 r->bfe_mbuf = NULL; 1116 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1117 } 1118 sc->bfe_tx_cnt--; 1119 BFE_INC(i, BFE_TX_LIST_CNT); 1120 } 1121 1122 if(i != sc->bfe_tx_cons) { 1123 /* we freed up some mbufs */ 1124 sc->bfe_tx_cons = i; 1125 ifp->if_flags &= ~IFF_OACTIVE; 1126 } 1127 if(sc->bfe_tx_cnt == 0) 1128 ifp->if_timer = 0; 1129 else 1130 ifp->if_timer = 5; 1131} 1132 1133/* Pass a received packet up the stack */ 1134static void 1135bfe_rxeof(struct bfe_softc *sc) 1136{ 1137 struct mbuf *m; 1138 struct ifnet *ifp; 1139 struct bfe_rxheader *rxheader; 1140 struct bfe_data *r; 1141 int cons; 1142 u_int32_t status, current, len, flags; 1143 1144 BFE_LOCK_ASSERT(sc); 1145 cons = sc->bfe_rx_cons; 1146 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1147 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1148 1149 ifp = &sc->arpcom.ac_if; 1150 1151 while(current != cons) { 1152 r = &sc->bfe_rx_ring[cons]; 1153 m = r->bfe_mbuf; 1154 rxheader = mtod(m, struct bfe_rxheader*); 1155 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1156 len = rxheader->len; 1157 r->bfe_mbuf = NULL; 1158 1159 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1160 flags = rxheader->flags; 1161 1162 len -= ETHER_CRC_LEN; 1163 1164 /* flag an error and try again */ 1165 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1166 ifp->if_ierrors++; 1167 if (flags & BFE_RX_FLAG_SERR) 1168 ifp->if_collisions++; 1169 bfe_list_newbuf(sc, cons, m); 1170 BFE_INC(cons, BFE_RX_LIST_CNT); 1171 continue; 1172 } 1173 1174 /* Go past the rx header */ 1175 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1176 m_adj(m, BFE_RX_OFFSET); 1177 m->m_len = m->m_pkthdr.len = len; 1178 } else { 1179 bfe_list_newbuf(sc, cons, m); 1180 ifp->if_ierrors++; 1181 BFE_INC(cons, BFE_RX_LIST_CNT); 1182 continue; 1183 } 1184 1185 ifp->if_ipackets++; 1186 m->m_pkthdr.rcvif = ifp; 1187 BFE_UNLOCK(sc); 1188 (*ifp->if_input)(ifp, m); 1189 BFE_LOCK(sc); 1190 1191 BFE_INC(cons, BFE_RX_LIST_CNT); 1192 } 1193 sc->bfe_rx_cons = cons; 1194} 1195 1196static void 1197bfe_intr(void *xsc) 1198{ 1199 struct bfe_softc *sc = xsc; 1200 struct ifnet *ifp; 1201 u_int32_t istat, imask, flag; 1202 1203 ifp = &sc->arpcom.ac_if; 1204 1205 BFE_LOCK(sc); 1206 1207 istat = CSR_READ_4(sc, BFE_ISTAT); 1208 imask = CSR_READ_4(sc, BFE_IMASK); 1209 1210 /* 1211 * Defer unsolicited interrupts - This is necessary because setting the 1212 * chips interrupt mask register to 0 doesn't actually stop the 1213 * interrupts 1214 */ 1215 istat &= imask; 1216 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1217 CSR_READ_4(sc, BFE_ISTAT); 1218 1219 /* not expecting this interrupt, disregard it */ 1220 if(istat == 0) { 1221 BFE_UNLOCK(sc); 1222 return; 1223 } 1224 1225 if(istat & BFE_ISTAT_ERRORS) { 1226 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1227 if(flag & BFE_STAT_EMASK) 1228 ifp->if_oerrors++; 1229 1230 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1231 if(flag & BFE_RX_FLAG_ERRORS) 1232 ifp->if_ierrors++; 1233 1234 ifp->if_flags &= ~IFF_RUNNING; 1235 bfe_init_locked(sc); 1236 } 1237 1238 /* A packet was received */ 1239 if(istat & BFE_ISTAT_RX) 1240 bfe_rxeof(sc); 1241 1242 /* A packet was sent */ 1243 if(istat & BFE_ISTAT_TX) 1244 bfe_txeof(sc); 1245 1246 /* We have packets pending, fire them out */ 1247 if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1248 bfe_start_locked(ifp); 1249 1250 BFE_UNLOCK(sc); 1251} 1252 1253static int 1254bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1255{ 1256 struct bfe_desc *d = NULL; 1257 struct bfe_data *r = NULL; 1258 struct mbuf *m; 1259 u_int32_t frag, cur, cnt = 0; 1260 int chainlen = 0; 1261 1262 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1263 return (ENOBUFS); 1264 1265 /* 1266 * Count the number of frags in this chain to see if 1267 * we need to m_defrag. Since the descriptor list is shared 1268 * by all packets, we'll m_defrag long chains so that they 1269 * do not use up the entire list, even if they would fit. 1270 */ 1271 for(m = m_head; m != NULL; m = m->m_next) 1272 chainlen++; 1273 1274 1275 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1276 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1277 m = m_defrag(m_head, M_DONTWAIT); 1278 if (m == NULL) 1279 return (ENOBUFS); 1280 m_head = m; 1281 } 1282 1283 /* 1284 * Start packing the mbufs in this chain into 1285 * the fragment pointers. Stop when we run out 1286 * of fragments or hit the end of the mbuf chain. 1287 */ 1288 m = m_head; 1289 cur = frag = *txidx; 1290 cnt = 0; 1291 1292 for(m = m_head; m != NULL; m = m->m_next) { 1293 if(m->m_len != 0) { 1294 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1295 return (ENOBUFS); 1296 1297 d = &sc->bfe_tx_list[cur]; 1298 r = &sc->bfe_tx_ring[cur]; 1299 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1300 /* always intterupt on completion */ 1301 d->bfe_ctrl |= BFE_DESC_IOC; 1302 if(cnt == 0) 1303 /* Set start of frame */ 1304 d->bfe_ctrl |= BFE_DESC_SOF; 1305 if(cur == BFE_TX_LIST_CNT - 1) 1306 /* 1307 * Tell the chip to wrap to the start of 1308 * the descriptor list 1309 */ 1310 d->bfe_ctrl |= BFE_DESC_EOT; 1311 1312 bus_dmamap_load(sc->bfe_tag, 1313 r->bfe_map, mtod(m, void*), m->m_len, 1314 bfe_dma_map_desc, d, 0); 1315 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1316 BUS_DMASYNC_PREREAD); 1317 1318 frag = cur; 1319 BFE_INC(cur, BFE_TX_LIST_CNT); 1320 cnt++; 1321 } 1322 } 1323 1324 if (m != NULL) 1325 return (ENOBUFS); 1326 1327 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1328 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1329 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1330 1331 *txidx = cur; 1332 sc->bfe_tx_cnt += cnt; 1333 return (0); 1334} 1335 1336/* 1337 * Set up to transmit a packet. 1338 */ 1339static void 1340bfe_start(struct ifnet *ifp) 1341{ 1342 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1343 bfe_start_locked(ifp); 1344 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1345} 1346 1347/* 1348 * Set up to transmit a packet. The softc is already locked. 1349 */ 1350static void 1351bfe_start_locked(struct ifnet *ifp) 1352{ 1353 struct bfe_softc *sc; 1354 struct mbuf *m_head = NULL; 1355 int idx, queued = 0; 1356 1357 sc = ifp->if_softc; 1358 idx = sc->bfe_tx_prod; 1359 1360 BFE_LOCK_ASSERT(sc); 1361 1362 /* 1363 * Not much point trying to send if the link is down 1364 * or we have nothing to send. 1365 */ 1366 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1367 return; 1368 1369 if (ifp->if_flags & IFF_OACTIVE) 1370 return; 1371 1372 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1373 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1374 if(m_head == NULL) 1375 break; 1376 1377 /* 1378 * Pack the data into the tx ring. If we dont have 1379 * enough room, let the chip drain the ring. 1380 */ 1381 if(bfe_encap(sc, m_head, &idx)) { 1382 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1383 ifp->if_flags |= IFF_OACTIVE; 1384 break; 1385 } 1386 1387 queued++; 1388 1389 /* 1390 * If there's a BPF listener, bounce a copy of this frame 1391 * to him. 1392 */ 1393 BPF_MTAP(ifp, m_head); 1394 } 1395 1396 if (queued) { 1397 sc->bfe_tx_prod = idx; 1398 /* Transmit - twice due to apparent hardware bug */ 1399 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1400 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1401 1402 /* 1403 * Set a timeout in case the chip goes out to lunch. 1404 */ 1405 ifp->if_timer = 5; 1406 } 1407} 1408 1409static void 1410bfe_init(void *xsc) 1411{ 1412 BFE_LOCK((struct bfe_softc *)xsc); 1413 bfe_init_locked(xsc); 1414 BFE_UNLOCK((struct bfe_softc *)xsc); 1415} 1416 1417static void 1418bfe_init_locked(void *xsc) 1419{ 1420 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1421 struct ifnet *ifp = &sc->arpcom.ac_if; 1422 1423 BFE_LOCK_ASSERT(sc); 1424 1425 if (ifp->if_flags & IFF_RUNNING) 1426 return; 1427 1428 bfe_stop(sc); 1429 bfe_chip_reset(sc); 1430 1431 if (bfe_list_rx_init(sc) == ENOBUFS) { 1432 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1433 sc->bfe_unit); 1434 bfe_stop(sc); 1435 return; 1436 } 1437 1438 bfe_set_rx_mode(sc); 1439 1440 /* Enable the chip and core */ 1441 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1442 /* Enable interrupts */ 1443 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1444 1445 bfe_ifmedia_upd(ifp); 1446 ifp->if_flags |= IFF_RUNNING; 1447 ifp->if_flags &= ~IFF_OACTIVE; 1448 1449 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1450} 1451 1452/* 1453 * Set media options. 1454 */ 1455static int 1456bfe_ifmedia_upd(struct ifnet *ifp) 1457{ 1458 struct bfe_softc *sc; 1459 struct mii_data *mii; 1460 1461 sc = ifp->if_softc; 1462 1463 mii = device_get_softc(sc->bfe_miibus); 1464 sc->bfe_link = 0; 1465 if (mii->mii_instance) { 1466 struct mii_softc *miisc; 1467 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1468 miisc = LIST_NEXT(miisc, mii_list)) 1469 mii_phy_reset(miisc); 1470 } 1471 mii_mediachg(mii); 1472 1473 return (0); 1474} 1475 1476/* 1477 * Report current media status. 1478 */ 1479static void 1480bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1481{ 1482 struct bfe_softc *sc = ifp->if_softc; 1483 struct mii_data *mii; 1484 1485 mii = device_get_softc(sc->bfe_miibus); 1486 mii_pollstat(mii); 1487 ifmr->ifm_active = mii->mii_media_active; 1488 ifmr->ifm_status = mii->mii_media_status; 1489} 1490 1491static int 1492bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1493{ 1494 struct bfe_softc *sc = ifp->if_softc; 1495 struct ifreq *ifr = (struct ifreq *) data; 1496 struct mii_data *mii; 1497 int error = 0; 1498 1499 switch(command) { 1500 case SIOCSIFFLAGS: 1501 BFE_LOCK(sc); 1502 if(ifp->if_flags & IFF_UP) 1503 if(ifp->if_flags & IFF_RUNNING) 1504 bfe_set_rx_mode(sc); 1505 else 1506 bfe_init_locked(sc); 1507 else if(ifp->if_flags & IFF_RUNNING) 1508 bfe_stop(sc); 1509 BFE_UNLOCK(sc); 1510 break; 1511 case SIOCADDMULTI: 1512 case SIOCDELMULTI: 1513 BFE_LOCK(sc); 1514 if(ifp->if_flags & IFF_RUNNING) 1515 bfe_set_rx_mode(sc); 1516 BFE_UNLOCK(sc); 1517 break; 1518 case SIOCGIFMEDIA: 1519 case SIOCSIFMEDIA: 1520 mii = device_get_softc(sc->bfe_miibus); 1521 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1522 command); 1523 break; 1524 default: 1525 error = ether_ioctl(ifp, command, data); 1526 break; 1527 } 1528 1529 return (error); 1530} 1531 1532static void 1533bfe_watchdog(struct ifnet *ifp) 1534{ 1535 struct bfe_softc *sc; 1536 1537 sc = ifp->if_softc; 1538 1539 BFE_LOCK(sc); 1540 1541 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1542 1543 ifp->if_flags &= ~IFF_RUNNING; 1544 bfe_init_locked(sc); 1545 1546 ifp->if_oerrors++; 1547 1548 BFE_UNLOCK(sc); 1549} 1550 1551static void 1552bfe_tick(void *xsc) 1553{ 1554 struct bfe_softc *sc = xsc; 1555 struct mii_data *mii; 1556 1557 if (sc == NULL) 1558 return; 1559 1560 BFE_LOCK(sc); 1561 1562 mii = device_get_softc(sc->bfe_miibus); 1563 1564 bfe_stats_update(sc); 1565 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1566 1567 if(sc->bfe_link) { 1568 BFE_UNLOCK(sc); 1569 return; 1570 } 1571 1572 mii_tick(mii); 1573 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1574 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1575 sc->bfe_link++; 1576 1577 BFE_UNLOCK(sc); 1578} 1579 1580/* 1581 * Stop the adapter and free any mbufs allocated to the 1582 * RX and TX lists. 1583 */ 1584static void 1585bfe_stop(struct bfe_softc *sc) 1586{ 1587 struct ifnet *ifp; 1588 1589 BFE_LOCK_ASSERT(sc); 1590 1591 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1592 1593 ifp = &sc->arpcom.ac_if; 1594 1595 bfe_chip_halt(sc); 1596 bfe_tx_ring_free(sc); 1597 bfe_rx_ring_free(sc); 1598 1599 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1600} 1601