if_bfe.c revision 126966
1/* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 */ 5 6/* 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 126966 2004-03-14 07:12:25Z mdodd $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/sockio.h> 36#include <sys/mbuf.h> 37#include <sys/malloc.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/queue.h> 41 42#include <net/if.h> 43#include <net/if_arp.h> 44#include <net/ethernet.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#include <net/bpf.h> 49 50#include <net/if_types.h> 51#include <net/if_vlan_var.h> 52 53#include <netinet/in_systm.h> 54#include <netinet/in.h> 55#include <netinet/ip.h> 56 57#include <machine/clock.h> /* for DELAY */ 58#include <machine/bus_memio.h> 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/bus.h> 62#include <sys/rman.h> 63 64#include <dev/mii/mii.h> 65#include <dev/mii/miivar.h> 66#include "miidevs.h" 67 68#include <dev/pci/pcireg.h> 69#include <dev/pci/pcivar.h> 70 71#include <dev/bfe/if_bfereg.h> 72 73MODULE_DEPEND(bfe, pci, 1, 1, 1); 74MODULE_DEPEND(bfe, ether, 1, 1, 1); 75MODULE_DEPEND(bfe, miibus, 1, 1, 1); 76 77/* "controller miibus0" required. See GENERIC if you get errors here. */ 78#include "miibus_if.h" 79 80#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 81 82static struct bfe_type bfe_devs[] = { 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 84 "Broadcom BCM4401 Fast Ethernet" }, 85 { 0, 0, NULL } 86}; 87 88static int bfe_probe (device_t); 89static int bfe_attach (device_t); 90static int bfe_detach (device_t); 91static void bfe_release_resources (struct bfe_softc *); 92static void bfe_intr (void *); 93static void bfe_start (struct ifnet *); 94static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 95static void bfe_init (void *); 96static void bfe_stop (struct bfe_softc *); 97static void bfe_watchdog (struct ifnet *); 98static void bfe_shutdown (device_t); 99static void bfe_tick (void *); 100static void bfe_txeof (struct bfe_softc *); 101static void bfe_rxeof (struct bfe_softc *); 102static void bfe_set_rx_mode (struct bfe_softc *); 103static int bfe_list_rx_init (struct bfe_softc *); 104static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 105static void bfe_rx_ring_free (struct bfe_softc *); 106 107static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 108static int bfe_ifmedia_upd (struct ifnet *); 109static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110static int bfe_miibus_readreg (device_t, int, int); 111static int bfe_miibus_writereg (device_t, int, int, int); 112static void bfe_miibus_statchg (device_t); 113static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 114 u_long, const int); 115static void bfe_get_config (struct bfe_softc *sc); 116static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 117static void bfe_stats_update (struct bfe_softc *); 118static void bfe_clear_stats (struct bfe_softc *); 119static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 120static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 121static int bfe_resetphy (struct bfe_softc *); 122static int bfe_setupphy (struct bfe_softc *); 123static void bfe_chip_reset (struct bfe_softc *); 124static void bfe_chip_halt (struct bfe_softc *); 125static void bfe_core_reset (struct bfe_softc *); 126static void bfe_core_disable (struct bfe_softc *); 127static int bfe_dma_alloc (device_t); 128static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 129static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 130static void bfe_cam_write (struct bfe_softc *, u_char *, int); 131 132static device_method_t bfe_methods[] = { 133 /* Device interface */ 134 DEVMETHOD(device_probe, bfe_probe), 135 DEVMETHOD(device_attach, bfe_attach), 136 DEVMETHOD(device_detach, bfe_detach), 137 DEVMETHOD(device_shutdown, bfe_shutdown), 138 139 /* bus interface */ 140 DEVMETHOD(bus_print_child, bus_generic_print_child), 141 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 142 143 /* MII interface */ 144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 146 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 147 148 { 0, 0 } 149}; 150 151static driver_t bfe_driver = { 152 "bfe", 153 bfe_methods, 154 sizeof(struct bfe_softc) 155}; 156 157static devclass_t bfe_devclass; 158 159DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 160DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 161 162/* 163 * Probe for a Broadcom 4401 chip. 164 */ 165static int 166bfe_probe(device_t dev) 167{ 168 struct bfe_type *t; 169 struct bfe_softc *sc; 170 171 t = bfe_devs; 172 173 sc = device_get_softc(dev); 174 bzero(sc, sizeof(struct bfe_softc)); 175 sc->bfe_unit = device_get_unit(dev); 176 sc->bfe_dev = dev; 177 178 while(t->bfe_name != NULL) { 179 if ((pci_get_vendor(dev) == t->bfe_vid) && 180 (pci_get_device(dev) == t->bfe_did)) { 181 device_set_desc_copy(dev, t->bfe_name); 182 return(0); 183 } 184 t++; 185 } 186 187 return(ENXIO); 188} 189 190static int 191bfe_dma_alloc(device_t dev) 192{ 193 struct bfe_softc *sc; 194 int error, i; 195 196 sc = device_get_softc(dev); 197 198 /* parent tag */ 199 error = bus_dma_tag_create(NULL, /* parent */ 200 PAGE_SIZE, 0, /* alignment, boundary */ 201 BUS_SPACE_MAXADDR, /* lowaddr */ 202 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 203 NULL, NULL, /* filter, filterarg */ 204 MAXBSIZE, /* maxsize */ 205 BUS_SPACE_UNRESTRICTED, /* num of segments */ 206 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 207 BUS_DMA_ALLOCNOW, /* flags */ 208 NULL, NULL, /* lockfunc, lockarg */ 209 &sc->bfe_parent_tag); 210 211 /* tag for TX ring */ 212 error = bus_dma_tag_create(sc->bfe_parent_tag, 213 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 214 BUS_SPACE_MAXADDR, 215 BUS_SPACE_MAXADDR, 216 NULL, NULL, 217 BFE_TX_LIST_SIZE, 218 1, 219 BUS_SPACE_MAXSIZE_32BIT, 220 0, 221 NULL, NULL, 222 &sc->bfe_tx_tag); 223 224 if (error) { 225 device_printf(dev, "could not allocate dma tag\n"); 226 return(ENOMEM); 227 } 228 229 /* tag for RX ring */ 230 error = bus_dma_tag_create(sc->bfe_parent_tag, 231 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 232 BUS_SPACE_MAXADDR, 233 BUS_SPACE_MAXADDR, 234 NULL, NULL, 235 BFE_RX_LIST_SIZE, 236 1, 237 BUS_SPACE_MAXSIZE_32BIT, 238 0, 239 NULL, NULL, 240 &sc->bfe_rx_tag); 241 242 if (error) { 243 device_printf(dev, "could not allocate dma tag\n"); 244 return(ENOMEM); 245 } 246 247 /* tag for mbufs */ 248 error = bus_dma_tag_create(sc->bfe_parent_tag, 249 ETHER_ALIGN, 0, 250 BUS_SPACE_MAXADDR, 251 BUS_SPACE_MAXADDR, 252 NULL, NULL, 253 MCLBYTES, 254 1, 255 BUS_SPACE_MAXSIZE_32BIT, 256 0, 257 NULL, NULL, 258 &sc->bfe_tag); 259 260 if (error) { 261 device_printf(dev, "could not allocate dma tag\n"); 262 return(ENOMEM); 263 } 264 265 /* pre allocate dmamaps for RX list */ 266 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 267 error = bus_dmamap_create(sc->bfe_tag, 0, 268 &sc->bfe_rx_ring[i].bfe_map); 269 if (error) { 270 device_printf(dev, "cannot create DMA map for RX\n"); 271 return(ENOMEM); 272 } 273 } 274 275 /* pre allocate dmamaps for TX list */ 276 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 277 error = bus_dmamap_create(sc->bfe_tag, 0, 278 &sc->bfe_tx_ring[i].bfe_map); 279 if (error) { 280 device_printf(dev, "cannot create DMA map for TX\n"); 281 return(ENOMEM); 282 } 283 } 284 285 /* Alloc dma for rx ring */ 286 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 287 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 288 289 if(error) 290 return(ENOMEM); 291 292 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 293 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 294 sc->bfe_rx_list, sizeof(struct bfe_desc), 295 bfe_dma_map, &sc->bfe_rx_dma, 0); 296 297 if(error) 298 return(ENOMEM); 299 300 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 301 302 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 303 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 304 if (error) 305 return(ENOMEM); 306 307 308 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 309 sc->bfe_tx_list, sizeof(struct bfe_desc), 310 bfe_dma_map, &sc->bfe_tx_dma, 0); 311 if(error) 312 return(ENOMEM); 313 314 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 315 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 316 317 return(0); 318} 319 320static int 321bfe_attach(device_t dev) 322{ 323 struct ifnet *ifp; 324 struct bfe_softc *sc; 325 int unit, error = 0, rid; 326 327 sc = device_get_softc(dev); 328 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 329 MTX_DEF | MTX_RECURSE); 330 331 unit = device_get_unit(dev); 332 sc->bfe_dev = dev; 333 sc->bfe_unit = unit; 334 335 /* 336 * Handle power management nonsense. 337 */ 338 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 339 u_int32_t membase, irq; 340 341 /* Save important PCI config data. */ 342 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 343 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 344 345 /* Reset the power state. */ 346 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 347 sc->bfe_unit, pci_get_powerstate(dev)); 348 349 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 350 351 /* Restore PCI config data. */ 352 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 353 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 354 } 355 356 /* 357 * Map control/status registers. 358 */ 359 pci_enable_busmaster(dev); 360 361 rid = BFE_PCI_MEMLO; 362 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, 363 RF_ACTIVE); 364 if (sc->bfe_res == NULL) { 365 printf ("bfe%d: couldn't map memory\n", unit); 366 error = ENXIO; 367 goto fail; 368 } 369 370 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 371 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 372 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 373 374 /* Allocate interrupt */ 375 rid = 0; 376 377 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 378 RF_SHAREABLE | RF_ACTIVE); 379 if (sc->bfe_irq == NULL) { 380 printf("bfe%d: couldn't map interrupt\n", unit); 381 error = ENXIO; 382 goto fail; 383 } 384 385 if (bfe_dma_alloc(dev)) { 386 printf("bfe%d: failed to allocate DMA resources\n", 387 sc->bfe_unit); 388 bfe_release_resources(sc); 389 error = ENXIO; 390 goto fail; 391 } 392 393 /* Set up ifnet structure */ 394 ifp = &sc->arpcom.ac_if; 395 ifp->if_softc = sc; 396 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 397 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 398 ifp->if_ioctl = bfe_ioctl; 399 ifp->if_output = ether_output; 400 ifp->if_start = bfe_start; 401 ifp->if_watchdog = bfe_watchdog; 402 ifp->if_init = bfe_init; 403 ifp->if_mtu = ETHERMTU; 404 ifp->if_baudrate = 10000000; 405 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN; 406 407 bfe_get_config(sc); 408 409 /* Reset the chip and turn on the PHY */ 410 bfe_chip_reset(sc); 411 412 if (mii_phy_probe(dev, &sc->bfe_miibus, 413 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 414 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 415 error = ENXIO; 416 goto fail; 417 } 418 419 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 420 callout_handle_init(&sc->bfe_stat_ch); 421 422 /* 423 * Hook interrupt last to avoid having to lock softc 424 */ 425 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 426 bfe_intr, sc, &sc->bfe_intrhand); 427 428 if (error) { 429 bfe_release_resources(sc); 430 printf("bfe%d: couldn't set up irq\n", unit); 431 goto fail; 432 } 433fail: 434 if(error) 435 bfe_release_resources(sc); 436 return(error); 437} 438 439static int 440bfe_detach(device_t dev) 441{ 442 struct bfe_softc *sc; 443 struct ifnet *ifp; 444 445 sc = device_get_softc(dev); 446 447 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 448 BFE_LOCK(scp); 449 450 ifp = &sc->arpcom.ac_if; 451 452 if (device_is_attached(dev)) { 453 bfe_stop(sc); 454 ether_ifdetach(ifp); 455 } 456 457 bfe_chip_reset(sc); 458 459 bus_generic_detach(dev); 460 if(sc->bfe_miibus != NULL) 461 device_delete_child(dev, sc->bfe_miibus); 462 463 bfe_release_resources(sc); 464 BFE_UNLOCK(sc); 465 mtx_destroy(&sc->bfe_mtx); 466 467 return(0); 468} 469 470/* 471 * Stop all chip I/O so that the kernel's probe routines don't 472 * get confused by errant DMAs when rebooting. 473 */ 474static void 475bfe_shutdown(device_t dev) 476{ 477 struct bfe_softc *sc; 478 479 sc = device_get_softc(dev); 480 BFE_LOCK(sc); 481 bfe_stop(sc); 482 483 BFE_UNLOCK(sc); 484 return; 485} 486 487static int 488bfe_miibus_readreg(device_t dev, int phy, int reg) 489{ 490 struct bfe_softc *sc; 491 u_int32_t ret; 492 493 sc = device_get_softc(dev); 494 if(phy != sc->bfe_phyaddr) 495 return(0); 496 bfe_readphy(sc, reg, &ret); 497 498 return(ret); 499} 500 501static int 502bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 503{ 504 struct bfe_softc *sc; 505 506 sc = device_get_softc(dev); 507 if(phy != sc->bfe_phyaddr) 508 return(0); 509 bfe_writephy(sc, reg, val); 510 511 return(0); 512} 513 514static void 515bfe_miibus_statchg(device_t dev) 516{ 517 return; 518} 519 520static void 521bfe_tx_ring_free(struct bfe_softc *sc) 522{ 523 int i; 524 525 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 526 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 527 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 528 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 529 bus_dmamap_unload(sc->bfe_tag, 530 sc->bfe_tx_ring[i].bfe_map); 531 bus_dmamap_destroy(sc->bfe_tag, 532 sc->bfe_tx_ring[i].bfe_map); 533 } 534 } 535 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 536 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 537} 538 539static void 540bfe_rx_ring_free(struct bfe_softc *sc) 541{ 542 int i; 543 544 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 545 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 546 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 547 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 548 bus_dmamap_unload(sc->bfe_tag, 549 sc->bfe_rx_ring[i].bfe_map); 550 bus_dmamap_destroy(sc->bfe_tag, 551 sc->bfe_rx_ring[i].bfe_map); 552 } 553 } 554 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 555 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 556} 557 558 559static int 560bfe_list_rx_init(struct bfe_softc *sc) 561{ 562 int i; 563 564 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 565 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 566 return ENOBUFS; 567 } 568 569 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 570 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 571 572 sc->bfe_rx_cons = 0; 573 574 return(0); 575} 576 577static int 578bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 579{ 580 struct bfe_rxheader *rx_header; 581 struct bfe_desc *d; 582 struct bfe_data *r; 583 u_int32_t ctrl; 584 585 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 586 return(EINVAL); 587 588 if(m == NULL) { 589 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 590 if(m == NULL) 591 return(ENOBUFS); 592 m->m_len = m->m_pkthdr.len = MCLBYTES; 593 } 594 else 595 m->m_data = m->m_ext.ext_buf; 596 597 rx_header = mtod(m, struct bfe_rxheader *); 598 rx_header->len = 0; 599 rx_header->flags = 0; 600 601 /* Map the mbuf into DMA */ 602 sc->bfe_rx_cnt = c; 603 d = &sc->bfe_rx_list[c]; 604 r = &sc->bfe_rx_ring[c]; 605 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 606 MCLBYTES, bfe_dma_map_desc, d, 0); 607 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 608 609 ctrl = ETHER_MAX_LEN + 32; 610 611 if(c == BFE_RX_LIST_CNT - 1) 612 ctrl |= BFE_DESC_EOT; 613 614 d->bfe_ctrl = ctrl; 615 r->bfe_mbuf = m; 616 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 617 return(0); 618} 619 620static void 621bfe_get_config(struct bfe_softc *sc) 622{ 623 u_int8_t eeprom[128]; 624 625 bfe_read_eeprom(sc, eeprom); 626 627 sc->arpcom.ac_enaddr[0] = eeprom[79]; 628 sc->arpcom.ac_enaddr[1] = eeprom[78]; 629 sc->arpcom.ac_enaddr[2] = eeprom[81]; 630 sc->arpcom.ac_enaddr[3] = eeprom[80]; 631 sc->arpcom.ac_enaddr[4] = eeprom[83]; 632 sc->arpcom.ac_enaddr[5] = eeprom[82]; 633 634 sc->bfe_phyaddr = eeprom[90] & 0x1f; 635 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 636 637 sc->bfe_core_unit = 0; 638 sc->bfe_dma_offset = BFE_PCI_DMA; 639} 640 641static void 642bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 643{ 644 u_int32_t bar_orig, pci_rev, val; 645 646 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 647 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 648 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 649 650 val = CSR_READ_4(sc, BFE_SBINTVEC); 651 val |= cores; 652 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 653 654 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 655 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 656 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 657 658 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 659} 660 661static void 662bfe_clear_stats(struct bfe_softc *sc) 663{ 664 u_long reg; 665 666 BFE_LOCK(sc); 667 668 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 669 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 670 CSR_READ_4(sc, reg); 671 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 672 CSR_READ_4(sc, reg); 673 674 BFE_UNLOCK(sc); 675} 676 677static int 678bfe_resetphy(struct bfe_softc *sc) 679{ 680 u_int32_t val; 681 682 BFE_LOCK(sc); 683 bfe_writephy(sc, 0, BMCR_RESET); 684 DELAY(100); 685 bfe_readphy(sc, 0, &val); 686 if (val & BMCR_RESET) { 687 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 688 BFE_UNLOCK(sc); 689 return ENXIO; 690 } 691 BFE_UNLOCK(sc); 692 return 0; 693} 694 695static void 696bfe_chip_halt(struct bfe_softc *sc) 697{ 698 BFE_LOCK(sc); 699 /* disable interrupts - not that it actually does..*/ 700 CSR_WRITE_4(sc, BFE_IMASK, 0); 701 CSR_READ_4(sc, BFE_IMASK); 702 703 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 704 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 705 706 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 707 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 708 DELAY(10); 709 710 BFE_UNLOCK(sc); 711} 712 713static void 714bfe_chip_reset(struct bfe_softc *sc) 715{ 716 u_int32_t val; 717 718 BFE_LOCK(sc); 719 720 /* Set the interrupt vector for the enet core */ 721 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 722 723 /* is core up? */ 724 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 725 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 726 if (val == BFE_CLOCK) { 727 /* It is, so shut it down */ 728 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 729 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 730 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 731 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 732 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 733 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 734 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 735 100, 0); 736 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 737 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 738 } 739 740 bfe_core_reset(sc); 741 bfe_clear_stats(sc); 742 743 /* 744 * We want the phy registers to be accessible even when 745 * the driver is "downed" so initialize MDC preamble, frequency, 746 * and whether internal or external phy here. 747 */ 748 749 /* 4402 has 62.5Mhz SB clock and internal phy */ 750 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 751 752 /* Internal or external PHY? */ 753 val = CSR_READ_4(sc, BFE_DEVCTRL); 754 if(!(val & BFE_IPP)) 755 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 756 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 757 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 758 DELAY(100); 759 } 760 761 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB); 762 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 763 BFE_LAZY_FC_MASK)); 764 765 /* 766 * We don't want lazy interrupts, so just send them at 767 * the end of a frame, please 768 */ 769 BFE_OR(sc, BFE_RCV_LAZY, 0); 770 771 /* Set max lengths, accounting for VLAN tags */ 772 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 773 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 774 775 /* Set watermark XXX - magic */ 776 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 777 778 /* 779 * Initialise DMA channels 780 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 781 */ 782 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 783 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 784 785 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 786 BFE_RX_CTRL_ENABLE); 787 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 788 789 bfe_resetphy(sc); 790 bfe_setupphy(sc); 791 792 BFE_UNLOCK(sc); 793} 794 795static void 796bfe_core_disable(struct bfe_softc *sc) 797{ 798 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 799 return; 800 801 /* 802 * Set reject, wait for it set, then wait for the core to stop 803 * being busy, then set reset and reject and enable the clocks. 804 */ 805 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 806 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 807 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 808 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 809 BFE_RESET)); 810 CSR_READ_4(sc, BFE_SBTMSLOW); 811 DELAY(10); 812 /* Leave reset and reject set */ 813 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 814 DELAY(10); 815} 816 817static void 818bfe_core_reset(struct bfe_softc *sc) 819{ 820 u_int32_t val; 821 822 /* Disable the core */ 823 bfe_core_disable(sc); 824 825 /* and bring it back up */ 826 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 827 CSR_READ_4(sc, BFE_SBTMSLOW); 828 DELAY(10); 829 830 /* Chip bug, clear SERR, IB and TO if they are set. */ 831 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 832 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 833 val = CSR_READ_4(sc, BFE_SBIMSTATE); 834 if (val & (BFE_IBE | BFE_TO)) 835 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 836 837 /* Clear reset and allow it to move through the core */ 838 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 839 CSR_READ_4(sc, BFE_SBTMSLOW); 840 DELAY(10); 841 842 /* Leave the clock set */ 843 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 844 CSR_READ_4(sc, BFE_SBTMSLOW); 845 DELAY(10); 846} 847 848static void 849bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 850{ 851 u_int32_t val; 852 853 val = ((u_int32_t) data[2]) << 24; 854 val |= ((u_int32_t) data[3]) << 16; 855 val |= ((u_int32_t) data[4]) << 8; 856 val |= ((u_int32_t) data[5]); 857 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 858 val = (BFE_CAM_HI_VALID | 859 (((u_int32_t) data[0]) << 8) | 860 (((u_int32_t) data[1]))); 861 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 862 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 863 (index << BFE_CAM_INDEX_SHIFT))); 864 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 865} 866 867static void 868bfe_set_rx_mode(struct bfe_softc *sc) 869{ 870 struct ifnet *ifp = &sc->arpcom.ac_if; 871 struct ifmultiaddr *ifma; 872 u_int32_t val; 873 int i = 0; 874 875 val = CSR_READ_4(sc, BFE_RXCONF); 876 877 if (ifp->if_flags & IFF_PROMISC) 878 val |= BFE_RXCONF_PROMISC; 879 else 880 val &= ~BFE_RXCONF_PROMISC; 881 882 if (ifp->if_flags & IFF_BROADCAST) 883 val &= ~BFE_RXCONF_DBCAST; 884 else 885 val |= BFE_RXCONF_DBCAST; 886 887 888 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 889 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 890 891 if (ifp->if_flags & IFF_ALLMULTI) 892 val |= BFE_RXCONF_ALLMULTI; 893 else { 894 val &= ~BFE_RXCONF_ALLMULTI; 895 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 896 if (ifma->ifma_addr->sa_family != AF_LINK) 897 continue; 898 bfe_cam_write(sc, 899 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 900 } 901 } 902 903 CSR_WRITE_4(sc, BFE_RXCONF, val); 904 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 905} 906 907static void 908bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 909{ 910 u_int32_t *ptr; 911 912 ptr = arg; 913 *ptr = segs->ds_addr; 914} 915 916static void 917bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 918{ 919 struct bfe_desc *d; 920 921 d = arg; 922 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 923 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 924} 925 926static void 927bfe_release_resources(struct bfe_softc *sc) 928{ 929 device_t dev; 930 int i; 931 932 dev = sc->bfe_dev; 933 934 if (sc->bfe_vpd_prodname != NULL) 935 free(sc->bfe_vpd_prodname, M_DEVBUF); 936 937 if (sc->bfe_vpd_readonly != NULL) 938 free(sc->bfe_vpd_readonly, M_DEVBUF); 939 940 if (sc->bfe_intrhand != NULL) 941 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 942 943 if (sc->bfe_irq != NULL) 944 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 945 946 if (sc->bfe_res != NULL) 947 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 948 949 if(sc->bfe_tx_tag != NULL) { 950 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 951 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 952 sc->bfe_tx_map); 953 bus_dma_tag_destroy(sc->bfe_tx_tag); 954 sc->bfe_tx_tag = NULL; 955 } 956 957 if(sc->bfe_rx_tag != NULL) { 958 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 959 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 960 sc->bfe_rx_map); 961 bus_dma_tag_destroy(sc->bfe_rx_tag); 962 sc->bfe_rx_tag = NULL; 963 } 964 965 if(sc->bfe_tag != NULL) { 966 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 967 bus_dmamap_destroy(sc->bfe_tag, 968 sc->bfe_tx_ring[i].bfe_map); 969 } 970 bus_dma_tag_destroy(sc->bfe_tag); 971 sc->bfe_tag = NULL; 972 } 973 974 if(sc->bfe_parent_tag != NULL) 975 bus_dma_tag_destroy(sc->bfe_parent_tag); 976 977 return; 978} 979 980static void 981bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 982{ 983 long i; 984 u_int16_t *ptr = (u_int16_t *)data; 985 986 for(i = 0; i < 128; i += 2) 987 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 988} 989 990static int 991bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 992 u_long timeout, const int clear) 993{ 994 u_long i; 995 996 for (i = 0; i < timeout; i++) { 997 u_int32_t val = CSR_READ_4(sc, reg); 998 999 if (clear && !(val & bit)) 1000 break; 1001 if (!clear && (val & bit)) 1002 break; 1003 DELAY(10); 1004 } 1005 if (i == timeout) { 1006 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1007 "%x to %s.\n", sc->bfe_unit, bit, reg, 1008 (clear ? "clear" : "set")); 1009 return -1; 1010 } 1011 return 0; 1012} 1013 1014static int 1015bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1016{ 1017 int err; 1018 1019 BFE_LOCK(sc); 1020 /* Clear MII ISR */ 1021 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1022 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1023 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1024 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1025 (reg << BFE_MDIO_RA_SHIFT) | 1026 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1027 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1028 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1029 1030 BFE_UNLOCK(sc); 1031 return err; 1032} 1033 1034static int 1035bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1036{ 1037 int status; 1038 1039 BFE_LOCK(sc); 1040 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1041 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1042 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1043 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1044 (reg << BFE_MDIO_RA_SHIFT) | 1045 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1046 (val & BFE_MDIO_DATA_DATA))); 1047 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1048 BFE_UNLOCK(sc); 1049 1050 return status; 1051} 1052 1053/* 1054 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1055 * twice 1056 */ 1057static int 1058bfe_setupphy(struct bfe_softc *sc) 1059{ 1060 u_int32_t val; 1061 BFE_LOCK(sc); 1062 1063 /* Enable activity LED */ 1064 bfe_readphy(sc, 26, &val); 1065 bfe_writephy(sc, 26, val & 0x7fff); 1066 bfe_readphy(sc, 26, &val); 1067 1068 /* Enable traffic meter LED mode */ 1069 bfe_readphy(sc, 27, &val); 1070 bfe_writephy(sc, 27, val | (1 << 6)); 1071 1072 BFE_UNLOCK(sc); 1073 return 0; 1074} 1075 1076static void 1077bfe_stats_update(struct bfe_softc *sc) 1078{ 1079 u_long reg; 1080 u_int32_t *val; 1081 1082 val = &sc->bfe_hwstats.tx_good_octets; 1083 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1084 *val++ += CSR_READ_4(sc, reg); 1085 } 1086 val = &sc->bfe_hwstats.rx_good_octets; 1087 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1088 *val++ += CSR_READ_4(sc, reg); 1089 } 1090} 1091 1092static void 1093bfe_txeof(struct bfe_softc *sc) 1094{ 1095 struct ifnet *ifp; 1096 int i, chipidx; 1097 1098 BFE_LOCK(sc); 1099 1100 ifp = &sc->arpcom.ac_if; 1101 1102 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1103 chipidx /= sizeof(struct bfe_desc); 1104 1105 i = sc->bfe_tx_cons; 1106 /* Go through the mbufs and free those that have been transmitted */ 1107 while(i != chipidx) { 1108 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1109 if(r->bfe_mbuf != NULL) { 1110 ifp->if_opackets++; 1111 m_freem(r->bfe_mbuf); 1112 r->bfe_mbuf = NULL; 1113 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1114 } 1115 sc->bfe_tx_cnt--; 1116 BFE_INC(i, BFE_TX_LIST_CNT); 1117 } 1118 1119 if(i != sc->bfe_tx_cons) { 1120 /* we freed up some mbufs */ 1121 sc->bfe_tx_cons = i; 1122 ifp->if_flags &= ~IFF_OACTIVE; 1123 } 1124 if(sc->bfe_tx_cnt == 0) 1125 ifp->if_timer = 0; 1126 else 1127 ifp->if_timer = 5; 1128 1129 BFE_UNLOCK(sc); 1130} 1131 1132/* Pass a received packet up the stack */ 1133static void 1134bfe_rxeof(struct bfe_softc *sc) 1135{ 1136 struct mbuf *m; 1137 struct ifnet *ifp; 1138 struct bfe_rxheader *rxheader; 1139 struct bfe_data *r; 1140 int cons; 1141 u_int32_t status, current, len, flags; 1142 1143 BFE_LOCK(sc); 1144 cons = sc->bfe_rx_cons; 1145 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1146 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1147 1148 ifp = &sc->arpcom.ac_if; 1149 1150 while(current != cons) { 1151 r = &sc->bfe_rx_ring[cons]; 1152 m = r->bfe_mbuf; 1153 rxheader = mtod(m, struct bfe_rxheader*); 1154 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1155 len = rxheader->len; 1156 r->bfe_mbuf = NULL; 1157 1158 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1159 flags = rxheader->flags; 1160 1161 len -= ETHER_CRC_LEN; 1162 1163 /* flag an error and try again */ 1164 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1165 ifp->if_ierrors++; 1166 if (flags & BFE_RX_FLAG_SERR) 1167 ifp->if_collisions++; 1168 bfe_list_newbuf(sc, cons, m); 1169 BFE_INC(cons, BFE_RX_LIST_CNT); 1170 continue; 1171 } 1172 1173 /* Go past the rx header */ 1174 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1175 m_adj(m, BFE_RX_OFFSET); 1176 m->m_len = m->m_pkthdr.len = len; 1177 } else { 1178 bfe_list_newbuf(sc, cons, m); 1179 ifp->if_ierrors++; 1180 BFE_INC(cons, BFE_RX_LIST_CNT); 1181 continue; 1182 } 1183 1184 ifp->if_ipackets++; 1185 m->m_pkthdr.rcvif = ifp; 1186 BFE_UNLOCK(sc); 1187 (*ifp->if_input)(ifp, m); 1188 BFE_LOCK(sc); 1189 1190 BFE_INC(cons, BFE_RX_LIST_CNT); 1191 } 1192 sc->bfe_rx_cons = cons; 1193 BFE_UNLOCK(sc); 1194} 1195 1196static void 1197bfe_intr(void *xsc) 1198{ 1199 struct bfe_softc *sc = xsc; 1200 struct ifnet *ifp; 1201 u_int32_t istat, imask, flag; 1202 1203 ifp = &sc->arpcom.ac_if; 1204 1205 BFE_LOCK(sc); 1206 1207 istat = CSR_READ_4(sc, BFE_ISTAT); 1208 imask = CSR_READ_4(sc, BFE_IMASK); 1209 1210 /* 1211 * Defer unsolicited interrupts - This is necessary because setting the 1212 * chips interrupt mask register to 0 doesn't actually stop the 1213 * interrupts 1214 */ 1215 istat &= imask; 1216 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1217 CSR_READ_4(sc, BFE_ISTAT); 1218 1219 /* not expecting this interrupt, disregard it */ 1220 if(istat == 0) { 1221 BFE_UNLOCK(sc); 1222 return; 1223 } 1224 1225 if(istat & BFE_ISTAT_ERRORS) { 1226 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1227 if(flag & BFE_STAT_EMASK) 1228 ifp->if_oerrors++; 1229 1230 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1231 if(flag & BFE_RX_FLAG_ERRORS) 1232 ifp->if_ierrors++; 1233 1234 ifp->if_flags &= ~IFF_RUNNING; 1235 bfe_init(sc); 1236 } 1237 1238 /* A packet was received */ 1239 if(istat & BFE_ISTAT_RX) 1240 bfe_rxeof(sc); 1241 1242 /* A packet was sent */ 1243 if(istat & BFE_ISTAT_TX) 1244 bfe_txeof(sc); 1245 1246 /* We have packets pending, fire them out */ 1247 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1248 bfe_start(ifp); 1249 1250 BFE_UNLOCK(sc); 1251} 1252 1253static int 1254bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1255{ 1256 struct bfe_desc *d = NULL; 1257 struct bfe_data *r = NULL; 1258 struct mbuf *m; 1259 u_int32_t frag, cur, cnt = 0; 1260 int chainlen = 0; 1261 1262 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1263 return(ENOBUFS); 1264 1265 /* 1266 * Count the number of frags in this chain to see if 1267 * we need to m_defrag. Since the descriptor list is shared 1268 * by all packets, we'll m_defrag long chains so that they 1269 * do not use up the entire list, even if they would fit. 1270 */ 1271 for(m = m_head; m != NULL; m = m->m_next) 1272 chainlen++; 1273 1274 1275 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1276 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1277 m = m_defrag(m_head, M_DONTWAIT); 1278 if (m == NULL) 1279 return(ENOBUFS); 1280 m_head = m; 1281 } 1282 1283 /* 1284 * Start packing the mbufs in this chain into 1285 * the fragment pointers. Stop when we run out 1286 * of fragments or hit the end of the mbuf chain. 1287 */ 1288 m = m_head; 1289 cur = frag = *txidx; 1290 cnt = 0; 1291 1292 for(m = m_head; m != NULL; m = m->m_next) { 1293 if(m->m_len != 0) { 1294 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1295 return(ENOBUFS); 1296 1297 d = &sc->bfe_tx_list[cur]; 1298 r = &sc->bfe_tx_ring[cur]; 1299 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1300 /* always intterupt on completion */ 1301 d->bfe_ctrl |= BFE_DESC_IOC; 1302 if(cnt == 0) 1303 /* Set start of frame */ 1304 d->bfe_ctrl |= BFE_DESC_SOF; 1305 if(cur == BFE_TX_LIST_CNT - 1) 1306 /* 1307 * Tell the chip to wrap to the start of 1308 * the descriptor list 1309 */ 1310 d->bfe_ctrl |= BFE_DESC_EOT; 1311 1312 bus_dmamap_load(sc->bfe_tag, 1313 r->bfe_map, mtod(m, void*), m->m_len, 1314 bfe_dma_map_desc, d, 0); 1315 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1316 BUS_DMASYNC_PREREAD); 1317 1318 frag = cur; 1319 BFE_INC(cur, BFE_TX_LIST_CNT); 1320 cnt++; 1321 } 1322 } 1323 1324 if (m != NULL) 1325 return(ENOBUFS); 1326 1327 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1328 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1329 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1330 1331 *txidx = cur; 1332 sc->bfe_tx_cnt += cnt; 1333 return (0); 1334} 1335 1336/* 1337 * Set up to transmit a packet 1338 */ 1339static void 1340bfe_start(struct ifnet *ifp) 1341{ 1342 struct bfe_softc *sc; 1343 struct mbuf *m_head = NULL; 1344 int idx; 1345 1346 sc = ifp->if_softc; 1347 idx = sc->bfe_tx_prod; 1348 1349 BFE_LOCK(sc); 1350 1351 /* 1352 * Not much point trying to send if the link is down 1353 * or we have nothing to send. 1354 */ 1355 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1356 BFE_UNLOCK(sc); 1357 return; 1358 } 1359 1360 if (ifp->if_flags & IFF_OACTIVE) { 1361 BFE_UNLOCK(sc); 1362 return; 1363 } 1364 1365 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1366 IF_DEQUEUE(&ifp->if_snd, m_head); 1367 if(m_head == NULL) 1368 break; 1369 1370 /* 1371 * Pack the data into the tx ring. If we dont have 1372 * enough room, let the chip drain the ring. 1373 */ 1374 if(bfe_encap(sc, m_head, &idx)) { 1375 IF_PREPEND(&ifp->if_snd, m_head); 1376 ifp->if_flags |= IFF_OACTIVE; 1377 break; 1378 } 1379 1380 /* 1381 * If there's a BPF listener, bounce a copy of this frame 1382 * to him. 1383 */ 1384 BPF_MTAP(ifp, m_head); 1385 } 1386 1387 sc->bfe_tx_prod = idx; 1388 /* Transmit - twice due to apparent hardware bug */ 1389 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1390 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1391 1392 /* 1393 * Set a timeout in case the chip goes out to lunch. 1394 */ 1395 ifp->if_timer = 5; 1396 BFE_UNLOCK(sc); 1397} 1398 1399static void 1400bfe_init(void *xsc) 1401{ 1402 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1403 struct ifnet *ifp = &sc->arpcom.ac_if; 1404 1405 BFE_LOCK(sc); 1406 1407 if (ifp->if_flags & IFF_RUNNING) { 1408 BFE_UNLOCK(sc); 1409 return; 1410 } 1411 1412 bfe_stop(sc); 1413 bfe_chip_reset(sc); 1414 1415 if (bfe_list_rx_init(sc) == ENOBUFS) { 1416 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1417 sc->bfe_unit); 1418 bfe_stop(sc); 1419 return; 1420 } 1421 1422 bfe_set_rx_mode(sc); 1423 1424 /* Enable the chip and core */ 1425 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1426 /* Enable interrupts */ 1427 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1428 1429 bfe_ifmedia_upd(ifp); 1430 ifp->if_flags |= IFF_RUNNING; 1431 ifp->if_flags &= ~IFF_OACTIVE; 1432 1433 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1434 BFE_UNLOCK(sc); 1435} 1436 1437/* 1438 * Set media options. 1439 */ 1440static int 1441bfe_ifmedia_upd(struct ifnet *ifp) 1442{ 1443 struct bfe_softc *sc; 1444 struct mii_data *mii; 1445 1446 sc = ifp->if_softc; 1447 1448 BFE_LOCK(sc); 1449 1450 mii = device_get_softc(sc->bfe_miibus); 1451 sc->bfe_link = 0; 1452 if (mii->mii_instance) { 1453 struct mii_softc *miisc; 1454 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1455 miisc = LIST_NEXT(miisc, mii_list)) 1456 mii_phy_reset(miisc); 1457 } 1458 mii_mediachg(mii); 1459 1460 BFE_UNLOCK(sc); 1461 return(0); 1462} 1463 1464/* 1465 * Report current media status. 1466 */ 1467static void 1468bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1469{ 1470 struct bfe_softc *sc = ifp->if_softc; 1471 struct mii_data *mii; 1472 1473 BFE_LOCK(sc); 1474 1475 mii = device_get_softc(sc->bfe_miibus); 1476 mii_pollstat(mii); 1477 ifmr->ifm_active = mii->mii_media_active; 1478 ifmr->ifm_status = mii->mii_media_status; 1479 1480 BFE_UNLOCK(sc); 1481} 1482 1483static int 1484bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1485{ 1486 struct bfe_softc *sc = ifp->if_softc; 1487 struct ifreq *ifr = (struct ifreq *) data; 1488 struct mii_data *mii; 1489 int error = 0; 1490 1491 BFE_LOCK(sc); 1492 1493 switch(command) { 1494 case SIOCSIFFLAGS: 1495 if(ifp->if_flags & IFF_UP) 1496 if(ifp->if_flags & IFF_RUNNING) 1497 bfe_set_rx_mode(sc); 1498 else 1499 bfe_init(sc); 1500 else if(ifp->if_flags & IFF_RUNNING) 1501 bfe_stop(sc); 1502 break; 1503 case SIOCADDMULTI: 1504 case SIOCDELMULTI: 1505 if(ifp->if_flags & IFF_RUNNING) 1506 bfe_set_rx_mode(sc); 1507 break; 1508 case SIOCGIFMEDIA: 1509 case SIOCSIFMEDIA: 1510 mii = device_get_softc(sc->bfe_miibus); 1511 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1512 command); 1513 break; 1514 default: 1515 error = ether_ioctl(ifp, command, data); 1516 break; 1517 } 1518 1519 BFE_UNLOCK(sc); 1520 return error; 1521} 1522 1523static void 1524bfe_watchdog(struct ifnet *ifp) 1525{ 1526 struct bfe_softc *sc; 1527 1528 sc = ifp->if_softc; 1529 1530 BFE_LOCK(sc); 1531 1532 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1533 1534 ifp->if_flags &= ~IFF_RUNNING; 1535 bfe_init(sc); 1536 1537 ifp->if_oerrors++; 1538 1539 BFE_UNLOCK(sc); 1540} 1541 1542static void 1543bfe_tick(void *xsc) 1544{ 1545 struct bfe_softc *sc = xsc; 1546 struct mii_data *mii; 1547 1548 if (sc == NULL) 1549 return; 1550 1551 BFE_LOCK(sc); 1552 1553 mii = device_get_softc(sc->bfe_miibus); 1554 1555 bfe_stats_update(sc); 1556 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1557 1558 if(sc->bfe_link) { 1559 BFE_UNLOCK(sc); 1560 return; 1561 } 1562 1563 mii_tick(mii); 1564 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1565 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1566 sc->bfe_link++; 1567 1568 BFE_UNLOCK(sc); 1569} 1570 1571/* 1572 * Stop the adapter and free any mbufs allocated to the 1573 * RX and TX lists. 1574 */ 1575static void 1576bfe_stop(struct bfe_softc *sc) 1577{ 1578 struct ifnet *ifp; 1579 1580 BFE_LOCK(sc); 1581 1582 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1583 1584 ifp = &sc->arpcom.ac_if; 1585 1586 bfe_chip_halt(sc); 1587 bfe_tx_ring_free(sc); 1588 bfe_rx_ring_free(sc); 1589 1590 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1591 1592 BFE_UNLOCK(sc); 1593} 1594