if_bfe.c revision 180954
1139749Simp/*- 2119917Swpaul * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3119917Swpaul * and Duncan Barclay<dmlb@dmlb.org> 4139749Simp * 5119917Swpaul * Redistribution and use in source and binary forms, with or without 6119917Swpaul * modification, are permitted provided that the following conditions 7119917Swpaul * are met: 8119917Swpaul * 1. Redistributions of source code must retain the above copyright 9119917Swpaul * notice, this list of conditions and the following disclaimer. 10119917Swpaul * 2. Redistributions in binary form must reproduce the above copyright 11119917Swpaul * notice, this list of conditions and the following disclaimer in the 12119917Swpaul * documentation and/or other materials provided with the distribution. 13119917Swpaul * 14119917Swpaul * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15119917Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16119917Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17119917Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18119917Swpaul * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19119917Swpaul * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20119917Swpaul * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21119917Swpaul * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22119917Swpaul * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23119917Swpaul * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24119917Swpaul * SUCH DAMAGE. 25119917Swpaul */ 26119917Swpaul 27119917Swpaul 28119917Swpaul#include <sys/cdefs.h> 29119917Swpaul__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 180954 2008-07-29 09:02:00Z yongari $"); 30119917Swpaul 31119917Swpaul#include <sys/param.h> 32119917Swpaul#include <sys/systm.h> 33119917Swpaul#include <sys/sockio.h> 34119917Swpaul#include <sys/mbuf.h> 35119917Swpaul#include <sys/malloc.h> 36119917Swpaul#include <sys/kernel.h> 37129879Sphk#include <sys/module.h> 38119917Swpaul#include <sys/socket.h> 39119917Swpaul#include <sys/queue.h> 40119917Swpaul 41119917Swpaul#include <net/if.h> 42119917Swpaul#include <net/if_arp.h> 43119917Swpaul#include <net/ethernet.h> 44119917Swpaul#include <net/if_dl.h> 45119917Swpaul#include <net/if_media.h> 46119917Swpaul 47119917Swpaul#include <net/bpf.h> 48119917Swpaul 49119917Swpaul#include <net/if_types.h> 50119917Swpaul#include <net/if_vlan_var.h> 51119917Swpaul 52119917Swpaul#include <netinet/in_systm.h> 53119917Swpaul#include <netinet/in.h> 54119917Swpaul#include <netinet/ip.h> 55119917Swpaul 56119917Swpaul#include <machine/bus.h> 57119917Swpaul#include <machine/resource.h> 58119917Swpaul#include <sys/bus.h> 59119917Swpaul#include <sys/rman.h> 60119917Swpaul 61119917Swpaul#include <dev/mii/mii.h> 62119917Swpaul#include <dev/mii/miivar.h> 63119917Swpaul#include "miidevs.h" 64119917Swpaul 65119917Swpaul#include <dev/pci/pcireg.h> 66119917Swpaul#include <dev/pci/pcivar.h> 67119917Swpaul 68119917Swpaul#include <dev/bfe/if_bfereg.h> 69119917Swpaul 70119917SwpaulMODULE_DEPEND(bfe, pci, 1, 1, 1); 71119917SwpaulMODULE_DEPEND(bfe, ether, 1, 1, 1); 72119917SwpaulMODULE_DEPEND(bfe, miibus, 1, 1, 1); 73119917Swpaul 74151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 75119917Swpaul#include "miibus_if.h" 76119917Swpaul 77119917Swpaul#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 78119917Swpaul 79119917Swpaulstatic struct bfe_type bfe_devs[] = { 80119917Swpaul { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 81119917Swpaul "Broadcom BCM4401 Fast Ethernet" }, 82134590Sdes { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 83134590Sdes "Broadcom BCM4401-B0 Fast Ethernet" }, 84119917Swpaul { 0, 0, NULL } 85119917Swpaul}; 86119917Swpaul 87119917Swpaulstatic int bfe_probe (device_t); 88119917Swpaulstatic int bfe_attach (device_t); 89119917Swpaulstatic int bfe_detach (device_t); 90164456Sjhbstatic int bfe_suspend (device_t); 91164456Sjhbstatic int bfe_resume (device_t); 92119917Swpaulstatic void bfe_release_resources (struct bfe_softc *); 93119917Swpaulstatic void bfe_intr (void *); 94119917Swpaulstatic void bfe_start (struct ifnet *); 95136804Smtmstatic void bfe_start_locked (struct ifnet *); 96119917Swpaulstatic int bfe_ioctl (struct ifnet *, u_long, caddr_t); 97119917Swpaulstatic void bfe_init (void *); 98136804Smtmstatic void bfe_init_locked (void *); 99119917Swpaulstatic void bfe_stop (struct bfe_softc *); 100175787Syongaristatic void bfe_watchdog (struct bfe_softc *); 101173839Syongaristatic int bfe_shutdown (device_t); 102119917Swpaulstatic void bfe_tick (void *); 103119917Swpaulstatic void bfe_txeof (struct bfe_softc *); 104119917Swpaulstatic void bfe_rxeof (struct bfe_softc *); 105119917Swpaulstatic void bfe_set_rx_mode (struct bfe_softc *); 106119917Swpaulstatic int bfe_list_rx_init (struct bfe_softc *); 107119917Swpaulstatic int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 108119917Swpaulstatic void bfe_rx_ring_free (struct bfe_softc *); 109119917Swpaul 110119917Swpaulstatic void bfe_pci_setup (struct bfe_softc *, u_int32_t); 111119917Swpaulstatic int bfe_ifmedia_upd (struct ifnet *); 112119917Swpaulstatic void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 113119917Swpaulstatic int bfe_miibus_readreg (device_t, int, int); 114119917Swpaulstatic int bfe_miibus_writereg (device_t, int, int, int); 115119917Swpaulstatic void bfe_miibus_statchg (device_t); 116133282Sdesstatic int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 117119917Swpaul u_long, const int); 118119917Swpaulstatic void bfe_get_config (struct bfe_softc *sc); 119119917Swpaulstatic void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 120119917Swpaulstatic void bfe_stats_update (struct bfe_softc *); 121119917Swpaulstatic void bfe_clear_stats (struct bfe_softc *); 122119917Swpaulstatic int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 123119917Swpaulstatic int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 124119917Swpaulstatic int bfe_resetphy (struct bfe_softc *); 125119917Swpaulstatic int bfe_setupphy (struct bfe_softc *); 126119917Swpaulstatic void bfe_chip_reset (struct bfe_softc *); 127119917Swpaulstatic void bfe_chip_halt (struct bfe_softc *); 128119917Swpaulstatic void bfe_core_reset (struct bfe_softc *); 129119917Swpaulstatic void bfe_core_disable (struct bfe_softc *); 130119917Swpaulstatic int bfe_dma_alloc (device_t); 131119917Swpaulstatic void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 132119917Swpaulstatic void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 133119917Swpaulstatic void bfe_cam_write (struct bfe_softc *, u_char *, int); 134119917Swpaul 135119917Swpaulstatic device_method_t bfe_methods[] = { 136119917Swpaul /* Device interface */ 137119917Swpaul DEVMETHOD(device_probe, bfe_probe), 138119917Swpaul DEVMETHOD(device_attach, bfe_attach), 139119917Swpaul DEVMETHOD(device_detach, bfe_detach), 140119917Swpaul DEVMETHOD(device_shutdown, bfe_shutdown), 141164456Sjhb DEVMETHOD(device_suspend, bfe_suspend), 142164456Sjhb DEVMETHOD(device_resume, bfe_resume), 143119917Swpaul 144119917Swpaul /* bus interface */ 145119917Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 146119917Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147119917Swpaul 148119917Swpaul /* MII interface */ 149119917Swpaul DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 150119917Swpaul DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 151119917Swpaul DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 152119917Swpaul 153119917Swpaul { 0, 0 } 154119917Swpaul}; 155119917Swpaul 156119917Swpaulstatic driver_t bfe_driver = { 157119917Swpaul "bfe", 158119917Swpaul bfe_methods, 159119917Swpaul sizeof(struct bfe_softc) 160119917Swpaul}; 161119917Swpaul 162119917Swpaulstatic devclass_t bfe_devclass; 163119917Swpaul 164119917SwpaulDRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 165119917SwpaulDRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 166119917Swpaul 167119917Swpaul/* 168133282Sdes * Probe for a Broadcom 4401 chip. 169119917Swpaul */ 170119917Swpaulstatic int 171119917Swpaulbfe_probe(device_t dev) 172119917Swpaul{ 173119917Swpaul struct bfe_type *t; 174180952Syongari uint16_t vendor, devid; 175119917Swpaul 176119917Swpaul t = bfe_devs; 177180952Syongari vendor = pci_get_vendor(dev); 178180952Syongari devid = pci_get_device(dev); 179119917Swpaul 180180954Syongari while (t->bfe_name != NULL) { 181180952Syongari if (vendor == t->bfe_vid && devid == t->bfe_did) { 182119917Swpaul device_set_desc_copy(dev, t->bfe_name); 183143163Simp return (BUS_PROBE_DEFAULT); 184119917Swpaul } 185119917Swpaul t++; 186119917Swpaul } 187119917Swpaul 188133282Sdes return (ENXIO); 189119917Swpaul} 190119917Swpaul 191119917Swpaulstatic int 192119917Swpaulbfe_dma_alloc(device_t dev) 193119917Swpaul{ 194119917Swpaul struct bfe_softc *sc; 195119917Swpaul int error, i; 196119917Swpaul 197119917Swpaul sc = device_get_softc(dev); 198119917Swpaul 199158075Sscottl /* 200158075Sscottl * parent tag. Apparently the chip cannot handle any DMA address 201158075Sscottl * greater than 1GB. 202158075Sscottl */ 203119917Swpaul error = bus_dma_tag_create(NULL, /* parent */ 204159013Ssilby 4096, 0, /* alignment, boundary */ 205158103Ssilby 0x3FFFFFFF, /* lowaddr */ 206158075Sscottl BUS_SPACE_MAXADDR, /* highaddr */ 207119917Swpaul NULL, NULL, /* filter, filterarg */ 208119917Swpaul MAXBSIZE, /* maxsize */ 209119917Swpaul BUS_SPACE_UNRESTRICTED, /* num of segments */ 210119917Swpaul BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 211159021Ssilby 0, /* flags */ 212119917Swpaul NULL, NULL, /* lockfunc, lockarg */ 213119917Swpaul &sc->bfe_parent_tag); 214119917Swpaul 215119917Swpaul /* tag for TX ring */ 216126470Sjulian error = bus_dma_tag_create(sc->bfe_parent_tag, 217159013Ssilby 4096, 0, 218126470Sjulian BUS_SPACE_MAXADDR, 219133282Sdes BUS_SPACE_MAXADDR, 220126470Sjulian NULL, NULL, 221126470Sjulian BFE_TX_LIST_SIZE, 222126470Sjulian 1, 223126470Sjulian BUS_SPACE_MAXSIZE_32BIT, 224159021Ssilby 0, 225126470Sjulian NULL, NULL, 226126470Sjulian &sc->bfe_tx_tag); 227119917Swpaul 228119917Swpaul if (error) { 229119917Swpaul device_printf(dev, "could not allocate dma tag\n"); 230133282Sdes return (ENOMEM); 231119917Swpaul } 232119917Swpaul 233119917Swpaul /* tag for RX ring */ 234126470Sjulian error = bus_dma_tag_create(sc->bfe_parent_tag, 235159013Ssilby 4096, 0, 236126470Sjulian BUS_SPACE_MAXADDR, 237126470Sjulian BUS_SPACE_MAXADDR, 238126470Sjulian NULL, NULL, 239126470Sjulian BFE_RX_LIST_SIZE, 240126470Sjulian 1, 241126470Sjulian BUS_SPACE_MAXSIZE_32BIT, 242159021Ssilby 0, 243126470Sjulian NULL, NULL, 244126470Sjulian &sc->bfe_rx_tag); 245119917Swpaul 246119917Swpaul if (error) { 247119917Swpaul device_printf(dev, "could not allocate dma tag\n"); 248133282Sdes return (ENOMEM); 249119917Swpaul } 250119917Swpaul 251119917Swpaul /* tag for mbufs */ 252126470Sjulian error = bus_dma_tag_create(sc->bfe_parent_tag, 253126470Sjulian ETHER_ALIGN, 0, 254126470Sjulian BUS_SPACE_MAXADDR, 255126470Sjulian BUS_SPACE_MAXADDR, 256126470Sjulian NULL, NULL, 257126470Sjulian MCLBYTES, 258126470Sjulian 1, 259126470Sjulian BUS_SPACE_MAXSIZE_32BIT, 260158075Sscottl BUS_DMA_ALLOCNOW, 261126470Sjulian NULL, NULL, 262126470Sjulian &sc->bfe_tag); 263119917Swpaul 264119917Swpaul if (error) { 265119917Swpaul device_printf(dev, "could not allocate dma tag\n"); 266133282Sdes return (ENOMEM); 267119917Swpaul } 268119917Swpaul 269119917Swpaul /* pre allocate dmamaps for RX list */ 270119917Swpaul for (i = 0; i < BFE_RX_LIST_CNT; i++) { 271126470Sjulian error = bus_dmamap_create(sc->bfe_tag, 0, 272126470Sjulian &sc->bfe_rx_ring[i].bfe_map); 273119917Swpaul if (error) { 274119917Swpaul device_printf(dev, "cannot create DMA map for RX\n"); 275133282Sdes return (ENOMEM); 276119917Swpaul } 277119917Swpaul } 278119917Swpaul 279119917Swpaul /* pre allocate dmamaps for TX list */ 280119917Swpaul for (i = 0; i < BFE_TX_LIST_CNT; i++) { 281126470Sjulian error = bus_dmamap_create(sc->bfe_tag, 0, 282126470Sjulian &sc->bfe_tx_ring[i].bfe_map); 283119917Swpaul if (error) { 284119917Swpaul device_printf(dev, "cannot create DMA map for TX\n"); 285133282Sdes return (ENOMEM); 286119917Swpaul } 287119917Swpaul } 288119917Swpaul 289119917Swpaul /* Alloc dma for rx ring */ 290119917Swpaul error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 291119917Swpaul BUS_DMA_NOWAIT, &sc->bfe_rx_map); 292119917Swpaul 293180954Syongari if (error) 294133282Sdes return (ENOMEM); 295119917Swpaul 296119917Swpaul bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 297119917Swpaul error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 298119917Swpaul sc->bfe_rx_list, sizeof(struct bfe_desc), 299158285Ssilby bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_NOWAIT); 300119917Swpaul 301180954Syongari if (error) 302133282Sdes return (ENOMEM); 303119917Swpaul 304158102Ssilby bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 305119917Swpaul 306133282Sdes error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 307119917Swpaul BUS_DMA_NOWAIT, &sc->bfe_tx_map); 308133282Sdes if (error) 309133282Sdes return (ENOMEM); 310119917Swpaul 311119917Swpaul 312133282Sdes error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 313133282Sdes sc->bfe_tx_list, sizeof(struct bfe_desc), 314158285Ssilby bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_NOWAIT); 315180954Syongari if (error) 316133282Sdes return (ENOMEM); 317119917Swpaul 318119917Swpaul bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 319158102Ssilby bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 320119917Swpaul 321133282Sdes return (0); 322119917Swpaul} 323119917Swpaul 324119917Swpaulstatic int 325119917Swpaulbfe_attach(device_t dev) 326119917Swpaul{ 327147256Sbrooks struct ifnet *ifp = NULL; 328119917Swpaul struct bfe_softc *sc; 329180950Syongari int error = 0, rid; 330119917Swpaul 331119917Swpaul sc = device_get_softc(dev); 332119917Swpaul mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 333136804Smtm MTX_DEF); 334175787Syongari callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 335119917Swpaul 336119917Swpaul sc->bfe_dev = dev; 337119917Swpaul 338119917Swpaul /* 339119917Swpaul * Map control/status registers. 340119917Swpaul */ 341119917Swpaul pci_enable_busmaster(dev); 342119917Swpaul 343119917Swpaul rid = BFE_PCI_MEMLO; 344127135Snjl sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 345119917Swpaul RF_ACTIVE); 346119917Swpaul if (sc->bfe_res == NULL) { 347180950Syongari device_printf(dev, "couldn't map memory\n"); 348119917Swpaul error = ENXIO; 349119917Swpaul goto fail; 350119917Swpaul } 351119917Swpaul 352119917Swpaul sc->bfe_btag = rman_get_bustag(sc->bfe_res); 353119917Swpaul sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 354119917Swpaul sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 355119917Swpaul 356119917Swpaul /* Allocate interrupt */ 357119917Swpaul rid = 0; 358119917Swpaul 359127135Snjl sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 360119917Swpaul RF_SHAREABLE | RF_ACTIVE); 361119917Swpaul if (sc->bfe_irq == NULL) { 362180950Syongari device_printf(dev, "couldn't map interrupt\n"); 363119917Swpaul error = ENXIO; 364119917Swpaul goto fail; 365119917Swpaul } 366119917Swpaul 367119917Swpaul if (bfe_dma_alloc(dev)) { 368180950Syongari device_printf(dev, "failed to allocate DMA resources\n"); 369119917Swpaul error = ENXIO; 370119917Swpaul goto fail; 371119917Swpaul } 372119917Swpaul 373119917Swpaul /* Set up ifnet structure */ 374147256Sbrooks ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 375147256Sbrooks if (ifp == NULL) { 376180950Syongari device_printf(dev, "failed to if_alloc()\n"); 377147256Sbrooks error = ENOSPC; 378147256Sbrooks goto fail; 379147256Sbrooks } 380119917Swpaul ifp->if_softc = sc; 381121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 382119917Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 383119917Swpaul ifp->if_ioctl = bfe_ioctl; 384119917Swpaul ifp->if_start = bfe_start; 385119917Swpaul ifp->if_init = bfe_init; 386119917Swpaul ifp->if_mtu = ETHERMTU; 387131455Smlaier IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 388131455Smlaier ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 389131455Smlaier IFQ_SET_READY(&ifp->if_snd); 390119917Swpaul 391119917Swpaul bfe_get_config(sc); 392119917Swpaul 393119917Swpaul /* Reset the chip and turn on the PHY */ 394136804Smtm BFE_LOCK(sc); 395119917Swpaul bfe_chip_reset(sc); 396136804Smtm BFE_UNLOCK(sc); 397119917Swpaul 398119917Swpaul if (mii_phy_probe(dev, &sc->bfe_miibus, 399119917Swpaul bfe_ifmedia_upd, bfe_ifmedia_sts)) { 400180950Syongari device_printf(dev, "MII without any PHY!\n"); 401119917Swpaul error = ENXIO; 402119917Swpaul goto fail; 403119917Swpaul } 404119917Swpaul 405147256Sbrooks ether_ifattach(ifp, sc->bfe_enaddr); 406119917Swpaul 407119917Swpaul /* 408129708Sdes * Tell the upper layer(s) we support long frames. 409129708Sdes */ 410129708Sdes ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 411129708Sdes ifp->if_capabilities |= IFCAP_VLAN_MTU; 412129709Sdes ifp->if_capenable |= IFCAP_VLAN_MTU; 413129708Sdes 414129708Sdes /* 415119917Swpaul * Hook interrupt last to avoid having to lock softc 416119917Swpaul */ 417136804Smtm error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 418166901Spiso NULL, bfe_intr, sc, &sc->bfe_intrhand); 419119917Swpaul 420119917Swpaul if (error) { 421180950Syongari device_printf(dev, "couldn't set up irq\n"); 422119917Swpaul goto fail; 423119917Swpaul } 424119917Swpaulfail: 425150215Sru if (error) 426119917Swpaul bfe_release_resources(sc); 427133282Sdes return (error); 428119917Swpaul} 429119917Swpaul 430119917Swpaulstatic int 431119917Swpaulbfe_detach(device_t dev) 432119917Swpaul{ 433119917Swpaul struct bfe_softc *sc; 434119917Swpaul struct ifnet *ifp; 435119917Swpaul 436119917Swpaul sc = device_get_softc(dev); 437119917Swpaul 438119917Swpaul KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 439119917Swpaul 440147256Sbrooks ifp = sc->bfe_ifp; 441119917Swpaul 442119917Swpaul if (device_is_attached(dev)) { 443175787Syongari BFE_LOCK(sc); 444119917Swpaul bfe_stop(sc); 445175787Syongari BFE_UNLOCK(sc); 446175787Syongari callout_drain(&sc->bfe_stat_co); 447175787Syongari if (ifp != NULL) 448175787Syongari ether_ifdetach(ifp); 449119917Swpaul } 450119917Swpaul 451119917Swpaul bfe_chip_reset(sc); 452119917Swpaul 453119917Swpaul bus_generic_detach(dev); 454180954Syongari if (sc->bfe_miibus != NULL) 455119917Swpaul device_delete_child(dev, sc->bfe_miibus); 456119917Swpaul 457119917Swpaul bfe_release_resources(sc); 458119917Swpaul mtx_destroy(&sc->bfe_mtx); 459119917Swpaul 460133282Sdes return (0); 461119917Swpaul} 462119917Swpaul 463119917Swpaul/* 464119917Swpaul * Stop all chip I/O so that the kernel's probe routines don't 465119917Swpaul * get confused by errant DMAs when rebooting. 466119917Swpaul */ 467173839Syongaristatic int 468119917Swpaulbfe_shutdown(device_t dev) 469119917Swpaul{ 470119917Swpaul struct bfe_softc *sc; 471119917Swpaul 472119917Swpaul sc = device_get_softc(dev); 473119917Swpaul BFE_LOCK(sc); 474133282Sdes bfe_stop(sc); 475119917Swpaul 476119917Swpaul BFE_UNLOCK(sc); 477173839Syongari 478173839Syongari return (0); 479119917Swpaul} 480119917Swpaul 481119917Swpaulstatic int 482164456Sjhbbfe_suspend(device_t dev) 483164456Sjhb{ 484164456Sjhb struct bfe_softc *sc; 485164456Sjhb 486164456Sjhb sc = device_get_softc(dev); 487164456Sjhb BFE_LOCK(sc); 488164456Sjhb bfe_stop(sc); 489164456Sjhb BFE_UNLOCK(sc); 490164456Sjhb 491164456Sjhb return (0); 492164456Sjhb} 493164456Sjhb 494164456Sjhbstatic int 495164456Sjhbbfe_resume(device_t dev) 496164456Sjhb{ 497164456Sjhb struct bfe_softc *sc; 498164456Sjhb struct ifnet *ifp; 499164456Sjhb 500164456Sjhb sc = device_get_softc(dev); 501164456Sjhb ifp = sc->bfe_ifp; 502164456Sjhb BFE_LOCK(sc); 503164456Sjhb bfe_chip_reset(sc); 504164456Sjhb if (ifp->if_flags & IFF_UP) { 505164456Sjhb bfe_init_locked(sc); 506164456Sjhb if (ifp->if_drv_flags & IFF_DRV_RUNNING && 507164456Sjhb !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 508164456Sjhb bfe_start_locked(ifp); 509164456Sjhb } 510164456Sjhb BFE_UNLOCK(sc); 511164456Sjhb 512164456Sjhb return (0); 513164456Sjhb} 514164456Sjhb 515164456Sjhbstatic int 516119917Swpaulbfe_miibus_readreg(device_t dev, int phy, int reg) 517119917Swpaul{ 518119917Swpaul struct bfe_softc *sc; 519119917Swpaul u_int32_t ret; 520119917Swpaul 521119917Swpaul sc = device_get_softc(dev); 522180954Syongari if (phy != sc->bfe_phyaddr) 523133282Sdes return (0); 524119917Swpaul bfe_readphy(sc, reg, &ret); 525119917Swpaul 526133282Sdes return (ret); 527119917Swpaul} 528119917Swpaul 529119917Swpaulstatic int 530119917Swpaulbfe_miibus_writereg(device_t dev, int phy, int reg, int val) 531119917Swpaul{ 532119917Swpaul struct bfe_softc *sc; 533119917Swpaul 534119917Swpaul sc = device_get_softc(dev); 535180954Syongari if (phy != sc->bfe_phyaddr) 536133282Sdes return (0); 537133282Sdes bfe_writephy(sc, reg, val); 538119917Swpaul 539133282Sdes return (0); 540119917Swpaul} 541119917Swpaul 542119917Swpaulstatic void 543119917Swpaulbfe_miibus_statchg(device_t dev) 544119917Swpaul{ 545175787Syongari struct bfe_softc *sc; 546175787Syongari struct mii_data *mii; 547175787Syongari u_int32_t val, flow; 548175787Syongari 549175787Syongari sc = device_get_softc(dev); 550175787Syongari mii = device_get_softc(sc->bfe_miibus); 551175787Syongari 552175787Syongari if ((mii->mii_media_status & IFM_ACTIVE) != 0) { 553175787Syongari if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 554175787Syongari sc->bfe_link = 1; 555175787Syongari } else 556175787Syongari sc->bfe_link = 0; 557175787Syongari 558175787Syongari /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 559175787Syongari val = CSR_READ_4(sc, BFE_TX_CTRL); 560175787Syongari val &= ~BFE_TX_DUPLEX; 561175787Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 562175787Syongari val |= BFE_TX_DUPLEX; 563175787Syongari flow = 0; 564175787Syongari#ifdef notyet 565175787Syongari flow = CSR_READ_4(sc, BFE_RXCONF); 566175787Syongari flow &= ~BFE_RXCONF_FLOW; 567175787Syongari if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 568175787Syongari IFM_ETH_RXPAUSE) != 0) 569175787Syongari flow |= BFE_RXCONF_FLOW; 570175787Syongari CSR_WRITE_4(sc, BFE_RXCONF, flow); 571175787Syongari /* 572175787Syongari * It seems that the hardware has Tx pause issues 573175787Syongari * so enable only Rx pause. 574175787Syongari */ 575175787Syongari flow = CSR_READ_4(sc, BFE_MAC_FLOW); 576175787Syongari flow &= ~BFE_FLOW_PAUSE_ENAB; 577175787Syongari CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 578175787Syongari#endif 579175787Syongari } 580175787Syongari CSR_WRITE_4(sc, BFE_TX_CTRL, val); 581119917Swpaul} 582119917Swpaul 583119917Swpaulstatic void 584119917Swpaulbfe_tx_ring_free(struct bfe_softc *sc) 585119917Swpaul{ 586126470Sjulian int i; 587133282Sdes 588126470Sjulian for(i = 0; i < BFE_TX_LIST_CNT; i++) { 589180954Syongari if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 590126470Sjulian m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 591126470Sjulian sc->bfe_tx_ring[i].bfe_mbuf = NULL; 592126470Sjulian bus_dmamap_unload(sc->bfe_tag, 593126470Sjulian sc->bfe_tx_ring[i].bfe_map); 594126470Sjulian } 595126470Sjulian } 596126470Sjulian bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 597158102Ssilby bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 598119917Swpaul} 599119917Swpaul 600119917Swpaulstatic void 601119917Swpaulbfe_rx_ring_free(struct bfe_softc *sc) 602119917Swpaul{ 603119917Swpaul int i; 604119917Swpaul 605119917Swpaul for (i = 0; i < BFE_RX_LIST_CNT; i++) { 606119917Swpaul if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 607119917Swpaul m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 608119917Swpaul sc->bfe_rx_ring[i].bfe_mbuf = NULL; 609119917Swpaul bus_dmamap_unload(sc->bfe_tag, 610119917Swpaul sc->bfe_rx_ring[i].bfe_map); 611119917Swpaul } 612119917Swpaul } 613119917Swpaul bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 614158102Ssilby bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 615119917Swpaul} 616119917Swpaul 617133282Sdesstatic int 618119917Swpaulbfe_list_rx_init(struct bfe_softc *sc) 619119917Swpaul{ 620119917Swpaul int i; 621119917Swpaul 622119917Swpaul for(i = 0; i < BFE_RX_LIST_CNT; i++) { 623180954Syongari if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 624133282Sdes return (ENOBUFS); 625119917Swpaul } 626119917Swpaul 627158102Ssilby bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 628119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 629119917Swpaul 630119917Swpaul sc->bfe_rx_cons = 0; 631119917Swpaul 632133282Sdes return (0); 633119917Swpaul} 634119917Swpaul 635119917Swpaulstatic int 636119917Swpaulbfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 637119917Swpaul{ 638119917Swpaul struct bfe_rxheader *rx_header; 639119917Swpaul struct bfe_desc *d; 640119917Swpaul struct bfe_data *r; 641119917Swpaul u_int32_t ctrl; 642178687Syongari int allocated, error; 643119917Swpaul 644119917Swpaul if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 645133282Sdes return (EINVAL); 646119917Swpaul 647178687Syongari allocated = 0; 648180954Syongari if (m == NULL) { 649119917Swpaul m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 650180954Syongari if (m == NULL) 651133282Sdes return (ENOBUFS); 652119917Swpaul m->m_len = m->m_pkthdr.len = MCLBYTES; 653178687Syongari allocated++; 654119917Swpaul } 655119917Swpaul else 656119917Swpaul m->m_data = m->m_ext.ext_buf; 657119917Swpaul 658119917Swpaul rx_header = mtod(m, struct bfe_rxheader *); 659119917Swpaul rx_header->len = 0; 660119917Swpaul rx_header->flags = 0; 661119917Swpaul 662119917Swpaul /* Map the mbuf into DMA */ 663119917Swpaul sc->bfe_rx_cnt = c; 664119917Swpaul d = &sc->bfe_rx_list[c]; 665119917Swpaul r = &sc->bfe_rx_ring[c]; 666158285Ssilby error = bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 667158285Ssilby MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 668178687Syongari if (error != 0) { 669178687Syongari if (allocated != 0) 670178687Syongari m_free(m); 671178687Syongari if (error != ENOMEM) 672180950Syongari device_printf(sc->bfe_dev, 673180950Syongari "failed to map RX buffer, error %d\n", error); 674178687Syongari return (ENOBUFS); 675178687Syongari } 676158102Ssilby bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 677119917Swpaul 678119917Swpaul ctrl = ETHER_MAX_LEN + 32; 679119917Swpaul 680180954Syongari if (c == BFE_RX_LIST_CNT - 1) 681119917Swpaul ctrl |= BFE_DESC_EOT; 682119917Swpaul 683119917Swpaul d->bfe_ctrl = ctrl; 684119917Swpaul r->bfe_mbuf = m; 685158102Ssilby bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE); 686133282Sdes return (0); 687119917Swpaul} 688119917Swpaul 689119917Swpaulstatic void 690119917Swpaulbfe_get_config(struct bfe_softc *sc) 691119917Swpaul{ 692119917Swpaul u_int8_t eeprom[128]; 693119917Swpaul 694119917Swpaul bfe_read_eeprom(sc, eeprom); 695119917Swpaul 696147256Sbrooks sc->bfe_enaddr[0] = eeprom[79]; 697147256Sbrooks sc->bfe_enaddr[1] = eeprom[78]; 698147256Sbrooks sc->bfe_enaddr[2] = eeprom[81]; 699147256Sbrooks sc->bfe_enaddr[3] = eeprom[80]; 700147256Sbrooks sc->bfe_enaddr[4] = eeprom[83]; 701147256Sbrooks sc->bfe_enaddr[5] = eeprom[82]; 702119917Swpaul 703119917Swpaul sc->bfe_phyaddr = eeprom[90] & 0x1f; 704119917Swpaul sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 705119917Swpaul 706133282Sdes sc->bfe_core_unit = 0; 707119917Swpaul sc->bfe_dma_offset = BFE_PCI_DMA; 708119917Swpaul} 709119917Swpaul 710119917Swpaulstatic void 711119917Swpaulbfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 712119917Swpaul{ 713119917Swpaul u_int32_t bar_orig, pci_rev, val; 714119917Swpaul 715119917Swpaul bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 716119917Swpaul pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 717119917Swpaul pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 718119917Swpaul 719119917Swpaul val = CSR_READ_4(sc, BFE_SBINTVEC); 720119917Swpaul val |= cores; 721119917Swpaul CSR_WRITE_4(sc, BFE_SBINTVEC, val); 722119917Swpaul 723119917Swpaul val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 724119917Swpaul val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 725119917Swpaul CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 726119917Swpaul 727119917Swpaul pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 728119917Swpaul} 729119917Swpaul 730133282Sdesstatic void 731119917Swpaulbfe_clear_stats(struct bfe_softc *sc) 732119917Swpaul{ 733119917Swpaul u_long reg; 734119917Swpaul 735136804Smtm BFE_LOCK_ASSERT(sc); 736119917Swpaul 737119917Swpaul CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 738119917Swpaul for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 739119917Swpaul CSR_READ_4(sc, reg); 740119917Swpaul for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 741119917Swpaul CSR_READ_4(sc, reg); 742119917Swpaul} 743119917Swpaul 744133282Sdesstatic int 745119917Swpaulbfe_resetphy(struct bfe_softc *sc) 746119917Swpaul{ 747119917Swpaul u_int32_t val; 748119917Swpaul 749119917Swpaul bfe_writephy(sc, 0, BMCR_RESET); 750119917Swpaul DELAY(100); 751119917Swpaul bfe_readphy(sc, 0, &val); 752119917Swpaul if (val & BMCR_RESET) { 753180950Syongari device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 754133282Sdes return (ENXIO); 755119917Swpaul } 756133282Sdes return (0); 757119917Swpaul} 758119917Swpaul 759119917Swpaulstatic void 760119917Swpaulbfe_chip_halt(struct bfe_softc *sc) 761119917Swpaul{ 762136804Smtm BFE_LOCK_ASSERT(sc); 763119917Swpaul /* disable interrupts - not that it actually does..*/ 764119917Swpaul CSR_WRITE_4(sc, BFE_IMASK, 0); 765119917Swpaul CSR_READ_4(sc, BFE_IMASK); 766119917Swpaul 767119917Swpaul CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 768119917Swpaul bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 769119917Swpaul 770119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 771119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 772119917Swpaul DELAY(10); 773119917Swpaul} 774119917Swpaul 775119917Swpaulstatic void 776119917Swpaulbfe_chip_reset(struct bfe_softc *sc) 777119917Swpaul{ 778133282Sdes u_int32_t val; 779119917Swpaul 780136804Smtm BFE_LOCK_ASSERT(sc); 781119917Swpaul 782119917Swpaul /* Set the interrupt vector for the enet core */ 783119917Swpaul bfe_pci_setup(sc, BFE_INTVEC_ENET0); 784119917Swpaul 785119917Swpaul /* is core up? */ 786126470Sjulian val = CSR_READ_4(sc, BFE_SBTMSLOW) & 787126470Sjulian (BFE_RESET | BFE_REJECT | BFE_CLOCK); 788119917Swpaul if (val == BFE_CLOCK) { 789119917Swpaul /* It is, so shut it down */ 790119917Swpaul CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 791119917Swpaul CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 792119917Swpaul bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 793119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 794119917Swpaul sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 795133282Sdes if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 796126470Sjulian bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 797126470Sjulian 100, 0); 798119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 799119917Swpaul sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 800119917Swpaul } 801119917Swpaul 802119917Swpaul bfe_core_reset(sc); 803119917Swpaul bfe_clear_stats(sc); 804119917Swpaul 805119917Swpaul /* 806119917Swpaul * We want the phy registers to be accessible even when 807119917Swpaul * the driver is "downed" so initialize MDC preamble, frequency, 808119917Swpaul * and whether internal or external phy here. 809119917Swpaul */ 810119917Swpaul 811119917Swpaul /* 4402 has 62.5Mhz SB clock and internal phy */ 812119917Swpaul CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 813119917Swpaul 814119917Swpaul /* Internal or external PHY? */ 815119917Swpaul val = CSR_READ_4(sc, BFE_DEVCTRL); 816180954Syongari if (!(val & BFE_IPP)) 817119917Swpaul CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 818180954Syongari else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 819119917Swpaul BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 820119917Swpaul DELAY(100); 821119917Swpaul } 822119917Swpaul 823133282Sdes /* Enable CRC32 generation and set proper LED modes */ 824133282Sdes BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 825129602Sdmlb 826133282Sdes /* Reset or clear powerdown control bit */ 827133282Sdes BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 828129602Sdmlb 829133282Sdes CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 830119917Swpaul BFE_LAZY_FC_MASK)); 831119917Swpaul 832133282Sdes /* 833126470Sjulian * We don't want lazy interrupts, so just send them at 834133282Sdes * the end of a frame, please 835119917Swpaul */ 836119917Swpaul BFE_OR(sc, BFE_RCV_LAZY, 0); 837119917Swpaul 838119917Swpaul /* Set max lengths, accounting for VLAN tags */ 839119917Swpaul CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 840119917Swpaul CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 841119917Swpaul 842119917Swpaul /* Set watermark XXX - magic */ 843119917Swpaul CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 844119917Swpaul 845133282Sdes /* 846126470Sjulian * Initialise DMA channels 847133282Sdes * - not forgetting dma addresses need to be added to BFE_PCI_DMA 848119917Swpaul */ 849119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 850119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 851119917Swpaul 852133282Sdes CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 853119917Swpaul BFE_RX_CTRL_ENABLE); 854119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 855119917Swpaul 856119917Swpaul bfe_resetphy(sc); 857119917Swpaul bfe_setupphy(sc); 858119917Swpaul} 859119917Swpaul 860119917Swpaulstatic void 861119917Swpaulbfe_core_disable(struct bfe_softc *sc) 862119917Swpaul{ 863180954Syongari if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 864119917Swpaul return; 865119917Swpaul 866133282Sdes /* 867126470Sjulian * Set reject, wait for it set, then wait for the core to stop 868126470Sjulian * being busy, then set reset and reject and enable the clocks. 869119917Swpaul */ 870119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 871119917Swpaul bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 872119917Swpaul bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 873119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 874119917Swpaul BFE_RESET)); 875119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 876119917Swpaul DELAY(10); 877119917Swpaul /* Leave reset and reject set */ 878119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 879119917Swpaul DELAY(10); 880119917Swpaul} 881119917Swpaul 882119917Swpaulstatic void 883119917Swpaulbfe_core_reset(struct bfe_softc *sc) 884119917Swpaul{ 885119917Swpaul u_int32_t val; 886119917Swpaul 887119917Swpaul /* Disable the core */ 888119917Swpaul bfe_core_disable(sc); 889119917Swpaul 890119917Swpaul /* and bring it back up */ 891119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 892119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 893119917Swpaul DELAY(10); 894119917Swpaul 895119917Swpaul /* Chip bug, clear SERR, IB and TO if they are set. */ 896119917Swpaul if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 897119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 898119917Swpaul val = CSR_READ_4(sc, BFE_SBIMSTATE); 899119917Swpaul if (val & (BFE_IBE | BFE_TO)) 900119917Swpaul CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 901119917Swpaul 902119917Swpaul /* Clear reset and allow it to move through the core */ 903119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 904119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 905119917Swpaul DELAY(10); 906119917Swpaul 907119917Swpaul /* Leave the clock set */ 908119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 909119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 910119917Swpaul DELAY(10); 911119917Swpaul} 912119917Swpaul 913133282Sdesstatic void 914119917Swpaulbfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 915119917Swpaul{ 916119917Swpaul u_int32_t val; 917119917Swpaul 918119917Swpaul val = ((u_int32_t) data[2]) << 24; 919119917Swpaul val |= ((u_int32_t) data[3]) << 16; 920119917Swpaul val |= ((u_int32_t) data[4]) << 8; 921119917Swpaul val |= ((u_int32_t) data[5]); 922119917Swpaul CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 923119917Swpaul val = (BFE_CAM_HI_VALID | 924119917Swpaul (((u_int32_t) data[0]) << 8) | 925119917Swpaul (((u_int32_t) data[1]))); 926119917Swpaul CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 927119917Swpaul CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 928129602Sdmlb ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 929119917Swpaul bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 930119917Swpaul} 931119917Swpaul 932133282Sdesstatic void 933119917Swpaulbfe_set_rx_mode(struct bfe_softc *sc) 934119917Swpaul{ 935147256Sbrooks struct ifnet *ifp = sc->bfe_ifp; 936119917Swpaul struct ifmultiaddr *ifma; 937119917Swpaul u_int32_t val; 938119917Swpaul int i = 0; 939119917Swpaul 940119917Swpaul val = CSR_READ_4(sc, BFE_RXCONF); 941119917Swpaul 942119917Swpaul if (ifp->if_flags & IFF_PROMISC) 943119917Swpaul val |= BFE_RXCONF_PROMISC; 944119917Swpaul else 945119917Swpaul val &= ~BFE_RXCONF_PROMISC; 946119917Swpaul 947119917Swpaul if (ifp->if_flags & IFF_BROADCAST) 948119917Swpaul val &= ~BFE_RXCONF_DBCAST; 949119917Swpaul else 950119917Swpaul val |= BFE_RXCONF_DBCAST; 951119917Swpaul 952119917Swpaul 953119917Swpaul CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 954152315Sru bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 955119917Swpaul 956119917Swpaul if (ifp->if_flags & IFF_ALLMULTI) 957119917Swpaul val |= BFE_RXCONF_ALLMULTI; 958119917Swpaul else { 959119917Swpaul val &= ~BFE_RXCONF_ALLMULTI; 960148654Srwatson IF_ADDR_LOCK(ifp); 961119917Swpaul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 962119917Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 963119917Swpaul continue; 964126470Sjulian bfe_cam_write(sc, 965126470Sjulian LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 966119917Swpaul } 967148654Srwatson IF_ADDR_UNLOCK(ifp); 968119917Swpaul } 969119917Swpaul 970119917Swpaul CSR_WRITE_4(sc, BFE_RXCONF, val); 971119917Swpaul BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 972119917Swpaul} 973119917Swpaul 974119917Swpaulstatic void 975119917Swpaulbfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 976119917Swpaul{ 977119917Swpaul u_int32_t *ptr; 978119917Swpaul 979119917Swpaul ptr = arg; 980119917Swpaul *ptr = segs->ds_addr; 981119917Swpaul} 982119917Swpaul 983119917Swpaulstatic void 984119917Swpaulbfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 985119917Swpaul{ 986119917Swpaul struct bfe_desc *d; 987119917Swpaul 988119917Swpaul d = arg; 989119917Swpaul /* The chip needs all addresses to be added to BFE_PCI_DMA */ 990119917Swpaul d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 991119917Swpaul} 992119917Swpaul 993119917Swpaulstatic void 994119917Swpaulbfe_release_resources(struct bfe_softc *sc) 995119917Swpaul{ 996119917Swpaul device_t dev; 997119917Swpaul int i; 998119917Swpaul 999119917Swpaul dev = sc->bfe_dev; 1000119917Swpaul 1001119917Swpaul if (sc->bfe_vpd_prodname != NULL) 1002119917Swpaul free(sc->bfe_vpd_prodname, M_DEVBUF); 1003119917Swpaul 1004119917Swpaul if (sc->bfe_vpd_readonly != NULL) 1005119917Swpaul free(sc->bfe_vpd_readonly, M_DEVBUF); 1006119917Swpaul 1007119917Swpaul if (sc->bfe_intrhand != NULL) 1008119917Swpaul bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 1009119917Swpaul 1010119917Swpaul if (sc->bfe_irq != NULL) 1011119917Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1012119917Swpaul 1013119917Swpaul if (sc->bfe_res != NULL) 1014119917Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 1015119917Swpaul 1016150215Sru if (sc->bfe_ifp != NULL) 1017150215Sru if_free(sc->bfe_ifp); 1018150215Sru 1019180954Syongari if (sc->bfe_tx_tag != NULL) { 1020119917Swpaul bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 1021126470Sjulian bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 1022126470Sjulian sc->bfe_tx_map); 1023119917Swpaul bus_dma_tag_destroy(sc->bfe_tx_tag); 1024119917Swpaul sc->bfe_tx_tag = NULL; 1025119917Swpaul } 1026119917Swpaul 1027180954Syongari if (sc->bfe_rx_tag != NULL) { 1028119917Swpaul bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 1029126470Sjulian bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 1030126470Sjulian sc->bfe_rx_map); 1031119917Swpaul bus_dma_tag_destroy(sc->bfe_rx_tag); 1032119917Swpaul sc->bfe_rx_tag = NULL; 1033119917Swpaul } 1034119917Swpaul 1035180954Syongari if (sc->bfe_tag != NULL) { 1036119917Swpaul for(i = 0; i < BFE_TX_LIST_CNT; i++) { 1037126470Sjulian bus_dmamap_destroy(sc->bfe_tag, 1038126470Sjulian sc->bfe_tx_ring[i].bfe_map); 1039119917Swpaul } 1040143750Savatar for(i = 0; i < BFE_RX_LIST_CNT; i++) { 1041143750Savatar bus_dmamap_destroy(sc->bfe_tag, 1042143750Savatar sc->bfe_rx_ring[i].bfe_map); 1043143750Savatar } 1044119917Swpaul bus_dma_tag_destroy(sc->bfe_tag); 1045126470Sjulian sc->bfe_tag = NULL; 1046119917Swpaul } 1047119917Swpaul 1048180954Syongari if (sc->bfe_parent_tag != NULL) 1049119917Swpaul bus_dma_tag_destroy(sc->bfe_parent_tag); 1050119917Swpaul 1051119917Swpaul return; 1052119917Swpaul} 1053119917Swpaul 1054119917Swpaulstatic void 1055119917Swpaulbfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1056119917Swpaul{ 1057119917Swpaul long i; 1058119917Swpaul u_int16_t *ptr = (u_int16_t *)data; 1059119917Swpaul 1060119917Swpaul for(i = 0; i < 128; i += 2) 1061119917Swpaul ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1062119917Swpaul} 1063119917Swpaul 1064119917Swpaulstatic int 1065133282Sdesbfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1066119917Swpaul u_long timeout, const int clear) 1067119917Swpaul{ 1068119917Swpaul u_long i; 1069119917Swpaul 1070119917Swpaul for (i = 0; i < timeout; i++) { 1071119917Swpaul u_int32_t val = CSR_READ_4(sc, reg); 1072119917Swpaul 1073119917Swpaul if (clear && !(val & bit)) 1074119917Swpaul break; 1075119917Swpaul if (!clear && (val & bit)) 1076119917Swpaul break; 1077119917Swpaul DELAY(10); 1078119917Swpaul } 1079119917Swpaul if (i == timeout) { 1080180950Syongari device_printf(sc->bfe_dev, 1081180950Syongari "BUG! Timeout waiting for bit %08x of register " 1082180950Syongari "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1083133282Sdes return (-1); 1084119917Swpaul } 1085133282Sdes return (0); 1086119917Swpaul} 1087119917Swpaul 1088119917Swpaulstatic int 1089119917Swpaulbfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1090119917Swpaul{ 1091133282Sdes int err; 1092119917Swpaul 1093119917Swpaul /* Clear MII ISR */ 1094119917Swpaul CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1095119917Swpaul CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1096119917Swpaul (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1097119917Swpaul (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1098119917Swpaul (reg << BFE_MDIO_RA_SHIFT) | 1099119917Swpaul (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1100119917Swpaul err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1101119917Swpaul *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1102119917Swpaul 1103133282Sdes return (err); 1104119917Swpaul} 1105119917Swpaul 1106119917Swpaulstatic int 1107119917Swpaulbfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1108119917Swpaul{ 1109119917Swpaul int status; 1110119917Swpaul 1111119917Swpaul CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1112119917Swpaul CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1113119917Swpaul (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1114119917Swpaul (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1115119917Swpaul (reg << BFE_MDIO_RA_SHIFT) | 1116119917Swpaul (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1117119917Swpaul (val & BFE_MDIO_DATA_DATA))); 1118119917Swpaul status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1119119917Swpaul 1120133282Sdes return (status); 1121119917Swpaul} 1122119917Swpaul 1123133282Sdes/* 1124119917Swpaul * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1125119917Swpaul * twice 1126119917Swpaul */ 1127119917Swpaulstatic int 1128119917Swpaulbfe_setupphy(struct bfe_softc *sc) 1129119917Swpaul{ 1130119917Swpaul u_int32_t val; 1131119917Swpaul 1132119917Swpaul /* Enable activity LED */ 1133119917Swpaul bfe_readphy(sc, 26, &val); 1134133282Sdes bfe_writephy(sc, 26, val & 0x7fff); 1135119917Swpaul bfe_readphy(sc, 26, &val); 1136119917Swpaul 1137119917Swpaul /* Enable traffic meter LED mode */ 1138119917Swpaul bfe_readphy(sc, 27, &val); 1139119917Swpaul bfe_writephy(sc, 27, val | (1 << 6)); 1140119917Swpaul 1141133282Sdes return (0); 1142119917Swpaul} 1143119917Swpaul 1144133282Sdesstatic void 1145119917Swpaulbfe_stats_update(struct bfe_softc *sc) 1146119917Swpaul{ 1147119917Swpaul u_long reg; 1148119917Swpaul u_int32_t *val; 1149119917Swpaul 1150119917Swpaul val = &sc->bfe_hwstats.tx_good_octets; 1151119917Swpaul for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1152119917Swpaul *val++ += CSR_READ_4(sc, reg); 1153119917Swpaul } 1154119917Swpaul val = &sc->bfe_hwstats.rx_good_octets; 1155119917Swpaul for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1156119917Swpaul *val++ += CSR_READ_4(sc, reg); 1157119917Swpaul } 1158119917Swpaul} 1159119917Swpaul 1160119917Swpaulstatic void 1161119917Swpaulbfe_txeof(struct bfe_softc *sc) 1162119917Swpaul{ 1163119917Swpaul struct ifnet *ifp; 1164119917Swpaul int i, chipidx; 1165119917Swpaul 1166136804Smtm BFE_LOCK_ASSERT(sc); 1167119917Swpaul 1168147256Sbrooks ifp = sc->bfe_ifp; 1169119917Swpaul 1170119917Swpaul chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1171119917Swpaul chipidx /= sizeof(struct bfe_desc); 1172119917Swpaul 1173126470Sjulian i = sc->bfe_tx_cons; 1174119917Swpaul /* Go through the mbufs and free those that have been transmitted */ 1175180954Syongari while (i != chipidx) { 1176119917Swpaul struct bfe_data *r = &sc->bfe_tx_ring[i]; 1177180954Syongari if (r->bfe_mbuf != NULL) { 1178119917Swpaul ifp->if_opackets++; 1179119917Swpaul m_freem(r->bfe_mbuf); 1180119917Swpaul r->bfe_mbuf = NULL; 1181119917Swpaul } 1182158285Ssilby bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1183126470Sjulian sc->bfe_tx_cnt--; 1184126470Sjulian BFE_INC(i, BFE_TX_LIST_CNT); 1185119917Swpaul } 1186119917Swpaul 1187180954Syongari if (i != sc->bfe_tx_cons) { 1188119917Swpaul /* we freed up some mbufs */ 1189119917Swpaul sc->bfe_tx_cons = i; 1190148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1191119917Swpaul } 1192175787Syongari 1193175787Syongari if (sc->bfe_tx_cnt == 0) 1194175787Syongari sc->bfe_watchdog_timer = 0; 1195119917Swpaul} 1196119917Swpaul 1197119917Swpaul/* Pass a received packet up the stack */ 1198119917Swpaulstatic void 1199119917Swpaulbfe_rxeof(struct bfe_softc *sc) 1200119917Swpaul{ 1201119917Swpaul struct mbuf *m; 1202119917Swpaul struct ifnet *ifp; 1203119917Swpaul struct bfe_rxheader *rxheader; 1204119917Swpaul struct bfe_data *r; 1205119917Swpaul int cons; 1206119917Swpaul u_int32_t status, current, len, flags; 1207119917Swpaul 1208136804Smtm BFE_LOCK_ASSERT(sc); 1209119917Swpaul cons = sc->bfe_rx_cons; 1210119917Swpaul status = CSR_READ_4(sc, BFE_DMARX_STAT); 1211119917Swpaul current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1212119917Swpaul 1213147256Sbrooks ifp = sc->bfe_ifp; 1214119917Swpaul 1215180954Syongari while (current != cons) { 1216119917Swpaul r = &sc->bfe_rx_ring[cons]; 1217119917Swpaul m = r->bfe_mbuf; 1218119917Swpaul rxheader = mtod(m, struct bfe_rxheader*); 1219158102Ssilby bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD); 1220119917Swpaul len = rxheader->len; 1221119917Swpaul r->bfe_mbuf = NULL; 1222119917Swpaul 1223119917Swpaul bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1224119917Swpaul flags = rxheader->flags; 1225119917Swpaul 1226119917Swpaul len -= ETHER_CRC_LEN; 1227119917Swpaul 1228119917Swpaul /* flag an error and try again */ 1229119917Swpaul if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1230119917Swpaul ifp->if_ierrors++; 1231119917Swpaul if (flags & BFE_RX_FLAG_SERR) 1232119917Swpaul ifp->if_collisions++; 1233119917Swpaul bfe_list_newbuf(sc, cons, m); 1234126473Sjulian BFE_INC(cons, BFE_RX_LIST_CNT); 1235119917Swpaul continue; 1236119917Swpaul } 1237119917Swpaul 1238119917Swpaul /* Go past the rx header */ 1239119917Swpaul if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1240119917Swpaul m_adj(m, BFE_RX_OFFSET); 1241119917Swpaul m->m_len = m->m_pkthdr.len = len; 1242119917Swpaul } else { 1243119917Swpaul bfe_list_newbuf(sc, cons, m); 1244119917Swpaul ifp->if_ierrors++; 1245126473Sjulian BFE_INC(cons, BFE_RX_LIST_CNT); 1246119917Swpaul continue; 1247119917Swpaul } 1248119917Swpaul 1249119917Swpaul ifp->if_ipackets++; 1250119917Swpaul m->m_pkthdr.rcvif = ifp; 1251122689Ssam BFE_UNLOCK(sc); 1252119917Swpaul (*ifp->if_input)(ifp, m); 1253122689Ssam BFE_LOCK(sc); 1254119917Swpaul 1255126470Sjulian BFE_INC(cons, BFE_RX_LIST_CNT); 1256119917Swpaul } 1257119917Swpaul sc->bfe_rx_cons = cons; 1258119917Swpaul} 1259119917Swpaul 1260119917Swpaulstatic void 1261119917Swpaulbfe_intr(void *xsc) 1262119917Swpaul{ 1263119917Swpaul struct bfe_softc *sc = xsc; 1264119917Swpaul struct ifnet *ifp; 1265119917Swpaul u_int32_t istat, imask, flag; 1266119917Swpaul 1267147256Sbrooks ifp = sc->bfe_ifp; 1268119917Swpaul 1269119917Swpaul BFE_LOCK(sc); 1270119917Swpaul 1271119917Swpaul istat = CSR_READ_4(sc, BFE_ISTAT); 1272119917Swpaul imask = CSR_READ_4(sc, BFE_IMASK); 1273119917Swpaul 1274133282Sdes /* 1275119917Swpaul * Defer unsolicited interrupts - This is necessary because setting the 1276119917Swpaul * chips interrupt mask register to 0 doesn't actually stop the 1277119917Swpaul * interrupts 1278119917Swpaul */ 1279119917Swpaul istat &= imask; 1280119917Swpaul CSR_WRITE_4(sc, BFE_ISTAT, istat); 1281119917Swpaul CSR_READ_4(sc, BFE_ISTAT); 1282119917Swpaul 1283119917Swpaul /* not expecting this interrupt, disregard it */ 1284180954Syongari if (istat == 0) { 1285119917Swpaul BFE_UNLOCK(sc); 1286119917Swpaul return; 1287119917Swpaul } 1288119917Swpaul 1289180954Syongari if (istat & BFE_ISTAT_ERRORS) { 1290159013Ssilby 1291159013Ssilby if (istat & BFE_ISTAT_DSCE) { 1292180950Syongari device_printf(sc->bfe_dev, "Descriptor Error\n"); 1293159013Ssilby bfe_stop(sc); 1294159013Ssilby BFE_UNLOCK(sc); 1295159013Ssilby return; 1296159013Ssilby } 1297159013Ssilby 1298159013Ssilby if (istat & BFE_ISTAT_DPE) { 1299180950Syongari device_printf(sc->bfe_dev, 1300180950Syongari "Descriptor Protocol Error\n"); 1301159013Ssilby bfe_stop(sc); 1302159013Ssilby BFE_UNLOCK(sc); 1303159013Ssilby return; 1304159013Ssilby } 1305159013Ssilby 1306119917Swpaul flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1307180954Syongari if (flag & BFE_STAT_EMASK) 1308119917Swpaul ifp->if_oerrors++; 1309119917Swpaul 1310119917Swpaul flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1311180954Syongari if (flag & BFE_RX_FLAG_ERRORS) 1312119917Swpaul ifp->if_ierrors++; 1313119917Swpaul 1314148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1315136804Smtm bfe_init_locked(sc); 1316119917Swpaul } 1317119917Swpaul 1318119917Swpaul /* A packet was received */ 1319180954Syongari if (istat & BFE_ISTAT_RX) 1320119917Swpaul bfe_rxeof(sc); 1321119917Swpaul 1322119917Swpaul /* A packet was sent */ 1323180954Syongari if (istat & BFE_ISTAT_TX) 1324119917Swpaul bfe_txeof(sc); 1325119917Swpaul 1326133282Sdes /* We have packets pending, fire them out */ 1327148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1328148887Srwatson !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1329136804Smtm bfe_start_locked(ifp); 1330119917Swpaul 1331119917Swpaul BFE_UNLOCK(sc); 1332119917Swpaul} 1333119917Swpaul 1334119917Swpaulstatic int 1335158285Ssilbybfe_encap(struct bfe_softc *sc, struct mbuf **m_head, u_int32_t *txidx) 1336119917Swpaul{ 1337119917Swpaul struct bfe_desc *d = NULL; 1338119917Swpaul struct bfe_data *r = NULL; 1339133282Sdes struct mbuf *m; 1340126470Sjulian u_int32_t frag, cur, cnt = 0; 1341119917Swpaul int chainlen = 0; 1342158285Ssilby int error; 1343119917Swpaul 1344180954Syongari if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1345133282Sdes return (ENOBUFS); 1346119917Swpaul 1347119917Swpaul /* 1348119917Swpaul * Count the number of frags in this chain to see if 1349119917Swpaul * we need to m_defrag. Since the descriptor list is shared 1350119917Swpaul * by all packets, we'll m_defrag long chains so that they 1351119917Swpaul * do not use up the entire list, even if they would fit. 1352119917Swpaul */ 1353158285Ssilby for(m = *m_head; m != NULL; m = m->m_next) 1354119917Swpaul chainlen++; 1355119917Swpaul 1356119917Swpaul 1357133282Sdes if ((chainlen > BFE_TX_LIST_CNT / 4) || 1358119917Swpaul ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1359158285Ssilby m = m_defrag(*m_head, M_DONTWAIT); 1360133282Sdes if (m == NULL) 1361133282Sdes return (ENOBUFS); 1362158285Ssilby *m_head = m; 1363119917Swpaul } 1364119917Swpaul 1365119917Swpaul /* 1366119917Swpaul * Start packing the mbufs in this chain into 1367119917Swpaul * the fragment pointers. Stop when we run out 1368119917Swpaul * of fragments or hit the end of the mbuf chain. 1369119917Swpaul */ 1370119917Swpaul cur = frag = *txidx; 1371119917Swpaul cnt = 0; 1372119917Swpaul 1373158285Ssilby for(m = *m_head; m != NULL; m = m->m_next) { 1374180954Syongari if (m->m_len != 0) { 1375180954Syongari if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1376133282Sdes return (ENOBUFS); 1377119917Swpaul 1378119917Swpaul d = &sc->bfe_tx_list[cur]; 1379119917Swpaul r = &sc->bfe_tx_ring[cur]; 1380119917Swpaul d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1381119917Swpaul /* always intterupt on completion */ 1382119917Swpaul d->bfe_ctrl |= BFE_DESC_IOC; 1383180954Syongari if (cnt == 0) 1384119917Swpaul /* Set start of frame */ 1385119917Swpaul d->bfe_ctrl |= BFE_DESC_SOF; 1386180954Syongari if (cur == BFE_TX_LIST_CNT - 1) 1387126470Sjulian /* 1388126470Sjulian * Tell the chip to wrap to the start of 1389126470Sjulian * the descriptor list 1390126470Sjulian */ 1391119917Swpaul d->bfe_ctrl |= BFE_DESC_EOT; 1392119917Swpaul 1393158285Ssilby error = bus_dmamap_load(sc->bfe_tag, 1394133282Sdes r->bfe_map, mtod(m, void*), m->m_len, 1395158285Ssilby bfe_dma_map_desc, d, BUS_DMA_NOWAIT); 1396158285Ssilby if (error) 1397158285Ssilby return (ENOBUFS); 1398126470Sjulian bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1399158102Ssilby BUS_DMASYNC_PREWRITE); 1400119917Swpaul 1401119917Swpaul frag = cur; 1402126470Sjulian BFE_INC(cur, BFE_TX_LIST_CNT); 1403119917Swpaul cnt++; 1404119917Swpaul } 1405119917Swpaul } 1406119917Swpaul 1407119917Swpaul if (m != NULL) 1408133282Sdes return (ENOBUFS); 1409119917Swpaul 1410119917Swpaul sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1411158285Ssilby sc->bfe_tx_ring[frag].bfe_mbuf = *m_head; 1412158102Ssilby bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE); 1413119917Swpaul 1414119917Swpaul *txidx = cur; 1415119917Swpaul sc->bfe_tx_cnt += cnt; 1416119917Swpaul return (0); 1417119917Swpaul} 1418119917Swpaul 1419119917Swpaul/* 1420136804Smtm * Set up to transmit a packet. 1421119917Swpaul */ 1422119917Swpaulstatic void 1423119917Swpaulbfe_start(struct ifnet *ifp) 1424119917Swpaul{ 1425136804Smtm BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1426136804Smtm bfe_start_locked(ifp); 1427136804Smtm BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1428136804Smtm} 1429136804Smtm 1430136804Smtm/* 1431136804Smtm * Set up to transmit a packet. The softc is already locked. 1432136804Smtm */ 1433136804Smtmstatic void 1434136804Smtmbfe_start_locked(struct ifnet *ifp) 1435136804Smtm{ 1436119917Swpaul struct bfe_softc *sc; 1437119917Swpaul struct mbuf *m_head = NULL; 1438136269Smlaier int idx, queued = 0; 1439119917Swpaul 1440119917Swpaul sc = ifp->if_softc; 1441119917Swpaul idx = sc->bfe_tx_prod; 1442119917Swpaul 1443136804Smtm BFE_LOCK_ASSERT(sc); 1444119917Swpaul 1445133282Sdes /* 1446126470Sjulian * Not much point trying to send if the link is down 1447126470Sjulian * or we have nothing to send. 1448119917Swpaul */ 1449136804Smtm if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) 1450119917Swpaul return; 1451119917Swpaul 1452175787Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1453175787Syongari IFF_DRV_RUNNING) 1454119917Swpaul return; 1455119917Swpaul 1456180954Syongari while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1457131455Smlaier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1458180954Syongari if (m_head == NULL) 1459119917Swpaul break; 1460119917Swpaul 1461133282Sdes /* 1462126470Sjulian * Pack the data into the tx ring. If we dont have 1463126470Sjulian * enough room, let the chip drain the ring. 1464119917Swpaul */ 1465180954Syongari if (bfe_encap(sc, &m_head, &idx)) { 1466131455Smlaier IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1467148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1468119917Swpaul break; 1469119917Swpaul } 1470119917Swpaul 1471136269Smlaier queued++; 1472136269Smlaier 1473119917Swpaul /* 1474119917Swpaul * If there's a BPF listener, bounce a copy of this frame 1475119917Swpaul * to him. 1476119917Swpaul */ 1477119917Swpaul BPF_MTAP(ifp, m_head); 1478119917Swpaul } 1479119917Swpaul 1480136269Smlaier if (queued) { 1481136269Smlaier sc->bfe_tx_prod = idx; 1482136269Smlaier /* Transmit - twice due to apparent hardware bug */ 1483136269Smlaier CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1484136269Smlaier CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1485119917Swpaul 1486136269Smlaier /* 1487136269Smlaier * Set a timeout in case the chip goes out to lunch. 1488136269Smlaier */ 1489175787Syongari sc->bfe_watchdog_timer = 5; 1490136269Smlaier } 1491119917Swpaul} 1492119917Swpaul 1493119917Swpaulstatic void 1494119917Swpaulbfe_init(void *xsc) 1495119917Swpaul{ 1496136804Smtm BFE_LOCK((struct bfe_softc *)xsc); 1497136804Smtm bfe_init_locked(xsc); 1498136804Smtm BFE_UNLOCK((struct bfe_softc *)xsc); 1499136804Smtm} 1500136804Smtm 1501136804Smtmstatic void 1502136804Smtmbfe_init_locked(void *xsc) 1503136804Smtm{ 1504119917Swpaul struct bfe_softc *sc = (struct bfe_softc*)xsc; 1505147256Sbrooks struct ifnet *ifp = sc->bfe_ifp; 1506175787Syongari struct mii_data *mii; 1507119917Swpaul 1508136804Smtm BFE_LOCK_ASSERT(sc); 1509119917Swpaul 1510175787Syongari mii = device_get_softc(sc->bfe_miibus); 1511175787Syongari 1512148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1513119917Swpaul return; 1514119917Swpaul 1515119917Swpaul bfe_stop(sc); 1516119917Swpaul bfe_chip_reset(sc); 1517119917Swpaul 1518119917Swpaul if (bfe_list_rx_init(sc) == ENOBUFS) { 1519180950Syongari device_printf(sc->bfe_dev, 1520180950Syongari "%s: Not enough memory for list buffers\n", __func__); 1521119917Swpaul bfe_stop(sc); 1522119917Swpaul return; 1523119917Swpaul } 1524119917Swpaul 1525119917Swpaul bfe_set_rx_mode(sc); 1526119917Swpaul 1527119917Swpaul /* Enable the chip and core */ 1528119917Swpaul BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1529119917Swpaul /* Enable interrupts */ 1530119917Swpaul CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1531119917Swpaul 1532175787Syongari /* Clear link state and change media. */ 1533175787Syongari sc->bfe_link = 0; 1534175787Syongari mii_mediachg(mii); 1535175787Syongari 1536148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 1537148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1538119917Swpaul 1539175787Syongari callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1540119917Swpaul} 1541119917Swpaul 1542119917Swpaul/* 1543119917Swpaul * Set media options. 1544119917Swpaul */ 1545119917Swpaulstatic int 1546119917Swpaulbfe_ifmedia_upd(struct ifnet *ifp) 1547119917Swpaul{ 1548119917Swpaul struct bfe_softc *sc; 1549119917Swpaul struct mii_data *mii; 1550175787Syongari int error; 1551119917Swpaul 1552119917Swpaul sc = ifp->if_softc; 1553175787Syongari BFE_LOCK(sc); 1554119917Swpaul 1555119917Swpaul mii = device_get_softc(sc->bfe_miibus); 1556119917Swpaul if (mii->mii_instance) { 1557119917Swpaul struct mii_softc *miisc; 1558119917Swpaul for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1559119917Swpaul miisc = LIST_NEXT(miisc, mii_list)) 1560119917Swpaul mii_phy_reset(miisc); 1561119917Swpaul } 1562175787Syongari error = mii_mediachg(mii); 1563175787Syongari BFE_UNLOCK(sc); 1564119917Swpaul 1565175787Syongari return (error); 1566119917Swpaul} 1567119917Swpaul 1568119917Swpaul/* 1569119917Swpaul * Report current media status. 1570119917Swpaul */ 1571119917Swpaulstatic void 1572119917Swpaulbfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1573119917Swpaul{ 1574119917Swpaul struct bfe_softc *sc = ifp->if_softc; 1575119917Swpaul struct mii_data *mii; 1576119917Swpaul 1577175787Syongari BFE_LOCK(sc); 1578119917Swpaul mii = device_get_softc(sc->bfe_miibus); 1579119917Swpaul mii_pollstat(mii); 1580119917Swpaul ifmr->ifm_active = mii->mii_media_active; 1581119917Swpaul ifmr->ifm_status = mii->mii_media_status; 1582175787Syongari BFE_UNLOCK(sc); 1583119917Swpaul} 1584119917Swpaul 1585119917Swpaulstatic int 1586119917Swpaulbfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1587119917Swpaul{ 1588119917Swpaul struct bfe_softc *sc = ifp->if_softc; 1589119917Swpaul struct ifreq *ifr = (struct ifreq *) data; 1590119917Swpaul struct mii_data *mii; 1591119917Swpaul int error = 0; 1592119917Swpaul 1593180954Syongari switch (command) { 1594180954Syongari case SIOCSIFFLAGS: 1595180954Syongari BFE_LOCK(sc); 1596180954Syongari if (ifp->if_flags & IFF_UP) 1597180954Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1598119917Swpaul bfe_set_rx_mode(sc); 1599180954Syongari else 1600180954Syongari bfe_init_locked(sc); 1601180954Syongari else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1602180954Syongari bfe_stop(sc); 1603180954Syongari BFE_UNLOCK(sc); 1604180954Syongari break; 1605180954Syongari case SIOCADDMULTI: 1606180954Syongari case SIOCDELMULTI: 1607180954Syongari BFE_LOCK(sc); 1608180954Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1609180954Syongari bfe_set_rx_mode(sc); 1610180954Syongari BFE_UNLOCK(sc); 1611180954Syongari break; 1612180954Syongari case SIOCGIFMEDIA: 1613180954Syongari case SIOCSIFMEDIA: 1614180954Syongari mii = device_get_softc(sc->bfe_miibus); 1615180954Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1616180954Syongari break; 1617180954Syongari default: 1618180954Syongari error = ether_ioctl(ifp, command, data); 1619180954Syongari break; 1620119917Swpaul } 1621119917Swpaul 1622133282Sdes return (error); 1623119917Swpaul} 1624119917Swpaul 1625119917Swpaulstatic void 1626175787Syongaribfe_watchdog(struct bfe_softc *sc) 1627119917Swpaul{ 1628175787Syongari struct ifnet *ifp; 1629119917Swpaul 1630175787Syongari BFE_LOCK_ASSERT(sc); 1631119917Swpaul 1632175787Syongari if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1633175787Syongari return; 1634119917Swpaul 1635175787Syongari ifp = sc->bfe_ifp; 1636175787Syongari 1637180950Syongari device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1638119917Swpaul 1639175787Syongari ifp->if_oerrors++; 1640148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1641136804Smtm bfe_init_locked(sc); 1642119917Swpaul 1643175787Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1644175787Syongari bfe_start_locked(ifp); 1645119917Swpaul} 1646119917Swpaul 1647119917Swpaulstatic void 1648119917Swpaulbfe_tick(void *xsc) 1649119917Swpaul{ 1650119917Swpaul struct bfe_softc *sc = xsc; 1651119917Swpaul struct mii_data *mii; 1652119917Swpaul 1653175787Syongari BFE_LOCK_ASSERT(sc); 1654119917Swpaul 1655119917Swpaul mii = device_get_softc(sc->bfe_miibus); 1656175787Syongari mii_tick(mii); 1657119917Swpaul bfe_stats_update(sc); 1658175787Syongari bfe_watchdog(sc); 1659175787Syongari callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1660119917Swpaul} 1661119917Swpaul 1662119917Swpaul/* 1663119917Swpaul * Stop the adapter and free any mbufs allocated to the 1664119917Swpaul * RX and TX lists. 1665119917Swpaul */ 1666119917Swpaulstatic void 1667119917Swpaulbfe_stop(struct bfe_softc *sc) 1668119917Swpaul{ 1669119917Swpaul struct ifnet *ifp; 1670119917Swpaul 1671136804Smtm BFE_LOCK_ASSERT(sc); 1672119917Swpaul 1673147256Sbrooks ifp = sc->bfe_ifp; 1674175787Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1675175787Syongari sc->bfe_link = 0; 1676175787Syongari callout_stop(&sc->bfe_stat_co); 1677175787Syongari sc->bfe_watchdog_timer = 0; 1678119917Swpaul 1679119917Swpaul bfe_chip_halt(sc); 1680126470Sjulian bfe_tx_ring_free(sc); 1681119917Swpaul bfe_rx_ring_free(sc); 1682119917Swpaul} 1683