if_bfe.c revision 131455
1119917Swpaul/* 2119917Swpaul * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3119917Swpaul * and Duncan Barclay<dmlb@dmlb.org> 4119917Swpaul */ 5119917Swpaul 6119917Swpaul/* 7119917Swpaul * Redistribution and use in source and binary forms, with or without 8119917Swpaul * modification, are permitted provided that the following conditions 9119917Swpaul * are met: 10119917Swpaul * 1. Redistributions of source code must retain the above copyright 11119917Swpaul * notice, this list of conditions and the following disclaimer. 12119917Swpaul * 2. Redistributions in binary form must reproduce the above copyright 13119917Swpaul * notice, this list of conditions and the following disclaimer in the 14119917Swpaul * documentation and/or other materials provided with the distribution. 15119917Swpaul * 16119917Swpaul * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17119917Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18119917Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19119917Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20119917Swpaul * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21119917Swpaul * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22119917Swpaul * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23119917Swpaul * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24119917Swpaul * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25119917Swpaul * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26119917Swpaul * SUCH DAMAGE. 27119917Swpaul */ 28119917Swpaul 29119917Swpaul 30119917Swpaul#include <sys/cdefs.h> 31119917Swpaul__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 131455 2004-07-02 12:16:02Z mlaier $"); 32119917Swpaul 33119917Swpaul#include <sys/param.h> 34119917Swpaul#include <sys/systm.h> 35119917Swpaul#include <sys/sockio.h> 36119917Swpaul#include <sys/mbuf.h> 37119917Swpaul#include <sys/malloc.h> 38119917Swpaul#include <sys/kernel.h> 39129879Sphk#include <sys/module.h> 40119917Swpaul#include <sys/socket.h> 41119917Swpaul#include <sys/queue.h> 42119917Swpaul 43119917Swpaul#include <net/if.h> 44119917Swpaul#include <net/if_arp.h> 45119917Swpaul#include <net/ethernet.h> 46119917Swpaul#include <net/if_dl.h> 47119917Swpaul#include <net/if_media.h> 48119917Swpaul 49119917Swpaul#include <net/bpf.h> 50119917Swpaul 51119917Swpaul#include <net/if_types.h> 52119917Swpaul#include <net/if_vlan_var.h> 53119917Swpaul 54119917Swpaul#include <netinet/in_systm.h> 55119917Swpaul#include <netinet/in.h> 56119917Swpaul#include <netinet/ip.h> 57119917Swpaul 58119917Swpaul#include <machine/clock.h> /* for DELAY */ 59119917Swpaul#include <machine/bus_memio.h> 60119917Swpaul#include <machine/bus.h> 61119917Swpaul#include <machine/resource.h> 62119917Swpaul#include <sys/bus.h> 63119917Swpaul#include <sys/rman.h> 64119917Swpaul 65119917Swpaul#include <dev/mii/mii.h> 66119917Swpaul#include <dev/mii/miivar.h> 67119917Swpaul#include "miidevs.h" 68119917Swpaul 69119917Swpaul#include <dev/pci/pcireg.h> 70119917Swpaul#include <dev/pci/pcivar.h> 71119917Swpaul 72119917Swpaul#include <dev/bfe/if_bfereg.h> 73119917Swpaul 74119917SwpaulMODULE_DEPEND(bfe, pci, 1, 1, 1); 75119917SwpaulMODULE_DEPEND(bfe, ether, 1, 1, 1); 76119917SwpaulMODULE_DEPEND(bfe, miibus, 1, 1, 1); 77119917Swpaul 78119917Swpaul/* "controller miibus0" required. See GENERIC if you get errors here. */ 79119917Swpaul#include "miibus_if.h" 80119917Swpaul 81119917Swpaul#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 82119917Swpaul 83119917Swpaulstatic struct bfe_type bfe_devs[] = { 84119917Swpaul { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 85119917Swpaul "Broadcom BCM4401 Fast Ethernet" }, 86119917Swpaul { 0, 0, NULL } 87119917Swpaul}; 88119917Swpaul 89119917Swpaulstatic int bfe_probe (device_t); 90119917Swpaulstatic int bfe_attach (device_t); 91119917Swpaulstatic int bfe_detach (device_t); 92119917Swpaulstatic void bfe_release_resources (struct bfe_softc *); 93119917Swpaulstatic void bfe_intr (void *); 94119917Swpaulstatic void bfe_start (struct ifnet *); 95119917Swpaulstatic int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96119917Swpaulstatic void bfe_init (void *); 97119917Swpaulstatic void bfe_stop (struct bfe_softc *); 98119917Swpaulstatic void bfe_watchdog (struct ifnet *); 99119917Swpaulstatic void bfe_shutdown (device_t); 100119917Swpaulstatic void bfe_tick (void *); 101119917Swpaulstatic void bfe_txeof (struct bfe_softc *); 102119917Swpaulstatic void bfe_rxeof (struct bfe_softc *); 103119917Swpaulstatic void bfe_set_rx_mode (struct bfe_softc *); 104119917Swpaulstatic int bfe_list_rx_init (struct bfe_softc *); 105119917Swpaulstatic int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 106119917Swpaulstatic void bfe_rx_ring_free (struct bfe_softc *); 107119917Swpaul 108119917Swpaulstatic void bfe_pci_setup (struct bfe_softc *, u_int32_t); 109119917Swpaulstatic int bfe_ifmedia_upd (struct ifnet *); 110119917Swpaulstatic void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111119917Swpaulstatic int bfe_miibus_readreg (device_t, int, int); 112119917Swpaulstatic int bfe_miibus_writereg (device_t, int, int, int); 113119917Swpaulstatic void bfe_miibus_statchg (device_t); 114119917Swpaulstatic int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 115119917Swpaul u_long, const int); 116119917Swpaulstatic void bfe_get_config (struct bfe_softc *sc); 117119917Swpaulstatic void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 118119917Swpaulstatic void bfe_stats_update (struct bfe_softc *); 119119917Swpaulstatic void bfe_clear_stats (struct bfe_softc *); 120119917Swpaulstatic int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 121119917Swpaulstatic int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 122119917Swpaulstatic int bfe_resetphy (struct bfe_softc *); 123119917Swpaulstatic int bfe_setupphy (struct bfe_softc *); 124119917Swpaulstatic void bfe_chip_reset (struct bfe_softc *); 125119917Swpaulstatic void bfe_chip_halt (struct bfe_softc *); 126119917Swpaulstatic void bfe_core_reset (struct bfe_softc *); 127119917Swpaulstatic void bfe_core_disable (struct bfe_softc *); 128119917Swpaulstatic int bfe_dma_alloc (device_t); 129119917Swpaulstatic void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 130119917Swpaulstatic void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 131119917Swpaulstatic void bfe_cam_write (struct bfe_softc *, u_char *, int); 132119917Swpaul 133119917Swpaulstatic device_method_t bfe_methods[] = { 134119917Swpaul /* Device interface */ 135119917Swpaul DEVMETHOD(device_probe, bfe_probe), 136119917Swpaul DEVMETHOD(device_attach, bfe_attach), 137119917Swpaul DEVMETHOD(device_detach, bfe_detach), 138119917Swpaul DEVMETHOD(device_shutdown, bfe_shutdown), 139119917Swpaul 140119917Swpaul /* bus interface */ 141119917Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 142119917Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143119917Swpaul 144119917Swpaul /* MII interface */ 145119917Swpaul DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 146119917Swpaul DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 147119917Swpaul DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 148119917Swpaul 149119917Swpaul { 0, 0 } 150119917Swpaul}; 151119917Swpaul 152119917Swpaulstatic driver_t bfe_driver = { 153119917Swpaul "bfe", 154119917Swpaul bfe_methods, 155119917Swpaul sizeof(struct bfe_softc) 156119917Swpaul}; 157119917Swpaul 158119917Swpaulstatic devclass_t bfe_devclass; 159119917Swpaul 160119917SwpaulDRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 161119917SwpaulDRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 162119917Swpaul 163119917Swpaul/* 164119917Swpaul * Probe for a Broadcom 4401 chip. 165119917Swpaul */ 166119917Swpaulstatic int 167119917Swpaulbfe_probe(device_t dev) 168119917Swpaul{ 169119917Swpaul struct bfe_type *t; 170119917Swpaul struct bfe_softc *sc; 171119917Swpaul 172119917Swpaul t = bfe_devs; 173119917Swpaul 174119917Swpaul sc = device_get_softc(dev); 175119917Swpaul bzero(sc, sizeof(struct bfe_softc)); 176119917Swpaul sc->bfe_unit = device_get_unit(dev); 177119917Swpaul sc->bfe_dev = dev; 178119917Swpaul 179119917Swpaul while(t->bfe_name != NULL) { 180119917Swpaul if ((pci_get_vendor(dev) == t->bfe_vid) && 181119917Swpaul (pci_get_device(dev) == t->bfe_did)) { 182119917Swpaul device_set_desc_copy(dev, t->bfe_name); 183119917Swpaul return(0); 184119917Swpaul } 185119917Swpaul t++; 186119917Swpaul } 187119917Swpaul 188119917Swpaul return(ENXIO); 189119917Swpaul} 190119917Swpaul 191119917Swpaulstatic int 192119917Swpaulbfe_dma_alloc(device_t dev) 193119917Swpaul{ 194119917Swpaul struct bfe_softc *sc; 195119917Swpaul int error, i; 196119917Swpaul 197119917Swpaul sc = device_get_softc(dev); 198119917Swpaul 199119917Swpaul /* parent tag */ 200119917Swpaul error = bus_dma_tag_create(NULL, /* parent */ 201119917Swpaul PAGE_SIZE, 0, /* alignment, boundary */ 202119917Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 203119917Swpaul BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 204119917Swpaul NULL, NULL, /* filter, filterarg */ 205119917Swpaul MAXBSIZE, /* maxsize */ 206119917Swpaul BUS_SPACE_UNRESTRICTED, /* num of segments */ 207119917Swpaul BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 208119917Swpaul BUS_DMA_ALLOCNOW, /* flags */ 209119917Swpaul NULL, NULL, /* lockfunc, lockarg */ 210119917Swpaul &sc->bfe_parent_tag); 211119917Swpaul 212119917Swpaul /* tag for TX ring */ 213126470Sjulian error = bus_dma_tag_create(sc->bfe_parent_tag, 214126470Sjulian BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 215126470Sjulian BUS_SPACE_MAXADDR, 216126470Sjulian BUS_SPACE_MAXADDR, 217126470Sjulian NULL, NULL, 218126470Sjulian BFE_TX_LIST_SIZE, 219126470Sjulian 1, 220126470Sjulian BUS_SPACE_MAXSIZE_32BIT, 221126470Sjulian 0, 222126470Sjulian NULL, NULL, 223126470Sjulian &sc->bfe_tx_tag); 224119917Swpaul 225119917Swpaul if (error) { 226119917Swpaul device_printf(dev, "could not allocate dma tag\n"); 227119917Swpaul return(ENOMEM); 228119917Swpaul } 229119917Swpaul 230119917Swpaul /* tag for RX ring */ 231126470Sjulian error = bus_dma_tag_create(sc->bfe_parent_tag, 232126470Sjulian BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 233126470Sjulian BUS_SPACE_MAXADDR, 234126470Sjulian BUS_SPACE_MAXADDR, 235126470Sjulian NULL, NULL, 236126470Sjulian BFE_RX_LIST_SIZE, 237126470Sjulian 1, 238126470Sjulian BUS_SPACE_MAXSIZE_32BIT, 239126470Sjulian 0, 240126470Sjulian NULL, NULL, 241126470Sjulian &sc->bfe_rx_tag); 242119917Swpaul 243119917Swpaul if (error) { 244119917Swpaul device_printf(dev, "could not allocate dma tag\n"); 245119917Swpaul return(ENOMEM); 246119917Swpaul } 247119917Swpaul 248119917Swpaul /* tag for mbufs */ 249126470Sjulian error = bus_dma_tag_create(sc->bfe_parent_tag, 250126470Sjulian ETHER_ALIGN, 0, 251126470Sjulian BUS_SPACE_MAXADDR, 252126470Sjulian BUS_SPACE_MAXADDR, 253126470Sjulian NULL, NULL, 254126470Sjulian MCLBYTES, 255126470Sjulian 1, 256126470Sjulian BUS_SPACE_MAXSIZE_32BIT, 257126470Sjulian 0, 258126470Sjulian NULL, NULL, 259126470Sjulian &sc->bfe_tag); 260119917Swpaul 261119917Swpaul if (error) { 262119917Swpaul device_printf(dev, "could not allocate dma tag\n"); 263119917Swpaul return(ENOMEM); 264119917Swpaul } 265119917Swpaul 266119917Swpaul /* pre allocate dmamaps for RX list */ 267119917Swpaul for (i = 0; i < BFE_RX_LIST_CNT; i++) { 268126470Sjulian error = bus_dmamap_create(sc->bfe_tag, 0, 269126470Sjulian &sc->bfe_rx_ring[i].bfe_map); 270119917Swpaul if (error) { 271119917Swpaul device_printf(dev, "cannot create DMA map for RX\n"); 272119917Swpaul return(ENOMEM); 273119917Swpaul } 274119917Swpaul } 275119917Swpaul 276119917Swpaul /* pre allocate dmamaps for TX list */ 277119917Swpaul for (i = 0; i < BFE_TX_LIST_CNT; i++) { 278126470Sjulian error = bus_dmamap_create(sc->bfe_tag, 0, 279126470Sjulian &sc->bfe_tx_ring[i].bfe_map); 280119917Swpaul if (error) { 281119917Swpaul device_printf(dev, "cannot create DMA map for TX\n"); 282119917Swpaul return(ENOMEM); 283119917Swpaul } 284119917Swpaul } 285119917Swpaul 286119917Swpaul /* Alloc dma for rx ring */ 287119917Swpaul error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 288119917Swpaul BUS_DMA_NOWAIT, &sc->bfe_rx_map); 289119917Swpaul 290119917Swpaul if(error) 291119917Swpaul return(ENOMEM); 292119917Swpaul 293119917Swpaul bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 294119917Swpaul error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 295119917Swpaul sc->bfe_rx_list, sizeof(struct bfe_desc), 296119917Swpaul bfe_dma_map, &sc->bfe_rx_dma, 0); 297119917Swpaul 298119917Swpaul if(error) 299119917Swpaul return(ENOMEM); 300119917Swpaul 301119917Swpaul bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 302119917Swpaul 303119917Swpaul error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 304119917Swpaul BUS_DMA_NOWAIT, &sc->bfe_tx_map); 305119917Swpaul if (error) 306119917Swpaul return(ENOMEM); 307119917Swpaul 308119917Swpaul 309119917Swpaul error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 310119917Swpaul sc->bfe_tx_list, sizeof(struct bfe_desc), 311119917Swpaul bfe_dma_map, &sc->bfe_tx_dma, 0); 312119917Swpaul if(error) 313119917Swpaul return(ENOMEM); 314119917Swpaul 315119917Swpaul bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 316119917Swpaul bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 317119917Swpaul 318119917Swpaul return(0); 319119917Swpaul} 320119917Swpaul 321119917Swpaulstatic int 322119917Swpaulbfe_attach(device_t dev) 323119917Swpaul{ 324119917Swpaul struct ifnet *ifp; 325119917Swpaul struct bfe_softc *sc; 326119917Swpaul int unit, error = 0, rid; 327119917Swpaul 328119917Swpaul sc = device_get_softc(dev); 329119917Swpaul mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 330119917Swpaul MTX_DEF | MTX_RECURSE); 331119917Swpaul 332119917Swpaul unit = device_get_unit(dev); 333119917Swpaul sc->bfe_dev = dev; 334119917Swpaul sc->bfe_unit = unit; 335119917Swpaul 336119917Swpaul /* 337119917Swpaul * Handle power management nonsense. 338119917Swpaul */ 339119917Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 340119917Swpaul u_int32_t membase, irq; 341119917Swpaul 342119917Swpaul /* Save important PCI config data. */ 343119917Swpaul membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 344119917Swpaul irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 345119917Swpaul 346119917Swpaul /* Reset the power state. */ 347126470Sjulian printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 348119917Swpaul sc->bfe_unit, pci_get_powerstate(dev)); 349119917Swpaul 350119917Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 351119917Swpaul 352119917Swpaul /* Restore PCI config data. */ 353119917Swpaul pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 354119917Swpaul pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 355119917Swpaul } 356119917Swpaul 357119917Swpaul /* 358119917Swpaul * Map control/status registers. 359119917Swpaul */ 360119917Swpaul pci_enable_busmaster(dev); 361119917Swpaul 362119917Swpaul rid = BFE_PCI_MEMLO; 363127135Snjl sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 364119917Swpaul RF_ACTIVE); 365119917Swpaul if (sc->bfe_res == NULL) { 366119917Swpaul printf ("bfe%d: couldn't map memory\n", unit); 367119917Swpaul error = ENXIO; 368119917Swpaul goto fail; 369119917Swpaul } 370119917Swpaul 371119917Swpaul sc->bfe_btag = rman_get_bustag(sc->bfe_res); 372119917Swpaul sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 373119917Swpaul sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 374119917Swpaul 375119917Swpaul /* Allocate interrupt */ 376119917Swpaul rid = 0; 377119917Swpaul 378127135Snjl sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 379119917Swpaul RF_SHAREABLE | RF_ACTIVE); 380119917Swpaul if (sc->bfe_irq == NULL) { 381119917Swpaul printf("bfe%d: couldn't map interrupt\n", unit); 382119917Swpaul error = ENXIO; 383119917Swpaul goto fail; 384119917Swpaul } 385119917Swpaul 386119917Swpaul if (bfe_dma_alloc(dev)) { 387126470Sjulian printf("bfe%d: failed to allocate DMA resources\n", 388126470Sjulian sc->bfe_unit); 389119917Swpaul bfe_release_resources(sc); 390119917Swpaul error = ENXIO; 391119917Swpaul goto fail; 392119917Swpaul } 393119917Swpaul 394119917Swpaul /* Set up ifnet structure */ 395119917Swpaul ifp = &sc->arpcom.ac_if; 396119917Swpaul ifp->if_softc = sc; 397121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 398119917Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 399119917Swpaul ifp->if_ioctl = bfe_ioctl; 400119917Swpaul ifp->if_start = bfe_start; 401119917Swpaul ifp->if_watchdog = bfe_watchdog; 402119917Swpaul ifp->if_init = bfe_init; 403119917Swpaul ifp->if_mtu = ETHERMTU; 404129708Sdes ifp->if_baudrate = 100000000; 405131455Smlaier IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 406131455Smlaier ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 407131455Smlaier IFQ_SET_READY(&ifp->if_snd); 408119917Swpaul 409119917Swpaul bfe_get_config(sc); 410119917Swpaul 411119917Swpaul /* Reset the chip and turn on the PHY */ 412119917Swpaul bfe_chip_reset(sc); 413119917Swpaul 414119917Swpaul if (mii_phy_probe(dev, &sc->bfe_miibus, 415119917Swpaul bfe_ifmedia_upd, bfe_ifmedia_sts)) { 416119917Swpaul printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 417119917Swpaul error = ENXIO; 418119917Swpaul goto fail; 419119917Swpaul } 420119917Swpaul 421119917Swpaul ether_ifattach(ifp, sc->arpcom.ac_enaddr); 422119917Swpaul callout_handle_init(&sc->bfe_stat_ch); 423119917Swpaul 424119917Swpaul /* 425129708Sdes * Tell the upper layer(s) we support long frames. 426129708Sdes */ 427129708Sdes ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 428129708Sdes ifp->if_capabilities |= IFCAP_VLAN_MTU; 429129709Sdes ifp->if_capenable |= IFCAP_VLAN_MTU; 430129708Sdes 431129708Sdes /* 432119917Swpaul * Hook interrupt last to avoid having to lock softc 433119917Swpaul */ 434119917Swpaul error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 435119917Swpaul bfe_intr, sc, &sc->bfe_intrhand); 436119917Swpaul 437119917Swpaul if (error) { 438119917Swpaul bfe_release_resources(sc); 439119917Swpaul printf("bfe%d: couldn't set up irq\n", unit); 440119917Swpaul goto fail; 441119917Swpaul } 442119917Swpaulfail: 443119917Swpaul if(error) 444119917Swpaul bfe_release_resources(sc); 445119917Swpaul return(error); 446119917Swpaul} 447119917Swpaul 448119917Swpaulstatic int 449119917Swpaulbfe_detach(device_t dev) 450119917Swpaul{ 451119917Swpaul struct bfe_softc *sc; 452119917Swpaul struct ifnet *ifp; 453119917Swpaul 454119917Swpaul sc = device_get_softc(dev); 455119917Swpaul 456119917Swpaul KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 457119917Swpaul BFE_LOCK(scp); 458119917Swpaul 459119917Swpaul ifp = &sc->arpcom.ac_if; 460119917Swpaul 461119917Swpaul if (device_is_attached(dev)) { 462119917Swpaul bfe_stop(sc); 463119917Swpaul ether_ifdetach(ifp); 464119917Swpaul } 465119917Swpaul 466119917Swpaul bfe_chip_reset(sc); 467119917Swpaul 468119917Swpaul bus_generic_detach(dev); 469119917Swpaul if(sc->bfe_miibus != NULL) 470119917Swpaul device_delete_child(dev, sc->bfe_miibus); 471119917Swpaul 472119917Swpaul bfe_release_resources(sc); 473119917Swpaul BFE_UNLOCK(sc); 474119917Swpaul mtx_destroy(&sc->bfe_mtx); 475119917Swpaul 476119917Swpaul return(0); 477119917Swpaul} 478119917Swpaul 479119917Swpaul/* 480119917Swpaul * Stop all chip I/O so that the kernel's probe routines don't 481119917Swpaul * get confused by errant DMAs when rebooting. 482119917Swpaul */ 483119917Swpaulstatic void 484119917Swpaulbfe_shutdown(device_t dev) 485119917Swpaul{ 486119917Swpaul struct bfe_softc *sc; 487119917Swpaul 488119917Swpaul sc = device_get_softc(dev); 489119917Swpaul BFE_LOCK(sc); 490119917Swpaul bfe_stop(sc); 491119917Swpaul 492119917Swpaul BFE_UNLOCK(sc); 493119917Swpaul return; 494119917Swpaul} 495119917Swpaul 496119917Swpaulstatic int 497119917Swpaulbfe_miibus_readreg(device_t dev, int phy, int reg) 498119917Swpaul{ 499119917Swpaul struct bfe_softc *sc; 500119917Swpaul u_int32_t ret; 501119917Swpaul 502119917Swpaul sc = device_get_softc(dev); 503119917Swpaul if(phy != sc->bfe_phyaddr) 504119917Swpaul return(0); 505119917Swpaul bfe_readphy(sc, reg, &ret); 506119917Swpaul 507119917Swpaul return(ret); 508119917Swpaul} 509119917Swpaul 510119917Swpaulstatic int 511119917Swpaulbfe_miibus_writereg(device_t dev, int phy, int reg, int val) 512119917Swpaul{ 513119917Swpaul struct bfe_softc *sc; 514119917Swpaul 515119917Swpaul sc = device_get_softc(dev); 516119917Swpaul if(phy != sc->bfe_phyaddr) 517119917Swpaul return(0); 518119917Swpaul bfe_writephy(sc, reg, val); 519119917Swpaul 520119917Swpaul return(0); 521119917Swpaul} 522119917Swpaul 523119917Swpaulstatic void 524119917Swpaulbfe_miibus_statchg(device_t dev) 525119917Swpaul{ 526119917Swpaul return; 527119917Swpaul} 528119917Swpaul 529119917Swpaulstatic void 530119917Swpaulbfe_tx_ring_free(struct bfe_softc *sc) 531119917Swpaul{ 532126470Sjulian int i; 533126470Sjulian 534126470Sjulian for(i = 0; i < BFE_TX_LIST_CNT; i++) { 535126470Sjulian if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 536126470Sjulian m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 537126470Sjulian sc->bfe_tx_ring[i].bfe_mbuf = NULL; 538126470Sjulian bus_dmamap_unload(sc->bfe_tag, 539126470Sjulian sc->bfe_tx_ring[i].bfe_map); 540126470Sjulian bus_dmamap_destroy(sc->bfe_tag, 541126470Sjulian sc->bfe_tx_ring[i].bfe_map); 542126470Sjulian } 543126470Sjulian } 544126470Sjulian bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 545126470Sjulian bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 546119917Swpaul} 547119917Swpaul 548119917Swpaulstatic void 549119917Swpaulbfe_rx_ring_free(struct bfe_softc *sc) 550119917Swpaul{ 551119917Swpaul int i; 552119917Swpaul 553119917Swpaul for (i = 0; i < BFE_RX_LIST_CNT; i++) { 554119917Swpaul if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 555119917Swpaul m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 556119917Swpaul sc->bfe_rx_ring[i].bfe_mbuf = NULL; 557119917Swpaul bus_dmamap_unload(sc->bfe_tag, 558119917Swpaul sc->bfe_rx_ring[i].bfe_map); 559119917Swpaul bus_dmamap_destroy(sc->bfe_tag, 560119917Swpaul sc->bfe_rx_ring[i].bfe_map); 561119917Swpaul } 562119917Swpaul } 563119917Swpaul bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 564119917Swpaul bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 565119917Swpaul} 566119917Swpaul 567119917Swpaul 568119917Swpaulstatic int 569119917Swpaulbfe_list_rx_init(struct bfe_softc *sc) 570119917Swpaul{ 571119917Swpaul int i; 572119917Swpaul 573119917Swpaul for(i = 0; i < BFE_RX_LIST_CNT; i++) { 574119917Swpaul if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 575119917Swpaul return ENOBUFS; 576119917Swpaul } 577119917Swpaul 578119917Swpaul bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 579119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 580119917Swpaul 581119917Swpaul sc->bfe_rx_cons = 0; 582119917Swpaul 583119917Swpaul return(0); 584119917Swpaul} 585119917Swpaul 586119917Swpaulstatic int 587119917Swpaulbfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 588119917Swpaul{ 589119917Swpaul struct bfe_rxheader *rx_header; 590119917Swpaul struct bfe_desc *d; 591119917Swpaul struct bfe_data *r; 592119917Swpaul u_int32_t ctrl; 593119917Swpaul 594119917Swpaul if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 595119917Swpaul return(EINVAL); 596119917Swpaul 597119917Swpaul if(m == NULL) { 598119917Swpaul m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 599119917Swpaul if(m == NULL) 600119917Swpaul return(ENOBUFS); 601119917Swpaul m->m_len = m->m_pkthdr.len = MCLBYTES; 602119917Swpaul } 603119917Swpaul else 604119917Swpaul m->m_data = m->m_ext.ext_buf; 605119917Swpaul 606119917Swpaul rx_header = mtod(m, struct bfe_rxheader *); 607119917Swpaul rx_header->len = 0; 608119917Swpaul rx_header->flags = 0; 609119917Swpaul 610119917Swpaul /* Map the mbuf into DMA */ 611119917Swpaul sc->bfe_rx_cnt = c; 612119917Swpaul d = &sc->bfe_rx_list[c]; 613119917Swpaul r = &sc->bfe_rx_ring[c]; 614119917Swpaul bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 615119917Swpaul MCLBYTES, bfe_dma_map_desc, d, 0); 616119917Swpaul bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 617119917Swpaul 618119917Swpaul ctrl = ETHER_MAX_LEN + 32; 619119917Swpaul 620119917Swpaul if(c == BFE_RX_LIST_CNT - 1) 621119917Swpaul ctrl |= BFE_DESC_EOT; 622119917Swpaul 623119917Swpaul d->bfe_ctrl = ctrl; 624119917Swpaul r->bfe_mbuf = m; 625119917Swpaul bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 626119917Swpaul return(0); 627119917Swpaul} 628119917Swpaul 629119917Swpaulstatic void 630119917Swpaulbfe_get_config(struct bfe_softc *sc) 631119917Swpaul{ 632119917Swpaul u_int8_t eeprom[128]; 633119917Swpaul 634119917Swpaul bfe_read_eeprom(sc, eeprom); 635119917Swpaul 636119917Swpaul sc->arpcom.ac_enaddr[0] = eeprom[79]; 637119917Swpaul sc->arpcom.ac_enaddr[1] = eeprom[78]; 638119917Swpaul sc->arpcom.ac_enaddr[2] = eeprom[81]; 639119917Swpaul sc->arpcom.ac_enaddr[3] = eeprom[80]; 640119917Swpaul sc->arpcom.ac_enaddr[4] = eeprom[83]; 641119917Swpaul sc->arpcom.ac_enaddr[5] = eeprom[82]; 642119917Swpaul 643119917Swpaul sc->bfe_phyaddr = eeprom[90] & 0x1f; 644119917Swpaul sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 645119917Swpaul 646119917Swpaul sc->bfe_core_unit = 0; 647119917Swpaul sc->bfe_dma_offset = BFE_PCI_DMA; 648119917Swpaul} 649119917Swpaul 650119917Swpaulstatic void 651119917Swpaulbfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 652119917Swpaul{ 653119917Swpaul u_int32_t bar_orig, pci_rev, val; 654119917Swpaul 655119917Swpaul bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 656119917Swpaul pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 657119917Swpaul pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 658119917Swpaul 659119917Swpaul val = CSR_READ_4(sc, BFE_SBINTVEC); 660119917Swpaul val |= cores; 661119917Swpaul CSR_WRITE_4(sc, BFE_SBINTVEC, val); 662119917Swpaul 663119917Swpaul val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 664119917Swpaul val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 665119917Swpaul CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 666119917Swpaul 667119917Swpaul pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 668119917Swpaul} 669119917Swpaul 670119917Swpaulstatic void 671119917Swpaulbfe_clear_stats(struct bfe_softc *sc) 672119917Swpaul{ 673119917Swpaul u_long reg; 674119917Swpaul 675119917Swpaul BFE_LOCK(sc); 676119917Swpaul 677119917Swpaul CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 678119917Swpaul for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 679119917Swpaul CSR_READ_4(sc, reg); 680119917Swpaul for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 681119917Swpaul CSR_READ_4(sc, reg); 682119917Swpaul 683119917Swpaul BFE_UNLOCK(sc); 684119917Swpaul} 685119917Swpaul 686119917Swpaulstatic int 687119917Swpaulbfe_resetphy(struct bfe_softc *sc) 688119917Swpaul{ 689119917Swpaul u_int32_t val; 690119917Swpaul 691119917Swpaul BFE_LOCK(sc); 692119917Swpaul bfe_writephy(sc, 0, BMCR_RESET); 693119917Swpaul DELAY(100); 694119917Swpaul bfe_readphy(sc, 0, &val); 695119917Swpaul if (val & BMCR_RESET) { 696119917Swpaul printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 697119917Swpaul BFE_UNLOCK(sc); 698119917Swpaul return ENXIO; 699119917Swpaul } 700119917Swpaul BFE_UNLOCK(sc); 701119917Swpaul return 0; 702119917Swpaul} 703119917Swpaul 704119917Swpaulstatic void 705119917Swpaulbfe_chip_halt(struct bfe_softc *sc) 706119917Swpaul{ 707119917Swpaul BFE_LOCK(sc); 708119917Swpaul /* disable interrupts - not that it actually does..*/ 709119917Swpaul CSR_WRITE_4(sc, BFE_IMASK, 0); 710119917Swpaul CSR_READ_4(sc, BFE_IMASK); 711119917Swpaul 712119917Swpaul CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 713119917Swpaul bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 714119917Swpaul 715119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 716119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 717119917Swpaul DELAY(10); 718119917Swpaul 719119917Swpaul BFE_UNLOCK(sc); 720119917Swpaul} 721119917Swpaul 722119917Swpaulstatic void 723119917Swpaulbfe_chip_reset(struct bfe_softc *sc) 724119917Swpaul{ 725126470Sjulian u_int32_t val; 726119917Swpaul 727119917Swpaul BFE_LOCK(sc); 728119917Swpaul 729119917Swpaul /* Set the interrupt vector for the enet core */ 730119917Swpaul bfe_pci_setup(sc, BFE_INTVEC_ENET0); 731119917Swpaul 732119917Swpaul /* is core up? */ 733126470Sjulian val = CSR_READ_4(sc, BFE_SBTMSLOW) & 734126470Sjulian (BFE_RESET | BFE_REJECT | BFE_CLOCK); 735119917Swpaul if (val == BFE_CLOCK) { 736119917Swpaul /* It is, so shut it down */ 737119917Swpaul CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 738119917Swpaul CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 739119917Swpaul bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 740119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 741119917Swpaul sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 742119917Swpaul if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 743126470Sjulian bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 744126470Sjulian 100, 0); 745119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 746119917Swpaul sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 747119917Swpaul } 748119917Swpaul 749119917Swpaul bfe_core_reset(sc); 750119917Swpaul bfe_clear_stats(sc); 751119917Swpaul 752119917Swpaul /* 753119917Swpaul * We want the phy registers to be accessible even when 754119917Swpaul * the driver is "downed" so initialize MDC preamble, frequency, 755119917Swpaul * and whether internal or external phy here. 756119917Swpaul */ 757119917Swpaul 758119917Swpaul /* 4402 has 62.5Mhz SB clock and internal phy */ 759119917Swpaul CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 760119917Swpaul 761119917Swpaul /* Internal or external PHY? */ 762119917Swpaul val = CSR_READ_4(sc, BFE_DEVCTRL); 763119917Swpaul if(!(val & BFE_IPP)) 764119917Swpaul CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 765119917Swpaul else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 766119917Swpaul BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 767119917Swpaul DELAY(100); 768119917Swpaul } 769119917Swpaul 770129602Sdmlb /* Enable CRC32 generation and set proper LED modes */ 771129602Sdmlb BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 772129602Sdmlb 773129602Sdmlb /* Reset or clear powerdown control bit */ 774129602Sdmlb BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 775129602Sdmlb 776119917Swpaul CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 777119917Swpaul BFE_LAZY_FC_MASK)); 778119917Swpaul 779119917Swpaul /* 780126470Sjulian * We don't want lazy interrupts, so just send them at 781126470Sjulian * the end of a frame, please 782119917Swpaul */ 783119917Swpaul BFE_OR(sc, BFE_RCV_LAZY, 0); 784119917Swpaul 785119917Swpaul /* Set max lengths, accounting for VLAN tags */ 786119917Swpaul CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 787119917Swpaul CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 788119917Swpaul 789119917Swpaul /* Set watermark XXX - magic */ 790119917Swpaul CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 791119917Swpaul 792119917Swpaul /* 793126470Sjulian * Initialise DMA channels 794126470Sjulian * - not forgetting dma addresses need to be added to BFE_PCI_DMA 795119917Swpaul */ 796119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 797119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 798119917Swpaul 799119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 800119917Swpaul BFE_RX_CTRL_ENABLE); 801119917Swpaul CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 802119917Swpaul 803119917Swpaul bfe_resetphy(sc); 804119917Swpaul bfe_setupphy(sc); 805119917Swpaul 806119917Swpaul BFE_UNLOCK(sc); 807119917Swpaul} 808119917Swpaul 809119917Swpaulstatic void 810119917Swpaulbfe_core_disable(struct bfe_softc *sc) 811119917Swpaul{ 812119917Swpaul if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 813119917Swpaul return; 814119917Swpaul 815119917Swpaul /* 816126470Sjulian * Set reject, wait for it set, then wait for the core to stop 817126470Sjulian * being busy, then set reset and reject and enable the clocks. 818119917Swpaul */ 819119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 820119917Swpaul bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 821119917Swpaul bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 822119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 823119917Swpaul BFE_RESET)); 824119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 825119917Swpaul DELAY(10); 826119917Swpaul /* Leave reset and reject set */ 827119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 828119917Swpaul DELAY(10); 829119917Swpaul} 830119917Swpaul 831119917Swpaulstatic void 832119917Swpaulbfe_core_reset(struct bfe_softc *sc) 833119917Swpaul{ 834119917Swpaul u_int32_t val; 835119917Swpaul 836119917Swpaul /* Disable the core */ 837119917Swpaul bfe_core_disable(sc); 838119917Swpaul 839119917Swpaul /* and bring it back up */ 840119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 841119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 842119917Swpaul DELAY(10); 843119917Swpaul 844119917Swpaul /* Chip bug, clear SERR, IB and TO if they are set. */ 845119917Swpaul if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 846119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 847119917Swpaul val = CSR_READ_4(sc, BFE_SBIMSTATE); 848119917Swpaul if (val & (BFE_IBE | BFE_TO)) 849119917Swpaul CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 850119917Swpaul 851119917Swpaul /* Clear reset and allow it to move through the core */ 852119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 853119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 854119917Swpaul DELAY(10); 855119917Swpaul 856119917Swpaul /* Leave the clock set */ 857119917Swpaul CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 858119917Swpaul CSR_READ_4(sc, BFE_SBTMSLOW); 859119917Swpaul DELAY(10); 860119917Swpaul} 861119917Swpaul 862119917Swpaulstatic void 863119917Swpaulbfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 864119917Swpaul{ 865119917Swpaul u_int32_t val; 866119917Swpaul 867119917Swpaul val = ((u_int32_t) data[2]) << 24; 868119917Swpaul val |= ((u_int32_t) data[3]) << 16; 869119917Swpaul val |= ((u_int32_t) data[4]) << 8; 870119917Swpaul val |= ((u_int32_t) data[5]); 871119917Swpaul CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 872119917Swpaul val = (BFE_CAM_HI_VALID | 873119917Swpaul (((u_int32_t) data[0]) << 8) | 874119917Swpaul (((u_int32_t) data[1]))); 875119917Swpaul CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 876119917Swpaul CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 877129602Sdmlb ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 878119917Swpaul bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 879119917Swpaul} 880119917Swpaul 881119917Swpaulstatic void 882119917Swpaulbfe_set_rx_mode(struct bfe_softc *sc) 883119917Swpaul{ 884119917Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 885119917Swpaul struct ifmultiaddr *ifma; 886119917Swpaul u_int32_t val; 887119917Swpaul int i = 0; 888119917Swpaul 889119917Swpaul val = CSR_READ_4(sc, BFE_RXCONF); 890119917Swpaul 891119917Swpaul if (ifp->if_flags & IFF_PROMISC) 892119917Swpaul val |= BFE_RXCONF_PROMISC; 893119917Swpaul else 894119917Swpaul val &= ~BFE_RXCONF_PROMISC; 895119917Swpaul 896119917Swpaul if (ifp->if_flags & IFF_BROADCAST) 897119917Swpaul val &= ~BFE_RXCONF_DBCAST; 898119917Swpaul else 899119917Swpaul val |= BFE_RXCONF_DBCAST; 900119917Swpaul 901119917Swpaul 902119917Swpaul CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 903119917Swpaul bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 904119917Swpaul 905119917Swpaul if (ifp->if_flags & IFF_ALLMULTI) 906119917Swpaul val |= BFE_RXCONF_ALLMULTI; 907119917Swpaul else { 908119917Swpaul val &= ~BFE_RXCONF_ALLMULTI; 909119917Swpaul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 910119917Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 911119917Swpaul continue; 912126470Sjulian bfe_cam_write(sc, 913126470Sjulian LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 914119917Swpaul } 915119917Swpaul } 916119917Swpaul 917119917Swpaul CSR_WRITE_4(sc, BFE_RXCONF, val); 918119917Swpaul BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 919119917Swpaul} 920119917Swpaul 921119917Swpaulstatic void 922119917Swpaulbfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 923119917Swpaul{ 924119917Swpaul u_int32_t *ptr; 925119917Swpaul 926119917Swpaul ptr = arg; 927119917Swpaul *ptr = segs->ds_addr; 928119917Swpaul} 929119917Swpaul 930119917Swpaulstatic void 931119917Swpaulbfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 932119917Swpaul{ 933119917Swpaul struct bfe_desc *d; 934119917Swpaul 935119917Swpaul d = arg; 936119917Swpaul /* The chip needs all addresses to be added to BFE_PCI_DMA */ 937119917Swpaul d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 938119917Swpaul} 939119917Swpaul 940119917Swpaulstatic void 941119917Swpaulbfe_release_resources(struct bfe_softc *sc) 942119917Swpaul{ 943119917Swpaul device_t dev; 944119917Swpaul int i; 945119917Swpaul 946119917Swpaul dev = sc->bfe_dev; 947119917Swpaul 948119917Swpaul if (sc->bfe_vpd_prodname != NULL) 949119917Swpaul free(sc->bfe_vpd_prodname, M_DEVBUF); 950119917Swpaul 951119917Swpaul if (sc->bfe_vpd_readonly != NULL) 952119917Swpaul free(sc->bfe_vpd_readonly, M_DEVBUF); 953119917Swpaul 954119917Swpaul if (sc->bfe_intrhand != NULL) 955119917Swpaul bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 956119917Swpaul 957119917Swpaul if (sc->bfe_irq != NULL) 958119917Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 959119917Swpaul 960119917Swpaul if (sc->bfe_res != NULL) 961119917Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 962119917Swpaul 963119917Swpaul if(sc->bfe_tx_tag != NULL) { 964119917Swpaul bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 965126470Sjulian bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 966126470Sjulian sc->bfe_tx_map); 967119917Swpaul bus_dma_tag_destroy(sc->bfe_tx_tag); 968119917Swpaul sc->bfe_tx_tag = NULL; 969119917Swpaul } 970119917Swpaul 971119917Swpaul if(sc->bfe_rx_tag != NULL) { 972119917Swpaul bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 973126470Sjulian bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 974126470Sjulian sc->bfe_rx_map); 975119917Swpaul bus_dma_tag_destroy(sc->bfe_rx_tag); 976119917Swpaul sc->bfe_rx_tag = NULL; 977119917Swpaul } 978119917Swpaul 979119917Swpaul if(sc->bfe_tag != NULL) { 980119917Swpaul for(i = 0; i < BFE_TX_LIST_CNT; i++) { 981126470Sjulian bus_dmamap_destroy(sc->bfe_tag, 982126470Sjulian sc->bfe_tx_ring[i].bfe_map); 983119917Swpaul } 984119917Swpaul bus_dma_tag_destroy(sc->bfe_tag); 985126470Sjulian sc->bfe_tag = NULL; 986119917Swpaul } 987119917Swpaul 988119917Swpaul if(sc->bfe_parent_tag != NULL) 989119917Swpaul bus_dma_tag_destroy(sc->bfe_parent_tag); 990119917Swpaul 991119917Swpaul return; 992119917Swpaul} 993119917Swpaul 994119917Swpaulstatic void 995119917Swpaulbfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 996119917Swpaul{ 997119917Swpaul long i; 998119917Swpaul u_int16_t *ptr = (u_int16_t *)data; 999119917Swpaul 1000119917Swpaul for(i = 0; i < 128; i += 2) 1001119917Swpaul ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1002119917Swpaul} 1003119917Swpaul 1004119917Swpaulstatic int 1005119917Swpaulbfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1006119917Swpaul u_long timeout, const int clear) 1007119917Swpaul{ 1008119917Swpaul u_long i; 1009119917Swpaul 1010119917Swpaul for (i = 0; i < timeout; i++) { 1011119917Swpaul u_int32_t val = CSR_READ_4(sc, reg); 1012119917Swpaul 1013119917Swpaul if (clear && !(val & bit)) 1014119917Swpaul break; 1015119917Swpaul if (!clear && (val & bit)) 1016119917Swpaul break; 1017119917Swpaul DELAY(10); 1018119917Swpaul } 1019119917Swpaul if (i == timeout) { 1020119917Swpaul printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1021119917Swpaul "%x to %s.\n", sc->bfe_unit, bit, reg, 1022119917Swpaul (clear ? "clear" : "set")); 1023119917Swpaul return -1; 1024119917Swpaul } 1025119917Swpaul return 0; 1026119917Swpaul} 1027119917Swpaul 1028119917Swpaulstatic int 1029119917Swpaulbfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1030119917Swpaul{ 1031119917Swpaul int err; 1032119917Swpaul 1033119917Swpaul BFE_LOCK(sc); 1034119917Swpaul /* Clear MII ISR */ 1035119917Swpaul CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1036119917Swpaul CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1037119917Swpaul (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1038119917Swpaul (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1039119917Swpaul (reg << BFE_MDIO_RA_SHIFT) | 1040119917Swpaul (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1041119917Swpaul err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1042119917Swpaul *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1043119917Swpaul 1044119917Swpaul BFE_UNLOCK(sc); 1045119917Swpaul return err; 1046119917Swpaul} 1047119917Swpaul 1048119917Swpaulstatic int 1049119917Swpaulbfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1050119917Swpaul{ 1051119917Swpaul int status; 1052119917Swpaul 1053119917Swpaul BFE_LOCK(sc); 1054119917Swpaul CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1055119917Swpaul CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1056119917Swpaul (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1057119917Swpaul (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1058119917Swpaul (reg << BFE_MDIO_RA_SHIFT) | 1059119917Swpaul (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1060119917Swpaul (val & BFE_MDIO_DATA_DATA))); 1061119917Swpaul status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1062119917Swpaul BFE_UNLOCK(sc); 1063119917Swpaul 1064119917Swpaul return status; 1065119917Swpaul} 1066119917Swpaul 1067119917Swpaul/* 1068119917Swpaul * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1069119917Swpaul * twice 1070119917Swpaul */ 1071119917Swpaulstatic int 1072119917Swpaulbfe_setupphy(struct bfe_softc *sc) 1073119917Swpaul{ 1074119917Swpaul u_int32_t val; 1075119917Swpaul BFE_LOCK(sc); 1076119917Swpaul 1077119917Swpaul /* Enable activity LED */ 1078119917Swpaul bfe_readphy(sc, 26, &val); 1079119917Swpaul bfe_writephy(sc, 26, val & 0x7fff); 1080119917Swpaul bfe_readphy(sc, 26, &val); 1081119917Swpaul 1082119917Swpaul /* Enable traffic meter LED mode */ 1083119917Swpaul bfe_readphy(sc, 27, &val); 1084119917Swpaul bfe_writephy(sc, 27, val | (1 << 6)); 1085119917Swpaul 1086119917Swpaul BFE_UNLOCK(sc); 1087119917Swpaul return 0; 1088119917Swpaul} 1089119917Swpaul 1090119917Swpaulstatic void 1091119917Swpaulbfe_stats_update(struct bfe_softc *sc) 1092119917Swpaul{ 1093119917Swpaul u_long reg; 1094119917Swpaul u_int32_t *val; 1095119917Swpaul 1096119917Swpaul val = &sc->bfe_hwstats.tx_good_octets; 1097119917Swpaul for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1098119917Swpaul *val++ += CSR_READ_4(sc, reg); 1099119917Swpaul } 1100119917Swpaul val = &sc->bfe_hwstats.rx_good_octets; 1101119917Swpaul for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1102119917Swpaul *val++ += CSR_READ_4(sc, reg); 1103119917Swpaul } 1104119917Swpaul} 1105119917Swpaul 1106119917Swpaulstatic void 1107119917Swpaulbfe_txeof(struct bfe_softc *sc) 1108119917Swpaul{ 1109119917Swpaul struct ifnet *ifp; 1110119917Swpaul int i, chipidx; 1111119917Swpaul 1112119917Swpaul BFE_LOCK(sc); 1113119917Swpaul 1114119917Swpaul ifp = &sc->arpcom.ac_if; 1115119917Swpaul 1116119917Swpaul chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1117119917Swpaul chipidx /= sizeof(struct bfe_desc); 1118119917Swpaul 1119126470Sjulian i = sc->bfe_tx_cons; 1120119917Swpaul /* Go through the mbufs and free those that have been transmitted */ 1121126470Sjulian while(i != chipidx) { 1122119917Swpaul struct bfe_data *r = &sc->bfe_tx_ring[i]; 1123119917Swpaul if(r->bfe_mbuf != NULL) { 1124119917Swpaul ifp->if_opackets++; 1125119917Swpaul m_freem(r->bfe_mbuf); 1126119917Swpaul r->bfe_mbuf = NULL; 1127119917Swpaul bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1128119917Swpaul } 1129126470Sjulian sc->bfe_tx_cnt--; 1130126470Sjulian BFE_INC(i, BFE_TX_LIST_CNT); 1131119917Swpaul } 1132119917Swpaul 1133119917Swpaul if(i != sc->bfe_tx_cons) { 1134119917Swpaul /* we freed up some mbufs */ 1135119917Swpaul sc->bfe_tx_cons = i; 1136119917Swpaul ifp->if_flags &= ~IFF_OACTIVE; 1137119917Swpaul } 1138119917Swpaul if(sc->bfe_tx_cnt == 0) 1139119917Swpaul ifp->if_timer = 0; 1140119917Swpaul else 1141119917Swpaul ifp->if_timer = 5; 1142119917Swpaul 1143119917Swpaul BFE_UNLOCK(sc); 1144119917Swpaul} 1145119917Swpaul 1146119917Swpaul/* Pass a received packet up the stack */ 1147119917Swpaulstatic void 1148119917Swpaulbfe_rxeof(struct bfe_softc *sc) 1149119917Swpaul{ 1150119917Swpaul struct mbuf *m; 1151119917Swpaul struct ifnet *ifp; 1152119917Swpaul struct bfe_rxheader *rxheader; 1153119917Swpaul struct bfe_data *r; 1154119917Swpaul int cons; 1155119917Swpaul u_int32_t status, current, len, flags; 1156119917Swpaul 1157119917Swpaul BFE_LOCK(sc); 1158119917Swpaul cons = sc->bfe_rx_cons; 1159119917Swpaul status = CSR_READ_4(sc, BFE_DMARX_STAT); 1160119917Swpaul current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1161119917Swpaul 1162119917Swpaul ifp = &sc->arpcom.ac_if; 1163119917Swpaul 1164119917Swpaul while(current != cons) { 1165119917Swpaul r = &sc->bfe_rx_ring[cons]; 1166119917Swpaul m = r->bfe_mbuf; 1167119917Swpaul rxheader = mtod(m, struct bfe_rxheader*); 1168119917Swpaul bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1169119917Swpaul len = rxheader->len; 1170119917Swpaul r->bfe_mbuf = NULL; 1171119917Swpaul 1172119917Swpaul bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1173119917Swpaul flags = rxheader->flags; 1174119917Swpaul 1175119917Swpaul len -= ETHER_CRC_LEN; 1176119917Swpaul 1177119917Swpaul /* flag an error and try again */ 1178119917Swpaul if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1179119917Swpaul ifp->if_ierrors++; 1180119917Swpaul if (flags & BFE_RX_FLAG_SERR) 1181119917Swpaul ifp->if_collisions++; 1182119917Swpaul bfe_list_newbuf(sc, cons, m); 1183126473Sjulian BFE_INC(cons, BFE_RX_LIST_CNT); 1184119917Swpaul continue; 1185119917Swpaul } 1186119917Swpaul 1187119917Swpaul /* Go past the rx header */ 1188119917Swpaul if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1189119917Swpaul m_adj(m, BFE_RX_OFFSET); 1190119917Swpaul m->m_len = m->m_pkthdr.len = len; 1191119917Swpaul } else { 1192119917Swpaul bfe_list_newbuf(sc, cons, m); 1193119917Swpaul ifp->if_ierrors++; 1194126473Sjulian BFE_INC(cons, BFE_RX_LIST_CNT); 1195119917Swpaul continue; 1196119917Swpaul } 1197119917Swpaul 1198119917Swpaul ifp->if_ipackets++; 1199119917Swpaul m->m_pkthdr.rcvif = ifp; 1200122689Ssam BFE_UNLOCK(sc); 1201119917Swpaul (*ifp->if_input)(ifp, m); 1202122689Ssam BFE_LOCK(sc); 1203119917Swpaul 1204126470Sjulian BFE_INC(cons, BFE_RX_LIST_CNT); 1205119917Swpaul } 1206119917Swpaul sc->bfe_rx_cons = cons; 1207119917Swpaul BFE_UNLOCK(sc); 1208119917Swpaul} 1209119917Swpaul 1210119917Swpaulstatic void 1211119917Swpaulbfe_intr(void *xsc) 1212119917Swpaul{ 1213119917Swpaul struct bfe_softc *sc = xsc; 1214119917Swpaul struct ifnet *ifp; 1215119917Swpaul u_int32_t istat, imask, flag; 1216119917Swpaul 1217119917Swpaul ifp = &sc->arpcom.ac_if; 1218119917Swpaul 1219119917Swpaul BFE_LOCK(sc); 1220119917Swpaul 1221119917Swpaul istat = CSR_READ_4(sc, BFE_ISTAT); 1222119917Swpaul imask = CSR_READ_4(sc, BFE_IMASK); 1223119917Swpaul 1224119917Swpaul /* 1225119917Swpaul * Defer unsolicited interrupts - This is necessary because setting the 1226119917Swpaul * chips interrupt mask register to 0 doesn't actually stop the 1227119917Swpaul * interrupts 1228119917Swpaul */ 1229119917Swpaul istat &= imask; 1230119917Swpaul CSR_WRITE_4(sc, BFE_ISTAT, istat); 1231119917Swpaul CSR_READ_4(sc, BFE_ISTAT); 1232119917Swpaul 1233119917Swpaul /* not expecting this interrupt, disregard it */ 1234119917Swpaul if(istat == 0) { 1235119917Swpaul BFE_UNLOCK(sc); 1236119917Swpaul return; 1237119917Swpaul } 1238119917Swpaul 1239119917Swpaul if(istat & BFE_ISTAT_ERRORS) { 1240119917Swpaul flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1241119917Swpaul if(flag & BFE_STAT_EMASK) 1242119917Swpaul ifp->if_oerrors++; 1243119917Swpaul 1244119917Swpaul flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1245119917Swpaul if(flag & BFE_RX_FLAG_ERRORS) 1246119917Swpaul ifp->if_ierrors++; 1247119917Swpaul 1248119917Swpaul ifp->if_flags &= ~IFF_RUNNING; 1249119917Swpaul bfe_init(sc); 1250119917Swpaul } 1251119917Swpaul 1252119917Swpaul /* A packet was received */ 1253119917Swpaul if(istat & BFE_ISTAT_RX) 1254119917Swpaul bfe_rxeof(sc); 1255119917Swpaul 1256119917Swpaul /* A packet was sent */ 1257119917Swpaul if(istat & BFE_ISTAT_TX) 1258119917Swpaul bfe_txeof(sc); 1259119917Swpaul 1260119917Swpaul /* We have packets pending, fire them out */ 1261131455Smlaier if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1262119917Swpaul bfe_start(ifp); 1263119917Swpaul 1264119917Swpaul BFE_UNLOCK(sc); 1265119917Swpaul} 1266119917Swpaul 1267119917Swpaulstatic int 1268119917Swpaulbfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1269119917Swpaul{ 1270119917Swpaul struct bfe_desc *d = NULL; 1271119917Swpaul struct bfe_data *r = NULL; 1272126470Sjulian struct mbuf *m; 1273126470Sjulian u_int32_t frag, cur, cnt = 0; 1274119917Swpaul int chainlen = 0; 1275119917Swpaul 1276119917Swpaul if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1277119917Swpaul return(ENOBUFS); 1278119917Swpaul 1279119917Swpaul /* 1280119917Swpaul * Count the number of frags in this chain to see if 1281119917Swpaul * we need to m_defrag. Since the descriptor list is shared 1282119917Swpaul * by all packets, we'll m_defrag long chains so that they 1283119917Swpaul * do not use up the entire list, even if they would fit. 1284119917Swpaul */ 1285119917Swpaul for(m = m_head; m != NULL; m = m->m_next) 1286119917Swpaul chainlen++; 1287119917Swpaul 1288119917Swpaul 1289119917Swpaul if ((chainlen > BFE_TX_LIST_CNT / 4) || 1290119917Swpaul ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1291119917Swpaul m = m_defrag(m_head, M_DONTWAIT); 1292119917Swpaul if (m == NULL) 1293119917Swpaul return(ENOBUFS); 1294119917Swpaul m_head = m; 1295119917Swpaul } 1296119917Swpaul 1297119917Swpaul /* 1298119917Swpaul * Start packing the mbufs in this chain into 1299119917Swpaul * the fragment pointers. Stop when we run out 1300119917Swpaul * of fragments or hit the end of the mbuf chain. 1301119917Swpaul */ 1302119917Swpaul m = m_head; 1303119917Swpaul cur = frag = *txidx; 1304119917Swpaul cnt = 0; 1305119917Swpaul 1306119917Swpaul for(m = m_head; m != NULL; m = m->m_next) { 1307119917Swpaul if(m->m_len != 0) { 1308119917Swpaul if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1309119917Swpaul return(ENOBUFS); 1310119917Swpaul 1311119917Swpaul d = &sc->bfe_tx_list[cur]; 1312119917Swpaul r = &sc->bfe_tx_ring[cur]; 1313119917Swpaul d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1314119917Swpaul /* always intterupt on completion */ 1315119917Swpaul d->bfe_ctrl |= BFE_DESC_IOC; 1316119917Swpaul if(cnt == 0) 1317119917Swpaul /* Set start of frame */ 1318119917Swpaul d->bfe_ctrl |= BFE_DESC_SOF; 1319119917Swpaul if(cur == BFE_TX_LIST_CNT - 1) 1320126470Sjulian /* 1321126470Sjulian * Tell the chip to wrap to the start of 1322126470Sjulian * the descriptor list 1323126470Sjulian */ 1324119917Swpaul d->bfe_ctrl |= BFE_DESC_EOT; 1325119917Swpaul 1326126470Sjulian bus_dmamap_load(sc->bfe_tag, 1327126470Sjulian r->bfe_map, mtod(m, void*), m->m_len, 1328126470Sjulian bfe_dma_map_desc, d, 0); 1329126470Sjulian bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1330126470Sjulian BUS_DMASYNC_PREREAD); 1331119917Swpaul 1332119917Swpaul frag = cur; 1333126470Sjulian BFE_INC(cur, BFE_TX_LIST_CNT); 1334119917Swpaul cnt++; 1335119917Swpaul } 1336119917Swpaul } 1337119917Swpaul 1338119917Swpaul if (m != NULL) 1339119917Swpaul return(ENOBUFS); 1340119917Swpaul 1341119917Swpaul sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1342119917Swpaul sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1343119917Swpaul bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1344119917Swpaul 1345119917Swpaul *txidx = cur; 1346119917Swpaul sc->bfe_tx_cnt += cnt; 1347119917Swpaul return (0); 1348119917Swpaul} 1349119917Swpaul 1350119917Swpaul/* 1351119917Swpaul * Set up to transmit a packet 1352119917Swpaul */ 1353119917Swpaulstatic void 1354119917Swpaulbfe_start(struct ifnet *ifp) 1355119917Swpaul{ 1356119917Swpaul struct bfe_softc *sc; 1357119917Swpaul struct mbuf *m_head = NULL; 1358119917Swpaul int idx; 1359119917Swpaul 1360119917Swpaul sc = ifp->if_softc; 1361119917Swpaul idx = sc->bfe_tx_prod; 1362119917Swpaul 1363119917Swpaul BFE_LOCK(sc); 1364119917Swpaul 1365119917Swpaul /* 1366126470Sjulian * Not much point trying to send if the link is down 1367126470Sjulian * or we have nothing to send. 1368119917Swpaul */ 1369119917Swpaul if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1370119917Swpaul BFE_UNLOCK(sc); 1371119917Swpaul return; 1372119917Swpaul } 1373119917Swpaul 1374119917Swpaul if (ifp->if_flags & IFF_OACTIVE) { 1375119917Swpaul BFE_UNLOCK(sc); 1376119917Swpaul return; 1377119917Swpaul } 1378119917Swpaul 1379119917Swpaul while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1380131455Smlaier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1381119917Swpaul if(m_head == NULL) 1382119917Swpaul break; 1383119917Swpaul 1384119917Swpaul /* 1385126470Sjulian * Pack the data into the tx ring. If we dont have 1386126470Sjulian * enough room, let the chip drain the ring. 1387119917Swpaul */ 1388119917Swpaul if(bfe_encap(sc, m_head, &idx)) { 1389131455Smlaier IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1390119917Swpaul ifp->if_flags |= IFF_OACTIVE; 1391119917Swpaul break; 1392119917Swpaul } 1393119917Swpaul 1394119917Swpaul /* 1395119917Swpaul * If there's a BPF listener, bounce a copy of this frame 1396119917Swpaul * to him. 1397119917Swpaul */ 1398119917Swpaul BPF_MTAP(ifp, m_head); 1399119917Swpaul } 1400119917Swpaul 1401119917Swpaul sc->bfe_tx_prod = idx; 1402119917Swpaul /* Transmit - twice due to apparent hardware bug */ 1403119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1404119917Swpaul CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1405119917Swpaul 1406119917Swpaul /* 1407119917Swpaul * Set a timeout in case the chip goes out to lunch. 1408119917Swpaul */ 1409119917Swpaul ifp->if_timer = 5; 1410119917Swpaul BFE_UNLOCK(sc); 1411119917Swpaul} 1412119917Swpaul 1413119917Swpaulstatic void 1414119917Swpaulbfe_init(void *xsc) 1415119917Swpaul{ 1416119917Swpaul struct bfe_softc *sc = (struct bfe_softc*)xsc; 1417119917Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 1418119917Swpaul 1419119917Swpaul BFE_LOCK(sc); 1420119917Swpaul 1421119917Swpaul if (ifp->if_flags & IFF_RUNNING) { 1422119917Swpaul BFE_UNLOCK(sc); 1423119917Swpaul return; 1424119917Swpaul } 1425119917Swpaul 1426119917Swpaul bfe_stop(sc); 1427119917Swpaul bfe_chip_reset(sc); 1428119917Swpaul 1429119917Swpaul if (bfe_list_rx_init(sc) == ENOBUFS) { 1430126470Sjulian printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1431126470Sjulian sc->bfe_unit); 1432119917Swpaul bfe_stop(sc); 1433119917Swpaul return; 1434119917Swpaul } 1435119917Swpaul 1436119917Swpaul bfe_set_rx_mode(sc); 1437119917Swpaul 1438119917Swpaul /* Enable the chip and core */ 1439119917Swpaul BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1440119917Swpaul /* Enable interrupts */ 1441119917Swpaul CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1442119917Swpaul 1443119917Swpaul bfe_ifmedia_upd(ifp); 1444119917Swpaul ifp->if_flags |= IFF_RUNNING; 1445119917Swpaul ifp->if_flags &= ~IFF_OACTIVE; 1446119917Swpaul 1447119917Swpaul sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1448119917Swpaul BFE_UNLOCK(sc); 1449119917Swpaul} 1450119917Swpaul 1451119917Swpaul/* 1452119917Swpaul * Set media options. 1453119917Swpaul */ 1454119917Swpaulstatic int 1455119917Swpaulbfe_ifmedia_upd(struct ifnet *ifp) 1456119917Swpaul{ 1457119917Swpaul struct bfe_softc *sc; 1458119917Swpaul struct mii_data *mii; 1459119917Swpaul 1460119917Swpaul sc = ifp->if_softc; 1461119917Swpaul 1462119917Swpaul BFE_LOCK(sc); 1463119917Swpaul 1464119917Swpaul mii = device_get_softc(sc->bfe_miibus); 1465119917Swpaul sc->bfe_link = 0; 1466119917Swpaul if (mii->mii_instance) { 1467119917Swpaul struct mii_softc *miisc; 1468119917Swpaul for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1469119917Swpaul miisc = LIST_NEXT(miisc, mii_list)) 1470119917Swpaul mii_phy_reset(miisc); 1471119917Swpaul } 1472119917Swpaul mii_mediachg(mii); 1473119917Swpaul 1474119917Swpaul BFE_UNLOCK(sc); 1475119917Swpaul return(0); 1476119917Swpaul} 1477119917Swpaul 1478119917Swpaul/* 1479119917Swpaul * Report current media status. 1480119917Swpaul */ 1481119917Swpaulstatic void 1482119917Swpaulbfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1483119917Swpaul{ 1484119917Swpaul struct bfe_softc *sc = ifp->if_softc; 1485119917Swpaul struct mii_data *mii; 1486119917Swpaul 1487119917Swpaul BFE_LOCK(sc); 1488119917Swpaul 1489119917Swpaul mii = device_get_softc(sc->bfe_miibus); 1490119917Swpaul mii_pollstat(mii); 1491119917Swpaul ifmr->ifm_active = mii->mii_media_active; 1492119917Swpaul ifmr->ifm_status = mii->mii_media_status; 1493119917Swpaul 1494119917Swpaul BFE_UNLOCK(sc); 1495119917Swpaul} 1496119917Swpaul 1497119917Swpaulstatic int 1498119917Swpaulbfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1499119917Swpaul{ 1500119917Swpaul struct bfe_softc *sc = ifp->if_softc; 1501119917Swpaul struct ifreq *ifr = (struct ifreq *) data; 1502119917Swpaul struct mii_data *mii; 1503119917Swpaul int error = 0; 1504119917Swpaul 1505119917Swpaul BFE_LOCK(sc); 1506119917Swpaul 1507119917Swpaul switch(command) { 1508119917Swpaul case SIOCSIFFLAGS: 1509119917Swpaul if(ifp->if_flags & IFF_UP) 1510119917Swpaul if(ifp->if_flags & IFF_RUNNING) 1511119917Swpaul bfe_set_rx_mode(sc); 1512119917Swpaul else 1513119917Swpaul bfe_init(sc); 1514119917Swpaul else if(ifp->if_flags & IFF_RUNNING) 1515119917Swpaul bfe_stop(sc); 1516119917Swpaul break; 1517119917Swpaul case SIOCADDMULTI: 1518119917Swpaul case SIOCDELMULTI: 1519119917Swpaul if(ifp->if_flags & IFF_RUNNING) 1520119917Swpaul bfe_set_rx_mode(sc); 1521119917Swpaul break; 1522119917Swpaul case SIOCGIFMEDIA: 1523119917Swpaul case SIOCSIFMEDIA: 1524119917Swpaul mii = device_get_softc(sc->bfe_miibus); 1525126470Sjulian error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1526126470Sjulian command); 1527119917Swpaul break; 1528119917Swpaul default: 1529119917Swpaul error = ether_ioctl(ifp, command, data); 1530119917Swpaul break; 1531119917Swpaul } 1532119917Swpaul 1533119917Swpaul BFE_UNLOCK(sc); 1534119917Swpaul return error; 1535119917Swpaul} 1536119917Swpaul 1537119917Swpaulstatic void 1538119917Swpaulbfe_watchdog(struct ifnet *ifp) 1539119917Swpaul{ 1540119917Swpaul struct bfe_softc *sc; 1541119917Swpaul 1542119917Swpaul sc = ifp->if_softc; 1543119917Swpaul 1544119917Swpaul BFE_LOCK(sc); 1545119917Swpaul 1546119917Swpaul printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1547119917Swpaul 1548119917Swpaul ifp->if_flags &= ~IFF_RUNNING; 1549119917Swpaul bfe_init(sc); 1550119917Swpaul 1551119917Swpaul ifp->if_oerrors++; 1552119917Swpaul 1553119917Swpaul BFE_UNLOCK(sc); 1554119917Swpaul} 1555119917Swpaul 1556119917Swpaulstatic void 1557119917Swpaulbfe_tick(void *xsc) 1558119917Swpaul{ 1559119917Swpaul struct bfe_softc *sc = xsc; 1560119917Swpaul struct mii_data *mii; 1561119917Swpaul 1562119917Swpaul if (sc == NULL) 1563119917Swpaul return; 1564119917Swpaul 1565119917Swpaul BFE_LOCK(sc); 1566119917Swpaul 1567119917Swpaul mii = device_get_softc(sc->bfe_miibus); 1568119917Swpaul 1569119917Swpaul bfe_stats_update(sc); 1570119917Swpaul sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1571119917Swpaul 1572119917Swpaul if(sc->bfe_link) { 1573119917Swpaul BFE_UNLOCK(sc); 1574119917Swpaul return; 1575119917Swpaul } 1576119917Swpaul 1577119917Swpaul mii_tick(mii); 1578119917Swpaul if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1579119917Swpaul IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1580119917Swpaul sc->bfe_link++; 1581119917Swpaul 1582119917Swpaul BFE_UNLOCK(sc); 1583119917Swpaul} 1584119917Swpaul 1585119917Swpaul/* 1586119917Swpaul * Stop the adapter and free any mbufs allocated to the 1587119917Swpaul * RX and TX lists. 1588119917Swpaul */ 1589119917Swpaulstatic void 1590119917Swpaulbfe_stop(struct bfe_softc *sc) 1591119917Swpaul{ 1592119917Swpaul struct ifnet *ifp; 1593119917Swpaul 1594119917Swpaul BFE_LOCK(sc); 1595119917Swpaul 1596119917Swpaul untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1597119917Swpaul 1598119917Swpaul ifp = &sc->arpcom.ac_if; 1599119917Swpaul 1600119917Swpaul bfe_chip_halt(sc); 1601126470Sjulian bfe_tx_ring_free(sc); 1602119917Swpaul bfe_rx_ring_free(sc); 1603119917Swpaul 1604119917Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1605119917Swpaul 1606119917Swpaul BFE_UNLOCK(sc); 1607119917Swpaul} 1608