if_bfe.c revision 129879
1/* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 */ 5 6/* 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 129879 2004-05-30 20:08:47Z phk $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/sockio.h> 36#include <sys/mbuf.h> 37#include <sys/malloc.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/socket.h> 41#include <sys/queue.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48 49#include <net/bpf.h> 50 51#include <net/if_types.h> 52#include <net/if_vlan_var.h> 53 54#include <netinet/in_systm.h> 55#include <netinet/in.h> 56#include <netinet/ip.h> 57 58#include <machine/clock.h> /* for DELAY */ 59#include <machine/bus_memio.h> 60#include <machine/bus.h> 61#include <machine/resource.h> 62#include <sys/bus.h> 63#include <sys/rman.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67#include "miidevs.h" 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <dev/bfe/if_bfereg.h> 73 74MODULE_DEPEND(bfe, pci, 1, 1, 1); 75MODULE_DEPEND(bfe, ether, 1, 1, 1); 76MODULE_DEPEND(bfe, miibus, 1, 1, 1); 77 78/* "controller miibus0" required. See GENERIC if you get errors here. */ 79#include "miibus_if.h" 80 81#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 82 83static struct bfe_type bfe_devs[] = { 84 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 85 "Broadcom BCM4401 Fast Ethernet" }, 86 { 0, 0, NULL } 87}; 88 89static int bfe_probe (device_t); 90static int bfe_attach (device_t); 91static int bfe_detach (device_t); 92static void bfe_release_resources (struct bfe_softc *); 93static void bfe_intr (void *); 94static void bfe_start (struct ifnet *); 95static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96static void bfe_init (void *); 97static void bfe_stop (struct bfe_softc *); 98static void bfe_watchdog (struct ifnet *); 99static void bfe_shutdown (device_t); 100static void bfe_tick (void *); 101static void bfe_txeof (struct bfe_softc *); 102static void bfe_rxeof (struct bfe_softc *); 103static void bfe_set_rx_mode (struct bfe_softc *); 104static int bfe_list_rx_init (struct bfe_softc *); 105static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 106static void bfe_rx_ring_free (struct bfe_softc *); 107 108static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 109static int bfe_ifmedia_upd (struct ifnet *); 110static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111static int bfe_miibus_readreg (device_t, int, int); 112static int bfe_miibus_writereg (device_t, int, int, int); 113static void bfe_miibus_statchg (device_t); 114static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 115 u_long, const int); 116static void bfe_get_config (struct bfe_softc *sc); 117static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 118static void bfe_stats_update (struct bfe_softc *); 119static void bfe_clear_stats (struct bfe_softc *); 120static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 121static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 122static int bfe_resetphy (struct bfe_softc *); 123static int bfe_setupphy (struct bfe_softc *); 124static void bfe_chip_reset (struct bfe_softc *); 125static void bfe_chip_halt (struct bfe_softc *); 126static void bfe_core_reset (struct bfe_softc *); 127static void bfe_core_disable (struct bfe_softc *); 128static int bfe_dma_alloc (device_t); 129static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 130static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 131static void bfe_cam_write (struct bfe_softc *, u_char *, int); 132 133static device_method_t bfe_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, bfe_probe), 136 DEVMETHOD(device_attach, bfe_attach), 137 DEVMETHOD(device_detach, bfe_detach), 138 DEVMETHOD(device_shutdown, bfe_shutdown), 139 140 /* bus interface */ 141 DEVMETHOD(bus_print_child, bus_generic_print_child), 142 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143 144 /* MII interface */ 145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 148 149 { 0, 0 } 150}; 151 152static driver_t bfe_driver = { 153 "bfe", 154 bfe_methods, 155 sizeof(struct bfe_softc) 156}; 157 158static devclass_t bfe_devclass; 159 160DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 161DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 162 163/* 164 * Probe for a Broadcom 4401 chip. 165 */ 166static int 167bfe_probe(device_t dev) 168{ 169 struct bfe_type *t; 170 struct bfe_softc *sc; 171 172 t = bfe_devs; 173 174 sc = device_get_softc(dev); 175 bzero(sc, sizeof(struct bfe_softc)); 176 sc->bfe_unit = device_get_unit(dev); 177 sc->bfe_dev = dev; 178 179 while(t->bfe_name != NULL) { 180 if ((pci_get_vendor(dev) == t->bfe_vid) && 181 (pci_get_device(dev) == t->bfe_did)) { 182 device_set_desc_copy(dev, t->bfe_name); 183 return(0); 184 } 185 t++; 186 } 187 188 return(ENXIO); 189} 190 191static int 192bfe_dma_alloc(device_t dev) 193{ 194 struct bfe_softc *sc; 195 int error, i; 196 197 sc = device_get_softc(dev); 198 199 /* parent tag */ 200 error = bus_dma_tag_create(NULL, /* parent */ 201 PAGE_SIZE, 0, /* alignment, boundary */ 202 BUS_SPACE_MAXADDR, /* lowaddr */ 203 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 204 NULL, NULL, /* filter, filterarg */ 205 MAXBSIZE, /* maxsize */ 206 BUS_SPACE_UNRESTRICTED, /* num of segments */ 207 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 208 BUS_DMA_ALLOCNOW, /* flags */ 209 NULL, NULL, /* lockfunc, lockarg */ 210 &sc->bfe_parent_tag); 211 212 /* tag for TX ring */ 213 error = bus_dma_tag_create(sc->bfe_parent_tag, 214 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 215 BUS_SPACE_MAXADDR, 216 BUS_SPACE_MAXADDR, 217 NULL, NULL, 218 BFE_TX_LIST_SIZE, 219 1, 220 BUS_SPACE_MAXSIZE_32BIT, 221 0, 222 NULL, NULL, 223 &sc->bfe_tx_tag); 224 225 if (error) { 226 device_printf(dev, "could not allocate dma tag\n"); 227 return(ENOMEM); 228 } 229 230 /* tag for RX ring */ 231 error = bus_dma_tag_create(sc->bfe_parent_tag, 232 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 233 BUS_SPACE_MAXADDR, 234 BUS_SPACE_MAXADDR, 235 NULL, NULL, 236 BFE_RX_LIST_SIZE, 237 1, 238 BUS_SPACE_MAXSIZE_32BIT, 239 0, 240 NULL, NULL, 241 &sc->bfe_rx_tag); 242 243 if (error) { 244 device_printf(dev, "could not allocate dma tag\n"); 245 return(ENOMEM); 246 } 247 248 /* tag for mbufs */ 249 error = bus_dma_tag_create(sc->bfe_parent_tag, 250 ETHER_ALIGN, 0, 251 BUS_SPACE_MAXADDR, 252 BUS_SPACE_MAXADDR, 253 NULL, NULL, 254 MCLBYTES, 255 1, 256 BUS_SPACE_MAXSIZE_32BIT, 257 0, 258 NULL, NULL, 259 &sc->bfe_tag); 260 261 if (error) { 262 device_printf(dev, "could not allocate dma tag\n"); 263 return(ENOMEM); 264 } 265 266 /* pre allocate dmamaps for RX list */ 267 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 268 error = bus_dmamap_create(sc->bfe_tag, 0, 269 &sc->bfe_rx_ring[i].bfe_map); 270 if (error) { 271 device_printf(dev, "cannot create DMA map for RX\n"); 272 return(ENOMEM); 273 } 274 } 275 276 /* pre allocate dmamaps for TX list */ 277 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 278 error = bus_dmamap_create(sc->bfe_tag, 0, 279 &sc->bfe_tx_ring[i].bfe_map); 280 if (error) { 281 device_printf(dev, "cannot create DMA map for TX\n"); 282 return(ENOMEM); 283 } 284 } 285 286 /* Alloc dma for rx ring */ 287 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 288 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 289 290 if(error) 291 return(ENOMEM); 292 293 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 294 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 295 sc->bfe_rx_list, sizeof(struct bfe_desc), 296 bfe_dma_map, &sc->bfe_rx_dma, 0); 297 298 if(error) 299 return(ENOMEM); 300 301 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 302 303 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 304 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 305 if (error) 306 return(ENOMEM); 307 308 309 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 310 sc->bfe_tx_list, sizeof(struct bfe_desc), 311 bfe_dma_map, &sc->bfe_tx_dma, 0); 312 if(error) 313 return(ENOMEM); 314 315 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 316 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 317 318 return(0); 319} 320 321static int 322bfe_attach(device_t dev) 323{ 324 struct ifnet *ifp; 325 struct bfe_softc *sc; 326 int unit, error = 0, rid; 327 328 sc = device_get_softc(dev); 329 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 330 MTX_DEF | MTX_RECURSE); 331 332 unit = device_get_unit(dev); 333 sc->bfe_dev = dev; 334 sc->bfe_unit = unit; 335 336 /* 337 * Handle power management nonsense. 338 */ 339 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 340 u_int32_t membase, irq; 341 342 /* Save important PCI config data. */ 343 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 344 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 345 346 /* Reset the power state. */ 347 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 348 sc->bfe_unit, pci_get_powerstate(dev)); 349 350 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 351 352 /* Restore PCI config data. */ 353 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 354 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 355 } 356 357 /* 358 * Map control/status registers. 359 */ 360 pci_enable_busmaster(dev); 361 362 rid = BFE_PCI_MEMLO; 363 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 364 RF_ACTIVE); 365 if (sc->bfe_res == NULL) { 366 printf ("bfe%d: couldn't map memory\n", unit); 367 error = ENXIO; 368 goto fail; 369 } 370 371 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 372 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 373 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 374 375 /* Allocate interrupt */ 376 rid = 0; 377 378 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 379 RF_SHAREABLE | RF_ACTIVE); 380 if (sc->bfe_irq == NULL) { 381 printf("bfe%d: couldn't map interrupt\n", unit); 382 error = ENXIO; 383 goto fail; 384 } 385 386 if (bfe_dma_alloc(dev)) { 387 printf("bfe%d: failed to allocate DMA resources\n", 388 sc->bfe_unit); 389 bfe_release_resources(sc); 390 error = ENXIO; 391 goto fail; 392 } 393 394 /* Set up ifnet structure */ 395 ifp = &sc->arpcom.ac_if; 396 ifp->if_softc = sc; 397 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 398 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 399 ifp->if_ioctl = bfe_ioctl; 400 ifp->if_start = bfe_start; 401 ifp->if_watchdog = bfe_watchdog; 402 ifp->if_init = bfe_init; 403 ifp->if_mtu = ETHERMTU; 404 ifp->if_baudrate = 100000000; 405 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN; 406 407 bfe_get_config(sc); 408 409 /* Reset the chip and turn on the PHY */ 410 bfe_chip_reset(sc); 411 412 if (mii_phy_probe(dev, &sc->bfe_miibus, 413 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 414 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 415 error = ENXIO; 416 goto fail; 417 } 418 419 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 420 callout_handle_init(&sc->bfe_stat_ch); 421 422 /* 423 * Tell the upper layer(s) we support long frames. 424 */ 425 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 426 ifp->if_capabilities |= IFCAP_VLAN_MTU; 427 ifp->if_capenable |= IFCAP_VLAN_MTU; 428 429 /* 430 * Hook interrupt last to avoid having to lock softc 431 */ 432 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 433 bfe_intr, sc, &sc->bfe_intrhand); 434 435 if (error) { 436 bfe_release_resources(sc); 437 printf("bfe%d: couldn't set up irq\n", unit); 438 goto fail; 439 } 440fail: 441 if(error) 442 bfe_release_resources(sc); 443 return(error); 444} 445 446static int 447bfe_detach(device_t dev) 448{ 449 struct bfe_softc *sc; 450 struct ifnet *ifp; 451 452 sc = device_get_softc(dev); 453 454 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 455 BFE_LOCK(scp); 456 457 ifp = &sc->arpcom.ac_if; 458 459 if (device_is_attached(dev)) { 460 bfe_stop(sc); 461 ether_ifdetach(ifp); 462 } 463 464 bfe_chip_reset(sc); 465 466 bus_generic_detach(dev); 467 if(sc->bfe_miibus != NULL) 468 device_delete_child(dev, sc->bfe_miibus); 469 470 bfe_release_resources(sc); 471 BFE_UNLOCK(sc); 472 mtx_destroy(&sc->bfe_mtx); 473 474 return(0); 475} 476 477/* 478 * Stop all chip I/O so that the kernel's probe routines don't 479 * get confused by errant DMAs when rebooting. 480 */ 481static void 482bfe_shutdown(device_t dev) 483{ 484 struct bfe_softc *sc; 485 486 sc = device_get_softc(dev); 487 BFE_LOCK(sc); 488 bfe_stop(sc); 489 490 BFE_UNLOCK(sc); 491 return; 492} 493 494static int 495bfe_miibus_readreg(device_t dev, int phy, int reg) 496{ 497 struct bfe_softc *sc; 498 u_int32_t ret; 499 500 sc = device_get_softc(dev); 501 if(phy != sc->bfe_phyaddr) 502 return(0); 503 bfe_readphy(sc, reg, &ret); 504 505 return(ret); 506} 507 508static int 509bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 510{ 511 struct bfe_softc *sc; 512 513 sc = device_get_softc(dev); 514 if(phy != sc->bfe_phyaddr) 515 return(0); 516 bfe_writephy(sc, reg, val); 517 518 return(0); 519} 520 521static void 522bfe_miibus_statchg(device_t dev) 523{ 524 return; 525} 526 527static void 528bfe_tx_ring_free(struct bfe_softc *sc) 529{ 530 int i; 531 532 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 533 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 534 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 535 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 536 bus_dmamap_unload(sc->bfe_tag, 537 sc->bfe_tx_ring[i].bfe_map); 538 bus_dmamap_destroy(sc->bfe_tag, 539 sc->bfe_tx_ring[i].bfe_map); 540 } 541 } 542 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 543 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 544} 545 546static void 547bfe_rx_ring_free(struct bfe_softc *sc) 548{ 549 int i; 550 551 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 552 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 553 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 554 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 555 bus_dmamap_unload(sc->bfe_tag, 556 sc->bfe_rx_ring[i].bfe_map); 557 bus_dmamap_destroy(sc->bfe_tag, 558 sc->bfe_rx_ring[i].bfe_map); 559 } 560 } 561 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 562 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 563} 564 565 566static int 567bfe_list_rx_init(struct bfe_softc *sc) 568{ 569 int i; 570 571 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 572 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 573 return ENOBUFS; 574 } 575 576 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 577 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 578 579 sc->bfe_rx_cons = 0; 580 581 return(0); 582} 583 584static int 585bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 586{ 587 struct bfe_rxheader *rx_header; 588 struct bfe_desc *d; 589 struct bfe_data *r; 590 u_int32_t ctrl; 591 592 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 593 return(EINVAL); 594 595 if(m == NULL) { 596 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 597 if(m == NULL) 598 return(ENOBUFS); 599 m->m_len = m->m_pkthdr.len = MCLBYTES; 600 } 601 else 602 m->m_data = m->m_ext.ext_buf; 603 604 rx_header = mtod(m, struct bfe_rxheader *); 605 rx_header->len = 0; 606 rx_header->flags = 0; 607 608 /* Map the mbuf into DMA */ 609 sc->bfe_rx_cnt = c; 610 d = &sc->bfe_rx_list[c]; 611 r = &sc->bfe_rx_ring[c]; 612 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 613 MCLBYTES, bfe_dma_map_desc, d, 0); 614 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 615 616 ctrl = ETHER_MAX_LEN + 32; 617 618 if(c == BFE_RX_LIST_CNT - 1) 619 ctrl |= BFE_DESC_EOT; 620 621 d->bfe_ctrl = ctrl; 622 r->bfe_mbuf = m; 623 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 624 return(0); 625} 626 627static void 628bfe_get_config(struct bfe_softc *sc) 629{ 630 u_int8_t eeprom[128]; 631 632 bfe_read_eeprom(sc, eeprom); 633 634 sc->arpcom.ac_enaddr[0] = eeprom[79]; 635 sc->arpcom.ac_enaddr[1] = eeprom[78]; 636 sc->arpcom.ac_enaddr[2] = eeprom[81]; 637 sc->arpcom.ac_enaddr[3] = eeprom[80]; 638 sc->arpcom.ac_enaddr[4] = eeprom[83]; 639 sc->arpcom.ac_enaddr[5] = eeprom[82]; 640 641 sc->bfe_phyaddr = eeprom[90] & 0x1f; 642 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 643 644 sc->bfe_core_unit = 0; 645 sc->bfe_dma_offset = BFE_PCI_DMA; 646} 647 648static void 649bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 650{ 651 u_int32_t bar_orig, pci_rev, val; 652 653 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 654 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 655 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 656 657 val = CSR_READ_4(sc, BFE_SBINTVEC); 658 val |= cores; 659 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 660 661 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 662 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 663 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 664 665 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 666} 667 668static void 669bfe_clear_stats(struct bfe_softc *sc) 670{ 671 u_long reg; 672 673 BFE_LOCK(sc); 674 675 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 676 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 677 CSR_READ_4(sc, reg); 678 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 679 CSR_READ_4(sc, reg); 680 681 BFE_UNLOCK(sc); 682} 683 684static int 685bfe_resetphy(struct bfe_softc *sc) 686{ 687 u_int32_t val; 688 689 BFE_LOCK(sc); 690 bfe_writephy(sc, 0, BMCR_RESET); 691 DELAY(100); 692 bfe_readphy(sc, 0, &val); 693 if (val & BMCR_RESET) { 694 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 695 BFE_UNLOCK(sc); 696 return ENXIO; 697 } 698 BFE_UNLOCK(sc); 699 return 0; 700} 701 702static void 703bfe_chip_halt(struct bfe_softc *sc) 704{ 705 BFE_LOCK(sc); 706 /* disable interrupts - not that it actually does..*/ 707 CSR_WRITE_4(sc, BFE_IMASK, 0); 708 CSR_READ_4(sc, BFE_IMASK); 709 710 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 711 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 712 713 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 714 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 715 DELAY(10); 716 717 BFE_UNLOCK(sc); 718} 719 720static void 721bfe_chip_reset(struct bfe_softc *sc) 722{ 723 u_int32_t val; 724 725 BFE_LOCK(sc); 726 727 /* Set the interrupt vector for the enet core */ 728 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 729 730 /* is core up? */ 731 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 732 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 733 if (val == BFE_CLOCK) { 734 /* It is, so shut it down */ 735 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 736 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 737 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 738 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 739 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 740 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 741 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 742 100, 0); 743 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 744 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 745 } 746 747 bfe_core_reset(sc); 748 bfe_clear_stats(sc); 749 750 /* 751 * We want the phy registers to be accessible even when 752 * the driver is "downed" so initialize MDC preamble, frequency, 753 * and whether internal or external phy here. 754 */ 755 756 /* 4402 has 62.5Mhz SB clock and internal phy */ 757 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 758 759 /* Internal or external PHY? */ 760 val = CSR_READ_4(sc, BFE_DEVCTRL); 761 if(!(val & BFE_IPP)) 762 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 763 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 764 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 765 DELAY(100); 766 } 767 768 /* Enable CRC32 generation and set proper LED modes */ 769 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 770 771 /* Reset or clear powerdown control bit */ 772 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 773 774 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 775 BFE_LAZY_FC_MASK)); 776 777 /* 778 * We don't want lazy interrupts, so just send them at 779 * the end of a frame, please 780 */ 781 BFE_OR(sc, BFE_RCV_LAZY, 0); 782 783 /* Set max lengths, accounting for VLAN tags */ 784 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 785 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 786 787 /* Set watermark XXX - magic */ 788 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 789 790 /* 791 * Initialise DMA channels 792 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 793 */ 794 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 795 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 796 797 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 798 BFE_RX_CTRL_ENABLE); 799 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 800 801 bfe_resetphy(sc); 802 bfe_setupphy(sc); 803 804 BFE_UNLOCK(sc); 805} 806 807static void 808bfe_core_disable(struct bfe_softc *sc) 809{ 810 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 811 return; 812 813 /* 814 * Set reject, wait for it set, then wait for the core to stop 815 * being busy, then set reset and reject and enable the clocks. 816 */ 817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 818 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 819 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 820 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 821 BFE_RESET)); 822 CSR_READ_4(sc, BFE_SBTMSLOW); 823 DELAY(10); 824 /* Leave reset and reject set */ 825 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 826 DELAY(10); 827} 828 829static void 830bfe_core_reset(struct bfe_softc *sc) 831{ 832 u_int32_t val; 833 834 /* Disable the core */ 835 bfe_core_disable(sc); 836 837 /* and bring it back up */ 838 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 839 CSR_READ_4(sc, BFE_SBTMSLOW); 840 DELAY(10); 841 842 /* Chip bug, clear SERR, IB and TO if they are set. */ 843 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 844 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 845 val = CSR_READ_4(sc, BFE_SBIMSTATE); 846 if (val & (BFE_IBE | BFE_TO)) 847 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 848 849 /* Clear reset and allow it to move through the core */ 850 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 851 CSR_READ_4(sc, BFE_SBTMSLOW); 852 DELAY(10); 853 854 /* Leave the clock set */ 855 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 856 CSR_READ_4(sc, BFE_SBTMSLOW); 857 DELAY(10); 858} 859 860static void 861bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 862{ 863 u_int32_t val; 864 865 val = ((u_int32_t) data[2]) << 24; 866 val |= ((u_int32_t) data[3]) << 16; 867 val |= ((u_int32_t) data[4]) << 8; 868 val |= ((u_int32_t) data[5]); 869 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 870 val = (BFE_CAM_HI_VALID | 871 (((u_int32_t) data[0]) << 8) | 872 (((u_int32_t) data[1]))); 873 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 874 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 875 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 876 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 877} 878 879static void 880bfe_set_rx_mode(struct bfe_softc *sc) 881{ 882 struct ifnet *ifp = &sc->arpcom.ac_if; 883 struct ifmultiaddr *ifma; 884 u_int32_t val; 885 int i = 0; 886 887 val = CSR_READ_4(sc, BFE_RXCONF); 888 889 if (ifp->if_flags & IFF_PROMISC) 890 val |= BFE_RXCONF_PROMISC; 891 else 892 val &= ~BFE_RXCONF_PROMISC; 893 894 if (ifp->if_flags & IFF_BROADCAST) 895 val &= ~BFE_RXCONF_DBCAST; 896 else 897 val |= BFE_RXCONF_DBCAST; 898 899 900 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 901 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 902 903 if (ifp->if_flags & IFF_ALLMULTI) 904 val |= BFE_RXCONF_ALLMULTI; 905 else { 906 val &= ~BFE_RXCONF_ALLMULTI; 907 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 908 if (ifma->ifma_addr->sa_family != AF_LINK) 909 continue; 910 bfe_cam_write(sc, 911 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 912 } 913 } 914 915 CSR_WRITE_4(sc, BFE_RXCONF, val); 916 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 917} 918 919static void 920bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 921{ 922 u_int32_t *ptr; 923 924 ptr = arg; 925 *ptr = segs->ds_addr; 926} 927 928static void 929bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 930{ 931 struct bfe_desc *d; 932 933 d = arg; 934 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 935 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 936} 937 938static void 939bfe_release_resources(struct bfe_softc *sc) 940{ 941 device_t dev; 942 int i; 943 944 dev = sc->bfe_dev; 945 946 if (sc->bfe_vpd_prodname != NULL) 947 free(sc->bfe_vpd_prodname, M_DEVBUF); 948 949 if (sc->bfe_vpd_readonly != NULL) 950 free(sc->bfe_vpd_readonly, M_DEVBUF); 951 952 if (sc->bfe_intrhand != NULL) 953 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 954 955 if (sc->bfe_irq != NULL) 956 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 957 958 if (sc->bfe_res != NULL) 959 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 960 961 if(sc->bfe_tx_tag != NULL) { 962 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 963 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 964 sc->bfe_tx_map); 965 bus_dma_tag_destroy(sc->bfe_tx_tag); 966 sc->bfe_tx_tag = NULL; 967 } 968 969 if(sc->bfe_rx_tag != NULL) { 970 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 971 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 972 sc->bfe_rx_map); 973 bus_dma_tag_destroy(sc->bfe_rx_tag); 974 sc->bfe_rx_tag = NULL; 975 } 976 977 if(sc->bfe_tag != NULL) { 978 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 979 bus_dmamap_destroy(sc->bfe_tag, 980 sc->bfe_tx_ring[i].bfe_map); 981 } 982 bus_dma_tag_destroy(sc->bfe_tag); 983 sc->bfe_tag = NULL; 984 } 985 986 if(sc->bfe_parent_tag != NULL) 987 bus_dma_tag_destroy(sc->bfe_parent_tag); 988 989 return; 990} 991 992static void 993bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 994{ 995 long i; 996 u_int16_t *ptr = (u_int16_t *)data; 997 998 for(i = 0; i < 128; i += 2) 999 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1000} 1001 1002static int 1003bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1004 u_long timeout, const int clear) 1005{ 1006 u_long i; 1007 1008 for (i = 0; i < timeout; i++) { 1009 u_int32_t val = CSR_READ_4(sc, reg); 1010 1011 if (clear && !(val & bit)) 1012 break; 1013 if (!clear && (val & bit)) 1014 break; 1015 DELAY(10); 1016 } 1017 if (i == timeout) { 1018 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1019 "%x to %s.\n", sc->bfe_unit, bit, reg, 1020 (clear ? "clear" : "set")); 1021 return -1; 1022 } 1023 return 0; 1024} 1025 1026static int 1027bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1028{ 1029 int err; 1030 1031 BFE_LOCK(sc); 1032 /* Clear MII ISR */ 1033 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1034 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1035 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1036 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1037 (reg << BFE_MDIO_RA_SHIFT) | 1038 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1039 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1040 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1041 1042 BFE_UNLOCK(sc); 1043 return err; 1044} 1045 1046static int 1047bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1048{ 1049 int status; 1050 1051 BFE_LOCK(sc); 1052 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1053 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1054 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1055 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1056 (reg << BFE_MDIO_RA_SHIFT) | 1057 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1058 (val & BFE_MDIO_DATA_DATA))); 1059 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1060 BFE_UNLOCK(sc); 1061 1062 return status; 1063} 1064 1065/* 1066 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1067 * twice 1068 */ 1069static int 1070bfe_setupphy(struct bfe_softc *sc) 1071{ 1072 u_int32_t val; 1073 BFE_LOCK(sc); 1074 1075 /* Enable activity LED */ 1076 bfe_readphy(sc, 26, &val); 1077 bfe_writephy(sc, 26, val & 0x7fff); 1078 bfe_readphy(sc, 26, &val); 1079 1080 /* Enable traffic meter LED mode */ 1081 bfe_readphy(sc, 27, &val); 1082 bfe_writephy(sc, 27, val | (1 << 6)); 1083 1084 BFE_UNLOCK(sc); 1085 return 0; 1086} 1087 1088static void 1089bfe_stats_update(struct bfe_softc *sc) 1090{ 1091 u_long reg; 1092 u_int32_t *val; 1093 1094 val = &sc->bfe_hwstats.tx_good_octets; 1095 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1096 *val++ += CSR_READ_4(sc, reg); 1097 } 1098 val = &sc->bfe_hwstats.rx_good_octets; 1099 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1100 *val++ += CSR_READ_4(sc, reg); 1101 } 1102} 1103 1104static void 1105bfe_txeof(struct bfe_softc *sc) 1106{ 1107 struct ifnet *ifp; 1108 int i, chipidx; 1109 1110 BFE_LOCK(sc); 1111 1112 ifp = &sc->arpcom.ac_if; 1113 1114 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1115 chipidx /= sizeof(struct bfe_desc); 1116 1117 i = sc->bfe_tx_cons; 1118 /* Go through the mbufs and free those that have been transmitted */ 1119 while(i != chipidx) { 1120 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1121 if(r->bfe_mbuf != NULL) { 1122 ifp->if_opackets++; 1123 m_freem(r->bfe_mbuf); 1124 r->bfe_mbuf = NULL; 1125 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1126 } 1127 sc->bfe_tx_cnt--; 1128 BFE_INC(i, BFE_TX_LIST_CNT); 1129 } 1130 1131 if(i != sc->bfe_tx_cons) { 1132 /* we freed up some mbufs */ 1133 sc->bfe_tx_cons = i; 1134 ifp->if_flags &= ~IFF_OACTIVE; 1135 } 1136 if(sc->bfe_tx_cnt == 0) 1137 ifp->if_timer = 0; 1138 else 1139 ifp->if_timer = 5; 1140 1141 BFE_UNLOCK(sc); 1142} 1143 1144/* Pass a received packet up the stack */ 1145static void 1146bfe_rxeof(struct bfe_softc *sc) 1147{ 1148 struct mbuf *m; 1149 struct ifnet *ifp; 1150 struct bfe_rxheader *rxheader; 1151 struct bfe_data *r; 1152 int cons; 1153 u_int32_t status, current, len, flags; 1154 1155 BFE_LOCK(sc); 1156 cons = sc->bfe_rx_cons; 1157 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1158 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1159 1160 ifp = &sc->arpcom.ac_if; 1161 1162 while(current != cons) { 1163 r = &sc->bfe_rx_ring[cons]; 1164 m = r->bfe_mbuf; 1165 rxheader = mtod(m, struct bfe_rxheader*); 1166 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1167 len = rxheader->len; 1168 r->bfe_mbuf = NULL; 1169 1170 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1171 flags = rxheader->flags; 1172 1173 len -= ETHER_CRC_LEN; 1174 1175 /* flag an error and try again */ 1176 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1177 ifp->if_ierrors++; 1178 if (flags & BFE_RX_FLAG_SERR) 1179 ifp->if_collisions++; 1180 bfe_list_newbuf(sc, cons, m); 1181 BFE_INC(cons, BFE_RX_LIST_CNT); 1182 continue; 1183 } 1184 1185 /* Go past the rx header */ 1186 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1187 m_adj(m, BFE_RX_OFFSET); 1188 m->m_len = m->m_pkthdr.len = len; 1189 } else { 1190 bfe_list_newbuf(sc, cons, m); 1191 ifp->if_ierrors++; 1192 BFE_INC(cons, BFE_RX_LIST_CNT); 1193 continue; 1194 } 1195 1196 ifp->if_ipackets++; 1197 m->m_pkthdr.rcvif = ifp; 1198 BFE_UNLOCK(sc); 1199 (*ifp->if_input)(ifp, m); 1200 BFE_LOCK(sc); 1201 1202 BFE_INC(cons, BFE_RX_LIST_CNT); 1203 } 1204 sc->bfe_rx_cons = cons; 1205 BFE_UNLOCK(sc); 1206} 1207 1208static void 1209bfe_intr(void *xsc) 1210{ 1211 struct bfe_softc *sc = xsc; 1212 struct ifnet *ifp; 1213 u_int32_t istat, imask, flag; 1214 1215 ifp = &sc->arpcom.ac_if; 1216 1217 BFE_LOCK(sc); 1218 1219 istat = CSR_READ_4(sc, BFE_ISTAT); 1220 imask = CSR_READ_4(sc, BFE_IMASK); 1221 1222 /* 1223 * Defer unsolicited interrupts - This is necessary because setting the 1224 * chips interrupt mask register to 0 doesn't actually stop the 1225 * interrupts 1226 */ 1227 istat &= imask; 1228 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1229 CSR_READ_4(sc, BFE_ISTAT); 1230 1231 /* not expecting this interrupt, disregard it */ 1232 if(istat == 0) { 1233 BFE_UNLOCK(sc); 1234 return; 1235 } 1236 1237 if(istat & BFE_ISTAT_ERRORS) { 1238 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1239 if(flag & BFE_STAT_EMASK) 1240 ifp->if_oerrors++; 1241 1242 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1243 if(flag & BFE_RX_FLAG_ERRORS) 1244 ifp->if_ierrors++; 1245 1246 ifp->if_flags &= ~IFF_RUNNING; 1247 bfe_init(sc); 1248 } 1249 1250 /* A packet was received */ 1251 if(istat & BFE_ISTAT_RX) 1252 bfe_rxeof(sc); 1253 1254 /* A packet was sent */ 1255 if(istat & BFE_ISTAT_TX) 1256 bfe_txeof(sc); 1257 1258 /* We have packets pending, fire them out */ 1259 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1260 bfe_start(ifp); 1261 1262 BFE_UNLOCK(sc); 1263} 1264 1265static int 1266bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1267{ 1268 struct bfe_desc *d = NULL; 1269 struct bfe_data *r = NULL; 1270 struct mbuf *m; 1271 u_int32_t frag, cur, cnt = 0; 1272 int chainlen = 0; 1273 1274 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1275 return(ENOBUFS); 1276 1277 /* 1278 * Count the number of frags in this chain to see if 1279 * we need to m_defrag. Since the descriptor list is shared 1280 * by all packets, we'll m_defrag long chains so that they 1281 * do not use up the entire list, even if they would fit. 1282 */ 1283 for(m = m_head; m != NULL; m = m->m_next) 1284 chainlen++; 1285 1286 1287 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1288 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1289 m = m_defrag(m_head, M_DONTWAIT); 1290 if (m == NULL) 1291 return(ENOBUFS); 1292 m_head = m; 1293 } 1294 1295 /* 1296 * Start packing the mbufs in this chain into 1297 * the fragment pointers. Stop when we run out 1298 * of fragments or hit the end of the mbuf chain. 1299 */ 1300 m = m_head; 1301 cur = frag = *txidx; 1302 cnt = 0; 1303 1304 for(m = m_head; m != NULL; m = m->m_next) { 1305 if(m->m_len != 0) { 1306 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1307 return(ENOBUFS); 1308 1309 d = &sc->bfe_tx_list[cur]; 1310 r = &sc->bfe_tx_ring[cur]; 1311 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1312 /* always intterupt on completion */ 1313 d->bfe_ctrl |= BFE_DESC_IOC; 1314 if(cnt == 0) 1315 /* Set start of frame */ 1316 d->bfe_ctrl |= BFE_DESC_SOF; 1317 if(cur == BFE_TX_LIST_CNT - 1) 1318 /* 1319 * Tell the chip to wrap to the start of 1320 * the descriptor list 1321 */ 1322 d->bfe_ctrl |= BFE_DESC_EOT; 1323 1324 bus_dmamap_load(sc->bfe_tag, 1325 r->bfe_map, mtod(m, void*), m->m_len, 1326 bfe_dma_map_desc, d, 0); 1327 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1328 BUS_DMASYNC_PREREAD); 1329 1330 frag = cur; 1331 BFE_INC(cur, BFE_TX_LIST_CNT); 1332 cnt++; 1333 } 1334 } 1335 1336 if (m != NULL) 1337 return(ENOBUFS); 1338 1339 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1340 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1341 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1342 1343 *txidx = cur; 1344 sc->bfe_tx_cnt += cnt; 1345 return (0); 1346} 1347 1348/* 1349 * Set up to transmit a packet 1350 */ 1351static void 1352bfe_start(struct ifnet *ifp) 1353{ 1354 struct bfe_softc *sc; 1355 struct mbuf *m_head = NULL; 1356 int idx; 1357 1358 sc = ifp->if_softc; 1359 idx = sc->bfe_tx_prod; 1360 1361 BFE_LOCK(sc); 1362 1363 /* 1364 * Not much point trying to send if the link is down 1365 * or we have nothing to send. 1366 */ 1367 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1368 BFE_UNLOCK(sc); 1369 return; 1370 } 1371 1372 if (ifp->if_flags & IFF_OACTIVE) { 1373 BFE_UNLOCK(sc); 1374 return; 1375 } 1376 1377 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1378 IF_DEQUEUE(&ifp->if_snd, m_head); 1379 if(m_head == NULL) 1380 break; 1381 1382 /* 1383 * Pack the data into the tx ring. If we dont have 1384 * enough room, let the chip drain the ring. 1385 */ 1386 if(bfe_encap(sc, m_head, &idx)) { 1387 IF_PREPEND(&ifp->if_snd, m_head); 1388 ifp->if_flags |= IFF_OACTIVE; 1389 break; 1390 } 1391 1392 /* 1393 * If there's a BPF listener, bounce a copy of this frame 1394 * to him. 1395 */ 1396 BPF_MTAP(ifp, m_head); 1397 } 1398 1399 sc->bfe_tx_prod = idx; 1400 /* Transmit - twice due to apparent hardware bug */ 1401 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1402 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1403 1404 /* 1405 * Set a timeout in case the chip goes out to lunch. 1406 */ 1407 ifp->if_timer = 5; 1408 BFE_UNLOCK(sc); 1409} 1410 1411static void 1412bfe_init(void *xsc) 1413{ 1414 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1415 struct ifnet *ifp = &sc->arpcom.ac_if; 1416 1417 BFE_LOCK(sc); 1418 1419 if (ifp->if_flags & IFF_RUNNING) { 1420 BFE_UNLOCK(sc); 1421 return; 1422 } 1423 1424 bfe_stop(sc); 1425 bfe_chip_reset(sc); 1426 1427 if (bfe_list_rx_init(sc) == ENOBUFS) { 1428 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1429 sc->bfe_unit); 1430 bfe_stop(sc); 1431 return; 1432 } 1433 1434 bfe_set_rx_mode(sc); 1435 1436 /* Enable the chip and core */ 1437 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1438 /* Enable interrupts */ 1439 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1440 1441 bfe_ifmedia_upd(ifp); 1442 ifp->if_flags |= IFF_RUNNING; 1443 ifp->if_flags &= ~IFF_OACTIVE; 1444 1445 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1446 BFE_UNLOCK(sc); 1447} 1448 1449/* 1450 * Set media options. 1451 */ 1452static int 1453bfe_ifmedia_upd(struct ifnet *ifp) 1454{ 1455 struct bfe_softc *sc; 1456 struct mii_data *mii; 1457 1458 sc = ifp->if_softc; 1459 1460 BFE_LOCK(sc); 1461 1462 mii = device_get_softc(sc->bfe_miibus); 1463 sc->bfe_link = 0; 1464 if (mii->mii_instance) { 1465 struct mii_softc *miisc; 1466 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1467 miisc = LIST_NEXT(miisc, mii_list)) 1468 mii_phy_reset(miisc); 1469 } 1470 mii_mediachg(mii); 1471 1472 BFE_UNLOCK(sc); 1473 return(0); 1474} 1475 1476/* 1477 * Report current media status. 1478 */ 1479static void 1480bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1481{ 1482 struct bfe_softc *sc = ifp->if_softc; 1483 struct mii_data *mii; 1484 1485 BFE_LOCK(sc); 1486 1487 mii = device_get_softc(sc->bfe_miibus); 1488 mii_pollstat(mii); 1489 ifmr->ifm_active = mii->mii_media_active; 1490 ifmr->ifm_status = mii->mii_media_status; 1491 1492 BFE_UNLOCK(sc); 1493} 1494 1495static int 1496bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1497{ 1498 struct bfe_softc *sc = ifp->if_softc; 1499 struct ifreq *ifr = (struct ifreq *) data; 1500 struct mii_data *mii; 1501 int error = 0; 1502 1503 BFE_LOCK(sc); 1504 1505 switch(command) { 1506 case SIOCSIFFLAGS: 1507 if(ifp->if_flags & IFF_UP) 1508 if(ifp->if_flags & IFF_RUNNING) 1509 bfe_set_rx_mode(sc); 1510 else 1511 bfe_init(sc); 1512 else if(ifp->if_flags & IFF_RUNNING) 1513 bfe_stop(sc); 1514 break; 1515 case SIOCADDMULTI: 1516 case SIOCDELMULTI: 1517 if(ifp->if_flags & IFF_RUNNING) 1518 bfe_set_rx_mode(sc); 1519 break; 1520 case SIOCGIFMEDIA: 1521 case SIOCSIFMEDIA: 1522 mii = device_get_softc(sc->bfe_miibus); 1523 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1524 command); 1525 break; 1526 default: 1527 error = ether_ioctl(ifp, command, data); 1528 break; 1529 } 1530 1531 BFE_UNLOCK(sc); 1532 return error; 1533} 1534 1535static void 1536bfe_watchdog(struct ifnet *ifp) 1537{ 1538 struct bfe_softc *sc; 1539 1540 sc = ifp->if_softc; 1541 1542 BFE_LOCK(sc); 1543 1544 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1545 1546 ifp->if_flags &= ~IFF_RUNNING; 1547 bfe_init(sc); 1548 1549 ifp->if_oerrors++; 1550 1551 BFE_UNLOCK(sc); 1552} 1553 1554static void 1555bfe_tick(void *xsc) 1556{ 1557 struct bfe_softc *sc = xsc; 1558 struct mii_data *mii; 1559 1560 if (sc == NULL) 1561 return; 1562 1563 BFE_LOCK(sc); 1564 1565 mii = device_get_softc(sc->bfe_miibus); 1566 1567 bfe_stats_update(sc); 1568 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1569 1570 if(sc->bfe_link) { 1571 BFE_UNLOCK(sc); 1572 return; 1573 } 1574 1575 mii_tick(mii); 1576 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1577 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1578 sc->bfe_link++; 1579 1580 BFE_UNLOCK(sc); 1581} 1582 1583/* 1584 * Stop the adapter and free any mbufs allocated to the 1585 * RX and TX lists. 1586 */ 1587static void 1588bfe_stop(struct bfe_softc *sc) 1589{ 1590 struct ifnet *ifp; 1591 1592 BFE_LOCK(sc); 1593 1594 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1595 1596 ifp = &sc->arpcom.ac_if; 1597 1598 bfe_chip_halt(sc); 1599 bfe_tx_ring_free(sc); 1600 bfe_rx_ring_free(sc); 1601 1602 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1603 1604 BFE_UNLOCK(sc); 1605} 1606