if_bfe.c revision 129708
1/* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 */ 5 6/* 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 129708 2004-05-25 11:04:01Z des $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/sockio.h> 36#include <sys/mbuf.h> 37#include <sys/malloc.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/queue.h> 41 42#include <net/if.h> 43#include <net/if_arp.h> 44#include <net/ethernet.h> 45#include <net/if_dl.h> 46#include <net/if_media.h> 47 48#include <net/bpf.h> 49 50#include <net/if_types.h> 51#include <net/if_vlan_var.h> 52 53#include <netinet/in_systm.h> 54#include <netinet/in.h> 55#include <netinet/ip.h> 56 57#include <machine/clock.h> /* for DELAY */ 58#include <machine/bus_memio.h> 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/bus.h> 62#include <sys/rman.h> 63 64#include <dev/mii/mii.h> 65#include <dev/mii/miivar.h> 66#include "miidevs.h" 67 68#include <dev/pci/pcireg.h> 69#include <dev/pci/pcivar.h> 70 71#include <dev/bfe/if_bfereg.h> 72 73MODULE_DEPEND(bfe, pci, 1, 1, 1); 74MODULE_DEPEND(bfe, ether, 1, 1, 1); 75MODULE_DEPEND(bfe, miibus, 1, 1, 1); 76 77/* "controller miibus0" required. See GENERIC if you get errors here. */ 78#include "miibus_if.h" 79 80#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 81 82static struct bfe_type bfe_devs[] = { 83 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 84 "Broadcom BCM4401 Fast Ethernet" }, 85 { 0, 0, NULL } 86}; 87 88static int bfe_probe (device_t); 89static int bfe_attach (device_t); 90static int bfe_detach (device_t); 91static void bfe_release_resources (struct bfe_softc *); 92static void bfe_intr (void *); 93static void bfe_start (struct ifnet *); 94static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 95static void bfe_init (void *); 96static void bfe_stop (struct bfe_softc *); 97static void bfe_watchdog (struct ifnet *); 98static void bfe_shutdown (device_t); 99static void bfe_tick (void *); 100static void bfe_txeof (struct bfe_softc *); 101static void bfe_rxeof (struct bfe_softc *); 102static void bfe_set_rx_mode (struct bfe_softc *); 103static int bfe_list_rx_init (struct bfe_softc *); 104static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 105static void bfe_rx_ring_free (struct bfe_softc *); 106 107static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 108static int bfe_ifmedia_upd (struct ifnet *); 109static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110static int bfe_miibus_readreg (device_t, int, int); 111static int bfe_miibus_writereg (device_t, int, int, int); 112static void bfe_miibus_statchg (device_t); 113static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 114 u_long, const int); 115static void bfe_get_config (struct bfe_softc *sc); 116static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 117static void bfe_stats_update (struct bfe_softc *); 118static void bfe_clear_stats (struct bfe_softc *); 119static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 120static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 121static int bfe_resetphy (struct bfe_softc *); 122static int bfe_setupphy (struct bfe_softc *); 123static void bfe_chip_reset (struct bfe_softc *); 124static void bfe_chip_halt (struct bfe_softc *); 125static void bfe_core_reset (struct bfe_softc *); 126static void bfe_core_disable (struct bfe_softc *); 127static int bfe_dma_alloc (device_t); 128static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 129static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 130static void bfe_cam_write (struct bfe_softc *, u_char *, int); 131 132static device_method_t bfe_methods[] = { 133 /* Device interface */ 134 DEVMETHOD(device_probe, bfe_probe), 135 DEVMETHOD(device_attach, bfe_attach), 136 DEVMETHOD(device_detach, bfe_detach), 137 DEVMETHOD(device_shutdown, bfe_shutdown), 138 139 /* bus interface */ 140 DEVMETHOD(bus_print_child, bus_generic_print_child), 141 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 142 143 /* MII interface */ 144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 146 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 147 148 { 0, 0 } 149}; 150 151static driver_t bfe_driver = { 152 "bfe", 153 bfe_methods, 154 sizeof(struct bfe_softc) 155}; 156 157static devclass_t bfe_devclass; 158 159DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 160DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 161 162/* 163 * Probe for a Broadcom 4401 chip. 164 */ 165static int 166bfe_probe(device_t dev) 167{ 168 struct bfe_type *t; 169 struct bfe_softc *sc; 170 171 t = bfe_devs; 172 173 sc = device_get_softc(dev); 174 bzero(sc, sizeof(struct bfe_softc)); 175 sc->bfe_unit = device_get_unit(dev); 176 sc->bfe_dev = dev; 177 178 while(t->bfe_name != NULL) { 179 if ((pci_get_vendor(dev) == t->bfe_vid) && 180 (pci_get_device(dev) == t->bfe_did)) { 181 device_set_desc_copy(dev, t->bfe_name); 182 return(0); 183 } 184 t++; 185 } 186 187 return(ENXIO); 188} 189 190static int 191bfe_dma_alloc(device_t dev) 192{ 193 struct bfe_softc *sc; 194 int error, i; 195 196 sc = device_get_softc(dev); 197 198 /* parent tag */ 199 error = bus_dma_tag_create(NULL, /* parent */ 200 PAGE_SIZE, 0, /* alignment, boundary */ 201 BUS_SPACE_MAXADDR, /* lowaddr */ 202 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 203 NULL, NULL, /* filter, filterarg */ 204 MAXBSIZE, /* maxsize */ 205 BUS_SPACE_UNRESTRICTED, /* num of segments */ 206 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 207 BUS_DMA_ALLOCNOW, /* flags */ 208 NULL, NULL, /* lockfunc, lockarg */ 209 &sc->bfe_parent_tag); 210 211 /* tag for TX ring */ 212 error = bus_dma_tag_create(sc->bfe_parent_tag, 213 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 214 BUS_SPACE_MAXADDR, 215 BUS_SPACE_MAXADDR, 216 NULL, NULL, 217 BFE_TX_LIST_SIZE, 218 1, 219 BUS_SPACE_MAXSIZE_32BIT, 220 0, 221 NULL, NULL, 222 &sc->bfe_tx_tag); 223 224 if (error) { 225 device_printf(dev, "could not allocate dma tag\n"); 226 return(ENOMEM); 227 } 228 229 /* tag for RX ring */ 230 error = bus_dma_tag_create(sc->bfe_parent_tag, 231 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 232 BUS_SPACE_MAXADDR, 233 BUS_SPACE_MAXADDR, 234 NULL, NULL, 235 BFE_RX_LIST_SIZE, 236 1, 237 BUS_SPACE_MAXSIZE_32BIT, 238 0, 239 NULL, NULL, 240 &sc->bfe_rx_tag); 241 242 if (error) { 243 device_printf(dev, "could not allocate dma tag\n"); 244 return(ENOMEM); 245 } 246 247 /* tag for mbufs */ 248 error = bus_dma_tag_create(sc->bfe_parent_tag, 249 ETHER_ALIGN, 0, 250 BUS_SPACE_MAXADDR, 251 BUS_SPACE_MAXADDR, 252 NULL, NULL, 253 MCLBYTES, 254 1, 255 BUS_SPACE_MAXSIZE_32BIT, 256 0, 257 NULL, NULL, 258 &sc->bfe_tag); 259 260 if (error) { 261 device_printf(dev, "could not allocate dma tag\n"); 262 return(ENOMEM); 263 } 264 265 /* pre allocate dmamaps for RX list */ 266 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 267 error = bus_dmamap_create(sc->bfe_tag, 0, 268 &sc->bfe_rx_ring[i].bfe_map); 269 if (error) { 270 device_printf(dev, "cannot create DMA map for RX\n"); 271 return(ENOMEM); 272 } 273 } 274 275 /* pre allocate dmamaps for TX list */ 276 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 277 error = bus_dmamap_create(sc->bfe_tag, 0, 278 &sc->bfe_tx_ring[i].bfe_map); 279 if (error) { 280 device_printf(dev, "cannot create DMA map for TX\n"); 281 return(ENOMEM); 282 } 283 } 284 285 /* Alloc dma for rx ring */ 286 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 287 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 288 289 if(error) 290 return(ENOMEM); 291 292 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 293 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 294 sc->bfe_rx_list, sizeof(struct bfe_desc), 295 bfe_dma_map, &sc->bfe_rx_dma, 0); 296 297 if(error) 298 return(ENOMEM); 299 300 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 301 302 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 303 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 304 if (error) 305 return(ENOMEM); 306 307 308 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 309 sc->bfe_tx_list, sizeof(struct bfe_desc), 310 bfe_dma_map, &sc->bfe_tx_dma, 0); 311 if(error) 312 return(ENOMEM); 313 314 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 315 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 316 317 return(0); 318} 319 320static int 321bfe_attach(device_t dev) 322{ 323 struct ifnet *ifp; 324 struct bfe_softc *sc; 325 int unit, error = 0, rid; 326 327 sc = device_get_softc(dev); 328 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 329 MTX_DEF | MTX_RECURSE); 330 331 unit = device_get_unit(dev); 332 sc->bfe_dev = dev; 333 sc->bfe_unit = unit; 334 335 /* 336 * Handle power management nonsense. 337 */ 338 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 339 u_int32_t membase, irq; 340 341 /* Save important PCI config data. */ 342 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 343 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 344 345 /* Reset the power state. */ 346 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 347 sc->bfe_unit, pci_get_powerstate(dev)); 348 349 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 350 351 /* Restore PCI config data. */ 352 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 353 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 354 } 355 356 /* 357 * Map control/status registers. 358 */ 359 pci_enable_busmaster(dev); 360 361 rid = BFE_PCI_MEMLO; 362 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 363 RF_ACTIVE); 364 if (sc->bfe_res == NULL) { 365 printf ("bfe%d: couldn't map memory\n", unit); 366 error = ENXIO; 367 goto fail; 368 } 369 370 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 371 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 372 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 373 374 /* Allocate interrupt */ 375 rid = 0; 376 377 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 378 RF_SHAREABLE | RF_ACTIVE); 379 if (sc->bfe_irq == NULL) { 380 printf("bfe%d: couldn't map interrupt\n", unit); 381 error = ENXIO; 382 goto fail; 383 } 384 385 if (bfe_dma_alloc(dev)) { 386 printf("bfe%d: failed to allocate DMA resources\n", 387 sc->bfe_unit); 388 bfe_release_resources(sc); 389 error = ENXIO; 390 goto fail; 391 } 392 393 /* Set up ifnet structure */ 394 ifp = &sc->arpcom.ac_if; 395 ifp->if_softc = sc; 396 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 397 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 398 ifp->if_ioctl = bfe_ioctl; 399 ifp->if_start = bfe_start; 400 ifp->if_watchdog = bfe_watchdog; 401 ifp->if_init = bfe_init; 402 ifp->if_mtu = ETHERMTU; 403 ifp->if_baudrate = 100000000; 404 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN; 405 406 bfe_get_config(sc); 407 408 /* Reset the chip and turn on the PHY */ 409 bfe_chip_reset(sc); 410 411 if (mii_phy_probe(dev, &sc->bfe_miibus, 412 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 413 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 414 error = ENXIO; 415 goto fail; 416 } 417 418 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 419 callout_handle_init(&sc->bfe_stat_ch); 420 421 /* 422 * Tell the upper layer(s) we support long frames. 423 */ 424 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 425 ifp->if_capabilities |= IFCAP_VLAN_MTU; 426 427 /* 428 * Hook interrupt last to avoid having to lock softc 429 */ 430 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 431 bfe_intr, sc, &sc->bfe_intrhand); 432 433 if (error) { 434 bfe_release_resources(sc); 435 printf("bfe%d: couldn't set up irq\n", unit); 436 goto fail; 437 } 438fail: 439 if(error) 440 bfe_release_resources(sc); 441 return(error); 442} 443 444static int 445bfe_detach(device_t dev) 446{ 447 struct bfe_softc *sc; 448 struct ifnet *ifp; 449 450 sc = device_get_softc(dev); 451 452 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 453 BFE_LOCK(scp); 454 455 ifp = &sc->arpcom.ac_if; 456 457 if (device_is_attached(dev)) { 458 bfe_stop(sc); 459 ether_ifdetach(ifp); 460 } 461 462 bfe_chip_reset(sc); 463 464 bus_generic_detach(dev); 465 if(sc->bfe_miibus != NULL) 466 device_delete_child(dev, sc->bfe_miibus); 467 468 bfe_release_resources(sc); 469 BFE_UNLOCK(sc); 470 mtx_destroy(&sc->bfe_mtx); 471 472 return(0); 473} 474 475/* 476 * Stop all chip I/O so that the kernel's probe routines don't 477 * get confused by errant DMAs when rebooting. 478 */ 479static void 480bfe_shutdown(device_t dev) 481{ 482 struct bfe_softc *sc; 483 484 sc = device_get_softc(dev); 485 BFE_LOCK(sc); 486 bfe_stop(sc); 487 488 BFE_UNLOCK(sc); 489 return; 490} 491 492static int 493bfe_miibus_readreg(device_t dev, int phy, int reg) 494{ 495 struct bfe_softc *sc; 496 u_int32_t ret; 497 498 sc = device_get_softc(dev); 499 if(phy != sc->bfe_phyaddr) 500 return(0); 501 bfe_readphy(sc, reg, &ret); 502 503 return(ret); 504} 505 506static int 507bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 508{ 509 struct bfe_softc *sc; 510 511 sc = device_get_softc(dev); 512 if(phy != sc->bfe_phyaddr) 513 return(0); 514 bfe_writephy(sc, reg, val); 515 516 return(0); 517} 518 519static void 520bfe_miibus_statchg(device_t dev) 521{ 522 return; 523} 524 525static void 526bfe_tx_ring_free(struct bfe_softc *sc) 527{ 528 int i; 529 530 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 531 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 532 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 533 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 534 bus_dmamap_unload(sc->bfe_tag, 535 sc->bfe_tx_ring[i].bfe_map); 536 bus_dmamap_destroy(sc->bfe_tag, 537 sc->bfe_tx_ring[i].bfe_map); 538 } 539 } 540 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 541 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 542} 543 544static void 545bfe_rx_ring_free(struct bfe_softc *sc) 546{ 547 int i; 548 549 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 550 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 551 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 552 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 553 bus_dmamap_unload(sc->bfe_tag, 554 sc->bfe_rx_ring[i].bfe_map); 555 bus_dmamap_destroy(sc->bfe_tag, 556 sc->bfe_rx_ring[i].bfe_map); 557 } 558 } 559 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 560 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 561} 562 563 564static int 565bfe_list_rx_init(struct bfe_softc *sc) 566{ 567 int i; 568 569 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 570 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 571 return ENOBUFS; 572 } 573 574 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 575 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 576 577 sc->bfe_rx_cons = 0; 578 579 return(0); 580} 581 582static int 583bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 584{ 585 struct bfe_rxheader *rx_header; 586 struct bfe_desc *d; 587 struct bfe_data *r; 588 u_int32_t ctrl; 589 590 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 591 return(EINVAL); 592 593 if(m == NULL) { 594 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 595 if(m == NULL) 596 return(ENOBUFS); 597 m->m_len = m->m_pkthdr.len = MCLBYTES; 598 } 599 else 600 m->m_data = m->m_ext.ext_buf; 601 602 rx_header = mtod(m, struct bfe_rxheader *); 603 rx_header->len = 0; 604 rx_header->flags = 0; 605 606 /* Map the mbuf into DMA */ 607 sc->bfe_rx_cnt = c; 608 d = &sc->bfe_rx_list[c]; 609 r = &sc->bfe_rx_ring[c]; 610 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 611 MCLBYTES, bfe_dma_map_desc, d, 0); 612 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 613 614 ctrl = ETHER_MAX_LEN + 32; 615 616 if(c == BFE_RX_LIST_CNT - 1) 617 ctrl |= BFE_DESC_EOT; 618 619 d->bfe_ctrl = ctrl; 620 r->bfe_mbuf = m; 621 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 622 return(0); 623} 624 625static void 626bfe_get_config(struct bfe_softc *sc) 627{ 628 u_int8_t eeprom[128]; 629 630 bfe_read_eeprom(sc, eeprom); 631 632 sc->arpcom.ac_enaddr[0] = eeprom[79]; 633 sc->arpcom.ac_enaddr[1] = eeprom[78]; 634 sc->arpcom.ac_enaddr[2] = eeprom[81]; 635 sc->arpcom.ac_enaddr[3] = eeprom[80]; 636 sc->arpcom.ac_enaddr[4] = eeprom[83]; 637 sc->arpcom.ac_enaddr[5] = eeprom[82]; 638 639 sc->bfe_phyaddr = eeprom[90] & 0x1f; 640 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 641 642 sc->bfe_core_unit = 0; 643 sc->bfe_dma_offset = BFE_PCI_DMA; 644} 645 646static void 647bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 648{ 649 u_int32_t bar_orig, pci_rev, val; 650 651 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 652 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 653 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 654 655 val = CSR_READ_4(sc, BFE_SBINTVEC); 656 val |= cores; 657 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 658 659 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 660 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 661 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 662 663 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 664} 665 666static void 667bfe_clear_stats(struct bfe_softc *sc) 668{ 669 u_long reg; 670 671 BFE_LOCK(sc); 672 673 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 674 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 675 CSR_READ_4(sc, reg); 676 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 677 CSR_READ_4(sc, reg); 678 679 BFE_UNLOCK(sc); 680} 681 682static int 683bfe_resetphy(struct bfe_softc *sc) 684{ 685 u_int32_t val; 686 687 BFE_LOCK(sc); 688 bfe_writephy(sc, 0, BMCR_RESET); 689 DELAY(100); 690 bfe_readphy(sc, 0, &val); 691 if (val & BMCR_RESET) { 692 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 693 BFE_UNLOCK(sc); 694 return ENXIO; 695 } 696 BFE_UNLOCK(sc); 697 return 0; 698} 699 700static void 701bfe_chip_halt(struct bfe_softc *sc) 702{ 703 BFE_LOCK(sc); 704 /* disable interrupts - not that it actually does..*/ 705 CSR_WRITE_4(sc, BFE_IMASK, 0); 706 CSR_READ_4(sc, BFE_IMASK); 707 708 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 709 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 710 711 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 712 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 713 DELAY(10); 714 715 BFE_UNLOCK(sc); 716} 717 718static void 719bfe_chip_reset(struct bfe_softc *sc) 720{ 721 u_int32_t val; 722 723 BFE_LOCK(sc); 724 725 /* Set the interrupt vector for the enet core */ 726 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 727 728 /* is core up? */ 729 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 730 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 731 if (val == BFE_CLOCK) { 732 /* It is, so shut it down */ 733 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 734 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 735 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 736 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 737 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 738 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 739 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 740 100, 0); 741 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 742 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 743 } 744 745 bfe_core_reset(sc); 746 bfe_clear_stats(sc); 747 748 /* 749 * We want the phy registers to be accessible even when 750 * the driver is "downed" so initialize MDC preamble, frequency, 751 * and whether internal or external phy here. 752 */ 753 754 /* 4402 has 62.5Mhz SB clock and internal phy */ 755 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 756 757 /* Internal or external PHY? */ 758 val = CSR_READ_4(sc, BFE_DEVCTRL); 759 if(!(val & BFE_IPP)) 760 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 761 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 762 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 763 DELAY(100); 764 } 765 766 /* Enable CRC32 generation and set proper LED modes */ 767 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 768 769 /* Reset or clear powerdown control bit */ 770 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 771 772 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 773 BFE_LAZY_FC_MASK)); 774 775 /* 776 * We don't want lazy interrupts, so just send them at 777 * the end of a frame, please 778 */ 779 BFE_OR(sc, BFE_RCV_LAZY, 0); 780 781 /* Set max lengths, accounting for VLAN tags */ 782 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 783 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 784 785 /* Set watermark XXX - magic */ 786 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 787 788 /* 789 * Initialise DMA channels 790 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 791 */ 792 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 793 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 794 795 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 796 BFE_RX_CTRL_ENABLE); 797 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 798 799 bfe_resetphy(sc); 800 bfe_setupphy(sc); 801 802 BFE_UNLOCK(sc); 803} 804 805static void 806bfe_core_disable(struct bfe_softc *sc) 807{ 808 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 809 return; 810 811 /* 812 * Set reject, wait for it set, then wait for the core to stop 813 * being busy, then set reset and reject and enable the clocks. 814 */ 815 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 816 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 817 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 818 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 819 BFE_RESET)); 820 CSR_READ_4(sc, BFE_SBTMSLOW); 821 DELAY(10); 822 /* Leave reset and reject set */ 823 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 824 DELAY(10); 825} 826 827static void 828bfe_core_reset(struct bfe_softc *sc) 829{ 830 u_int32_t val; 831 832 /* Disable the core */ 833 bfe_core_disable(sc); 834 835 /* and bring it back up */ 836 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 837 CSR_READ_4(sc, BFE_SBTMSLOW); 838 DELAY(10); 839 840 /* Chip bug, clear SERR, IB and TO if they are set. */ 841 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 842 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 843 val = CSR_READ_4(sc, BFE_SBIMSTATE); 844 if (val & (BFE_IBE | BFE_TO)) 845 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 846 847 /* Clear reset and allow it to move through the core */ 848 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 849 CSR_READ_4(sc, BFE_SBTMSLOW); 850 DELAY(10); 851 852 /* Leave the clock set */ 853 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 854 CSR_READ_4(sc, BFE_SBTMSLOW); 855 DELAY(10); 856} 857 858static void 859bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 860{ 861 u_int32_t val; 862 863 val = ((u_int32_t) data[2]) << 24; 864 val |= ((u_int32_t) data[3]) << 16; 865 val |= ((u_int32_t) data[4]) << 8; 866 val |= ((u_int32_t) data[5]); 867 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 868 val = (BFE_CAM_HI_VALID | 869 (((u_int32_t) data[0]) << 8) | 870 (((u_int32_t) data[1]))); 871 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 872 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 873 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 874 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 875} 876 877static void 878bfe_set_rx_mode(struct bfe_softc *sc) 879{ 880 struct ifnet *ifp = &sc->arpcom.ac_if; 881 struct ifmultiaddr *ifma; 882 u_int32_t val; 883 int i = 0; 884 885 val = CSR_READ_4(sc, BFE_RXCONF); 886 887 if (ifp->if_flags & IFF_PROMISC) 888 val |= BFE_RXCONF_PROMISC; 889 else 890 val &= ~BFE_RXCONF_PROMISC; 891 892 if (ifp->if_flags & IFF_BROADCAST) 893 val &= ~BFE_RXCONF_DBCAST; 894 else 895 val |= BFE_RXCONF_DBCAST; 896 897 898 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 899 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 900 901 if (ifp->if_flags & IFF_ALLMULTI) 902 val |= BFE_RXCONF_ALLMULTI; 903 else { 904 val &= ~BFE_RXCONF_ALLMULTI; 905 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 906 if (ifma->ifma_addr->sa_family != AF_LINK) 907 continue; 908 bfe_cam_write(sc, 909 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 910 } 911 } 912 913 CSR_WRITE_4(sc, BFE_RXCONF, val); 914 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 915} 916 917static void 918bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 919{ 920 u_int32_t *ptr; 921 922 ptr = arg; 923 *ptr = segs->ds_addr; 924} 925 926static void 927bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 928{ 929 struct bfe_desc *d; 930 931 d = arg; 932 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 933 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 934} 935 936static void 937bfe_release_resources(struct bfe_softc *sc) 938{ 939 device_t dev; 940 int i; 941 942 dev = sc->bfe_dev; 943 944 if (sc->bfe_vpd_prodname != NULL) 945 free(sc->bfe_vpd_prodname, M_DEVBUF); 946 947 if (sc->bfe_vpd_readonly != NULL) 948 free(sc->bfe_vpd_readonly, M_DEVBUF); 949 950 if (sc->bfe_intrhand != NULL) 951 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 952 953 if (sc->bfe_irq != NULL) 954 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 955 956 if (sc->bfe_res != NULL) 957 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 958 959 if(sc->bfe_tx_tag != NULL) { 960 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 961 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 962 sc->bfe_tx_map); 963 bus_dma_tag_destroy(sc->bfe_tx_tag); 964 sc->bfe_tx_tag = NULL; 965 } 966 967 if(sc->bfe_rx_tag != NULL) { 968 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 969 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 970 sc->bfe_rx_map); 971 bus_dma_tag_destroy(sc->bfe_rx_tag); 972 sc->bfe_rx_tag = NULL; 973 } 974 975 if(sc->bfe_tag != NULL) { 976 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 977 bus_dmamap_destroy(sc->bfe_tag, 978 sc->bfe_tx_ring[i].bfe_map); 979 } 980 bus_dma_tag_destroy(sc->bfe_tag); 981 sc->bfe_tag = NULL; 982 } 983 984 if(sc->bfe_parent_tag != NULL) 985 bus_dma_tag_destroy(sc->bfe_parent_tag); 986 987 return; 988} 989 990static void 991bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 992{ 993 long i; 994 u_int16_t *ptr = (u_int16_t *)data; 995 996 for(i = 0; i < 128; i += 2) 997 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 998} 999 1000static int 1001bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1002 u_long timeout, const int clear) 1003{ 1004 u_long i; 1005 1006 for (i = 0; i < timeout; i++) { 1007 u_int32_t val = CSR_READ_4(sc, reg); 1008 1009 if (clear && !(val & bit)) 1010 break; 1011 if (!clear && (val & bit)) 1012 break; 1013 DELAY(10); 1014 } 1015 if (i == timeout) { 1016 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1017 "%x to %s.\n", sc->bfe_unit, bit, reg, 1018 (clear ? "clear" : "set")); 1019 return -1; 1020 } 1021 return 0; 1022} 1023 1024static int 1025bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1026{ 1027 int err; 1028 1029 BFE_LOCK(sc); 1030 /* Clear MII ISR */ 1031 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1032 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1033 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1034 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1035 (reg << BFE_MDIO_RA_SHIFT) | 1036 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1037 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1038 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1039 1040 BFE_UNLOCK(sc); 1041 return err; 1042} 1043 1044static int 1045bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1046{ 1047 int status; 1048 1049 BFE_LOCK(sc); 1050 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1051 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1052 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1053 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1054 (reg << BFE_MDIO_RA_SHIFT) | 1055 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1056 (val & BFE_MDIO_DATA_DATA))); 1057 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1058 BFE_UNLOCK(sc); 1059 1060 return status; 1061} 1062 1063/* 1064 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1065 * twice 1066 */ 1067static int 1068bfe_setupphy(struct bfe_softc *sc) 1069{ 1070 u_int32_t val; 1071 BFE_LOCK(sc); 1072 1073 /* Enable activity LED */ 1074 bfe_readphy(sc, 26, &val); 1075 bfe_writephy(sc, 26, val & 0x7fff); 1076 bfe_readphy(sc, 26, &val); 1077 1078 /* Enable traffic meter LED mode */ 1079 bfe_readphy(sc, 27, &val); 1080 bfe_writephy(sc, 27, val | (1 << 6)); 1081 1082 BFE_UNLOCK(sc); 1083 return 0; 1084} 1085 1086static void 1087bfe_stats_update(struct bfe_softc *sc) 1088{ 1089 u_long reg; 1090 u_int32_t *val; 1091 1092 val = &sc->bfe_hwstats.tx_good_octets; 1093 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1094 *val++ += CSR_READ_4(sc, reg); 1095 } 1096 val = &sc->bfe_hwstats.rx_good_octets; 1097 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1098 *val++ += CSR_READ_4(sc, reg); 1099 } 1100} 1101 1102static void 1103bfe_txeof(struct bfe_softc *sc) 1104{ 1105 struct ifnet *ifp; 1106 int i, chipidx; 1107 1108 BFE_LOCK(sc); 1109 1110 ifp = &sc->arpcom.ac_if; 1111 1112 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1113 chipidx /= sizeof(struct bfe_desc); 1114 1115 i = sc->bfe_tx_cons; 1116 /* Go through the mbufs and free those that have been transmitted */ 1117 while(i != chipidx) { 1118 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1119 if(r->bfe_mbuf != NULL) { 1120 ifp->if_opackets++; 1121 m_freem(r->bfe_mbuf); 1122 r->bfe_mbuf = NULL; 1123 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1124 } 1125 sc->bfe_tx_cnt--; 1126 BFE_INC(i, BFE_TX_LIST_CNT); 1127 } 1128 1129 if(i != sc->bfe_tx_cons) { 1130 /* we freed up some mbufs */ 1131 sc->bfe_tx_cons = i; 1132 ifp->if_flags &= ~IFF_OACTIVE; 1133 } 1134 if(sc->bfe_tx_cnt == 0) 1135 ifp->if_timer = 0; 1136 else 1137 ifp->if_timer = 5; 1138 1139 BFE_UNLOCK(sc); 1140} 1141 1142/* Pass a received packet up the stack */ 1143static void 1144bfe_rxeof(struct bfe_softc *sc) 1145{ 1146 struct mbuf *m; 1147 struct ifnet *ifp; 1148 struct bfe_rxheader *rxheader; 1149 struct bfe_data *r; 1150 int cons; 1151 u_int32_t status, current, len, flags; 1152 1153 BFE_LOCK(sc); 1154 cons = sc->bfe_rx_cons; 1155 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1156 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1157 1158 ifp = &sc->arpcom.ac_if; 1159 1160 while(current != cons) { 1161 r = &sc->bfe_rx_ring[cons]; 1162 m = r->bfe_mbuf; 1163 rxheader = mtod(m, struct bfe_rxheader*); 1164 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1165 len = rxheader->len; 1166 r->bfe_mbuf = NULL; 1167 1168 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1169 flags = rxheader->flags; 1170 1171 len -= ETHER_CRC_LEN; 1172 1173 /* flag an error and try again */ 1174 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1175 ifp->if_ierrors++; 1176 if (flags & BFE_RX_FLAG_SERR) 1177 ifp->if_collisions++; 1178 bfe_list_newbuf(sc, cons, m); 1179 BFE_INC(cons, BFE_RX_LIST_CNT); 1180 continue; 1181 } 1182 1183 /* Go past the rx header */ 1184 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1185 m_adj(m, BFE_RX_OFFSET); 1186 m->m_len = m->m_pkthdr.len = len; 1187 } else { 1188 bfe_list_newbuf(sc, cons, m); 1189 ifp->if_ierrors++; 1190 BFE_INC(cons, BFE_RX_LIST_CNT); 1191 continue; 1192 } 1193 1194 ifp->if_ipackets++; 1195 m->m_pkthdr.rcvif = ifp; 1196 BFE_UNLOCK(sc); 1197 (*ifp->if_input)(ifp, m); 1198 BFE_LOCK(sc); 1199 1200 BFE_INC(cons, BFE_RX_LIST_CNT); 1201 } 1202 sc->bfe_rx_cons = cons; 1203 BFE_UNLOCK(sc); 1204} 1205 1206static void 1207bfe_intr(void *xsc) 1208{ 1209 struct bfe_softc *sc = xsc; 1210 struct ifnet *ifp; 1211 u_int32_t istat, imask, flag; 1212 1213 ifp = &sc->arpcom.ac_if; 1214 1215 BFE_LOCK(sc); 1216 1217 istat = CSR_READ_4(sc, BFE_ISTAT); 1218 imask = CSR_READ_4(sc, BFE_IMASK); 1219 1220 /* 1221 * Defer unsolicited interrupts - This is necessary because setting the 1222 * chips interrupt mask register to 0 doesn't actually stop the 1223 * interrupts 1224 */ 1225 istat &= imask; 1226 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1227 CSR_READ_4(sc, BFE_ISTAT); 1228 1229 /* not expecting this interrupt, disregard it */ 1230 if(istat == 0) { 1231 BFE_UNLOCK(sc); 1232 return; 1233 } 1234 1235 if(istat & BFE_ISTAT_ERRORS) { 1236 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1237 if(flag & BFE_STAT_EMASK) 1238 ifp->if_oerrors++; 1239 1240 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1241 if(flag & BFE_RX_FLAG_ERRORS) 1242 ifp->if_ierrors++; 1243 1244 ifp->if_flags &= ~IFF_RUNNING; 1245 bfe_init(sc); 1246 } 1247 1248 /* A packet was received */ 1249 if(istat & BFE_ISTAT_RX) 1250 bfe_rxeof(sc); 1251 1252 /* A packet was sent */ 1253 if(istat & BFE_ISTAT_TX) 1254 bfe_txeof(sc); 1255 1256 /* We have packets pending, fire them out */ 1257 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1258 bfe_start(ifp); 1259 1260 BFE_UNLOCK(sc); 1261} 1262 1263static int 1264bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1265{ 1266 struct bfe_desc *d = NULL; 1267 struct bfe_data *r = NULL; 1268 struct mbuf *m; 1269 u_int32_t frag, cur, cnt = 0; 1270 int chainlen = 0; 1271 1272 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1273 return(ENOBUFS); 1274 1275 /* 1276 * Count the number of frags in this chain to see if 1277 * we need to m_defrag. Since the descriptor list is shared 1278 * by all packets, we'll m_defrag long chains so that they 1279 * do not use up the entire list, even if they would fit. 1280 */ 1281 for(m = m_head; m != NULL; m = m->m_next) 1282 chainlen++; 1283 1284 1285 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1286 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1287 m = m_defrag(m_head, M_DONTWAIT); 1288 if (m == NULL) 1289 return(ENOBUFS); 1290 m_head = m; 1291 } 1292 1293 /* 1294 * Start packing the mbufs in this chain into 1295 * the fragment pointers. Stop when we run out 1296 * of fragments or hit the end of the mbuf chain. 1297 */ 1298 m = m_head; 1299 cur = frag = *txidx; 1300 cnt = 0; 1301 1302 for(m = m_head; m != NULL; m = m->m_next) { 1303 if(m->m_len != 0) { 1304 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1305 return(ENOBUFS); 1306 1307 d = &sc->bfe_tx_list[cur]; 1308 r = &sc->bfe_tx_ring[cur]; 1309 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1310 /* always intterupt on completion */ 1311 d->bfe_ctrl |= BFE_DESC_IOC; 1312 if(cnt == 0) 1313 /* Set start of frame */ 1314 d->bfe_ctrl |= BFE_DESC_SOF; 1315 if(cur == BFE_TX_LIST_CNT - 1) 1316 /* 1317 * Tell the chip to wrap to the start of 1318 * the descriptor list 1319 */ 1320 d->bfe_ctrl |= BFE_DESC_EOT; 1321 1322 bus_dmamap_load(sc->bfe_tag, 1323 r->bfe_map, mtod(m, void*), m->m_len, 1324 bfe_dma_map_desc, d, 0); 1325 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1326 BUS_DMASYNC_PREREAD); 1327 1328 frag = cur; 1329 BFE_INC(cur, BFE_TX_LIST_CNT); 1330 cnt++; 1331 } 1332 } 1333 1334 if (m != NULL) 1335 return(ENOBUFS); 1336 1337 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1338 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1339 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1340 1341 *txidx = cur; 1342 sc->bfe_tx_cnt += cnt; 1343 return (0); 1344} 1345 1346/* 1347 * Set up to transmit a packet 1348 */ 1349static void 1350bfe_start(struct ifnet *ifp) 1351{ 1352 struct bfe_softc *sc; 1353 struct mbuf *m_head = NULL; 1354 int idx; 1355 1356 sc = ifp->if_softc; 1357 idx = sc->bfe_tx_prod; 1358 1359 BFE_LOCK(sc); 1360 1361 /* 1362 * Not much point trying to send if the link is down 1363 * or we have nothing to send. 1364 */ 1365 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1366 BFE_UNLOCK(sc); 1367 return; 1368 } 1369 1370 if (ifp->if_flags & IFF_OACTIVE) { 1371 BFE_UNLOCK(sc); 1372 return; 1373 } 1374 1375 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1376 IF_DEQUEUE(&ifp->if_snd, m_head); 1377 if(m_head == NULL) 1378 break; 1379 1380 /* 1381 * Pack the data into the tx ring. If we dont have 1382 * enough room, let the chip drain the ring. 1383 */ 1384 if(bfe_encap(sc, m_head, &idx)) { 1385 IF_PREPEND(&ifp->if_snd, m_head); 1386 ifp->if_flags |= IFF_OACTIVE; 1387 break; 1388 } 1389 1390 /* 1391 * If there's a BPF listener, bounce a copy of this frame 1392 * to him. 1393 */ 1394 BPF_MTAP(ifp, m_head); 1395 } 1396 1397 sc->bfe_tx_prod = idx; 1398 /* Transmit - twice due to apparent hardware bug */ 1399 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1400 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1401 1402 /* 1403 * Set a timeout in case the chip goes out to lunch. 1404 */ 1405 ifp->if_timer = 5; 1406 BFE_UNLOCK(sc); 1407} 1408 1409static void 1410bfe_init(void *xsc) 1411{ 1412 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1413 struct ifnet *ifp = &sc->arpcom.ac_if; 1414 1415 BFE_LOCK(sc); 1416 1417 if (ifp->if_flags & IFF_RUNNING) { 1418 BFE_UNLOCK(sc); 1419 return; 1420 } 1421 1422 bfe_stop(sc); 1423 bfe_chip_reset(sc); 1424 1425 if (bfe_list_rx_init(sc) == ENOBUFS) { 1426 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1427 sc->bfe_unit); 1428 bfe_stop(sc); 1429 return; 1430 } 1431 1432 bfe_set_rx_mode(sc); 1433 1434 /* Enable the chip and core */ 1435 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1436 /* Enable interrupts */ 1437 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1438 1439 bfe_ifmedia_upd(ifp); 1440 ifp->if_flags |= IFF_RUNNING; 1441 ifp->if_flags &= ~IFF_OACTIVE; 1442 1443 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1444 BFE_UNLOCK(sc); 1445} 1446 1447/* 1448 * Set media options. 1449 */ 1450static int 1451bfe_ifmedia_upd(struct ifnet *ifp) 1452{ 1453 struct bfe_softc *sc; 1454 struct mii_data *mii; 1455 1456 sc = ifp->if_softc; 1457 1458 BFE_LOCK(sc); 1459 1460 mii = device_get_softc(sc->bfe_miibus); 1461 sc->bfe_link = 0; 1462 if (mii->mii_instance) { 1463 struct mii_softc *miisc; 1464 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1465 miisc = LIST_NEXT(miisc, mii_list)) 1466 mii_phy_reset(miisc); 1467 } 1468 mii_mediachg(mii); 1469 1470 BFE_UNLOCK(sc); 1471 return(0); 1472} 1473 1474/* 1475 * Report current media status. 1476 */ 1477static void 1478bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1479{ 1480 struct bfe_softc *sc = ifp->if_softc; 1481 struct mii_data *mii; 1482 1483 BFE_LOCK(sc); 1484 1485 mii = device_get_softc(sc->bfe_miibus); 1486 mii_pollstat(mii); 1487 ifmr->ifm_active = mii->mii_media_active; 1488 ifmr->ifm_status = mii->mii_media_status; 1489 1490 BFE_UNLOCK(sc); 1491} 1492 1493static int 1494bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1495{ 1496 struct bfe_softc *sc = ifp->if_softc; 1497 struct ifreq *ifr = (struct ifreq *) data; 1498 struct mii_data *mii; 1499 int error = 0; 1500 1501 BFE_LOCK(sc); 1502 1503 switch(command) { 1504 case SIOCSIFFLAGS: 1505 if(ifp->if_flags & IFF_UP) 1506 if(ifp->if_flags & IFF_RUNNING) 1507 bfe_set_rx_mode(sc); 1508 else 1509 bfe_init(sc); 1510 else if(ifp->if_flags & IFF_RUNNING) 1511 bfe_stop(sc); 1512 break; 1513 case SIOCADDMULTI: 1514 case SIOCDELMULTI: 1515 if(ifp->if_flags & IFF_RUNNING) 1516 bfe_set_rx_mode(sc); 1517 break; 1518 case SIOCGIFMEDIA: 1519 case SIOCSIFMEDIA: 1520 mii = device_get_softc(sc->bfe_miibus); 1521 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1522 command); 1523 break; 1524 default: 1525 error = ether_ioctl(ifp, command, data); 1526 break; 1527 } 1528 1529 BFE_UNLOCK(sc); 1530 return error; 1531} 1532 1533static void 1534bfe_watchdog(struct ifnet *ifp) 1535{ 1536 struct bfe_softc *sc; 1537 1538 sc = ifp->if_softc; 1539 1540 BFE_LOCK(sc); 1541 1542 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1543 1544 ifp->if_flags &= ~IFF_RUNNING; 1545 bfe_init(sc); 1546 1547 ifp->if_oerrors++; 1548 1549 BFE_UNLOCK(sc); 1550} 1551 1552static void 1553bfe_tick(void *xsc) 1554{ 1555 struct bfe_softc *sc = xsc; 1556 struct mii_data *mii; 1557 1558 if (sc == NULL) 1559 return; 1560 1561 BFE_LOCK(sc); 1562 1563 mii = device_get_softc(sc->bfe_miibus); 1564 1565 bfe_stats_update(sc); 1566 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1567 1568 if(sc->bfe_link) { 1569 BFE_UNLOCK(sc); 1570 return; 1571 } 1572 1573 mii_tick(mii); 1574 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1575 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1576 sc->bfe_link++; 1577 1578 BFE_UNLOCK(sc); 1579} 1580 1581/* 1582 * Stop the adapter and free any mbufs allocated to the 1583 * RX and TX lists. 1584 */ 1585static void 1586bfe_stop(struct bfe_softc *sc) 1587{ 1588 struct ifnet *ifp; 1589 1590 BFE_LOCK(sc); 1591 1592 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1593 1594 ifp = &sc->arpcom.ac_if; 1595 1596 bfe_chip_halt(sc); 1597 bfe_tx_ring_free(sc); 1598 bfe_rx_ring_free(sc); 1599 1600 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1601 1602 BFE_UNLOCK(sc); 1603} 1604