if_ath_tx.c revision 248671
152942Sbrian/*- 252942Sbrian * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 352942Sbrian * Copyright (c) 2010-2012 Adrian Chadd, Xenion Pty Ltd 452942Sbrian * All rights reserved. 552942Sbrian * 652942Sbrian * Redistribution and use in source and binary forms, with or without 752942Sbrian * modification, are permitted provided that the following conditions 852942Sbrian * are met: 952942Sbrian * 1. Redistributions of source code must retain the above copyright 1052942Sbrian * notice, this list of conditions and the following disclaimer, 1152942Sbrian * without modification. 1252942Sbrian * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1352942Sbrian * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 1452942Sbrian * redistribution must be conditioned upon including a substantially 1552942Sbrian * similar Disclaimer requirement for further binary redistribution. 1652942Sbrian * 1752942Sbrian * NO WARRANTY 1852942Sbrian * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1952942Sbrian * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2052942Sbrian * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 2152942Sbrian * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 2252942Sbrian * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 2352942Sbrian * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2452942Sbrian * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2552942Sbrian * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 2652942Sbrian * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2752942Sbrian * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 2852942Sbrian * THE POSSIBILITY OF SUCH DAMAGES. 2952942Sbrian */ 3052942Sbrian 3152942Sbrian#include <sys/cdefs.h> 3252942Sbrian__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_tx.c 248671 2013-03-24 00:03:12Z adrian $"); 3352942Sbrian 3452942Sbrian/* 3552942Sbrian * Driver for the Atheros Wireless LAN controller. 3652942Sbrian * 3774916Sbrian * This software is derived from work of Atsushi Onoe; his contribution 3874916Sbrian * is greatly appreciated. 3952942Sbrian */ 4052942Sbrian 4152942Sbrian#include "opt_inet.h" 4252942Sbrian#include "opt_ath.h" 4352942Sbrian#include "opt_wlan.h" 4452942Sbrian 4552942Sbrian#include <sys/param.h> 4652942Sbrian#include <sys/systm.h> 4752942Sbrian#include <sys/sysctl.h> 4852942Sbrian#include <sys/mbuf.h> 4952942Sbrian#include <sys/malloc.h> 5052942Sbrian#include <sys/lock.h> 5152942Sbrian#include <sys/mutex.h> 5271006Sbrian#include <sys/kernel.h> 5352942Sbrian#include <sys/socket.h> 5452942Sbrian#include <sys/sockio.h> 5552942Sbrian#include <sys/errno.h> 5696582Sbrian#include <sys/callout.h> 5752942Sbrian#include <sys/bus.h> 5852942Sbrian#include <sys/endian.h> 5952942Sbrian#include <sys/kthread.h> 6052942Sbrian#include <sys/taskqueue.h> 6152942Sbrian#include <sys/priv.h> 6252942Sbrian 6352942Sbrian#include <machine/bus.h> 6452942Sbrian 6552942Sbrian#include <net/if.h> 6652942Sbrian#include <net/if_dl.h> 6752942Sbrian#include <net/if_media.h> 6852942Sbrian#include <net/if_types.h> 6952942Sbrian#include <net/if_arp.h> 7052942Sbrian#include <net/ethernet.h> 7152942Sbrian#include <net/if_llc.h> 7252942Sbrian 7352942Sbrian#include <net80211/ieee80211_var.h> 7452942Sbrian#include <net80211/ieee80211_regdomain.h> 7552942Sbrian#ifdef IEEE80211_SUPPORT_SUPERG 7652942Sbrian#include <net80211/ieee80211_superg.h> 7752942Sbrian#endif 7852942Sbrian#ifdef IEEE80211_SUPPORT_TDMA 7952942Sbrian#include <net80211/ieee80211_tdma.h> 8052942Sbrian#endif 8152942Sbrian#include <net80211/ieee80211_ht.h> 8252942Sbrian 8381634Sbrian#include <net/bpf.h> 8481634Sbrian 8552942Sbrian#ifdef INET 8652942Sbrian#include <netinet/in.h> 8752942Sbrian#include <netinet/if_ether.h> 8852942Sbrian#endif 8952942Sbrian 9081634Sbrian#include <dev/ath/if_athvar.h> 9181634Sbrian#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 9252942Sbrian#include <dev/ath/ath_hal/ah_diagcodes.h> 9352942Sbrian 9474916Sbrian#include <dev/ath/if_ath_debug.h> 9596582Sbrian 9652942Sbrian#ifdef ATH_TX99_DIAG 9752942Sbrian#include <dev/ath/ath_tx99/ath_tx99.h> 9852942Sbrian#endif 9952942Sbrian 10052942Sbrian#include <dev/ath/if_ath_misc.h> 10152942Sbrian#include <dev/ath/if_ath_tx.h> 10252942Sbrian#include <dev/ath/if_ath_tx_ht.h> 10352942Sbrian 10452942Sbrian#ifdef ATH_DEBUG_ALQ 10552942Sbrian#include <dev/ath/if_ath_alq.h> 10652942Sbrian#endif 10796582Sbrian 10852942Sbrian/* 10952942Sbrian * How many retries to perform in software 11052942Sbrian */ 11152942Sbrian#define SWMAX_RETRIES 10 11252942Sbrian 113134789Sbrian/* 11452942Sbrian * What queue to throw the non-QoS TID traffic into 11552942Sbrian */ 11652942Sbrian#define ATH_NONQOS_TID_AC WME_AC_VO 11752942Sbrian 11852942Sbrian#if 0 11952942Sbrianstatic int ath_tx_node_is_asleep(struct ath_softc *sc, struct ath_node *an); 12052942Sbrian#endif 12152942Sbrianstatic int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, 12252942Sbrian int tid); 12352942Sbrianstatic int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, 124134789Sbrian int tid); 12552942Sbrianstatic ieee80211_seq ath_tx_tid_seqno_assign(struct ath_softc *sc, 12652942Sbrian struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0); 12752942Sbrianstatic int ath_tx_action_frame_override_queue(struct ath_softc *sc, 12852942Sbrian struct ieee80211_node *ni, struct mbuf *m0, int *tid); 12952942Sbrianstatic struct ath_buf * 13052942Sbrianath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an, 13152942Sbrian struct ath_tid *tid, struct ath_buf *bf); 13252942Sbrian 13352942Sbrian#ifdef ATH_DEBUG_ALQ 13452942Sbrianvoid 13552942Sbrianath_tx_alq_post(struct ath_softc *sc, struct ath_buf *bf_first) 13652942Sbrian{ 13752942Sbrian struct ath_buf *bf; 13852942Sbrian int i, n; 13952942Sbrian const char *ds; 14052942Sbrian 14152942Sbrian /* XXX we should skip out early if debugging isn't enabled! */ 14252942Sbrian bf = bf_first; 14352942Sbrian 14452942Sbrian while (bf != NULL) { 14552942Sbrian /* XXX should ensure bf_nseg > 0! */ 14652942Sbrian if (bf->bf_nseg == 0) 14752942Sbrian break; 14852942Sbrian n = ((bf->bf_nseg - 1) / sc->sc_tx_nmaps) + 1; 14952942Sbrian for (i = 0, ds = (const char *) bf->bf_desc; 15052942Sbrian i < n; 15152942Sbrian i++, ds += sc->sc_tx_desclen) { 15252942Sbrian if_ath_alq_post(&sc->sc_alq, 15352942Sbrian ATH_ALQ_EDMA_TXDESC, 15452942Sbrian sc->sc_tx_desclen, 15552942Sbrian ds); 15652942Sbrian } 15752942Sbrian bf = bf->bf_next; 15852942Sbrian } 15952942Sbrian} 16052942Sbrian#endif /* ATH_DEBUG_ALQ */ 16152942Sbrian 16252942Sbrian/* 16352942Sbrian * Whether to use the 11n rate scenario functions or not 16452942Sbrian */ 16552942Sbrianstatic inline int 16652942Sbrianath_tx_is_11n(struct ath_softc *sc) 16752942Sbrian{ 16852942Sbrian return ((sc->sc_ah->ah_magic == 0x20065416) || 16952942Sbrian (sc->sc_ah->ah_magic == 0x19741014)); 17052942Sbrian} 17152942Sbrian 17252942Sbrian/* 17352942Sbrian * Obtain the current TID from the given frame. 17452942Sbrian * 17552942Sbrian * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.) 17652942Sbrian * This has implications for which AC/priority the packet is placed 17752942Sbrian * in. 17852942Sbrian */ 17952942Sbrianstatic int 18052942Sbrianath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0) 18152942Sbrian{ 18252942Sbrian const struct ieee80211_frame *wh; 18396582Sbrian int pri = M_WME_GETAC(m0); 18496582Sbrian 18596582Sbrian wh = mtod(m0, const struct ieee80211_frame *); 18696582Sbrian if (! IEEE80211_QOS_HAS_SEQ(wh)) 18796582Sbrian return IEEE80211_NONQOS_TID; 18896582Sbrian else 18996582Sbrian return WME_AC_TO_TID(pri); 19096582Sbrian} 19196582Sbrian 19252942Sbrianstatic void 19352942Sbrianath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) 194134789Sbrian{ 19552942Sbrian struct ieee80211_frame *wh; 19652942Sbrian 19752942Sbrian wh = mtod(bf->bf_m, struct ieee80211_frame *); 19852942Sbrian /* Only update/resync if needed */ 19952942Sbrian if (bf->bf_state.bfs_isretried == 0) { 20052942Sbrian wh->i_fc[1] |= IEEE80211_FC1_RETRY; 20152942Sbrian bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 20252942Sbrian BUS_DMASYNC_PREWRITE); 20352942Sbrian } 20452942Sbrian bf->bf_state.bfs_isretried = 1; 20552942Sbrian bf->bf_state.bfs_retries ++; 20652942Sbrian} 20752942Sbrian 20852942Sbrian/* 20952942Sbrian * Determine what the correct AC queue for the given frame 21052942Sbrian * should be. 21152942Sbrian * 21252942Sbrian * This code assumes that the TIDs map consistently to 21352942Sbrian * the underlying hardware (or software) ath_txq. 21452942Sbrian * Since the sender may try to set an AC which is 21552942Sbrian * arbitrary, non-QoS TIDs may end up being put on 21652942Sbrian * completely different ACs. There's no way to put a 21752942Sbrian * TID into multiple ath_txq's for scheduling, so 21852942Sbrian * for now we override the AC/TXQ selection and set 21996582Sbrian * non-QOS TID frames into the BE queue. 22052942Sbrian * 22152942Sbrian * This may be completely incorrect - specifically, 22266898Sbrian * some management frames may end up out of order 22396582Sbrian * compared to the QoS traffic they're controlling. 22498638Sbrian * I'll look into this later. 22552942Sbrian */ 22652942Sbrianstatic int 22752942Sbrianath_tx_getac(struct ath_softc *sc, const struct mbuf *m0) 22852942Sbrian{ 22966898Sbrian const struct ieee80211_frame *wh; 23066898Sbrian int pri = M_WME_GETAC(m0); 23166898Sbrian wh = mtod(m0, const struct ieee80211_frame *); 23266898Sbrian if (IEEE80211_QOS_HAS_SEQ(wh)) 23366898Sbrian return pri; 23499086Sbrian 23599086Sbrian return ATH_NONQOS_TID_AC; 23699086Sbrian} 23799086Sbrian 23899086Sbrianvoid 23952942Sbrianath_txfrag_cleanup(struct ath_softc *sc, 24099086Sbrian ath_bufhead *frags, struct ieee80211_node *ni) 24199086Sbrian{ 24252942Sbrian struct ath_buf *bf, *next; 24399086Sbrian 24499086Sbrian ATH_TXBUF_LOCK_ASSERT(sc); 24552942Sbrian 24699086Sbrian TAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 24799086Sbrian /* NB: bf assumed clean */ 24899086Sbrian TAILQ_REMOVE(frags, bf, bf_list); 24999086Sbrian ath_returnbuf_head(sc, bf); 25099086Sbrian ieee80211_node_decref(ni); 25152942Sbrian } 25299086Sbrian} 25399086Sbrian 25499086Sbrian/* 25590975Sbrian * Setup xmit of a fragmented frame. Allocate a buffer 25699086Sbrian * for each frag and bump the node reference count to 25752942Sbrian * reflect the held reference to be setup by ath_tx_start. 25899086Sbrian */ 25999086Sbrianint 26099086Sbrianath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 26199086Sbrian struct mbuf *m0, struct ieee80211_node *ni) 26299086Sbrian{ 26399086Sbrian struct mbuf *m; 26499086Sbrian struct ath_buf *bf; 26599086Sbrian 26699086Sbrian ATH_TXBUF_LOCK(sc); 26799086Sbrian for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 26899086Sbrian /* XXX non-management? */ 26999086Sbrian bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL); 27099086Sbrian if (bf == NULL) { /* out of buffers, cleanup */ 27199086Sbrian device_printf(sc->sc_dev, "%s: no buffer?\n", 27299086Sbrian __func__); 27399086Sbrian ath_txfrag_cleanup(sc, frags, ni); 27499086Sbrian break; 27599086Sbrian } 27699086Sbrian ieee80211_node_incref(ni); 27799086Sbrian TAILQ_INSERT_TAIL(frags, bf, bf_list); 27899086Sbrian } 27999086Sbrian ATH_TXBUF_UNLOCK(sc); 28099086Sbrian 28199086Sbrian return !TAILQ_EMPTY(frags); 28299086Sbrian} 28399086Sbrian 28499086Sbrian/* 28599086Sbrian * Reclaim mbuf resources. For fragmented frames we 28699086Sbrian * need to claim each frag chained with m_nextpkt. 28799086Sbrian */ 28899086Sbrianvoid 28999086Sbrianath_freetx(struct mbuf *m) 29052942Sbrian{ 29199086Sbrian struct mbuf *next; 29299086Sbrian 29399086Sbrian do { 29499086Sbrian next = m->m_nextpkt; 29599086Sbrian m->m_nextpkt = NULL; 29699086Sbrian m_freem(m); 29799086Sbrian } while ((m = next) != NULL); 29899086Sbrian} 29999086Sbrian 30099086Sbrianstatic int 30199086Sbrianath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 30299086Sbrian{ 30399086Sbrian struct mbuf *m; 30499086Sbrian int error; 30599086Sbrian 30652942Sbrian /* 30799086Sbrian * Load the DMA map so any coalescing is done. This 30852942Sbrian * also calculates the number of descriptors we need. 30952942Sbrian */ 31052942Sbrian error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 31152942Sbrian bf->bf_segs, &bf->bf_nseg, 31252942Sbrian BUS_DMA_NOWAIT); 31352942Sbrian if (error == EFBIG) { 31452942Sbrian /* XXX packet requires too many descriptors */ 31553071Sbrian bf->bf_nseg = ATH_TXDESC+1; 31652942Sbrian } else if (error != 0) { 31752942Sbrian sc->sc_stats.ast_tx_busdma++; 31852942Sbrian ath_freetx(m0); 31952942Sbrian return error; 32052942Sbrian } 32152942Sbrian /* 32252942Sbrian * Discard null packets and check for packets that 32352942Sbrian * require too many TX descriptors. We try to convert 32452942Sbrian * the latter to a cluster. 32552942Sbrian */ 32678410Sbrian if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 32753733Sbrian sc->sc_stats.ast_tx_linear++; 32852942Sbrian m = m_collapse(m0, M_NOWAIT, ATH_TXDESC); 32952942Sbrian if (m == NULL) { 33052942Sbrian ath_freetx(m0); 33152942Sbrian sc->sc_stats.ast_tx_nombuf++; 33252942Sbrian return ENOMEM; 33352942Sbrian } 33493418Sbrian m0 = m; 33552942Sbrian error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 33652942Sbrian bf->bf_segs, &bf->bf_nseg, 33752942Sbrian BUS_DMA_NOWAIT); 33852942Sbrian if (error != 0) { 33952942Sbrian sc->sc_stats.ast_tx_busdma++; 34096582Sbrian ath_freetx(m0); 34196582Sbrian return error; 34252942Sbrian } 34352942Sbrian KASSERT(bf->bf_nseg <= ATH_TXDESC, 34452942Sbrian ("too many segments after defrag; nseg %u", bf->bf_nseg)); 34552942Sbrian } else if (bf->bf_nseg == 0) { /* null packet, discard */ 346134789Sbrian sc->sc_stats.ast_tx_nodata++; 34752942Sbrian ath_freetx(m0); 34852942Sbrian return EIO; 34952942Sbrian } 35052942Sbrian DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 35152942Sbrian __func__, m0, m0->m_pkthdr.len); 35252942Sbrian bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 35352942Sbrian bf->bf_m = m0; 35452942Sbrian 35552942Sbrian return 0; 35652942Sbrian} 35752942Sbrian 35852942Sbrian/* 35952942Sbrian * Chain together segments+descriptors for a frame - 11n or otherwise. 36052942Sbrian * 36152942Sbrian * For aggregates, this is called on each frame in the aggregate. 36252942Sbrian */ 36352942Sbrianstatic void 36452942Sbrianath_tx_chaindesclist(struct ath_softc *sc, struct ath_desc *ds0, 36552942Sbrian struct ath_buf *bf, int is_aggr, int is_first_subframe, 36652942Sbrian int is_last_subframe) 36752942Sbrian{ 36852942Sbrian struct ath_hal *ah = sc->sc_ah; 36952942Sbrian char *ds; 37052942Sbrian int i, bp, dsp; 37152942Sbrian HAL_DMA_ADDR bufAddrList[4]; 37252942Sbrian uint32_t segLenList[4]; 37352942Sbrian int numTxMaps = 1; 37452942Sbrian int isFirstDesc = 1; 37558028Sbrian 37652942Sbrian /* 37752942Sbrian * XXX There's txdma and txdma_mgmt; the descriptor 37852942Sbrian * sizes must match. 37952942Sbrian */ 38052942Sbrian struct ath_descdma *dd = &sc->sc_txdma; 38152942Sbrian 38252942Sbrian /* 38352942Sbrian * Fillin the remainder of the descriptor info. 38452942Sbrian */ 38552942Sbrian 38652942Sbrian /* 38752942Sbrian * We need the number of TX data pointers in each descriptor. 38852942Sbrian * EDMA and later chips support 4 TX buffers per descriptor; 38952942Sbrian * previous chips just support one. 39052942Sbrian */ 39152942Sbrian numTxMaps = sc->sc_tx_nmaps; 39252942Sbrian 39352942Sbrian /* 39458028Sbrian * For EDMA and later chips ensure the TX map is fully populated 39552942Sbrian * before advancing to the next descriptor. 39652942Sbrian */ 39752942Sbrian ds = (char *) bf->bf_desc; 39852942Sbrian bp = dsp = 0; 39952942Sbrian bzero(bufAddrList, sizeof(bufAddrList)); 40052942Sbrian bzero(segLenList, sizeof(segLenList)); 40152942Sbrian for (i = 0; i < bf->bf_nseg; i++) { 40252942Sbrian bufAddrList[bp] = bf->bf_segs[i].ds_addr; 40352942Sbrian segLenList[bp] = bf->bf_segs[i].ds_len; 40452942Sbrian bp++; 40552942Sbrian 40652942Sbrian /* 40758028Sbrian * Go to the next segment if this isn't the last segment 40852942Sbrian * and there's space in the current TX map. 40952942Sbrian */ 41052942Sbrian if ((i != bf->bf_nseg - 1) && (bp < numTxMaps)) 41152942Sbrian continue; 41252942Sbrian 41352942Sbrian /* 41452942Sbrian * Last segment or we're out of buffer pointers. 41552942Sbrian */ 41652942Sbrian bp = 0; 41752942Sbrian 41852942Sbrian if (i == bf->bf_nseg - 1) 41952942Sbrian ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 0); 42052942Sbrian else 42152942Sbrian ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 42252942Sbrian bf->bf_daddr + dd->dd_descsize * (dsp + 1)); 42352942Sbrian 42452942Sbrian /* 42552942Sbrian * XXX This assumes that bfs_txq is the actual destination 42652942Sbrian * hardware queue at this point. It may not have been 42752942Sbrian * assigned, it may actually be pointing to the multicast 42852942Sbrian * software TXQ id. These must be fixed! 42952942Sbrian */ 43052942Sbrian ath_hal_filltxdesc(ah, (struct ath_desc *) ds 43152942Sbrian , bufAddrList 43252942Sbrian , segLenList 43352942Sbrian , bf->bf_descid /* XXX desc id */ 43452942Sbrian , bf->bf_state.bfs_tx_queue 43552942Sbrian , isFirstDesc /* first segment */ 43652942Sbrian , i == bf->bf_nseg - 1 /* last segment */ 43752942Sbrian , (struct ath_desc *) ds0 /* first descriptor */ 43852942Sbrian ); 43952942Sbrian 44052942Sbrian /* 44152942Sbrian * Make sure the 11n aggregate fields are cleared. 44252942Sbrian * 44352942Sbrian * XXX TODO: this doesn't need to be called for 44452942Sbrian * aggregate frames; as it'll be called on all 44552942Sbrian * sub-frames. Since the descriptors are in 446134789Sbrian * non-cacheable memory, this leads to some 447134789Sbrian * rather slow writes on MIPS/ARM platforms. 448134789Sbrian */ 449134789Sbrian if (ath_tx_is_11n(sc)) 45052942Sbrian ath_hal_clr11n_aggr(sc->sc_ah, (struct ath_desc *) ds); 45152942Sbrian 45274916Sbrian /* 45374916Sbrian * If 11n is enabled, set it up as if it's an aggregate 45452942Sbrian * frame. 45552942Sbrian */ 45652942Sbrian if (is_last_subframe) { 45752942Sbrian ath_hal_set11n_aggr_last(sc->sc_ah, 45852942Sbrian (struct ath_desc *) ds); 45952942Sbrian } else if (is_aggr) { 46052942Sbrian /* 46152942Sbrian * This clears the aggrlen field; so 46274916Sbrian * the caller needs to call set_aggr_first()! 46374916Sbrian * 46452942Sbrian * XXX TODO: don't call this for the first 46552942Sbrian * descriptor in the first frame in an 46652942Sbrian * aggregate! 46752942Sbrian */ 46893418Sbrian ath_hal_set11n_aggr_middle(sc->sc_ah, 46993418Sbrian (struct ath_desc *) ds, 47052942Sbrian bf->bf_state.bfs_ndelim); 47152942Sbrian } 47252942Sbrian isFirstDesc = 0; 47352942Sbrian bf->bf_lastds = (struct ath_desc *) ds; 47452942Sbrian 47552942Sbrian /* 47652942Sbrian * Don't forget to skip to the next descriptor. 47752942Sbrian */ 47852942Sbrian ds += sc->sc_tx_desclen; 47952942Sbrian dsp++; 48052942Sbrian 48152942Sbrian /* 48252942Sbrian * .. and don't forget to blank these out! 48352942Sbrian */ 48452942Sbrian bzero(bufAddrList, sizeof(bufAddrList)); 48552942Sbrian bzero(segLenList, sizeof(segLenList)); 48652942Sbrian } 48752942Sbrian bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 48852942Sbrian} 48952942Sbrian 49052942Sbrian/* 49152942Sbrian * Set the rate control fields in the given descriptor based on 49252942Sbrian * the bf_state fields and node state. 49352942Sbrian * 49452942Sbrian * The bfs fields should already be set with the relevant rate 49552942Sbrian * control information, including whether MRR is to be enabled. 49652942Sbrian * 49752942Sbrian * Since the FreeBSD HAL currently sets up the first TX rate 49852942Sbrian * in ath_hal_setuptxdesc(), this will setup the MRR 49952942Sbrian * conditionally for the pre-11n chips, and call ath_buf_set_rate 50052942Sbrian * unconditionally for 11n chips. These require the 11n rate 50152942Sbrian * scenario to be set if MCS rates are enabled, so it's easier 50252942Sbrian * to just always call it. The caller can then only set rates 2, 3 50352942Sbrian * and 4 if multi-rate retry is needed. 50452942Sbrian */ 50552942Sbrianstatic void 50652942Sbrianath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 50752942Sbrian struct ath_buf *bf) 50852942Sbrian{ 50953535Sbrian struct ath_rc_series *rc = bf->bf_state.bfs_rc; 51052942Sbrian 51152942Sbrian /* If mrr is disabled, blank tries 1, 2, 3 */ 51252942Sbrian if (! bf->bf_state.bfs_ismrr) 51393418Sbrian rc[1].tries = rc[2].tries = rc[3].tries = 0; 51452942Sbrian 51552942Sbrian#if 0 51652942Sbrian /* 51752942Sbrian * If NOACK is set, just set ntries=1. 51852942Sbrian */ 51952942Sbrian else if (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) { 52052942Sbrian rc[1].tries = rc[2].tries = rc[3].tries = 0; 52152942Sbrian rc[0].tries = 1; 522134833Smarcel } 52352942Sbrian#endif 52452942Sbrian 52552942Sbrian /* 52652942Sbrian * Always call - that way a retried descriptor will 52752942Sbrian * have the MRR fields overwritten. 52852942Sbrian * 52952942Sbrian * XXX TODO: see if this is really needed - setting up 53052942Sbrian * the first descriptor should set the MRR fields to 0 53152942Sbrian * for us anyway. 53282277Sbrian */ 53352942Sbrian if (ath_tx_is_11n(sc)) { 53452942Sbrian ath_buf_set_rate(sc, ni, bf); 53552942Sbrian } else { 53652942Sbrian ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc 53752942Sbrian , rc[1].ratecode, rc[1].tries 53852942Sbrian , rc[2].ratecode, rc[2].tries 53952942Sbrian , rc[3].ratecode, rc[3].tries 54052942Sbrian ); 54152942Sbrian } 54252942Sbrian} 54352942Sbrian 54452942Sbrian/* 54552942Sbrian * Setup segments+descriptors for an 11n aggregate. 54652942Sbrian * bf_first is the first buffer in the aggregate. 54752942Sbrian * The descriptor list must already been linked together using 54852942Sbrian * bf->bf_next. 54952963Sbrian */ 55052942Sbrianstatic void 55152942Sbrianath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first) 55252942Sbrian{ 55352942Sbrian struct ath_buf *bf, *bf_prev = NULL; 55452942Sbrian struct ath_desc *ds0 = bf_first->bf_desc; 55552942Sbrian 55652942Sbrian DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n", 55752942Sbrian __func__, bf_first->bf_state.bfs_nframes, 55852942Sbrian bf_first->bf_state.bfs_al); 55952942Sbrian 56052942Sbrian bf = bf_first; 56152942Sbrian 56252942Sbrian if (bf->bf_state.bfs_txrate0 == 0) 56352942Sbrian device_printf(sc->sc_dev, "%s: bf=%p, txrate0=%d\n", 56452942Sbrian __func__, bf, 0); 56552942Sbrian if (bf->bf_state.bfs_rc[0].ratecode == 0) 56652942Sbrian device_printf(sc->sc_dev, "%s: bf=%p, rix0=%d\n", 56752942Sbrian __func__, bf, 0); 56852963Sbrian 56952942Sbrian /* 57052942Sbrian * Setup all descriptors of all subframes - this will 57152942Sbrian * call ath_hal_set11naggrmiddle() on every frame. 57252942Sbrian */ 57352942Sbrian while (bf != NULL) { 57452942Sbrian DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 57552942Sbrian "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n", 57652942Sbrian __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen, 57752942Sbrian SEQNO(bf->bf_state.bfs_seqno)); 57852942Sbrian 57952942Sbrian /* 58052942Sbrian * Setup the initial fields for the first descriptor - all 58193418Sbrian * the non-11n specific stuff. 58252942Sbrian */ 58352942Sbrian ath_hal_setuptxdesc(sc->sc_ah, bf->bf_desc 58452942Sbrian , bf->bf_state.bfs_pktlen /* packet length */ 58552942Sbrian , bf->bf_state.bfs_hdrlen /* header length */ 58652963Sbrian , bf->bf_state.bfs_atype /* Atheros packet type */ 58752942Sbrian , bf->bf_state.bfs_txpower /* txpower */ 58852942Sbrian , bf->bf_state.bfs_txrate0 58952942Sbrian , bf->bf_state.bfs_try0 /* series 0 rate/tries */ 59052942Sbrian , bf->bf_state.bfs_keyix /* key cache index */ 59152942Sbrian , bf->bf_state.bfs_txantenna /* antenna mode */ 59252942Sbrian , bf->bf_state.bfs_txflags | HAL_TXDESC_INTREQ /* flags */ 59352942Sbrian , bf->bf_state.bfs_ctsrate /* rts/cts rate */ 59452942Sbrian , bf->bf_state.bfs_ctsduration /* rts/cts duration */ 59552942Sbrian ); 59652942Sbrian 59752942Sbrian /* 59852942Sbrian * First descriptor? Setup the rate control and initial 59952942Sbrian * aggregate header information. 60052942Sbrian */ 60152942Sbrian if (bf == bf_first) { 60252942Sbrian /* 60352942Sbrian * setup first desc with rate and aggr info 60452942Sbrian */ 60552942Sbrian ath_tx_set_ratectrl(sc, bf->bf_node, bf); 60652942Sbrian } 60752942Sbrian 60852942Sbrian /* 60952942Sbrian * Setup the descriptors for a multi-descriptor frame. 61052942Sbrian * This is both aggregate and non-aggregate aware. 61152942Sbrian */ 61252942Sbrian ath_tx_chaindesclist(sc, ds0, bf, 61352942Sbrian 1, /* is_aggr */ 61452942Sbrian !! (bf == bf_first), /* is_first_subframe */ 61552942Sbrian !! (bf->bf_next == NULL) /* is_last_subframe */ 61652942Sbrian ); 61752942Sbrian 61852942Sbrian if (bf == bf_first) { 61952942Sbrian /* 62079854Sbrian * Initialise the first 11n aggregate with the 62179854Sbrian * aggregate length and aggregate enable bits. 62279854Sbrian */ 62379854Sbrian ath_hal_set11n_aggr_first(sc->sc_ah, 62479854Sbrian ds0, 62579854Sbrian bf->bf_state.bfs_al, 626132818Sglebius bf->bf_state.bfs_ndelim); 627132818Sglebius } 628132818Sglebius 629132818Sglebius /* 630132818Sglebius * Link the last descriptor of the previous frame 631132818Sglebius * to the beginning descriptor of this frame. 632132818Sglebius */ 633132818Sglebius if (bf_prev != NULL) 634132818Sglebius ath_hal_settxdesclink(sc->sc_ah, bf_prev->bf_lastds, 635132818Sglebius bf->bf_daddr); 636132818Sglebius 637132818Sglebius /* Save a copy so we can link the next descriptor in */ 638132818Sglebius bf_prev = bf; 63952942Sbrian bf = bf->bf_next; 64052942Sbrian } 64168032Sbrian 64252942Sbrian /* 64368846Sbrian * Set the first descriptor bf_lastds field to point to 64468846Sbrian * the last descriptor in the last subframe, that's where 64552942Sbrian * the status update will occur. 64652942Sbrian */ 64752942Sbrian bf_first->bf_lastds = bf_prev->bf_lastds; 64852942Sbrian 64952942Sbrian /* 65052942Sbrian * And bf_last in the first descriptor points to the end of 65152942Sbrian * the aggregate list. 65252942Sbrian */ 65352942Sbrian bf_first->bf_last = bf_prev; 65453062Sbrian 65553062Sbrian /* 65653062Sbrian * For non-AR9300 NICs, which require the rate control 65753062Sbrian * in the final descriptor - let's set that up now. 65853733Sbrian * 65953733Sbrian * This is because the filltxdesc() HAL call doesn't 66053733Sbrian * populate the last segment with rate control information 66153733Sbrian * if firstSeg is also true. For non-aggregate frames 66253733Sbrian * that is fine, as the first frame already has rate control 66353733Sbrian * info. But if the last frame in an aggregate has one 66453733Sbrian * descriptor, both firstseg and lastseg will be true and 66553733Sbrian * the rate info isn't copied. 66653733Sbrian * 66753733Sbrian * This is inefficient on MIPS/ARM platforms that have 66853733Sbrian * non-cachable memory for TX descriptors, but we'll just 66953733Sbrian * make do for now. 67053733Sbrian * 67153733Sbrian * As to why the rate table is stashed in the last descriptor 67253733Sbrian * rather than the first descriptor? Because proctxdesc() 67353733Sbrian * is called on the final descriptor in an MPDU or A-MPDU - 67453733Sbrian * ie, the one that gets updated by the hardware upon 67553733Sbrian * completion. That way proctxdesc() doesn't need to know 67696582Sbrian * about the first _and_ last TX descriptor. 67796582Sbrian */ 67852942Sbrian ath_hal_setuplasttxdesc(sc->sc_ah, bf_prev->bf_lastds, ds0); 67952942Sbrian 68071006Sbrian DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__); 68152942Sbrian} 68271006Sbrian 68371006Sbrian/* 68471006Sbrian * Hand-off a frame to the multicast TX queue. 68571006Sbrian * 68652942Sbrian * This is a software TXQ which will be appended to the CAB queue 68771006Sbrian * during the beacon setup code. 68871006Sbrian * 68971006Sbrian * XXX TODO: since the AR9300 EDMA TX queue support wants the QCU ID 69071006Sbrian * as part of the TX descriptor, bf_state.bfs_tx_queue must be updated 69171006Sbrian * with the actual hardware txq, or all of this will fall apart. 69252942Sbrian * 69352942Sbrian * XXX It may not be a bad idea to just stuff the QCU ID into bf_state 69452942Sbrian * and retire bfs_tx_queue; then make sure the CABQ QCU ID is populated 69571006Sbrian * correctly. 69671006Sbrian */ 69771006Sbrianstatic void 69871006Sbrianath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq, 69971006Sbrian struct ath_buf *bf) 70071006Sbrian{ 70171006Sbrian ATH_TX_LOCK_ASSERT(sc); 70271006Sbrian 70371006Sbrian KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 70471006Sbrian ("%s: busy status 0x%x", __func__, bf->bf_flags)); 70571006Sbrian if (txq->axq_link != NULL) { 70671006Sbrian struct ath_buf *last = ATH_TXQ_LAST(txq, axq_q_s); 70771006Sbrian struct ieee80211_frame *wh; 70871006Sbrian 70971006Sbrian /* mark previous frame */ 71071006Sbrian wh = mtod(last->bf_m, struct ieee80211_frame *); 71171006Sbrian wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 71271006Sbrian bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 71396582Sbrian BUS_DMASYNC_PREWRITE); 71496582Sbrian 71596582Sbrian /* link descriptor */ 71696582Sbrian *txq->axq_link = bf->bf_daddr; 71796582Sbrian } 71896582Sbrian ATH_TXQ_LOCK(txq); 71996582Sbrian ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 72096582Sbrian ath_hal_gettxdesclinkptr(sc->sc_ah, bf->bf_lastds, &txq->axq_link); 72196582Sbrian ATH_TXQ_UNLOCK(txq); 72296582Sbrian} 72396582Sbrian 72496582Sbrian/* 72596582Sbrian * Hand-off packet to a hardware queue. 72671006Sbrian */ 72752942Sbrianstatic void 72852942Sbrianath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq, 72952942Sbrian struct ath_buf *bf) 73052942Sbrian{ 73152942Sbrian struct ath_hal *ah = sc->sc_ah; 73252942Sbrian 73352942Sbrian /* 73452942Sbrian * Insert the frame on the outbound list and pass it on 73552942Sbrian * to the hardware. Multicast frames buffered for power 73652942Sbrian * save stations and transmit from the CAB queue are stored 737 * on a s/w only queue and loaded on to the CAB queue in 738 * the SWBA handler since frames only go out on DTIM and 739 * to avoid possible races. 740 */ 741 ATH_TX_LOCK_ASSERT(sc); 742 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 743 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 744 KASSERT(txq->axq_qnum != ATH_TXQ_SWQ, 745 ("ath_tx_handoff_hw called for mcast queue")); 746 747#if 0 748 /* 749 * This causes a LOR. Find out where the PCU lock is being 750 * held whilst the TXQ lock is grabbed - that shouldn't 751 * be occuring. 752 */ 753 ATH_PCU_LOCK(sc); 754 if (sc->sc_inreset_cnt) { 755 ATH_PCU_UNLOCK(sc); 756 DPRINTF(sc, ATH_DEBUG_RESET, 757 "%s: called with sc_in_reset != 0\n", 758 __func__); 759 DPRINTF(sc, ATH_DEBUG_XMIT, 760 "%s: queued: TXDP[%u] = %p (%p) depth %d\n", 761 __func__, txq->axq_qnum, 762 (caddr_t)bf->bf_daddr, bf->bf_desc, 763 txq->axq_depth); 764 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 765 if (bf->bf_state.bfs_aggr) 766 txq->axq_aggr_depth++; 767 /* 768 * There's no need to update axq_link; the hardware 769 * is in reset and once the reset is complete, any 770 * non-empty queues will simply have DMA restarted. 771 */ 772 return; 773 } 774 ATH_PCU_UNLOCK(sc); 775#endif 776 777 /* For now, so not to generate whitespace diffs */ 778 if (1) { 779 ATH_TXQ_LOCK(txq); 780#ifdef IEEE80211_SUPPORT_TDMA 781 int qbusy; 782 783 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 784 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 785 786 ATH_KTR(sc, ATH_KTR_TX, 4, 787 "ath_tx_handoff: txq=%u, add bf=%p, qbusy=%d, depth=%d", 788 txq->axq_qnum, bf, qbusy, txq->axq_depth); 789 if (txq->axq_link == NULL) { 790 /* 791 * Be careful writing the address to TXDP. If 792 * the tx q is enabled then this write will be 793 * ignored. Normally this is not an issue but 794 * when tdma is in use and the q is beacon gated 795 * this race can occur. If the q is busy then 796 * defer the work to later--either when another 797 * packet comes along or when we prepare a beacon 798 * frame at SWBA. 799 */ 800 if (!qbusy) { 801 ath_hal_puttxbuf(ah, txq->axq_qnum, 802 bf->bf_daddr); 803 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 804 DPRINTF(sc, ATH_DEBUG_XMIT, 805 "%s: TXDP[%u] = %p (%p) lastds=%p depth %d\n", 806 __func__, txq->axq_qnum, 807 (caddr_t)bf->bf_daddr, bf->bf_desc, 808 bf->bf_lastds, 809 txq->axq_depth); 810 ATH_KTR(sc, ATH_KTR_TX, 5, 811 "ath_tx_handoff: TXDP[%u] = %p (%p) " 812 "lastds=%p depth %d", 813 txq->axq_qnum, 814 (caddr_t)bf->bf_daddr, bf->bf_desc, 815 bf->bf_lastds, 816 txq->axq_depth); 817 } else { 818 txq->axq_flags |= ATH_TXQ_PUTPENDING; 819 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 820 "%s: Q%u busy, defer enable\n", __func__, 821 txq->axq_qnum); 822 ATH_KTR(sc, ATH_KTR_TX, 0, "defer enable"); 823 } 824 } else { 825 *txq->axq_link = bf->bf_daddr; 826 DPRINTF(sc, ATH_DEBUG_XMIT, 827 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 828 txq->axq_qnum, txq->axq_link, 829 (caddr_t)bf->bf_daddr, bf->bf_desc, 830 txq->axq_depth); 831 ATH_KTR(sc, ATH_KTR_TX, 5, 832 "ath_tx_handoff: link[%u](%p)=%p (%p) lastds=%p", 833 txq->axq_qnum, txq->axq_link, 834 (caddr_t)bf->bf_daddr, bf->bf_desc, 835 bf->bf_lastds); 836 837 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) { 838 /* 839 * The q was busy when we previously tried 840 * to write the address of the first buffer 841 * in the chain. Since it's not busy now 842 * handle this chore. We are certain the 843 * buffer at the front is the right one since 844 * axq_link is NULL only when the buffer list 845 * is/was empty. 846 */ 847 ath_hal_puttxbuf(ah, txq->axq_qnum, 848 TAILQ_FIRST(&txq->axq_q)->bf_daddr); 849 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 850 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 851 "%s: Q%u restarted\n", __func__, 852 txq->axq_qnum); 853 ATH_KTR(sc, ATH_KTR_TX, 4, 854 "ath_tx_handoff: txq[%d] restarted, bf=%p " 855 "daddr=%p ds=%p", 856 txq->axq_qnum, 857 bf, 858 (caddr_t)bf->bf_daddr, 859 bf->bf_desc); 860 } 861 } 862#else 863 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 864 ATH_KTR(sc, ATH_KTR_TX, 3, 865 "ath_tx_handoff: non-tdma: txq=%u, add bf=%p " 866 "depth=%d", 867 txq->axq_qnum, 868 bf, 869 txq->axq_depth); 870 if (txq->axq_link == NULL) { 871 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 872 DPRINTF(sc, ATH_DEBUG_XMIT, 873 "%s: TXDP[%u] = %p (%p) depth %d\n", 874 __func__, txq->axq_qnum, 875 (caddr_t)bf->bf_daddr, bf->bf_desc, 876 txq->axq_depth); 877 ATH_KTR(sc, ATH_KTR_TX, 5, 878 "ath_tx_handoff: non-tdma: TXDP[%u] = %p (%p) " 879 "lastds=%p depth %d", 880 txq->axq_qnum, 881 (caddr_t)bf->bf_daddr, bf->bf_desc, 882 bf->bf_lastds, 883 txq->axq_depth); 884 885 } else { 886 *txq->axq_link = bf->bf_daddr; 887 DPRINTF(sc, ATH_DEBUG_XMIT, 888 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 889 txq->axq_qnum, txq->axq_link, 890 (caddr_t)bf->bf_daddr, bf->bf_desc, 891 txq->axq_depth); 892 ATH_KTR(sc, ATH_KTR_TX, 5, 893 "ath_tx_handoff: non-tdma: link[%u](%p)=%p (%p) " 894 "lastds=%d", 895 txq->axq_qnum, txq->axq_link, 896 (caddr_t)bf->bf_daddr, bf->bf_desc, 897 bf->bf_lastds); 898 899 } 900#endif /* IEEE80211_SUPPORT_TDMA */ 901 if (bf->bf_state.bfs_aggr) 902 txq->axq_aggr_depth++; 903 ath_hal_gettxdesclinkptr(ah, bf->bf_lastds, &txq->axq_link); 904 ath_hal_txstart(ah, txq->axq_qnum); 905 ATH_TXQ_UNLOCK(txq); 906 ATH_KTR(sc, ATH_KTR_TX, 1, 907 "ath_tx_handoff: txq=%u, txstart", txq->axq_qnum); 908 } 909} 910 911/* 912 * Restart TX DMA for the given TXQ. 913 * 914 * This must be called whether the queue is empty or not. 915 */ 916static void 917ath_legacy_tx_dma_restart(struct ath_softc *sc, struct ath_txq *txq) 918{ 919 struct ath_hal *ah = sc->sc_ah; 920 struct ath_buf *bf, *bf_last; 921 922 ATH_TXQ_LOCK_ASSERT(txq); 923 /* This is always going to be cleared, empty or not */ 924 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 925 926 /* XXX make this ATH_TXQ_FIRST */ 927 bf = TAILQ_FIRST(&txq->axq_q); 928 bf_last = ATH_TXQ_LAST(txq, axq_q_s); 929 930 if (bf == NULL) 931 return; 932 933 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 934 ath_hal_gettxdesclinkptr(ah, bf_last->bf_lastds, &txq->axq_link); 935 ath_hal_txstart(ah, txq->axq_qnum); 936} 937 938/* 939 * Hand off a packet to the hardware (or mcast queue.) 940 * 941 * The relevant hardware txq should be locked. 942 */ 943static void 944ath_legacy_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq, 945 struct ath_buf *bf) 946{ 947 ATH_TX_LOCK_ASSERT(sc); 948 949#ifdef ATH_DEBUG_ALQ 950 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC)) 951 ath_tx_alq_post(sc, bf); 952#endif 953 954 if (txq->axq_qnum == ATH_TXQ_SWQ) 955 ath_tx_handoff_mcast(sc, txq, bf); 956 else 957 ath_tx_handoff_hw(sc, txq, bf); 958} 959 960static int 961ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni, 962 struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen, 963 int *keyix) 964{ 965 DPRINTF(sc, ATH_DEBUG_XMIT, 966 "%s: hdrlen=%d, pktlen=%d, isfrag=%d, iswep=%d, m0=%p\n", 967 __func__, 968 *hdrlen, 969 *pktlen, 970 isfrag, 971 iswep, 972 m0); 973 974 if (iswep) { 975 const struct ieee80211_cipher *cip; 976 struct ieee80211_key *k; 977 978 /* 979 * Construct the 802.11 header+trailer for an encrypted 980 * frame. The only reason this can fail is because of an 981 * unknown or unsupported cipher/key type. 982 */ 983 k = ieee80211_crypto_encap(ni, m0); 984 if (k == NULL) { 985 /* 986 * This can happen when the key is yanked after the 987 * frame was queued. Just discard the frame; the 988 * 802.11 layer counts failures and provides 989 * debugging/diagnostics. 990 */ 991 return (0); 992 } 993 /* 994 * Adjust the packet + header lengths for the crypto 995 * additions and calculate the h/w key index. When 996 * a s/w mic is done the frame will have had any mic 997 * added to it prior to entry so m0->m_pkthdr.len will 998 * account for it. Otherwise we need to add it to the 999 * packet length. 1000 */ 1001 cip = k->wk_cipher; 1002 (*hdrlen) += cip->ic_header; 1003 (*pktlen) += cip->ic_header + cip->ic_trailer; 1004 /* NB: frags always have any TKIP MIC done in s/w */ 1005 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 1006 (*pktlen) += cip->ic_miclen; 1007 (*keyix) = k->wk_keyix; 1008 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 1009 /* 1010 * Use station key cache slot, if assigned. 1011 */ 1012 (*keyix) = ni->ni_ucastkey.wk_keyix; 1013 if ((*keyix) == IEEE80211_KEYIX_NONE) 1014 (*keyix) = HAL_TXKEYIX_INVALID; 1015 } else 1016 (*keyix) = HAL_TXKEYIX_INVALID; 1017 1018 return (1); 1019} 1020 1021/* 1022 * Calculate whether interoperability protection is required for 1023 * this frame. 1024 * 1025 * This requires the rate control information be filled in, 1026 * as the protection requirement depends upon the current 1027 * operating mode / PHY. 1028 */ 1029static void 1030ath_tx_calc_protection(struct ath_softc *sc, struct ath_buf *bf) 1031{ 1032 struct ieee80211_frame *wh; 1033 uint8_t rix; 1034 uint16_t flags; 1035 int shortPreamble; 1036 const HAL_RATE_TABLE *rt = sc->sc_currates; 1037 struct ifnet *ifp = sc->sc_ifp; 1038 struct ieee80211com *ic = ifp->if_l2com; 1039 1040 flags = bf->bf_state.bfs_txflags; 1041 rix = bf->bf_state.bfs_rc[0].rix; 1042 shortPreamble = bf->bf_state.bfs_shpream; 1043 wh = mtod(bf->bf_m, struct ieee80211_frame *); 1044 1045 /* 1046 * If 802.11g protection is enabled, determine whether 1047 * to use RTS/CTS or just CTS. Note that this is only 1048 * done for OFDM unicast frames. 1049 */ 1050 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1051 rt->info[rix].phy == IEEE80211_T_OFDM && 1052 (flags & HAL_TXDESC_NOACK) == 0) { 1053 bf->bf_state.bfs_doprot = 1; 1054 /* XXX fragments must use CCK rates w/ protection */ 1055 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1056 flags |= HAL_TXDESC_RTSENA; 1057 } else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1058 flags |= HAL_TXDESC_CTSENA; 1059 } 1060 /* 1061 * For frags it would be desirable to use the 1062 * highest CCK rate for RTS/CTS. But stations 1063 * farther away may detect it at a lower CCK rate 1064 * so use the configured protection rate instead 1065 * (for now). 1066 */ 1067 sc->sc_stats.ast_tx_protect++; 1068 } 1069 1070 /* 1071 * If 11n protection is enabled and it's a HT frame, 1072 * enable RTS. 1073 * 1074 * XXX ic_htprotmode or ic_curhtprotmode? 1075 * XXX should it_htprotmode only matter if ic_curhtprotmode 1076 * XXX indicates it's not a HT pure environment? 1077 */ 1078 if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) && 1079 rt->info[rix].phy == IEEE80211_T_HT && 1080 (flags & HAL_TXDESC_NOACK) == 0) { 1081 flags |= HAL_TXDESC_RTSENA; 1082 sc->sc_stats.ast_tx_htprotect++; 1083 } 1084 bf->bf_state.bfs_txflags = flags; 1085} 1086 1087/* 1088 * Update the frame duration given the currently selected rate. 1089 * 1090 * This also updates the frame duration value, so it will require 1091 * a DMA flush. 1092 */ 1093static void 1094ath_tx_calc_duration(struct ath_softc *sc, struct ath_buf *bf) 1095{ 1096 struct ieee80211_frame *wh; 1097 uint8_t rix; 1098 uint16_t flags; 1099 int shortPreamble; 1100 struct ath_hal *ah = sc->sc_ah; 1101 const HAL_RATE_TABLE *rt = sc->sc_currates; 1102 int isfrag = bf->bf_m->m_flags & M_FRAG; 1103 1104 flags = bf->bf_state.bfs_txflags; 1105 rix = bf->bf_state.bfs_rc[0].rix; 1106 shortPreamble = bf->bf_state.bfs_shpream; 1107 wh = mtod(bf->bf_m, struct ieee80211_frame *); 1108 1109 /* 1110 * Calculate duration. This logically belongs in the 802.11 1111 * layer but it lacks sufficient information to calculate it. 1112 */ 1113 if ((flags & HAL_TXDESC_NOACK) == 0 && 1114 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 1115 u_int16_t dur; 1116 if (shortPreamble) 1117 dur = rt->info[rix].spAckDuration; 1118 else 1119 dur = rt->info[rix].lpAckDuration; 1120 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 1121 dur += dur; /* additional SIFS+ACK */ 1122 KASSERT(bf->bf_m->m_nextpkt != NULL, ("no fragment")); 1123 /* 1124 * Include the size of next fragment so NAV is 1125 * updated properly. The last fragment uses only 1126 * the ACK duration 1127 * 1128 * XXX TODO: ensure that the rate lookup for each 1129 * fragment is the same as the rate used by the 1130 * first fragment! 1131 */ 1132 dur += ath_hal_computetxtime(ah, rt, 1133 bf->bf_m->m_nextpkt->m_pkthdr.len, 1134 rix, shortPreamble); 1135 } 1136 if (isfrag) { 1137 /* 1138 * Force hardware to use computed duration for next 1139 * fragment by disabling multi-rate retry which updates 1140 * duration based on the multi-rate duration table. 1141 */ 1142 bf->bf_state.bfs_ismrr = 0; 1143 bf->bf_state.bfs_try0 = ATH_TXMGTTRY; 1144 /* XXX update bfs_rc[0].try? */ 1145 } 1146 1147 /* Update the duration field itself */ 1148 *(u_int16_t *)wh->i_dur = htole16(dur); 1149 } 1150} 1151 1152static uint8_t 1153ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt, 1154 int cix, int shortPreamble) 1155{ 1156 uint8_t ctsrate; 1157 1158 /* 1159 * CTS transmit rate is derived from the transmit rate 1160 * by looking in the h/w rate table. We must also factor 1161 * in whether or not a short preamble is to be used. 1162 */ 1163 /* NB: cix is set above where RTS/CTS is enabled */ 1164 KASSERT(cix != 0xff, ("cix not setup")); 1165 ctsrate = rt->info[cix].rateCode; 1166 1167 /* XXX this should only matter for legacy rates */ 1168 if (shortPreamble) 1169 ctsrate |= rt->info[cix].shortPreamble; 1170 1171 return (ctsrate); 1172} 1173 1174/* 1175 * Calculate the RTS/CTS duration for legacy frames. 1176 */ 1177static int 1178ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix, 1179 int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt, 1180 int flags) 1181{ 1182 int ctsduration = 0; 1183 1184 /* This mustn't be called for HT modes */ 1185 if (rt->info[cix].phy == IEEE80211_T_HT) { 1186 printf("%s: HT rate where it shouldn't be (0x%x)\n", 1187 __func__, rt->info[cix].rateCode); 1188 return (-1); 1189 } 1190 1191 /* 1192 * Compute the transmit duration based on the frame 1193 * size and the size of an ACK frame. We call into the 1194 * HAL to do the computation since it depends on the 1195 * characteristics of the actual PHY being used. 1196 * 1197 * NB: CTS is assumed the same size as an ACK so we can 1198 * use the precalculated ACK durations. 1199 */ 1200 if (shortPreamble) { 1201 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 1202 ctsduration += rt->info[cix].spAckDuration; 1203 ctsduration += ath_hal_computetxtime(ah, 1204 rt, pktlen, rix, AH_TRUE); 1205 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 1206 ctsduration += rt->info[rix].spAckDuration; 1207 } else { 1208 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 1209 ctsduration += rt->info[cix].lpAckDuration; 1210 ctsduration += ath_hal_computetxtime(ah, 1211 rt, pktlen, rix, AH_FALSE); 1212 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 1213 ctsduration += rt->info[rix].lpAckDuration; 1214 } 1215 1216 return (ctsduration); 1217} 1218 1219/* 1220 * Update the given ath_buf with updated rts/cts setup and duration 1221 * values. 1222 * 1223 * To support rate lookups for each software retry, the rts/cts rate 1224 * and cts duration must be re-calculated. 1225 * 1226 * This function assumes the RTS/CTS flags have been set as needed; 1227 * mrr has been disabled; and the rate control lookup has been done. 1228 * 1229 * XXX TODO: MRR need only be disabled for the pre-11n NICs. 1230 * XXX The 11n NICs support per-rate RTS/CTS configuration. 1231 */ 1232static void 1233ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf) 1234{ 1235 uint16_t ctsduration = 0; 1236 uint8_t ctsrate = 0; 1237 uint8_t rix = bf->bf_state.bfs_rc[0].rix; 1238 uint8_t cix = 0; 1239 const HAL_RATE_TABLE *rt = sc->sc_currates; 1240 1241 /* 1242 * No RTS/CTS enabled? Don't bother. 1243 */ 1244 if ((bf->bf_state.bfs_txflags & 1245 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) { 1246 /* XXX is this really needed? */ 1247 bf->bf_state.bfs_ctsrate = 0; 1248 bf->bf_state.bfs_ctsduration = 0; 1249 return; 1250 } 1251 1252 /* 1253 * If protection is enabled, use the protection rix control 1254 * rate. Otherwise use the rate0 control rate. 1255 */ 1256 if (bf->bf_state.bfs_doprot) 1257 rix = sc->sc_protrix; 1258 else 1259 rix = bf->bf_state.bfs_rc[0].rix; 1260 1261 /* 1262 * If the raw path has hard-coded ctsrate0 to something, 1263 * use it. 1264 */ 1265 if (bf->bf_state.bfs_ctsrate0 != 0) 1266 cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0); 1267 else 1268 /* Control rate from above */ 1269 cix = rt->info[rix].controlRate; 1270 1271 /* Calculate the rtscts rate for the given cix */ 1272 ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix, 1273 bf->bf_state.bfs_shpream); 1274 1275 /* The 11n chipsets do ctsduration calculations for you */ 1276 if (! ath_tx_is_11n(sc)) 1277 ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix, 1278 bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen, 1279 rt, bf->bf_state.bfs_txflags); 1280 1281 /* Squirrel away in ath_buf */ 1282 bf->bf_state.bfs_ctsrate = ctsrate; 1283 bf->bf_state.bfs_ctsduration = ctsduration; 1284 1285 /* 1286 * Must disable multi-rate retry when using RTS/CTS. 1287 */ 1288 if (!sc->sc_mrrprot) { 1289 bf->bf_state.bfs_ismrr = 0; 1290 bf->bf_state.bfs_try0 = 1291 bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */ 1292 } 1293} 1294 1295/* 1296 * Setup the descriptor chain for a normal or fast-frame 1297 * frame. 1298 * 1299 * XXX TODO: extend to include the destination hardware QCU ID. 1300 * Make sure that is correct. Make sure that when being added 1301 * to the mcastq, the CABQ QCUID is set or things will get a bit 1302 * odd. 1303 */ 1304static void 1305ath_tx_setds(struct ath_softc *sc, struct ath_buf *bf) 1306{ 1307 struct ath_desc *ds = bf->bf_desc; 1308 struct ath_hal *ah = sc->sc_ah; 1309 1310 if (bf->bf_state.bfs_txrate0 == 0) 1311 device_printf(sc->sc_dev, "%s: bf=%p, txrate0=%d\n", 1312 __func__, bf, 0); 1313 1314 ath_hal_setuptxdesc(ah, ds 1315 , bf->bf_state.bfs_pktlen /* packet length */ 1316 , bf->bf_state.bfs_hdrlen /* header length */ 1317 , bf->bf_state.bfs_atype /* Atheros packet type */ 1318 , bf->bf_state.bfs_txpower /* txpower */ 1319 , bf->bf_state.bfs_txrate0 1320 , bf->bf_state.bfs_try0 /* series 0 rate/tries */ 1321 , bf->bf_state.bfs_keyix /* key cache index */ 1322 , bf->bf_state.bfs_txantenna /* antenna mode */ 1323 , bf->bf_state.bfs_txflags /* flags */ 1324 , bf->bf_state.bfs_ctsrate /* rts/cts rate */ 1325 , bf->bf_state.bfs_ctsduration /* rts/cts duration */ 1326 ); 1327 1328 /* 1329 * This will be overriden when the descriptor chain is written. 1330 */ 1331 bf->bf_lastds = ds; 1332 bf->bf_last = bf; 1333 1334 /* Set rate control and descriptor chain for this frame */ 1335 ath_tx_set_ratectrl(sc, bf->bf_node, bf); 1336 ath_tx_chaindesclist(sc, ds, bf, 0, 0, 0); 1337} 1338 1339/* 1340 * Do a rate lookup. 1341 * 1342 * This performs a rate lookup for the given ath_buf only if it's required. 1343 * Non-data frames and raw frames don't require it. 1344 * 1345 * This populates the primary and MRR entries; MRR values are 1346 * then disabled later on if something requires it (eg RTS/CTS on 1347 * pre-11n chipsets. 1348 * 1349 * This needs to be done before the RTS/CTS fields are calculated 1350 * as they may depend upon the rate chosen. 1351 */ 1352static void 1353ath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf) 1354{ 1355 uint8_t rate, rix; 1356 int try0; 1357 1358 if (! bf->bf_state.bfs_doratelookup) 1359 return; 1360 1361 /* Get rid of any previous state */ 1362 bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1363 1364 ATH_NODE_LOCK(ATH_NODE(bf->bf_node)); 1365 ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream, 1366 bf->bf_state.bfs_pktlen, &rix, &try0, &rate); 1367 1368 /* In case MRR is disabled, make sure rc[0] is setup correctly */ 1369 bf->bf_state.bfs_rc[0].rix = rix; 1370 bf->bf_state.bfs_rc[0].ratecode = rate; 1371 bf->bf_state.bfs_rc[0].tries = try0; 1372 1373 if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY) 1374 ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix, 1375 bf->bf_state.bfs_rc); 1376 ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node)); 1377 1378 sc->sc_txrix = rix; /* for LED blinking */ 1379 sc->sc_lastdatarix = rix; /* for fast frames */ 1380 bf->bf_state.bfs_try0 = try0; 1381 bf->bf_state.bfs_txrate0 = rate; 1382} 1383 1384/* 1385 * Update the CLRDMASK bit in the ath_buf if it needs to be set. 1386 */ 1387static void 1388ath_tx_update_clrdmask(struct ath_softc *sc, struct ath_tid *tid, 1389 struct ath_buf *bf) 1390{ 1391 struct ath_node *an = ATH_NODE(bf->bf_node); 1392 1393 ATH_TX_LOCK_ASSERT(sc); 1394 1395 if (an->clrdmask == 1) { 1396 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 1397 an->clrdmask = 0; 1398 } 1399} 1400 1401/* 1402 * Transmit the given frame to the hardware. 1403 * 1404 * The frame must already be setup; rate control must already have 1405 * been done. 1406 * 1407 * XXX since the TXQ lock is being held here (and I dislike holding 1408 * it for this long when not doing software aggregation), later on 1409 * break this function into "setup_normal" and "xmit_normal". The 1410 * lock only needs to be held for the ath_tx_handoff call. 1411 */ 1412static void 1413ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq, 1414 struct ath_buf *bf) 1415{ 1416 struct ath_node *an = ATH_NODE(bf->bf_node); 1417 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid]; 1418 1419 ATH_TX_LOCK_ASSERT(sc); 1420 1421 /* 1422 * For now, just enable CLRDMASK. ath_tx_xmit_normal() does 1423 * set a completion handler however it doesn't (yet) properly 1424 * handle the strict ordering requirements needed for normal, 1425 * non-aggregate session frames. 1426 * 1427 * Once this is implemented, only set CLRDMASK like this for 1428 * frames that must go out - eg management/raw frames. 1429 */ 1430 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 1431 1432 /* Setup the descriptor before handoff */ 1433 ath_tx_do_ratelookup(sc, bf); 1434 ath_tx_calc_duration(sc, bf); 1435 ath_tx_calc_protection(sc, bf); 1436 ath_tx_set_rtscts(sc, bf); 1437 ath_tx_rate_fill_rcflags(sc, bf); 1438 ath_tx_setds(sc, bf); 1439 1440 /* Track per-TID hardware queue depth correctly */ 1441 tid->hwq_depth++; 1442 1443 /* Assign the completion handler */ 1444 bf->bf_comp = ath_tx_normal_comp; 1445 1446 /* Hand off to hardware */ 1447 ath_tx_handoff(sc, txq, bf); 1448} 1449 1450/* 1451 * Do the basic frame setup stuff that's required before the frame 1452 * is added to a software queue. 1453 * 1454 * All frames get mostly the same treatment and it's done once. 1455 * Retransmits fiddle with things like the rate control setup, 1456 * setting the retransmit bit in the packet; doing relevant DMA/bus 1457 * syncing and relinking it (back) into the hardware TX queue. 1458 * 1459 * Note that this may cause the mbuf to be reallocated, so 1460 * m0 may not be valid. 1461 */ 1462static int 1463ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni, 1464 struct ath_buf *bf, struct mbuf *m0, struct ath_txq *txq) 1465{ 1466 struct ieee80211vap *vap = ni->ni_vap; 1467 struct ath_hal *ah = sc->sc_ah; 1468 struct ifnet *ifp = sc->sc_ifp; 1469 struct ieee80211com *ic = ifp->if_l2com; 1470 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 1471 int error, iswep, ismcast, isfrag, ismrr; 1472 int keyix, hdrlen, pktlen, try0 = 0; 1473 u_int8_t rix = 0, txrate = 0; 1474 struct ath_desc *ds; 1475 struct ieee80211_frame *wh; 1476 u_int subtype, flags; 1477 HAL_PKT_TYPE atype; 1478 const HAL_RATE_TABLE *rt; 1479 HAL_BOOL shortPreamble; 1480 struct ath_node *an; 1481 u_int pri; 1482 1483 /* 1484 * To ensure that both sequence numbers and the CCMP PN handling 1485 * is "correct", make sure that the relevant TID queue is locked. 1486 * Otherwise the CCMP PN and seqno may appear out of order, causing 1487 * re-ordered frames to have out of order CCMP PN's, resulting 1488 * in many, many frame drops. 1489 */ 1490 ATH_TX_LOCK_ASSERT(sc); 1491 1492 wh = mtod(m0, struct ieee80211_frame *); 1493 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1494 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1495 isfrag = m0->m_flags & M_FRAG; 1496 hdrlen = ieee80211_anyhdrsize(wh); 1497 /* 1498 * Packet length must not include any 1499 * pad bytes; deduct them here. 1500 */ 1501 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 1502 1503 /* Handle encryption twiddling if needed */ 1504 if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen, 1505 &pktlen, &keyix)) { 1506 ath_freetx(m0); 1507 return EIO; 1508 } 1509 1510 /* packet header may have moved, reset our local pointer */ 1511 wh = mtod(m0, struct ieee80211_frame *); 1512 1513 pktlen += IEEE80211_CRC_LEN; 1514 1515 /* 1516 * Load the DMA map so any coalescing is done. This 1517 * also calculates the number of descriptors we need. 1518 */ 1519 error = ath_tx_dmasetup(sc, bf, m0); 1520 if (error != 0) 1521 return error; 1522 bf->bf_node = ni; /* NB: held reference */ 1523 m0 = bf->bf_m; /* NB: may have changed */ 1524 wh = mtod(m0, struct ieee80211_frame *); 1525 1526 /* setup descriptors */ 1527 ds = bf->bf_desc; 1528 rt = sc->sc_currates; 1529 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1530 1531 /* 1532 * NB: the 802.11 layer marks whether or not we should 1533 * use short preamble based on the current mode and 1534 * negotiated parameters. 1535 */ 1536 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1537 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 1538 shortPreamble = AH_TRUE; 1539 sc->sc_stats.ast_tx_shortpre++; 1540 } else { 1541 shortPreamble = AH_FALSE; 1542 } 1543 1544 an = ATH_NODE(ni); 1545 //flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1546 flags = 0; 1547 ismrr = 0; /* default no multi-rate retry*/ 1548 pri = M_WME_GETAC(m0); /* honor classification */ 1549 /* XXX use txparams instead of fixed values */ 1550 /* 1551 * Calculate Atheros packet type from IEEE80211 packet header, 1552 * setup for rate calculations, and select h/w transmit queue. 1553 */ 1554 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1555 case IEEE80211_FC0_TYPE_MGT: 1556 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1557 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1558 atype = HAL_PKT_TYPE_BEACON; 1559 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1560 atype = HAL_PKT_TYPE_PROBE_RESP; 1561 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1562 atype = HAL_PKT_TYPE_ATIM; 1563 else 1564 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 1565 rix = an->an_mgmtrix; 1566 txrate = rt->info[rix].rateCode; 1567 if (shortPreamble) 1568 txrate |= rt->info[rix].shortPreamble; 1569 try0 = ATH_TXMGTTRY; 1570 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1571 break; 1572 case IEEE80211_FC0_TYPE_CTL: 1573 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 1574 rix = an->an_mgmtrix; 1575 txrate = rt->info[rix].rateCode; 1576 if (shortPreamble) 1577 txrate |= rt->info[rix].shortPreamble; 1578 try0 = ATH_TXMGTTRY; 1579 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1580 break; 1581 case IEEE80211_FC0_TYPE_DATA: 1582 atype = HAL_PKT_TYPE_NORMAL; /* default */ 1583 /* 1584 * Data frames: multicast frames go out at a fixed rate, 1585 * EAPOL frames use the mgmt frame rate; otherwise consult 1586 * the rate control module for the rate to use. 1587 */ 1588 if (ismcast) { 1589 rix = an->an_mcastrix; 1590 txrate = rt->info[rix].rateCode; 1591 if (shortPreamble) 1592 txrate |= rt->info[rix].shortPreamble; 1593 try0 = 1; 1594 } else if (m0->m_flags & M_EAPOL) { 1595 /* XXX? maybe always use long preamble? */ 1596 rix = an->an_mgmtrix; 1597 txrate = rt->info[rix].rateCode; 1598 if (shortPreamble) 1599 txrate |= rt->info[rix].shortPreamble; 1600 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 1601 } else { 1602 /* 1603 * Do rate lookup on each TX, rather than using 1604 * the hard-coded TX information decided here. 1605 */ 1606 ismrr = 1; 1607 bf->bf_state.bfs_doratelookup = 1; 1608 } 1609 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 1610 flags |= HAL_TXDESC_NOACK; 1611 break; 1612 default: 1613 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 1614 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1615 /* XXX statistic */ 1616 ath_freetx(m0); 1617 return EIO; 1618 } 1619 1620 /* 1621 * There are two known scenarios where the frame AC doesn't match 1622 * what the destination TXQ is. 1623 * 1624 * + non-QoS frames (eg management?) that the net80211 stack has 1625 * assigned a higher AC to, but since it's a non-QoS TID, it's 1626 * being thrown into TID 16. TID 16 gets the AC_BE queue. 1627 * It's quite possible that management frames should just be 1628 * direct dispatched to hardware rather than go via the software 1629 * queue; that should be investigated in the future. There are 1630 * some specific scenarios where this doesn't make sense, mostly 1631 * surrounding ADDBA request/response - hence why that is special 1632 * cased. 1633 * 1634 * + Multicast frames going into the VAP mcast queue. That shows up 1635 * as "TXQ 11". 1636 * 1637 * This driver should eventually support separate TID and TXQ locking, 1638 * allowing for arbitrary AC frames to appear on arbitrary software 1639 * queues, being queued to the "correct" hardware queue when needed. 1640 */ 1641#if 0 1642 if (txq != sc->sc_ac2q[pri]) { 1643 device_printf(sc->sc_dev, 1644 "%s: txq=%p (%d), pri=%d, pri txq=%p (%d)\n", 1645 __func__, 1646 txq, 1647 txq->axq_qnum, 1648 pri, 1649 sc->sc_ac2q[pri], 1650 sc->sc_ac2q[pri]->axq_qnum); 1651 } 1652#endif 1653 1654 /* 1655 * Calculate miscellaneous flags. 1656 */ 1657 if (ismcast) { 1658 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 1659 } else if (pktlen > vap->iv_rtsthreshold && 1660 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 1661 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 1662 sc->sc_stats.ast_tx_rts++; 1663 } 1664 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 1665 sc->sc_stats.ast_tx_noack++; 1666#ifdef IEEE80211_SUPPORT_TDMA 1667 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 1668 DPRINTF(sc, ATH_DEBUG_TDMA, 1669 "%s: discard frame, ACK required w/ TDMA\n", __func__); 1670 sc->sc_stats.ast_tdma_ack++; 1671 ath_freetx(m0); 1672 return EIO; 1673 } 1674#endif 1675 1676 /* 1677 * Determine if a tx interrupt should be generated for 1678 * this descriptor. We take a tx interrupt to reap 1679 * descriptors when the h/w hits an EOL condition or 1680 * when the descriptor is specifically marked to generate 1681 * an interrupt. We periodically mark descriptors in this 1682 * way to insure timely replenishing of the supply needed 1683 * for sending frames. Defering interrupts reduces system 1684 * load and potentially allows more concurrent work to be 1685 * done but if done to aggressively can cause senders to 1686 * backup. 1687 * 1688 * NB: use >= to deal with sc_txintrperiod changing 1689 * dynamically through sysctl. 1690 */ 1691 if (flags & HAL_TXDESC_INTREQ) { 1692 txq->axq_intrcnt = 0; 1693 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 1694 flags |= HAL_TXDESC_INTREQ; 1695 txq->axq_intrcnt = 0; 1696 } 1697 1698 /* This point forward is actual TX bits */ 1699 1700 /* 1701 * At this point we are committed to sending the frame 1702 * and we don't need to look at m_nextpkt; clear it in 1703 * case this frame is part of frag chain. 1704 */ 1705 m0->m_nextpkt = NULL; 1706 1707 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1708 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len, 1709 sc->sc_hwmap[rix].ieeerate, -1); 1710 1711 if (ieee80211_radiotap_active_vap(vap)) { 1712 u_int64_t tsf = ath_hal_gettsf64(ah); 1713 1714 sc->sc_tx_th.wt_tsf = htole64(tsf); 1715 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1716 if (iswep) 1717 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1718 if (isfrag) 1719 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1720 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1721 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 1722 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1723 1724 ieee80211_radiotap_tx(vap, m0); 1725 } 1726 1727 /* Blank the legacy rate array */ 1728 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1729 1730 /* 1731 * ath_buf_set_rate needs at least one rate/try to setup 1732 * the rate scenario. 1733 */ 1734 bf->bf_state.bfs_rc[0].rix = rix; 1735 bf->bf_state.bfs_rc[0].tries = try0; 1736 bf->bf_state.bfs_rc[0].ratecode = txrate; 1737 1738 /* Store the decided rate index values away */ 1739 bf->bf_state.bfs_pktlen = pktlen; 1740 bf->bf_state.bfs_hdrlen = hdrlen; 1741 bf->bf_state.bfs_atype = atype; 1742 bf->bf_state.bfs_txpower = ni->ni_txpower; 1743 bf->bf_state.bfs_txrate0 = txrate; 1744 bf->bf_state.bfs_try0 = try0; 1745 bf->bf_state.bfs_keyix = keyix; 1746 bf->bf_state.bfs_txantenna = sc->sc_txantenna; 1747 bf->bf_state.bfs_txflags = flags; 1748 bf->bf_state.bfs_shpream = shortPreamble; 1749 1750 /* XXX this should be done in ath_tx_setrate() */ 1751 bf->bf_state.bfs_ctsrate0 = 0; /* ie, no hard-coded ctsrate */ 1752 bf->bf_state.bfs_ctsrate = 0; /* calculated later */ 1753 bf->bf_state.bfs_ctsduration = 0; 1754 bf->bf_state.bfs_ismrr = ismrr; 1755 1756 return 0; 1757} 1758 1759/* 1760 * Queue a frame to the hardware or software queue. 1761 * 1762 * This can be called by the net80211 code. 1763 * 1764 * XXX what about locking? Or, push the seqno assign into the 1765 * XXX aggregate scheduler so its serialised? 1766 * 1767 * XXX When sending management frames via ath_raw_xmit(), 1768 * should CLRDMASK be set unconditionally? 1769 */ 1770int 1771ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, 1772 struct ath_buf *bf, struct mbuf *m0) 1773{ 1774 struct ieee80211vap *vap = ni->ni_vap; 1775 struct ath_vap *avp = ATH_VAP(vap); 1776 int r = 0; 1777 u_int pri; 1778 int tid; 1779 struct ath_txq *txq; 1780 int ismcast; 1781 const struct ieee80211_frame *wh; 1782 int is_ampdu, is_ampdu_tx, is_ampdu_pending; 1783 ieee80211_seq seqno; 1784 uint8_t type, subtype; 1785 1786 ATH_TX_LOCK_ASSERT(sc); 1787 1788 /* 1789 * Determine the target hardware queue. 1790 * 1791 * For multicast frames, the txq gets overridden appropriately 1792 * depending upon the state of PS. 1793 * 1794 * For any other frame, we do a TID/QoS lookup inside the frame 1795 * to see what the TID should be. If it's a non-QoS frame, the 1796 * AC and TID are overridden. The TID/TXQ code assumes the 1797 * TID is on a predictable hardware TXQ, so we don't support 1798 * having a node TID queued to multiple hardware TXQs. 1799 * This may change in the future but would require some locking 1800 * fudgery. 1801 */ 1802 pri = ath_tx_getac(sc, m0); 1803 tid = ath_tx_gettid(sc, m0); 1804 1805 txq = sc->sc_ac2q[pri]; 1806 wh = mtod(m0, struct ieee80211_frame *); 1807 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1808 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1809 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1810 1811 /* 1812 * Enforce how deep the multicast queue can grow. 1813 * 1814 * XXX duplicated in ath_raw_xmit(). 1815 */ 1816 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1817 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 1818 sc->sc_stats.ast_tx_mcastq_overflow++; 1819 r = ENOBUFS; 1820 } 1821 if (r != 0) { 1822 m_freem(m0); 1823 return r; 1824 } 1825 } 1826 1827 /* A-MPDU TX */ 1828 is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid); 1829 is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid); 1830 is_ampdu = is_ampdu_tx | is_ampdu_pending; 1831 1832 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, ac=%d, is_ampdu=%d\n", 1833 __func__, tid, pri, is_ampdu); 1834 1835 /* Set local packet state, used to queue packets to hardware */ 1836 bf->bf_state.bfs_tid = tid; 1837 bf->bf_state.bfs_tx_queue = txq->axq_qnum; 1838 bf->bf_state.bfs_pri = pri; 1839 1840#if 1 1841 /* 1842 * When servicing one or more stations in power-save mode 1843 * (or) if there is some mcast data waiting on the mcast 1844 * queue (to prevent out of order delivery) multicast frames 1845 * must be bufferd until after the beacon. 1846 * 1847 * TODO: we should lock the mcastq before we check the length. 1848 */ 1849 if (sc->sc_cabq_enable && ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) { 1850 txq = &avp->av_mcastq; 1851 /* 1852 * Mark the frame as eventually belonging on the CAB 1853 * queue, so the descriptor setup functions will 1854 * correctly initialise the descriptor 'qcuId' field. 1855 */ 1856 bf->bf_state.bfs_tx_queue = sc->sc_cabq->axq_qnum; 1857 } 1858#endif 1859 1860 /* Do the generic frame setup */ 1861 /* XXX should just bzero the bf_state? */ 1862 bf->bf_state.bfs_dobaw = 0; 1863 1864 /* A-MPDU TX? Manually set sequence number */ 1865 /* 1866 * Don't do it whilst pending; the net80211 layer still 1867 * assigns them. 1868 */ 1869 if (is_ampdu_tx) { 1870 /* 1871 * Always call; this function will 1872 * handle making sure that null data frames 1873 * don't get a sequence number from the current 1874 * TID and thus mess with the BAW. 1875 */ 1876 seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0); 1877 1878 /* 1879 * Don't add QoS NULL frames to the BAW. 1880 */ 1881 if (IEEE80211_QOS_HAS_SEQ(wh) && 1882 subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL) { 1883 bf->bf_state.bfs_dobaw = 1; 1884 } 1885 } 1886 1887 /* 1888 * If needed, the sequence number has been assigned. 1889 * Squirrel it away somewhere easy to get to. 1890 */ 1891 bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT; 1892 1893 /* Is ampdu pending? fetch the seqno and print it out */ 1894 if (is_ampdu_pending) 1895 DPRINTF(sc, ATH_DEBUG_SW_TX, 1896 "%s: tid %d: ampdu pending, seqno %d\n", 1897 __func__, tid, M_SEQNO_GET(m0)); 1898 1899 /* This also sets up the DMA map */ 1900 r = ath_tx_normal_setup(sc, ni, bf, m0, txq); 1901 1902 if (r != 0) 1903 goto done; 1904 1905 /* At this point m0 could have changed! */ 1906 m0 = bf->bf_m; 1907 1908#if 1 1909 /* 1910 * If it's a multicast frame, do a direct-dispatch to the 1911 * destination hardware queue. Don't bother software 1912 * queuing it. 1913 */ 1914 /* 1915 * If it's a BAR frame, do a direct dispatch to the 1916 * destination hardware queue. Don't bother software 1917 * queuing it, as the TID will now be paused. 1918 * Sending a BAR frame can occur from the net80211 txa timer 1919 * (ie, retries) or from the ath txtask (completion call.) 1920 * It queues directly to hardware because the TID is paused 1921 * at this point (and won't be unpaused until the BAR has 1922 * either been TXed successfully or max retries has been 1923 * reached.) 1924 */ 1925 if (txq == &avp->av_mcastq) { 1926 DPRINTF(sc, ATH_DEBUG_SW_TX, 1927 "%s: bf=%p: mcastq: TX'ing\n", __func__, bf); 1928 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 1929 ath_tx_xmit_normal(sc, txq, bf); 1930 } else if (type == IEEE80211_FC0_TYPE_CTL && 1931 subtype == IEEE80211_FC0_SUBTYPE_BAR) { 1932 DPRINTF(sc, ATH_DEBUG_SW_TX, 1933 "%s: BAR: TX'ing direct\n", __func__); 1934 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 1935 ath_tx_xmit_normal(sc, txq, bf); 1936 } else { 1937 /* add to software queue */ 1938 DPRINTF(sc, ATH_DEBUG_SW_TX, 1939 "%s: bf=%p: swq: TX'ing\n", __func__, bf); 1940 ath_tx_swq(sc, ni, txq, bf); 1941 } 1942#else 1943 /* 1944 * For now, since there's no software queue, 1945 * direct-dispatch to the hardware. 1946 */ 1947 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 1948 ath_tx_xmit_normal(sc, txq, bf); 1949#endif 1950done: 1951 return 0; 1952} 1953 1954static int 1955ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 1956 struct ath_buf *bf, struct mbuf *m0, 1957 const struct ieee80211_bpf_params *params) 1958{ 1959 struct ifnet *ifp = sc->sc_ifp; 1960 struct ieee80211com *ic = ifp->if_l2com; 1961 struct ath_hal *ah = sc->sc_ah; 1962 struct ieee80211vap *vap = ni->ni_vap; 1963 int error, ismcast, ismrr; 1964 int keyix, hdrlen, pktlen, try0, txantenna; 1965 u_int8_t rix, txrate; 1966 struct ieee80211_frame *wh; 1967 u_int flags; 1968 HAL_PKT_TYPE atype; 1969 const HAL_RATE_TABLE *rt; 1970 struct ath_desc *ds; 1971 u_int pri; 1972 int o_tid = -1; 1973 int do_override; 1974 1975 ATH_TX_LOCK_ASSERT(sc); 1976 1977 wh = mtod(m0, struct ieee80211_frame *); 1978 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1979 hdrlen = ieee80211_anyhdrsize(wh); 1980 /* 1981 * Packet length must not include any 1982 * pad bytes; deduct them here. 1983 */ 1984 /* XXX honor IEEE80211_BPF_DATAPAD */ 1985 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 1986 1987 ATH_KTR(sc, ATH_KTR_TX, 2, 1988 "ath_tx_raw_start: ni=%p, bf=%p, raw", ni, bf); 1989 1990 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n", 1991 __func__, ismcast); 1992 1993 pri = params->ibp_pri & 3; 1994 /* Override pri if the frame isn't a QoS one */ 1995 if (! IEEE80211_QOS_HAS_SEQ(wh)) 1996 pri = ath_tx_getac(sc, m0); 1997 1998 /* XXX If it's an ADDBA, override the correct queue */ 1999 do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid); 2000 2001 /* Map ADDBA to the correct priority */ 2002 if (do_override) { 2003#if 0 2004 device_printf(sc->sc_dev, 2005 "%s: overriding tid %d pri %d -> %d\n", 2006 __func__, o_tid, pri, TID_TO_WME_AC(o_tid)); 2007#endif 2008 pri = TID_TO_WME_AC(o_tid); 2009 } 2010 2011 /* Handle encryption twiddling if needed */ 2012 if (! ath_tx_tag_crypto(sc, ni, 2013 m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0, 2014 &hdrlen, &pktlen, &keyix)) { 2015 ath_freetx(m0); 2016 return EIO; 2017 } 2018 /* packet header may have moved, reset our local pointer */ 2019 wh = mtod(m0, struct ieee80211_frame *); 2020 2021 /* Do the generic frame setup */ 2022 /* XXX should just bzero the bf_state? */ 2023 bf->bf_state.bfs_dobaw = 0; 2024 2025 error = ath_tx_dmasetup(sc, bf, m0); 2026 if (error != 0) 2027 return error; 2028 m0 = bf->bf_m; /* NB: may have changed */ 2029 wh = mtod(m0, struct ieee80211_frame *); 2030 bf->bf_node = ni; /* NB: held reference */ 2031 2032 /* Always enable CLRDMASK for raw frames for now.. */ 2033 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 2034 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 2035 if (params->ibp_flags & IEEE80211_BPF_RTS) 2036 flags |= HAL_TXDESC_RTSENA; 2037 else if (params->ibp_flags & IEEE80211_BPF_CTS) { 2038 /* XXX assume 11g/11n protection? */ 2039 bf->bf_state.bfs_doprot = 1; 2040 flags |= HAL_TXDESC_CTSENA; 2041 } 2042 /* XXX leave ismcast to injector? */ 2043 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 2044 flags |= HAL_TXDESC_NOACK; 2045 2046 rt = sc->sc_currates; 2047 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 2048 rix = ath_tx_findrix(sc, params->ibp_rate0); 2049 txrate = rt->info[rix].rateCode; 2050 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 2051 txrate |= rt->info[rix].shortPreamble; 2052 sc->sc_txrix = rix; 2053 try0 = params->ibp_try0; 2054 ismrr = (params->ibp_try1 != 0); 2055 txantenna = params->ibp_pri >> 2; 2056 if (txantenna == 0) /* XXX? */ 2057 txantenna = sc->sc_txantenna; 2058 2059 /* 2060 * Since ctsrate is fixed, store it away for later 2061 * use when the descriptor fields are being set. 2062 */ 2063 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) 2064 bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate; 2065 2066 /* 2067 * NB: we mark all packets as type PSPOLL so the h/w won't 2068 * set the sequence number, duration, etc. 2069 */ 2070 atype = HAL_PKT_TYPE_PSPOLL; 2071 2072 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 2073 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 2074 sc->sc_hwmap[rix].ieeerate, -1); 2075 2076 if (ieee80211_radiotap_active_vap(vap)) { 2077 u_int64_t tsf = ath_hal_gettsf64(ah); 2078 2079 sc->sc_tx_th.wt_tsf = htole64(tsf); 2080 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 2081 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2082 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2083 if (m0->m_flags & M_FRAG) 2084 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 2085 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 2086 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 2087 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 2088 2089 ieee80211_radiotap_tx(vap, m0); 2090 } 2091 2092 /* 2093 * Formulate first tx descriptor with tx controls. 2094 */ 2095 ds = bf->bf_desc; 2096 /* XXX check return value? */ 2097 2098 /* Store the decided rate index values away */ 2099 bf->bf_state.bfs_pktlen = pktlen; 2100 bf->bf_state.bfs_hdrlen = hdrlen; 2101 bf->bf_state.bfs_atype = atype; 2102 bf->bf_state.bfs_txpower = params->ibp_power; 2103 bf->bf_state.bfs_txrate0 = txrate; 2104 bf->bf_state.bfs_try0 = try0; 2105 bf->bf_state.bfs_keyix = keyix; 2106 bf->bf_state.bfs_txantenna = txantenna; 2107 bf->bf_state.bfs_txflags = flags; 2108 bf->bf_state.bfs_shpream = 2109 !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE); 2110 2111 /* Set local packet state, used to queue packets to hardware */ 2112 bf->bf_state.bfs_tid = WME_AC_TO_TID(pri); 2113 bf->bf_state.bfs_tx_queue = sc->sc_ac2q[pri]->axq_qnum; 2114 bf->bf_state.bfs_pri = pri; 2115 2116 /* XXX this should be done in ath_tx_setrate() */ 2117 bf->bf_state.bfs_ctsrate = 0; 2118 bf->bf_state.bfs_ctsduration = 0; 2119 bf->bf_state.bfs_ismrr = ismrr; 2120 2121 /* Blank the legacy rate array */ 2122 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 2123 2124 bf->bf_state.bfs_rc[0].rix = 2125 ath_tx_findrix(sc, params->ibp_rate0); 2126 bf->bf_state.bfs_rc[0].tries = try0; 2127 bf->bf_state.bfs_rc[0].ratecode = txrate; 2128 2129 if (ismrr) { 2130 int rix; 2131 2132 rix = ath_tx_findrix(sc, params->ibp_rate1); 2133 bf->bf_state.bfs_rc[1].rix = rix; 2134 bf->bf_state.bfs_rc[1].tries = params->ibp_try1; 2135 2136 rix = ath_tx_findrix(sc, params->ibp_rate2); 2137 bf->bf_state.bfs_rc[2].rix = rix; 2138 bf->bf_state.bfs_rc[2].tries = params->ibp_try2; 2139 2140 rix = ath_tx_findrix(sc, params->ibp_rate3); 2141 bf->bf_state.bfs_rc[3].rix = rix; 2142 bf->bf_state.bfs_rc[3].tries = params->ibp_try3; 2143 } 2144 /* 2145 * All the required rate control decisions have been made; 2146 * fill in the rc flags. 2147 */ 2148 ath_tx_rate_fill_rcflags(sc, bf); 2149 2150 /* NB: no buffered multicast in power save support */ 2151 2152 /* 2153 * If we're overiding the ADDBA destination, dump directly 2154 * into the hardware queue, right after any pending 2155 * frames to that node are. 2156 */ 2157 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n", 2158 __func__, do_override); 2159 2160#if 1 2161 if (do_override) { 2162 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 2163 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf); 2164 } else { 2165 /* Queue to software queue */ 2166 ath_tx_swq(sc, ni, sc->sc_ac2q[pri], bf); 2167 } 2168#else 2169 /* Direct-dispatch to the hardware */ 2170 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 2171 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf); 2172#endif 2173 return 0; 2174} 2175 2176/* 2177 * Send a raw frame. 2178 * 2179 * This can be called by net80211. 2180 */ 2181int 2182ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2183 const struct ieee80211_bpf_params *params) 2184{ 2185 struct ieee80211com *ic = ni->ni_ic; 2186 struct ifnet *ifp = ic->ic_ifp; 2187 struct ath_softc *sc = ifp->if_softc; 2188 struct ath_buf *bf; 2189 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2190 int error = 0; 2191 2192 ATH_PCU_LOCK(sc); 2193 if (sc->sc_inreset_cnt > 0) { 2194 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; bailing\n", 2195 __func__); 2196 error = EIO; 2197 ATH_PCU_UNLOCK(sc); 2198 goto bad0; 2199 } 2200 sc->sc_txstart_cnt++; 2201 ATH_PCU_UNLOCK(sc); 2202 2203 ATH_TX_LOCK(sc); 2204 2205 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 2206 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 2207 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ? 2208 "!running" : "invalid"); 2209 m_freem(m); 2210 error = ENETDOWN; 2211 goto bad; 2212 } 2213 2214 /* 2215 * Enforce how deep the multicast queue can grow. 2216 * 2217 * XXX duplicated in ath_tx_start(). 2218 */ 2219 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2220 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 2221 sc->sc_stats.ast_tx_mcastq_overflow++; 2222 error = ENOBUFS; 2223 } 2224 2225 if (error != 0) { 2226 m_freem(m); 2227 goto bad; 2228 } 2229 } 2230 2231 /* 2232 * Grab a TX buffer and associated resources. 2233 */ 2234 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT); 2235 if (bf == NULL) { 2236 sc->sc_stats.ast_tx_nobuf++; 2237 m_freem(m); 2238 error = ENOBUFS; 2239 goto bad; 2240 } 2241 ATH_KTR(sc, ATH_KTR_TX, 3, "ath_raw_xmit: m=%p, params=%p, bf=%p\n", 2242 m, params, bf); 2243 2244 if (params == NULL) { 2245 /* 2246 * Legacy path; interpret frame contents to decide 2247 * precisely how to send the frame. 2248 */ 2249 if (ath_tx_start(sc, ni, bf, m)) { 2250 error = EIO; /* XXX */ 2251 goto bad2; 2252 } 2253 } else { 2254 /* 2255 * Caller supplied explicit parameters to use in 2256 * sending the frame. 2257 */ 2258 if (ath_tx_raw_start(sc, ni, bf, m, params)) { 2259 error = EIO; /* XXX */ 2260 goto bad2; 2261 } 2262 } 2263 sc->sc_wd_timer = 5; 2264 ifp->if_opackets++; 2265 sc->sc_stats.ast_tx_raw++; 2266 2267 /* 2268 * Update the TIM - if there's anything queued to the 2269 * software queue and power save is enabled, we should 2270 * set the TIM. 2271 */ 2272 ath_tx_update_tim(sc, ni, 1); 2273 2274 ATH_TX_UNLOCK(sc); 2275 2276 ATH_PCU_LOCK(sc); 2277 sc->sc_txstart_cnt--; 2278 ATH_PCU_UNLOCK(sc); 2279 2280 return 0; 2281bad2: 2282 ATH_KTR(sc, ATH_KTR_TX, 3, "ath_raw_xmit: bad2: m=%p, params=%p, " 2283 "bf=%p", 2284 m, 2285 params, 2286 bf); 2287 ATH_TXBUF_LOCK(sc); 2288 ath_returnbuf_head(sc, bf); 2289 ATH_TXBUF_UNLOCK(sc); 2290bad: 2291 2292 ATH_TX_UNLOCK(sc); 2293 2294 ATH_PCU_LOCK(sc); 2295 sc->sc_txstart_cnt--; 2296 ATH_PCU_UNLOCK(sc); 2297bad0: 2298 ATH_KTR(sc, ATH_KTR_TX, 2, "ath_raw_xmit: bad0: m=%p, params=%p", 2299 m, params); 2300 ifp->if_oerrors++; 2301 sc->sc_stats.ast_tx_raw_fail++; 2302 ieee80211_free_node(ni); 2303 2304 return error; 2305} 2306 2307/* Some helper functions */ 2308 2309/* 2310 * ADDBA (and potentially others) need to be placed in the same 2311 * hardware queue as the TID/node it's relating to. This is so 2312 * it goes out after any pending non-aggregate frames to the 2313 * same node/TID. 2314 * 2315 * If this isn't done, the ADDBA can go out before the frames 2316 * queued in hardware. Even though these frames have a sequence 2317 * number -earlier- than the ADDBA can be transmitted (but 2318 * no frames whose sequence numbers are after the ADDBA should 2319 * be!) they'll arrive after the ADDBA - and the receiving end 2320 * will simply drop them as being out of the BAW. 2321 * 2322 * The frames can't be appended to the TID software queue - it'll 2323 * never be sent out. So these frames have to be directly 2324 * dispatched to the hardware, rather than queued in software. 2325 * So if this function returns true, the TXQ has to be 2326 * overridden and it has to be directly dispatched. 2327 * 2328 * It's a dirty hack, but someone's gotta do it. 2329 */ 2330 2331/* 2332 * XXX doesn't belong here! 2333 */ 2334static int 2335ieee80211_is_action(struct ieee80211_frame *wh) 2336{ 2337 /* Type: Management frame? */ 2338 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 2339 IEEE80211_FC0_TYPE_MGT) 2340 return 0; 2341 2342 /* Subtype: Action frame? */ 2343 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) != 2344 IEEE80211_FC0_SUBTYPE_ACTION) 2345 return 0; 2346 2347 return 1; 2348} 2349 2350#define MS(_v, _f) (((_v) & _f) >> _f##_S) 2351/* 2352 * Return an alternate TID for ADDBA request frames. 2353 * 2354 * Yes, this likely should be done in the net80211 layer. 2355 */ 2356static int 2357ath_tx_action_frame_override_queue(struct ath_softc *sc, 2358 struct ieee80211_node *ni, 2359 struct mbuf *m0, int *tid) 2360{ 2361 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 2362 struct ieee80211_action_ba_addbarequest *ia; 2363 uint8_t *frm; 2364 uint16_t baparamset; 2365 2366 /* Not action frame? Bail */ 2367 if (! ieee80211_is_action(wh)) 2368 return 0; 2369 2370 /* XXX Not needed for frames we send? */ 2371#if 0 2372 /* Correct length? */ 2373 if (! ieee80211_parse_action(ni, m)) 2374 return 0; 2375#endif 2376 2377 /* Extract out action frame */ 2378 frm = (u_int8_t *)&wh[1]; 2379 ia = (struct ieee80211_action_ba_addbarequest *) frm; 2380 2381 /* Not ADDBA? Bail */ 2382 if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA) 2383 return 0; 2384 if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST) 2385 return 0; 2386 2387 /* Extract TID, return it */ 2388 baparamset = le16toh(ia->rq_baparamset); 2389 *tid = (int) MS(baparamset, IEEE80211_BAPS_TID); 2390 2391 return 1; 2392} 2393#undef MS 2394 2395/* Per-node software queue operations */ 2396 2397/* 2398 * Add the current packet to the given BAW. 2399 * It is assumed that the current packet 2400 * 2401 * + fits inside the BAW; 2402 * + already has had a sequence number allocated. 2403 * 2404 * Since the BAW status may be modified by both the ath task and 2405 * the net80211/ifnet contexts, the TID must be locked. 2406 */ 2407void 2408ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an, 2409 struct ath_tid *tid, struct ath_buf *bf) 2410{ 2411 int index, cindex; 2412 struct ieee80211_tx_ampdu *tap; 2413 2414 ATH_TX_LOCK_ASSERT(sc); 2415 2416 if (bf->bf_state.bfs_isretried) 2417 return; 2418 2419 tap = ath_tx_get_tx_tid(an, tid->tid); 2420 2421 if (! bf->bf_state.bfs_dobaw) { 2422 device_printf(sc->sc_dev, 2423 "%s: dobaw=0, seqno=%d, window %d:%d\n", 2424 __func__, 2425 SEQNO(bf->bf_state.bfs_seqno), 2426 tap->txa_start, 2427 tap->txa_wnd); 2428 } 2429 2430 if (bf->bf_state.bfs_addedbaw) 2431 device_printf(sc->sc_dev, 2432 "%s: re-added? tid=%d, seqno %d; window %d:%d; " 2433 "baw head=%d tail=%d\n", 2434 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2435 tap->txa_start, tap->txa_wnd, tid->baw_head, 2436 tid->baw_tail); 2437 2438 /* 2439 * Verify that the given sequence number is not outside of the 2440 * BAW. Complain loudly if that's the case. 2441 */ 2442 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2443 SEQNO(bf->bf_state.bfs_seqno))) { 2444 device_printf(sc->sc_dev, 2445 "%s: bf=%p: outside of BAW?? tid=%d, seqno %d; window %d:%d; " 2446 "baw head=%d tail=%d\n", 2447 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2448 tap->txa_start, tap->txa_wnd, tid->baw_head, 2449 tid->baw_tail); 2450 } 2451 2452 /* 2453 * ni->ni_txseqs[] is the currently allocated seqno. 2454 * the txa state contains the current baw start. 2455 */ 2456 index = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno)); 2457 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2458 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2459 "%s: tid=%d, seqno %d; window %d:%d; index=%d cindex=%d " 2460 "baw head=%d tail=%d\n", 2461 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2462 tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head, 2463 tid->baw_tail); 2464 2465 2466#if 0 2467 assert(tid->tx_buf[cindex] == NULL); 2468#endif 2469 if (tid->tx_buf[cindex] != NULL) { 2470 device_printf(sc->sc_dev, 2471 "%s: ba packet dup (index=%d, cindex=%d, " 2472 "head=%d, tail=%d)\n", 2473 __func__, index, cindex, tid->baw_head, tid->baw_tail); 2474 device_printf(sc->sc_dev, 2475 "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n", 2476 __func__, 2477 tid->tx_buf[cindex], 2478 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno), 2479 bf, 2480 SEQNO(bf->bf_state.bfs_seqno) 2481 ); 2482 } 2483 tid->tx_buf[cindex] = bf; 2484 2485 if (index >= ((tid->baw_tail - tid->baw_head) & 2486 (ATH_TID_MAX_BUFS - 1))) { 2487 tid->baw_tail = cindex; 2488 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 2489 } 2490} 2491 2492/* 2493 * Flip the BAW buffer entry over from the existing one to the new one. 2494 * 2495 * When software retransmitting a (sub-)frame, it is entirely possible that 2496 * the frame ath_buf is marked as BUSY and can't be immediately reused. 2497 * In that instance the buffer is cloned and the new buffer is used for 2498 * retransmit. We thus need to update the ath_buf slot in the BAW buf 2499 * tracking array to maintain consistency. 2500 */ 2501static void 2502ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an, 2503 struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf) 2504{ 2505 int index, cindex; 2506 struct ieee80211_tx_ampdu *tap; 2507 int seqno = SEQNO(old_bf->bf_state.bfs_seqno); 2508 2509 ATH_TX_LOCK_ASSERT(sc); 2510 2511 tap = ath_tx_get_tx_tid(an, tid->tid); 2512 index = ATH_BA_INDEX(tap->txa_start, seqno); 2513 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2514 2515 /* 2516 * Just warn for now; if it happens then we should find out 2517 * about it. It's highly likely the aggregation session will 2518 * soon hang. 2519 */ 2520 if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) { 2521 device_printf(sc->sc_dev, "%s: retransmitted buffer" 2522 " has mismatching seqno's, BA session may hang.\n", 2523 __func__); 2524 device_printf(sc->sc_dev, "%s: old seqno=%d, new_seqno=%d\n", 2525 __func__, 2526 old_bf->bf_state.bfs_seqno, 2527 new_bf->bf_state.bfs_seqno); 2528 } 2529 2530 if (tid->tx_buf[cindex] != old_bf) { 2531 device_printf(sc->sc_dev, "%s: ath_buf pointer incorrect; " 2532 " has m BA session may hang.\n", 2533 __func__); 2534 device_printf(sc->sc_dev, "%s: old bf=%p, new bf=%p\n", 2535 __func__, 2536 old_bf, new_bf); 2537 } 2538 2539 tid->tx_buf[cindex] = new_bf; 2540} 2541 2542/* 2543 * seq_start - left edge of BAW 2544 * seq_next - current/next sequence number to allocate 2545 * 2546 * Since the BAW status may be modified by both the ath task and 2547 * the net80211/ifnet contexts, the TID must be locked. 2548 */ 2549static void 2550ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an, 2551 struct ath_tid *tid, const struct ath_buf *bf) 2552{ 2553 int index, cindex; 2554 struct ieee80211_tx_ampdu *tap; 2555 int seqno = SEQNO(bf->bf_state.bfs_seqno); 2556 2557 ATH_TX_LOCK_ASSERT(sc); 2558 2559 tap = ath_tx_get_tx_tid(an, tid->tid); 2560 index = ATH_BA_INDEX(tap->txa_start, seqno); 2561 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2562 2563 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2564 "%s: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, " 2565 "baw head=%d, tail=%d\n", 2566 __func__, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index, 2567 cindex, tid->baw_head, tid->baw_tail); 2568 2569 /* 2570 * If this occurs then we have a big problem - something else 2571 * has slid tap->txa_start along without updating the BAW 2572 * tracking start/end pointers. Thus the TX BAW state is now 2573 * completely busted. 2574 * 2575 * But for now, since I haven't yet fixed TDMA and buffer cloning, 2576 * it's quite possible that a cloned buffer is making its way 2577 * here and causing it to fire off. Disable TDMA for now. 2578 */ 2579 if (tid->tx_buf[cindex] != bf) { 2580 device_printf(sc->sc_dev, 2581 "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n", 2582 __func__, 2583 bf, SEQNO(bf->bf_state.bfs_seqno), 2584 tid->tx_buf[cindex], 2585 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno)); 2586 } 2587 2588 tid->tx_buf[cindex] = NULL; 2589 2590 while (tid->baw_head != tid->baw_tail && 2591 !tid->tx_buf[tid->baw_head]) { 2592 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 2593 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 2594 } 2595 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2596 "%s: baw is now %d:%d, baw head=%d\n", 2597 __func__, tap->txa_start, tap->txa_wnd, tid->baw_head); 2598} 2599 2600/* 2601 * Mark the current node/TID as ready to TX. 2602 * 2603 * This is done to make it easy for the software scheduler to 2604 * find which nodes have data to send. 2605 * 2606 * The TXQ lock must be held. 2607 */ 2608static void 2609ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid) 2610{ 2611 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2612 2613 ATH_TX_LOCK_ASSERT(sc); 2614 2615 if (tid->paused) 2616 return; /* paused, can't schedule yet */ 2617 2618 if (tid->sched) 2619 return; /* already scheduled */ 2620 2621 tid->sched = 1; 2622 2623 TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem); 2624} 2625 2626/* 2627 * Mark the current node as no longer needing to be polled for 2628 * TX packets. 2629 * 2630 * The TXQ lock must be held. 2631 */ 2632static void 2633ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid) 2634{ 2635 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2636 2637 ATH_TX_LOCK_ASSERT(sc); 2638 2639 if (tid->sched == 0) 2640 return; 2641 2642 tid->sched = 0; 2643 TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem); 2644} 2645 2646/* 2647 * Assign a sequence number manually to the given frame. 2648 * 2649 * This should only be called for A-MPDU TX frames. 2650 */ 2651static ieee80211_seq 2652ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni, 2653 struct ath_buf *bf, struct mbuf *m0) 2654{ 2655 struct ieee80211_frame *wh; 2656 int tid, pri; 2657 ieee80211_seq seqno; 2658 uint8_t subtype; 2659 2660 /* TID lookup */ 2661 wh = mtod(m0, struct ieee80211_frame *); 2662 pri = M_WME_GETAC(m0); /* honor classification */ 2663 tid = WME_AC_TO_TID(pri); 2664 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pri=%d, tid=%d, qos has seq=%d\n", 2665 __func__, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2666 2667 /* XXX Is it a control frame? Ignore */ 2668 2669 /* Does the packet require a sequence number? */ 2670 if (! IEEE80211_QOS_HAS_SEQ(wh)) 2671 return -1; 2672 2673 ATH_TX_LOCK_ASSERT(sc); 2674 2675 /* 2676 * Is it a QOS NULL Data frame? Give it a sequence number from 2677 * the default TID (IEEE80211_NONQOS_TID.) 2678 * 2679 * The RX path of everything I've looked at doesn't include the NULL 2680 * data frame sequence number in the aggregation state updates, so 2681 * assigning it a sequence number there will cause a BAW hole on the 2682 * RX side. 2683 */ 2684 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2685 if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) { 2686 /* XXX no locking for this TID? This is a bit of a problem. */ 2687 seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID]; 2688 INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE); 2689 } else { 2690 /* Manually assign sequence number */ 2691 seqno = ni->ni_txseqs[tid]; 2692 INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE); 2693 } 2694 *(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 2695 M_SEQNO_SET(m0, seqno); 2696 2697 /* Return so caller can do something with it if needed */ 2698 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: -> seqno=%d\n", __func__, seqno); 2699 return seqno; 2700} 2701 2702/* 2703 * Attempt to direct dispatch an aggregate frame to hardware. 2704 * If the frame is out of BAW, queue. 2705 * Otherwise, schedule it as a single frame. 2706 */ 2707static void 2708ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an, 2709 struct ath_txq *txq, struct ath_buf *bf) 2710{ 2711 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid]; 2712 struct ieee80211_tx_ampdu *tap; 2713 2714 ATH_TX_LOCK_ASSERT(sc); 2715 2716 tap = ath_tx_get_tx_tid(an, tid->tid); 2717 2718 /* paused? queue */ 2719 if (tid->paused) { 2720 ATH_TID_INSERT_HEAD(tid, bf, bf_list); 2721 /* XXX don't sched - we're paused! */ 2722 return; 2723 } 2724 2725 /* outside baw? queue */ 2726 if (bf->bf_state.bfs_dobaw && 2727 (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2728 SEQNO(bf->bf_state.bfs_seqno)))) { 2729 ATH_TID_INSERT_HEAD(tid, bf, bf_list); 2730 ath_tx_tid_sched(sc, tid); 2731 return; 2732 } 2733 2734 /* 2735 * This is a temporary check and should be removed once 2736 * all the relevant code paths have been fixed. 2737 * 2738 * During aggregate retries, it's possible that the head 2739 * frame will fail (which has the bfs_aggr and bfs_nframes 2740 * fields set for said aggregate) and will be retried as 2741 * a single frame. In this instance, the values should 2742 * be reset or the completion code will get upset with you. 2743 */ 2744 if (bf->bf_state.bfs_aggr != 0 || bf->bf_state.bfs_nframes > 1) { 2745 device_printf(sc->sc_dev, "%s: bfs_aggr=%d, bfs_nframes=%d\n", 2746 __func__, 2747 bf->bf_state.bfs_aggr, 2748 bf->bf_state.bfs_nframes); 2749 bf->bf_state.bfs_aggr = 0; 2750 bf->bf_state.bfs_nframes = 1; 2751 } 2752 2753 /* Update CLRDMASK just before this frame is queued */ 2754 ath_tx_update_clrdmask(sc, tid, bf); 2755 2756 /* Direct dispatch to hardware */ 2757 ath_tx_do_ratelookup(sc, bf); 2758 ath_tx_calc_duration(sc, bf); 2759 ath_tx_calc_protection(sc, bf); 2760 ath_tx_set_rtscts(sc, bf); 2761 ath_tx_rate_fill_rcflags(sc, bf); 2762 ath_tx_setds(sc, bf); 2763 2764 /* Statistics */ 2765 sc->sc_aggr_stats.aggr_low_hwq_single_pkt++; 2766 2767 /* Track per-TID hardware queue depth correctly */ 2768 tid->hwq_depth++; 2769 2770 /* Add to BAW */ 2771 if (bf->bf_state.bfs_dobaw) { 2772 ath_tx_addto_baw(sc, an, tid, bf); 2773 bf->bf_state.bfs_addedbaw = 1; 2774 } 2775 2776 /* Set completion handler, multi-frame aggregate or not */ 2777 bf->bf_comp = ath_tx_aggr_comp; 2778 2779 /* Hand off to hardware */ 2780 ath_tx_handoff(sc, txq, bf); 2781} 2782 2783/* 2784 * Attempt to send the packet. 2785 * If the queue isn't busy, direct-dispatch. 2786 * If the queue is busy enough, queue the given packet on the 2787 * relevant software queue. 2788 */ 2789void 2790ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_txq *txq, 2791 struct ath_buf *bf) 2792{ 2793 struct ath_node *an = ATH_NODE(ni); 2794 struct ieee80211_frame *wh; 2795 struct ath_tid *atid; 2796 int pri, tid; 2797 struct mbuf *m0 = bf->bf_m; 2798 2799 ATH_TX_LOCK_ASSERT(sc); 2800 2801 /* Fetch the TID - non-QoS frames get assigned to TID 16 */ 2802 wh = mtod(m0, struct ieee80211_frame *); 2803 pri = ath_tx_getac(sc, m0); 2804 tid = ath_tx_gettid(sc, m0); 2805 atid = &an->an_tid[tid]; 2806 2807 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d\n", 2808 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2809 2810 /* Set local packet state, used to queue packets to hardware */ 2811 /* XXX potentially duplicate info, re-check */ 2812 bf->bf_state.bfs_tid = tid; 2813 bf->bf_state.bfs_tx_queue = txq->axq_qnum; 2814 bf->bf_state.bfs_pri = pri; 2815 2816 /* 2817 * If the hardware queue isn't busy, queue it directly. 2818 * If the hardware queue is busy, queue it. 2819 * If the TID is paused or the traffic it outside BAW, software 2820 * queue it. 2821 */ 2822 if (atid->paused) { 2823 /* TID is paused, queue */ 2824 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: paused\n", __func__); 2825 ATH_TID_INSERT_TAIL(atid, bf, bf_list); 2826 } else if (ath_tx_ampdu_pending(sc, an, tid)) { 2827 /* AMPDU pending; queue */ 2828 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pending\n", __func__); 2829 ATH_TID_INSERT_TAIL(atid, bf, bf_list); 2830 /* XXX sched? */ 2831 } else if (ath_tx_ampdu_running(sc, an, tid)) { 2832 /* AMPDU running, attempt direct dispatch if possible */ 2833 2834 /* 2835 * Always queue the frame to the tail of the list. 2836 */ 2837 ATH_TID_INSERT_TAIL(atid, bf, bf_list); 2838 2839 /* 2840 * If the hardware queue isn't busy, direct dispatch 2841 * the head frame in the list. Don't schedule the 2842 * TID - let it build some more frames first? 2843 * 2844 * Otherwise, schedule the TID. 2845 */ 2846 if (txq->axq_depth < sc->sc_hwq_limit) { 2847 bf = ATH_TID_FIRST(atid); 2848 ATH_TID_REMOVE(atid, bf, bf_list); 2849 2850 /* 2851 * Ensure it's definitely treated as a non-AMPDU 2852 * frame - this information may have been left 2853 * over from a previous attempt. 2854 */ 2855 bf->bf_state.bfs_aggr = 0; 2856 bf->bf_state.bfs_nframes = 1; 2857 2858 /* Queue to the hardware */ 2859 ath_tx_xmit_aggr(sc, an, txq, bf); 2860 DPRINTF(sc, ATH_DEBUG_SW_TX, 2861 "%s: xmit_aggr\n", 2862 __func__); 2863 } else { 2864 DPRINTF(sc, ATH_DEBUG_SW_TX, 2865 "%s: ampdu; swq'ing\n", 2866 __func__); 2867 2868 ath_tx_tid_sched(sc, atid); 2869 } 2870 } else if (txq->axq_depth < sc->sc_hwq_limit) { 2871 /* AMPDU not running, attempt direct dispatch */ 2872 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: xmit_normal\n", __func__); 2873 /* See if clrdmask needs to be set */ 2874 ath_tx_update_clrdmask(sc, atid, bf); 2875 ath_tx_xmit_normal(sc, txq, bf); 2876 } else { 2877 /* Busy; queue */ 2878 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: swq'ing\n", __func__); 2879 ATH_TID_INSERT_TAIL(atid, bf, bf_list); 2880 ath_tx_tid_sched(sc, atid); 2881 } 2882} 2883 2884/* 2885 * Only set the clrdmask bit if none of the nodes are currently 2886 * filtered. 2887 * 2888 * XXX TODO: go through all the callers and check to see 2889 * which are being called in the context of looping over all 2890 * TIDs (eg, if all tids are being paused, resumed, etc.) 2891 * That'll avoid O(n^2) complexity here. 2892 */ 2893static void 2894ath_tx_set_clrdmask(struct ath_softc *sc, struct ath_node *an) 2895{ 2896 int i; 2897 2898 ATH_TX_LOCK_ASSERT(sc); 2899 2900 for (i = 0; i < IEEE80211_TID_SIZE; i++) { 2901 if (an->an_tid[i].isfiltered == 1) 2902 return; 2903 } 2904 an->clrdmask = 1; 2905} 2906 2907/* 2908 * Configure the per-TID node state. 2909 * 2910 * This likely belongs in if_ath_node.c but I can't think of anywhere 2911 * else to put it just yet. 2912 * 2913 * This sets up the SLISTs and the mutex as appropriate. 2914 */ 2915void 2916ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an) 2917{ 2918 int i, j; 2919 struct ath_tid *atid; 2920 2921 for (i = 0; i < IEEE80211_TID_SIZE; i++) { 2922 atid = &an->an_tid[i]; 2923 2924 /* XXX now with this bzer(), is the field 0'ing needed? */ 2925 bzero(atid, sizeof(*atid)); 2926 2927 TAILQ_INIT(&atid->tid_q); 2928 TAILQ_INIT(&atid->filtq.tid_q); 2929 atid->tid = i; 2930 atid->an = an; 2931 for (j = 0; j < ATH_TID_MAX_BUFS; j++) 2932 atid->tx_buf[j] = NULL; 2933 atid->baw_head = atid->baw_tail = 0; 2934 atid->paused = 0; 2935 atid->sched = 0; 2936 atid->hwq_depth = 0; 2937 atid->cleanup_inprogress = 0; 2938 if (i == IEEE80211_NONQOS_TID) 2939 atid->ac = ATH_NONQOS_TID_AC; 2940 else 2941 atid->ac = TID_TO_WME_AC(i); 2942 } 2943 an->clrdmask = 1; /* Always start by setting this bit */ 2944} 2945 2946/* 2947 * Pause the current TID. This stops packets from being transmitted 2948 * on it. 2949 * 2950 * Since this is also called from upper layers as well as the driver, 2951 * it will get the TID lock. 2952 */ 2953static void 2954ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid) 2955{ 2956 2957 ATH_TX_LOCK_ASSERT(sc); 2958 tid->paused++; 2959 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n", 2960 __func__, tid->paused); 2961} 2962 2963/* 2964 * Unpause the current TID, and schedule it if needed. 2965 */ 2966static void 2967ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid) 2968{ 2969 ATH_TX_LOCK_ASSERT(sc); 2970 2971 tid->paused--; 2972 2973 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n", 2974 __func__, tid->paused); 2975 2976 if (tid->paused) 2977 return; 2978 2979 /* 2980 * Override the clrdmask configuration for the next frame 2981 * from this TID, just to get the ball rolling. 2982 */ 2983 ath_tx_set_clrdmask(sc, tid->an); 2984 2985 if (tid->axq_depth == 0) 2986 return; 2987 2988 /* XXX isfiltered shouldn't ever be 0 at this point */ 2989 if (tid->isfiltered == 1) { 2990 device_printf(sc->sc_dev, "%s: filtered?!\n", __func__); 2991 return; 2992 } 2993 2994 ath_tx_tid_sched(sc, tid); 2995 2996 /* 2997 * Queue the software TX scheduler. 2998 */ 2999 ath_tx_swq_kick(sc); 3000} 3001 3002/* 3003 * Add the given ath_buf to the TID filtered frame list. 3004 * This requires the TID be filtered. 3005 */ 3006static void 3007ath_tx_tid_filt_addbuf(struct ath_softc *sc, struct ath_tid *tid, 3008 struct ath_buf *bf) 3009{ 3010 3011 ATH_TX_LOCK_ASSERT(sc); 3012 3013 if (! tid->isfiltered) 3014 device_printf(sc->sc_dev, "%s: not filtered?!\n", __func__); 3015 3016 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: bf=%p\n", __func__, bf); 3017 3018 /* Set the retry bit and bump the retry counter */ 3019 ath_tx_set_retry(sc, bf); 3020 sc->sc_stats.ast_tx_swfiltered++; 3021 3022 ATH_TID_FILT_INSERT_TAIL(tid, bf, bf_list); 3023} 3024 3025/* 3026 * Handle a completed filtered frame from the given TID. 3027 * This just enables/pauses the filtered frame state if required 3028 * and appends the filtered frame to the filtered queue. 3029 */ 3030static void 3031ath_tx_tid_filt_comp_buf(struct ath_softc *sc, struct ath_tid *tid, 3032 struct ath_buf *bf) 3033{ 3034 3035 ATH_TX_LOCK_ASSERT(sc); 3036 3037 if (! tid->isfiltered) { 3038 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: filter transition\n", 3039 __func__); 3040 tid->isfiltered = 1; 3041 ath_tx_tid_pause(sc, tid); 3042 } 3043 3044 /* Add the frame to the filter queue */ 3045 ath_tx_tid_filt_addbuf(sc, tid, bf); 3046} 3047 3048/* 3049 * Complete the filtered frame TX completion. 3050 * 3051 * If there are no more frames in the hardware queue, unpause/unfilter 3052 * the TID if applicable. Otherwise we will wait for a node PS transition 3053 * to unfilter. 3054 */ 3055static void 3056ath_tx_tid_filt_comp_complete(struct ath_softc *sc, struct ath_tid *tid) 3057{ 3058 struct ath_buf *bf; 3059 3060 ATH_TX_LOCK_ASSERT(sc); 3061 3062 if (tid->hwq_depth != 0) 3063 return; 3064 3065 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: hwq=0, transition back\n", 3066 __func__); 3067 tid->isfiltered = 0; 3068 /* XXX ath_tx_tid_resume() also calls ath_tx_set_clrdmask()! */ 3069 ath_tx_set_clrdmask(sc, tid->an); 3070 3071 /* XXX this is really quite inefficient */ 3072 while ((bf = ATH_TID_FILT_LAST(tid, ath_bufhead_s)) != NULL) { 3073 ATH_TID_FILT_REMOVE(tid, bf, bf_list); 3074 ATH_TID_INSERT_HEAD(tid, bf, bf_list); 3075 } 3076 3077 ath_tx_tid_resume(sc, tid); 3078} 3079 3080/* 3081 * Called when a single (aggregate or otherwise) frame is completed. 3082 * 3083 * Returns 1 if the buffer could be added to the filtered list 3084 * (cloned or otherwise), 0 if the buffer couldn't be added to the 3085 * filtered list (failed clone; expired retry) and the caller should 3086 * free it and handle it like a failure (eg by sending a BAR.) 3087 */ 3088static int 3089ath_tx_tid_filt_comp_single(struct ath_softc *sc, struct ath_tid *tid, 3090 struct ath_buf *bf) 3091{ 3092 struct ath_buf *nbf; 3093 int retval; 3094 3095 ATH_TX_LOCK_ASSERT(sc); 3096 3097 /* 3098 * Don't allow a filtered frame to live forever. 3099 */ 3100 if (bf->bf_state.bfs_retries > SWMAX_RETRIES) { 3101 sc->sc_stats.ast_tx_swretrymax++; 3102 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3103 "%s: bf=%p, seqno=%d, exceeded retries\n", 3104 __func__, 3105 bf, 3106 bf->bf_state.bfs_seqno); 3107 return (0); 3108 } 3109 3110 /* 3111 * A busy buffer can't be added to the retry list. 3112 * It needs to be cloned. 3113 */ 3114 if (bf->bf_flags & ATH_BUF_BUSY) { 3115 nbf = ath_tx_retry_clone(sc, tid->an, tid, bf); 3116 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3117 "%s: busy buffer clone: %p -> %p\n", 3118 __func__, bf, nbf); 3119 } else { 3120 nbf = bf; 3121 } 3122 3123 if (nbf == NULL) { 3124 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3125 "%s: busy buffer couldn't be cloned (%p)!\n", 3126 __func__, bf); 3127 retval = 1; 3128 } else { 3129 ath_tx_tid_filt_comp_buf(sc, tid, nbf); 3130 retval = 0; 3131 } 3132 ath_tx_tid_filt_comp_complete(sc, tid); 3133 3134 return (retval); 3135} 3136 3137static void 3138ath_tx_tid_filt_comp_aggr(struct ath_softc *sc, struct ath_tid *tid, 3139 struct ath_buf *bf_first, ath_bufhead *bf_q) 3140{ 3141 struct ath_buf *bf, *bf_next, *nbf; 3142 3143 ATH_TX_LOCK_ASSERT(sc); 3144 3145 bf = bf_first; 3146 while (bf) { 3147 bf_next = bf->bf_next; 3148 bf->bf_next = NULL; /* Remove it from the aggr list */ 3149 3150 /* 3151 * Don't allow a filtered frame to live forever. 3152 */ 3153 if (bf->bf_state.bfs_retries > SWMAX_RETRIES) { 3154 sc->sc_stats.ast_tx_swretrymax++; 3155 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3156 "%s: bf=%p, seqno=%d, exceeded retries\n", 3157 __func__, 3158 bf, 3159 bf->bf_state.bfs_seqno); 3160 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 3161 goto next; 3162 } 3163 3164 if (bf->bf_flags & ATH_BUF_BUSY) { 3165 nbf = ath_tx_retry_clone(sc, tid->an, tid, bf); 3166 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3167 "%s: busy buffer cloned: %p -> %p", 3168 __func__, bf, nbf); 3169 } else { 3170 nbf = bf; 3171 } 3172 3173 /* 3174 * If the buffer couldn't be cloned, add it to bf_q; 3175 * the caller will free the buffer(s) as required. 3176 */ 3177 if (nbf == NULL) { 3178 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3179 "%s: buffer couldn't be cloned! (%p)\n", 3180 __func__, bf); 3181 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 3182 } else { 3183 ath_tx_tid_filt_comp_buf(sc, tid, nbf); 3184 } 3185next: 3186 bf = bf_next; 3187 } 3188 3189 ath_tx_tid_filt_comp_complete(sc, tid); 3190} 3191 3192/* 3193 * Suspend the queue because we need to TX a BAR. 3194 */ 3195static void 3196ath_tx_tid_bar_suspend(struct ath_softc *sc, struct ath_tid *tid) 3197{ 3198 3199 ATH_TX_LOCK_ASSERT(sc); 3200 3201 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3202 "%s: tid=%p, bar_wait=%d, bar_tx=%d, called\n", 3203 __func__, 3204 tid, 3205 tid->bar_wait, 3206 tid->bar_tx); 3207 3208 /* We shouldn't be called when bar_tx is 1 */ 3209 if (tid->bar_tx) { 3210 device_printf(sc->sc_dev, "%s: bar_tx is 1?!\n", 3211 __func__); 3212 } 3213 3214 /* If we've already been called, just be patient. */ 3215 if (tid->bar_wait) 3216 return; 3217 3218 /* Wait! */ 3219 tid->bar_wait = 1; 3220 3221 /* Only one pause, no matter how many frames fail */ 3222 ath_tx_tid_pause(sc, tid); 3223} 3224 3225/* 3226 * We've finished with BAR handling - either we succeeded or 3227 * failed. Either way, unsuspend TX. 3228 */ 3229static void 3230ath_tx_tid_bar_unsuspend(struct ath_softc *sc, struct ath_tid *tid) 3231{ 3232 3233 ATH_TX_LOCK_ASSERT(sc); 3234 3235 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3236 "%s: tid=%p, called\n", 3237 __func__, 3238 tid); 3239 3240 if (tid->bar_tx == 0 || tid->bar_wait == 0) { 3241 device_printf(sc->sc_dev, "%s: bar_tx=%d, bar_wait=%d: ?\n", 3242 __func__, tid->bar_tx, tid->bar_wait); 3243 } 3244 3245 tid->bar_tx = tid->bar_wait = 0; 3246 ath_tx_tid_resume(sc, tid); 3247} 3248 3249/* 3250 * Return whether we're ready to TX a BAR frame. 3251 * 3252 * Requires the TID lock be held. 3253 */ 3254static int 3255ath_tx_tid_bar_tx_ready(struct ath_softc *sc, struct ath_tid *tid) 3256{ 3257 3258 ATH_TX_LOCK_ASSERT(sc); 3259 3260 if (tid->bar_wait == 0 || tid->hwq_depth > 0) 3261 return (0); 3262 3263 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, "%s: tid=%p (%d), bar ready\n", 3264 __func__, tid, tid->tid); 3265 3266 return (1); 3267} 3268 3269/* 3270 * Check whether the current TID is ready to have a BAR 3271 * TXed and if so, do the TX. 3272 * 3273 * Since the TID/TXQ lock can't be held during a call to 3274 * ieee80211_send_bar(), we have to do the dirty thing of unlocking it, 3275 * sending the BAR and locking it again. 3276 * 3277 * Eventually, the code to send the BAR should be broken out 3278 * from this routine so the lock doesn't have to be reacquired 3279 * just to be immediately dropped by the caller. 3280 */ 3281static void 3282ath_tx_tid_bar_tx(struct ath_softc *sc, struct ath_tid *tid) 3283{ 3284 struct ieee80211_tx_ampdu *tap; 3285 3286 ATH_TX_LOCK_ASSERT(sc); 3287 3288 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3289 "%s: tid=%p, called\n", 3290 __func__, 3291 tid); 3292 3293 tap = ath_tx_get_tx_tid(tid->an, tid->tid); 3294 3295 /* 3296 * This is an error condition! 3297 */ 3298 if (tid->bar_wait == 0 || tid->bar_tx == 1) { 3299 device_printf(sc->sc_dev, 3300 "%s: tid=%p, bar_tx=%d, bar_wait=%d: ?\n", 3301 __func__, 3302 tid, 3303 tid->bar_tx, 3304 tid->bar_wait); 3305 return; 3306 } 3307 3308 /* Don't do anything if we still have pending frames */ 3309 if (tid->hwq_depth > 0) { 3310 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3311 "%s: tid=%p, hwq_depth=%d, waiting\n", 3312 __func__, 3313 tid, 3314 tid->hwq_depth); 3315 return; 3316 } 3317 3318 /* We're now about to TX */ 3319 tid->bar_tx = 1; 3320 3321 /* 3322 * Override the clrdmask configuration for the next frame, 3323 * just to get the ball rolling. 3324 */ 3325 ath_tx_set_clrdmask(sc, tid->an); 3326 3327 /* 3328 * Calculate new BAW left edge, now that all frames have either 3329 * succeeded or failed. 3330 * 3331 * XXX verify this is _actually_ the valid value to begin at! 3332 */ 3333 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3334 "%s: tid=%p, new BAW left edge=%d\n", 3335 __func__, 3336 tid, 3337 tap->txa_start); 3338 3339 /* Try sending the BAR frame */ 3340 /* We can't hold the lock here! */ 3341 3342 ATH_TX_UNLOCK(sc); 3343 if (ieee80211_send_bar(&tid->an->an_node, tap, tap->txa_start) == 0) { 3344 /* Success? Now we wait for notification that it's done */ 3345 ATH_TX_LOCK(sc); 3346 return; 3347 } 3348 3349 /* Failure? For now, warn loudly and continue */ 3350 ATH_TX_LOCK(sc); 3351 device_printf(sc->sc_dev, "%s: tid=%p, failed to TX BAR, continue!\n", 3352 __func__, tid); 3353 ath_tx_tid_bar_unsuspend(sc, tid); 3354} 3355 3356static void 3357ath_tx_tid_drain_pkt(struct ath_softc *sc, struct ath_node *an, 3358 struct ath_tid *tid, ath_bufhead *bf_cq, struct ath_buf *bf) 3359{ 3360 3361 ATH_TX_LOCK_ASSERT(sc); 3362 3363 /* 3364 * If the current TID is running AMPDU, update 3365 * the BAW. 3366 */ 3367 if (ath_tx_ampdu_running(sc, an, tid->tid) && 3368 bf->bf_state.bfs_dobaw) { 3369 /* 3370 * Only remove the frame from the BAW if it's 3371 * been transmitted at least once; this means 3372 * the frame was in the BAW to begin with. 3373 */ 3374 if (bf->bf_state.bfs_retries > 0) { 3375 ath_tx_update_baw(sc, an, tid, bf); 3376 bf->bf_state.bfs_dobaw = 0; 3377 } 3378#if 0 3379 /* 3380 * This has become a non-fatal error now 3381 */ 3382 if (! bf->bf_state.bfs_addedbaw) 3383 device_printf(sc->sc_dev, 3384 "%s: wasn't added: seqno %d\n", 3385 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3386#endif 3387 } 3388 3389 /* Strip it out of an aggregate list if it was in one */ 3390 bf->bf_next = NULL; 3391 3392 /* Insert on the free queue to be freed by the caller */ 3393 TAILQ_INSERT_TAIL(bf_cq, bf, bf_list); 3394} 3395 3396static void 3397ath_tx_tid_drain_print(struct ath_softc *sc, struct ath_node *an, 3398 const char *pfx, struct ath_tid *tid, struct ath_buf *bf) 3399{ 3400 struct ieee80211_node *ni = &an->an_node; 3401 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 3402 struct ieee80211_tx_ampdu *tap; 3403 3404 tap = ath_tx_get_tx_tid(an, tid->tid); 3405 3406 device_printf(sc->sc_dev, 3407 "%s: %s: node %p: bf=%p: addbaw=%d, dobaw=%d, " 3408 "seqno=%d, retry=%d\n", 3409 __func__, pfx, ni, bf, 3410 bf->bf_state.bfs_addedbaw, 3411 bf->bf_state.bfs_dobaw, 3412 SEQNO(bf->bf_state.bfs_seqno), 3413 bf->bf_state.bfs_retries); 3414 device_printf(sc->sc_dev, 3415 "%s: node %p: bf=%p: txq[%d] axq_depth=%d, axq_aggr_depth=%d\n", 3416 __func__, ni, bf, 3417 txq->axq_qnum, 3418 txq->axq_depth, 3419 txq->axq_aggr_depth); 3420 3421 device_printf(sc->sc_dev, 3422 "%s: node %p: bf=%p: tid txq_depth=%d hwq_depth=%d, bar_wait=%d, isfiltered=%d\n", 3423 __func__, ni, bf, 3424 tid->axq_depth, 3425 tid->hwq_depth, 3426 tid->bar_wait, 3427 tid->isfiltered); 3428 device_printf(sc->sc_dev, 3429 "%s: node %p: tid %d: " 3430 "sched=%d, paused=%d, " 3431 "incomp=%d, baw_head=%d, " 3432 "baw_tail=%d txa_start=%d, ni_txseqs=%d\n", 3433 __func__, ni, tid->tid, 3434 tid->sched, tid->paused, 3435 tid->incomp, tid->baw_head, 3436 tid->baw_tail, tap == NULL ? -1 : tap->txa_start, 3437 ni->ni_txseqs[tid->tid]); 3438 3439 /* XXX Dump the frame, see what it is? */ 3440 ieee80211_dump_pkt(ni->ni_ic, 3441 mtod(bf->bf_m, const uint8_t *), 3442 bf->bf_m->m_len, 0, -1); 3443} 3444 3445/* 3446 * Free any packets currently pending in the software TX queue. 3447 * 3448 * This will be called when a node is being deleted. 3449 * 3450 * It can also be called on an active node during an interface 3451 * reset or state transition. 3452 * 3453 * (From Linux/reference): 3454 * 3455 * TODO: For frame(s) that are in the retry state, we will reuse the 3456 * sequence number(s) without setting the retry bit. The 3457 * alternative is to give up on these and BAR the receiver's window 3458 * forward. 3459 */ 3460static void 3461ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an, 3462 struct ath_tid *tid, ath_bufhead *bf_cq) 3463{ 3464 struct ath_buf *bf; 3465 struct ieee80211_tx_ampdu *tap; 3466 struct ieee80211_node *ni = &an->an_node; 3467 int t; 3468 3469 tap = ath_tx_get_tx_tid(an, tid->tid); 3470 3471 ATH_TX_LOCK_ASSERT(sc); 3472 3473 /* Walk the queue, free frames */ 3474 t = 0; 3475 for (;;) { 3476 bf = ATH_TID_FIRST(tid); 3477 if (bf == NULL) { 3478 break; 3479 } 3480 3481 if (t == 0) { 3482 ath_tx_tid_drain_print(sc, an, "norm", tid, bf); 3483 t = 1; 3484 } 3485 3486 ATH_TID_REMOVE(tid, bf, bf_list); 3487 ath_tx_tid_drain_pkt(sc, an, tid, bf_cq, bf); 3488 } 3489 3490 /* And now, drain the filtered frame queue */ 3491 t = 0; 3492 for (;;) { 3493 bf = ATH_TID_FILT_FIRST(tid); 3494 if (bf == NULL) 3495 break; 3496 3497 if (t == 0) { 3498 ath_tx_tid_drain_print(sc, an, "filt", tid, bf); 3499 t = 1; 3500 } 3501 3502 ATH_TID_FILT_REMOVE(tid, bf, bf_list); 3503 ath_tx_tid_drain_pkt(sc, an, tid, bf_cq, bf); 3504 } 3505 3506 /* 3507 * Override the clrdmask configuration for the next frame 3508 * in case there is some future transmission, just to get 3509 * the ball rolling. 3510 * 3511 * This won't hurt things if the TID is about to be freed. 3512 */ 3513 ath_tx_set_clrdmask(sc, tid->an); 3514 3515 /* 3516 * Now that it's completed, grab the TID lock and update 3517 * the sequence number and BAW window. 3518 * Because sequence numbers have been assigned to frames 3519 * that haven't been sent yet, it's entirely possible 3520 * we'll be called with some pending frames that have not 3521 * been transmitted. 3522 * 3523 * The cleaner solution is to do the sequence number allocation 3524 * when the packet is first transmitted - and thus the "retries" 3525 * check above would be enough to update the BAW/seqno. 3526 */ 3527 3528 /* But don't do it for non-QoS TIDs */ 3529 if (tap) { 3530#if 0 3531 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3532 "%s: node %p: TID %d: sliding BAW left edge to %d\n", 3533 __func__, an, tid->tid, tap->txa_start); 3534#endif 3535 ni->ni_txseqs[tid->tid] = tap->txa_start; 3536 tid->baw_tail = tid->baw_head; 3537 } 3538} 3539 3540/* 3541 * Flush all software queued packets for the given node. 3542 * 3543 * This occurs when a completion handler frees the last buffer 3544 * for a node, and the node is thus freed. This causes the node 3545 * to be cleaned up, which ends up calling ath_tx_node_flush. 3546 */ 3547void 3548ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an) 3549{ 3550 int tid; 3551 ath_bufhead bf_cq; 3552 struct ath_buf *bf; 3553 3554 TAILQ_INIT(&bf_cq); 3555 3556 ATH_KTR(sc, ATH_KTR_NODE, 1, "ath_tx_node_flush: flush node; ni=%p", 3557 &an->an_node); 3558 3559 ATH_TX_LOCK(sc); 3560 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 3561 struct ath_tid *atid = &an->an_tid[tid]; 3562 3563 /* Free packets */ 3564 ath_tx_tid_drain(sc, an, atid, &bf_cq); 3565 /* Remove this tid from the list of active tids */ 3566 ath_tx_tid_unsched(sc, atid); 3567 } 3568 ATH_TX_UNLOCK(sc); 3569 3570 /* Handle completed frames */ 3571 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3572 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3573 ath_tx_default_comp(sc, bf, 0); 3574 } 3575} 3576 3577/* 3578 * Drain all the software TXQs currently with traffic queued. 3579 */ 3580void 3581ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq) 3582{ 3583 struct ath_tid *tid; 3584 ath_bufhead bf_cq; 3585 struct ath_buf *bf; 3586 3587 TAILQ_INIT(&bf_cq); 3588 ATH_TX_LOCK(sc); 3589 3590 /* 3591 * Iterate over all active tids for the given txq, 3592 * flushing and unsched'ing them 3593 */ 3594 while (! TAILQ_EMPTY(&txq->axq_tidq)) { 3595 tid = TAILQ_FIRST(&txq->axq_tidq); 3596 ath_tx_tid_drain(sc, tid->an, tid, &bf_cq); 3597 ath_tx_tid_unsched(sc, tid); 3598 } 3599 3600 ATH_TX_UNLOCK(sc); 3601 3602 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3603 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3604 ath_tx_default_comp(sc, bf, 0); 3605 } 3606} 3607 3608/* 3609 * Handle completion of non-aggregate session frames. 3610 * 3611 * This (currently) doesn't implement software retransmission of 3612 * non-aggregate frames! 3613 * 3614 * Software retransmission of non-aggregate frames needs to obey 3615 * the strict sequence number ordering, and drop any frames that 3616 * will fail this. 3617 * 3618 * For now, filtered frames and frame transmission will cause 3619 * all kinds of issues. So we don't support them. 3620 * 3621 * So anyone queuing frames via ath_tx_normal_xmit() or 3622 * ath_tx_hw_queue_norm() must override and set CLRDMASK. 3623 */ 3624void 3625ath_tx_normal_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3626{ 3627 struct ieee80211_node *ni = bf->bf_node; 3628 struct ath_node *an = ATH_NODE(ni); 3629 int tid = bf->bf_state.bfs_tid; 3630 struct ath_tid *atid = &an->an_tid[tid]; 3631 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3632 3633 /* The TID state is protected behind the TXQ lock */ 3634 ATH_TX_LOCK(sc); 3635 3636 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: fail=%d, hwq_depth now %d\n", 3637 __func__, bf, fail, atid->hwq_depth - 1); 3638 3639 atid->hwq_depth--; 3640 3641#if 0 3642 /* 3643 * If the frame was filtered, stick it on the filter frame 3644 * queue and complain about it. It shouldn't happen! 3645 */ 3646 if ((ts->ts_status & HAL_TXERR_FILT) || 3647 (ts->ts_status != 0 && atid->isfiltered)) { 3648 device_printf(sc->sc_dev, 3649 "%s: isfiltered=%d, ts_status=%d: huh?\n", 3650 __func__, 3651 atid->isfiltered, 3652 ts->ts_status); 3653 ath_tx_tid_filt_comp_buf(sc, atid, bf); 3654 } 3655#endif 3656 if (atid->isfiltered) 3657 device_printf(sc->sc_dev, "%s: filtered?!\n", __func__); 3658 if (atid->hwq_depth < 0) 3659 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3660 __func__, atid->hwq_depth); 3661 3662 /* 3663 * If the queue is filtered, potentially mark it as complete 3664 * and reschedule it as needed. 3665 * 3666 * This is required as there may be a subsequent TX descriptor 3667 * for this end-node that has CLRDMASK set, so it's quite possible 3668 * that a filtered frame will be followed by a non-filtered 3669 * (complete or otherwise) frame. 3670 * 3671 * XXX should we do this before we complete the frame? 3672 */ 3673 if (atid->isfiltered) 3674 ath_tx_tid_filt_comp_complete(sc, atid); 3675 ATH_TX_UNLOCK(sc); 3676 3677 /* 3678 * punt to rate control if we're not being cleaned up 3679 * during a hw queue drain and the frame wanted an ACK. 3680 */ 3681 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 3682 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 3683 ts, bf->bf_state.bfs_pktlen, 3684 1, (ts->ts_status == 0) ? 0 : 1); 3685 3686 ath_tx_default_comp(sc, bf, fail); 3687} 3688 3689/* 3690 * Handle cleanup of aggregate session packets that aren't 3691 * an A-MPDU. 3692 * 3693 * There's no need to update the BAW here - the session is being 3694 * torn down. 3695 */ 3696static void 3697ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3698{ 3699 struct ieee80211_node *ni = bf->bf_node; 3700 struct ath_node *an = ATH_NODE(ni); 3701 int tid = bf->bf_state.bfs_tid; 3702 struct ath_tid *atid = &an->an_tid[tid]; 3703 3704 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: TID %d: incomp=%d\n", 3705 __func__, tid, atid->incomp); 3706 3707 ATH_TX_LOCK(sc); 3708 atid->incomp--; 3709 if (atid->incomp == 0) { 3710 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3711 "%s: TID %d: cleaned up! resume!\n", 3712 __func__, tid); 3713 atid->cleanup_inprogress = 0; 3714 ath_tx_tid_resume(sc, atid); 3715 } 3716 ATH_TX_UNLOCK(sc); 3717 3718 ath_tx_default_comp(sc, bf, 0); 3719} 3720 3721/* 3722 * Performs transmit side cleanup when TID changes from aggregated to 3723 * unaggregated. 3724 * 3725 * - Discard all retry frames from the s/w queue. 3726 * - Fix the tx completion function for all buffers in s/w queue. 3727 * - Count the number of unacked frames, and let transmit completion 3728 * handle it later. 3729 * 3730 * The caller is responsible for pausing the TID. 3731 */ 3732static void 3733ath_tx_tid_cleanup(struct ath_softc *sc, struct ath_node *an, int tid) 3734{ 3735 struct ath_tid *atid = &an->an_tid[tid]; 3736 struct ieee80211_tx_ampdu *tap; 3737 struct ath_buf *bf, *bf_next; 3738 ath_bufhead bf_cq; 3739 3740 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 3741 "%s: TID %d: called\n", __func__, tid); 3742 3743 TAILQ_INIT(&bf_cq); 3744 ATH_TX_LOCK(sc); 3745 3746 /* 3747 * Move the filtered frames to the TX queue, before 3748 * we run off and discard/process things. 3749 */ 3750 /* XXX this is really quite inefficient */ 3751 while ((bf = ATH_TID_FILT_LAST(atid, ath_bufhead_s)) != NULL) { 3752 ATH_TID_FILT_REMOVE(atid, bf, bf_list); 3753 ATH_TID_INSERT_HEAD(atid, bf, bf_list); 3754 } 3755 3756 /* 3757 * Update the frames in the software TX queue: 3758 * 3759 * + Discard retry frames in the queue 3760 * + Fix the completion function to be non-aggregate 3761 */ 3762 bf = ATH_TID_FIRST(atid); 3763 while (bf) { 3764 if (bf->bf_state.bfs_isretried) { 3765 bf_next = TAILQ_NEXT(bf, bf_list); 3766 ATH_TID_REMOVE(atid, bf, bf_list); 3767 if (bf->bf_state.bfs_dobaw) { 3768 ath_tx_update_baw(sc, an, atid, bf); 3769 if (! bf->bf_state.bfs_addedbaw) 3770 device_printf(sc->sc_dev, 3771 "%s: wasn't added: seqno %d\n", 3772 __func__, 3773 SEQNO(bf->bf_state.bfs_seqno)); 3774 } 3775 bf->bf_state.bfs_dobaw = 0; 3776 /* 3777 * Call the default completion handler with "fail" just 3778 * so upper levels are suitably notified about this. 3779 */ 3780 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3781 bf = bf_next; 3782 continue; 3783 } 3784 /* Give these the default completion handler */ 3785 bf->bf_comp = ath_tx_normal_comp; 3786 bf = TAILQ_NEXT(bf, bf_list); 3787 } 3788 3789 /* The caller is required to pause the TID */ 3790#if 0 3791 /* Pause the TID */ 3792 ath_tx_tid_pause(sc, atid); 3793#endif 3794 3795 /* 3796 * Calculate what hardware-queued frames exist based 3797 * on the current BAW size. Ie, what frames have been 3798 * added to the TX hardware queue for this TID but 3799 * not yet ACKed. 3800 */ 3801 tap = ath_tx_get_tx_tid(an, tid); 3802 /* Need the lock - fiddling with BAW */ 3803 while (atid->baw_head != atid->baw_tail) { 3804 if (atid->tx_buf[atid->baw_head]) { 3805 atid->incomp++; 3806 atid->cleanup_inprogress = 1; 3807 atid->tx_buf[atid->baw_head] = NULL; 3808 } 3809 INCR(atid->baw_head, ATH_TID_MAX_BUFS); 3810 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 3811 } 3812 3813 /* 3814 * If cleanup is required, defer TID scheduling 3815 * until all the HW queued packets have been 3816 * sent. 3817 */ 3818 if (! atid->cleanup_inprogress) 3819 ath_tx_tid_resume(sc, atid); 3820 3821 if (atid->cleanup_inprogress) 3822 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3823 "%s: TID %d: cleanup needed: %d packets\n", 3824 __func__, tid, atid->incomp); 3825 ATH_TX_UNLOCK(sc); 3826 3827 /* Handle completing frames and fail them */ 3828 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3829 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3830 ath_tx_default_comp(sc, bf, 1); 3831 } 3832} 3833 3834static struct ath_buf * 3835ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an, 3836 struct ath_tid *tid, struct ath_buf *bf) 3837{ 3838 struct ath_buf *nbf; 3839 int error; 3840 3841 nbf = ath_buf_clone(sc, bf); 3842 3843#if 0 3844 device_printf(sc->sc_dev, "%s: ATH_BUF_BUSY; cloning\n", 3845 __func__); 3846#endif 3847 3848 if (nbf == NULL) { 3849 /* Failed to clone */ 3850 device_printf(sc->sc_dev, 3851 "%s: failed to clone a busy buffer\n", 3852 __func__); 3853 return NULL; 3854 } 3855 3856 /* Setup the dma for the new buffer */ 3857 error = ath_tx_dmasetup(sc, nbf, nbf->bf_m); 3858 if (error != 0) { 3859 device_printf(sc->sc_dev, 3860 "%s: failed to setup dma for clone\n", 3861 __func__); 3862 /* 3863 * Put this at the head of the list, not tail; 3864 * that way it doesn't interfere with the 3865 * busy buffer logic (which uses the tail of 3866 * the list.) 3867 */ 3868 ATH_TXBUF_LOCK(sc); 3869 ath_returnbuf_head(sc, nbf); 3870 ATH_TXBUF_UNLOCK(sc); 3871 return NULL; 3872 } 3873 3874 /* Update BAW if required, before we free the original buf */ 3875 if (bf->bf_state.bfs_dobaw) 3876 ath_tx_switch_baw_buf(sc, an, tid, bf, nbf); 3877 3878 /* Free current buffer; return the older buffer */ 3879 bf->bf_m = NULL; 3880 bf->bf_node = NULL; 3881 ath_freebuf(sc, bf); 3882 3883 return nbf; 3884} 3885 3886/* 3887 * Handle retrying an unaggregate frame in an aggregate 3888 * session. 3889 * 3890 * If too many retries occur, pause the TID, wait for 3891 * any further retransmits (as there's no reason why 3892 * non-aggregate frames in an aggregate session are 3893 * transmitted in-order; they just have to be in-BAW) 3894 * and then queue a BAR. 3895 */ 3896static void 3897ath_tx_aggr_retry_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3898{ 3899 struct ieee80211_node *ni = bf->bf_node; 3900 struct ath_node *an = ATH_NODE(ni); 3901 int tid = bf->bf_state.bfs_tid; 3902 struct ath_tid *atid = &an->an_tid[tid]; 3903 struct ieee80211_tx_ampdu *tap; 3904 3905 ATH_TX_LOCK(sc); 3906 3907 tap = ath_tx_get_tx_tid(an, tid); 3908 3909 /* 3910 * If the buffer is marked as busy, we can't directly 3911 * reuse it. Instead, try to clone the buffer. 3912 * If the clone is successful, recycle the old buffer. 3913 * If the clone is unsuccessful, set bfs_retries to max 3914 * to force the next bit of code to free the buffer 3915 * for us. 3916 */ 3917 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3918 (bf->bf_flags & ATH_BUF_BUSY)) { 3919 struct ath_buf *nbf; 3920 nbf = ath_tx_retry_clone(sc, an, atid, bf); 3921 if (nbf) 3922 /* bf has been freed at this point */ 3923 bf = nbf; 3924 else 3925 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3926 } 3927 3928 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3929 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3930 "%s: exceeded retries; seqno %d\n", 3931 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3932 sc->sc_stats.ast_tx_swretrymax++; 3933 3934 /* Update BAW anyway */ 3935 if (bf->bf_state.bfs_dobaw) { 3936 ath_tx_update_baw(sc, an, atid, bf); 3937 if (! bf->bf_state.bfs_addedbaw) 3938 device_printf(sc->sc_dev, 3939 "%s: wasn't added: seqno %d\n", 3940 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3941 } 3942 bf->bf_state.bfs_dobaw = 0; 3943 3944 /* Suspend the TX queue and get ready to send the BAR */ 3945 ath_tx_tid_bar_suspend(sc, atid); 3946 3947 /* Send the BAR if there are no other frames waiting */ 3948 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3949 ath_tx_tid_bar_tx(sc, atid); 3950 3951 ATH_TX_UNLOCK(sc); 3952 3953 /* Free buffer, bf is free after this call */ 3954 ath_tx_default_comp(sc, bf, 0); 3955 return; 3956 } 3957 3958 /* 3959 * This increments the retry counter as well as 3960 * sets the retry flag in the ath_buf and packet 3961 * body. 3962 */ 3963 ath_tx_set_retry(sc, bf); 3964 sc->sc_stats.ast_tx_swretries++; 3965 3966 /* 3967 * Insert this at the head of the queue, so it's 3968 * retried before any current/subsequent frames. 3969 */ 3970 ATH_TID_INSERT_HEAD(atid, bf, bf_list); 3971 ath_tx_tid_sched(sc, atid); 3972 /* Send the BAR if there are no other frames waiting */ 3973 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3974 ath_tx_tid_bar_tx(sc, atid); 3975 3976 ATH_TX_UNLOCK(sc); 3977} 3978 3979/* 3980 * Common code for aggregate excessive retry/subframe retry. 3981 * If retrying, queues buffers to bf_q. If not, frees the 3982 * buffers. 3983 * 3984 * XXX should unify this with ath_tx_aggr_retry_unaggr() 3985 */ 3986static int 3987ath_tx_retry_subframe(struct ath_softc *sc, struct ath_buf *bf, 3988 ath_bufhead *bf_q) 3989{ 3990 struct ieee80211_node *ni = bf->bf_node; 3991 struct ath_node *an = ATH_NODE(ni); 3992 int tid = bf->bf_state.bfs_tid; 3993 struct ath_tid *atid = &an->an_tid[tid]; 3994 3995 ATH_TX_LOCK_ASSERT(sc); 3996 3997 /* XXX clr11naggr should be done for all subframes */ 3998 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 3999 ath_hal_set11nburstduration(sc->sc_ah, bf->bf_desc, 0); 4000 4001 /* ath_hal_set11n_virtualmorefrag(sc->sc_ah, bf->bf_desc, 0); */ 4002 4003 /* 4004 * If the buffer is marked as busy, we can't directly 4005 * reuse it. Instead, try to clone the buffer. 4006 * If the clone is successful, recycle the old buffer. 4007 * If the clone is unsuccessful, set bfs_retries to max 4008 * to force the next bit of code to free the buffer 4009 * for us. 4010 */ 4011 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 4012 (bf->bf_flags & ATH_BUF_BUSY)) { 4013 struct ath_buf *nbf; 4014 nbf = ath_tx_retry_clone(sc, an, atid, bf); 4015 if (nbf) 4016 /* bf has been freed at this point */ 4017 bf = nbf; 4018 else 4019 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 4020 } 4021 4022 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 4023 sc->sc_stats.ast_tx_swretrymax++; 4024 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 4025 "%s: max retries: seqno %d\n", 4026 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4027 ath_tx_update_baw(sc, an, atid, bf); 4028 if (! bf->bf_state.bfs_addedbaw) 4029 device_printf(sc->sc_dev, 4030 "%s: wasn't added: seqno %d\n", 4031 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4032 bf->bf_state.bfs_dobaw = 0; 4033 return 1; 4034 } 4035 4036 ath_tx_set_retry(sc, bf); 4037 sc->sc_stats.ast_tx_swretries++; 4038 bf->bf_next = NULL; /* Just to make sure */ 4039 4040 /* Clear the aggregate state */ 4041 bf->bf_state.bfs_aggr = 0; 4042 bf->bf_state.bfs_ndelim = 0; /* ??? needed? */ 4043 bf->bf_state.bfs_nframes = 1; 4044 4045 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 4046 return 0; 4047} 4048 4049/* 4050 * error pkt completion for an aggregate destination 4051 */ 4052static void 4053ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first, 4054 struct ath_tid *tid) 4055{ 4056 struct ieee80211_node *ni = bf_first->bf_node; 4057 struct ath_node *an = ATH_NODE(ni); 4058 struct ath_buf *bf_next, *bf; 4059 ath_bufhead bf_q; 4060 int drops = 0; 4061 struct ieee80211_tx_ampdu *tap; 4062 ath_bufhead bf_cq; 4063 4064 TAILQ_INIT(&bf_q); 4065 TAILQ_INIT(&bf_cq); 4066 4067 /* 4068 * Update rate control - all frames have failed. 4069 * 4070 * XXX use the length in the first frame in the series; 4071 * XXX just so things are consistent for now. 4072 */ 4073 ath_tx_update_ratectrl(sc, ni, bf_first->bf_state.bfs_rc, 4074 &bf_first->bf_status.ds_txstat, 4075 bf_first->bf_state.bfs_pktlen, 4076 bf_first->bf_state.bfs_nframes, bf_first->bf_state.bfs_nframes); 4077 4078 ATH_TX_LOCK(sc); 4079 tap = ath_tx_get_tx_tid(an, tid->tid); 4080 sc->sc_stats.ast_tx_aggr_failall++; 4081 4082 /* Retry all subframes */ 4083 bf = bf_first; 4084 while (bf) { 4085 bf_next = bf->bf_next; 4086 bf->bf_next = NULL; /* Remove it from the aggr list */ 4087 sc->sc_stats.ast_tx_aggr_fail++; 4088 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 4089 drops++; 4090 bf->bf_next = NULL; 4091 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 4092 } 4093 bf = bf_next; 4094 } 4095 4096 /* Prepend all frames to the beginning of the queue */ 4097 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 4098 TAILQ_REMOVE(&bf_q, bf, bf_list); 4099 ATH_TID_INSERT_HEAD(tid, bf, bf_list); 4100 } 4101 4102 /* 4103 * Schedule the TID to be re-tried. 4104 */ 4105 ath_tx_tid_sched(sc, tid); 4106 4107 /* 4108 * send bar if we dropped any frames 4109 * 4110 * Keep the txq lock held for now, as we need to ensure 4111 * that ni_txseqs[] is consistent (as it's being updated 4112 * in the ifnet TX context or raw TX context.) 4113 */ 4114 if (drops) { 4115 /* Suspend the TX queue and get ready to send the BAR */ 4116 ath_tx_tid_bar_suspend(sc, tid); 4117 } 4118 4119 /* 4120 * Send BAR if required 4121 */ 4122 if (ath_tx_tid_bar_tx_ready(sc, tid)) 4123 ath_tx_tid_bar_tx(sc, tid); 4124 4125 ATH_TX_UNLOCK(sc); 4126 4127 /* Complete frames which errored out */ 4128 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 4129 TAILQ_REMOVE(&bf_cq, bf, bf_list); 4130 ath_tx_default_comp(sc, bf, 0); 4131 } 4132} 4133 4134/* 4135 * Handle clean-up of packets from an aggregate list. 4136 * 4137 * There's no need to update the BAW here - the session is being 4138 * torn down. 4139 */ 4140static void 4141ath_tx_comp_cleanup_aggr(struct ath_softc *sc, struct ath_buf *bf_first) 4142{ 4143 struct ath_buf *bf, *bf_next; 4144 struct ieee80211_node *ni = bf_first->bf_node; 4145 struct ath_node *an = ATH_NODE(ni); 4146 int tid = bf_first->bf_state.bfs_tid; 4147 struct ath_tid *atid = &an->an_tid[tid]; 4148 4149 ATH_TX_LOCK(sc); 4150 4151 /* update incomp */ 4152 bf = bf_first; 4153 while (bf) { 4154 atid->incomp--; 4155 bf = bf->bf_next; 4156 } 4157 4158 if (atid->incomp == 0) { 4159 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4160 "%s: TID %d: cleaned up! resume!\n", 4161 __func__, tid); 4162 atid->cleanup_inprogress = 0; 4163 ath_tx_tid_resume(sc, atid); 4164 } 4165 4166 /* Send BAR if required */ 4167 /* XXX why would we send a BAR when transitioning to non-aggregation? */ 4168 /* 4169 * XXX TODO: we should likely just tear down the BAR state here, 4170 * rather than sending a BAR. 4171 */ 4172 if (ath_tx_tid_bar_tx_ready(sc, atid)) 4173 ath_tx_tid_bar_tx(sc, atid); 4174 4175 ATH_TX_UNLOCK(sc); 4176 4177 /* Handle frame completion */ 4178 bf = bf_first; 4179 while (bf) { 4180 bf_next = bf->bf_next; 4181 ath_tx_default_comp(sc, bf, 1); 4182 bf = bf_next; 4183 } 4184} 4185 4186/* 4187 * Handle completion of an set of aggregate frames. 4188 * 4189 * Note: the completion handler is the last descriptor in the aggregate, 4190 * not the last descriptor in the first frame. 4191 */ 4192static void 4193ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first, 4194 int fail) 4195{ 4196 //struct ath_desc *ds = bf->bf_lastds; 4197 struct ieee80211_node *ni = bf_first->bf_node; 4198 struct ath_node *an = ATH_NODE(ni); 4199 int tid = bf_first->bf_state.bfs_tid; 4200 struct ath_tid *atid = &an->an_tid[tid]; 4201 struct ath_tx_status ts; 4202 struct ieee80211_tx_ampdu *tap; 4203 ath_bufhead bf_q; 4204 ath_bufhead bf_cq; 4205 int seq_st, tx_ok; 4206 int hasba, isaggr; 4207 uint32_t ba[2]; 4208 struct ath_buf *bf, *bf_next; 4209 int ba_index; 4210 int drops = 0; 4211 int nframes = 0, nbad = 0, nf; 4212 int pktlen; 4213 /* XXX there's too much on the stack? */ 4214 struct ath_rc_series rc[ATH_RC_NUM]; 4215 int txseq; 4216 4217 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: called; hwq_depth=%d\n", 4218 __func__, atid->hwq_depth); 4219 4220 /* 4221 * Take a copy; this may be needed -after- bf_first 4222 * has been completed and freed. 4223 */ 4224 ts = bf_first->bf_status.ds_txstat; 4225 4226 TAILQ_INIT(&bf_q); 4227 TAILQ_INIT(&bf_cq); 4228 4229 /* The TID state is kept behind the TXQ lock */ 4230 ATH_TX_LOCK(sc); 4231 4232 atid->hwq_depth--; 4233 if (atid->hwq_depth < 0) 4234 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 4235 __func__, atid->hwq_depth); 4236 4237 /* 4238 * If the TID is filtered, handle completing the filter 4239 * transition before potentially kicking it to the cleanup 4240 * function. 4241 * 4242 * XXX this is duplicate work, ew. 4243 */ 4244 if (atid->isfiltered) 4245 ath_tx_tid_filt_comp_complete(sc, atid); 4246 4247 /* 4248 * Punt cleanup to the relevant function, not our problem now 4249 */ 4250 if (atid->cleanup_inprogress) { 4251 if (atid->isfiltered) 4252 device_printf(sc->sc_dev, 4253 "%s: isfiltered=1, normal_comp?\n", 4254 __func__); 4255 ATH_TX_UNLOCK(sc); 4256 ath_tx_comp_cleanup_aggr(sc, bf_first); 4257 return; 4258 } 4259 4260 /* 4261 * If the frame is filtered, transition to filtered frame 4262 * mode and add this to the filtered frame list. 4263 * 4264 * XXX TODO: figure out how this interoperates with 4265 * BAR, pause and cleanup states. 4266 */ 4267 if ((ts.ts_status & HAL_TXERR_FILT) || 4268 (ts.ts_status != 0 && atid->isfiltered)) { 4269 if (fail != 0) 4270 device_printf(sc->sc_dev, 4271 "%s: isfiltered=1, fail=%d\n", __func__, fail); 4272 ath_tx_tid_filt_comp_aggr(sc, atid, bf_first, &bf_cq); 4273 4274 /* Remove from BAW */ 4275 TAILQ_FOREACH_SAFE(bf, &bf_cq, bf_list, bf_next) { 4276 if (bf->bf_state.bfs_addedbaw) 4277 drops++; 4278 if (bf->bf_state.bfs_dobaw) { 4279 ath_tx_update_baw(sc, an, atid, bf); 4280 if (! bf->bf_state.bfs_addedbaw) 4281 device_printf(sc->sc_dev, 4282 "%s: wasn't added: seqno %d\n", 4283 __func__, 4284 SEQNO(bf->bf_state.bfs_seqno)); 4285 } 4286 bf->bf_state.bfs_dobaw = 0; 4287 } 4288 /* 4289 * If any intermediate frames in the BAW were dropped when 4290 * handling filtering things, send a BAR. 4291 */ 4292 if (drops) 4293 ath_tx_tid_bar_suspend(sc, atid); 4294 4295 /* 4296 * Finish up by sending a BAR if required and freeing 4297 * the frames outside of the TX lock. 4298 */ 4299 goto finish_send_bar; 4300 } 4301 4302 /* 4303 * XXX for now, use the first frame in the aggregate for 4304 * XXX rate control completion; it's at least consistent. 4305 */ 4306 pktlen = bf_first->bf_state.bfs_pktlen; 4307 4308 /* 4309 * Handle errors first! 4310 * 4311 * Here, handle _any_ error as a "exceeded retries" error. 4312 * Later on (when filtered frames are to be specially handled) 4313 * it'll have to be expanded. 4314 */ 4315#if 0 4316 if (ts.ts_status & HAL_TXERR_XRETRY) { 4317#endif 4318 if (ts.ts_status != 0) { 4319 ATH_TX_UNLOCK(sc); 4320 ath_tx_comp_aggr_error(sc, bf_first, atid); 4321 return; 4322 } 4323 4324 tap = ath_tx_get_tx_tid(an, tid); 4325 4326 /* 4327 * extract starting sequence and block-ack bitmap 4328 */ 4329 /* XXX endian-ness of seq_st, ba? */ 4330 seq_st = ts.ts_seqnum; 4331 hasba = !! (ts.ts_flags & HAL_TX_BA); 4332 tx_ok = (ts.ts_status == 0); 4333 isaggr = bf_first->bf_state.bfs_aggr; 4334 ba[0] = ts.ts_ba_low; 4335 ba[1] = ts.ts_ba_high; 4336 4337 /* 4338 * Copy the TX completion status and the rate control 4339 * series from the first descriptor, as it may be freed 4340 * before the rate control code can get its grubby fingers 4341 * into things. 4342 */ 4343 memcpy(rc, bf_first->bf_state.bfs_rc, sizeof(rc)); 4344 4345 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4346 "%s: txa_start=%d, tx_ok=%d, status=%.8x, flags=%.8x, " 4347 "isaggr=%d, seq_st=%d, hasba=%d, ba=%.8x, %.8x\n", 4348 __func__, tap->txa_start, tx_ok, ts.ts_status, ts.ts_flags, 4349 isaggr, seq_st, hasba, ba[0], ba[1]); 4350 4351 /* 4352 * The reference driver doesn't do this; it simply ignores 4353 * this check in its entirety. 4354 * 4355 * I've seen this occur when using iperf to send traffic 4356 * out tid 1 - the aggregate frames are all marked as TID 1, 4357 * but the TXSTATUS has TID=0. So, let's just ignore this 4358 * check. 4359 */ 4360#if 0 4361 /* Occasionally, the MAC sends a tx status for the wrong TID. */ 4362 if (tid != ts.ts_tid) { 4363 device_printf(sc->sc_dev, "%s: tid %d != hw tid %d\n", 4364 __func__, tid, ts.ts_tid); 4365 tx_ok = 0; 4366 } 4367#endif 4368 4369 /* AR5416 BA bug; this requires an interface reset */ 4370 if (isaggr && tx_ok && (! hasba)) { 4371 device_printf(sc->sc_dev, 4372 "%s: AR5416 bug: hasba=%d; txok=%d, isaggr=%d, " 4373 "seq_st=%d\n", 4374 __func__, hasba, tx_ok, isaggr, seq_st); 4375 /* XXX TODO: schedule an interface reset */ 4376#ifdef ATH_DEBUG 4377 ath_printtxbuf(sc, bf_first, 4378 sc->sc_ac2q[atid->ac]->axq_qnum, 0, 0); 4379#endif 4380 } 4381 4382 /* 4383 * Walk the list of frames, figure out which ones were correctly 4384 * sent and which weren't. 4385 */ 4386 bf = bf_first; 4387 nf = bf_first->bf_state.bfs_nframes; 4388 4389 /* bf_first is going to be invalid once this list is walked */ 4390 bf_first = NULL; 4391 4392 /* 4393 * Walk the list of completed frames and determine 4394 * which need to be completed and which need to be 4395 * retransmitted. 4396 * 4397 * For completed frames, the completion functions need 4398 * to be called at the end of this function as the last 4399 * node reference may free the node. 4400 * 4401 * Finally, since the TXQ lock can't be held during the 4402 * completion callback (to avoid lock recursion), 4403 * the completion calls have to be done outside of the 4404 * lock. 4405 */ 4406 while (bf) { 4407 nframes++; 4408 ba_index = ATH_BA_INDEX(seq_st, 4409 SEQNO(bf->bf_state.bfs_seqno)); 4410 bf_next = bf->bf_next; 4411 bf->bf_next = NULL; /* Remove it from the aggr list */ 4412 4413 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4414 "%s: checking bf=%p seqno=%d; ack=%d\n", 4415 __func__, bf, SEQNO(bf->bf_state.bfs_seqno), 4416 ATH_BA_ISSET(ba, ba_index)); 4417 4418 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) { 4419 sc->sc_stats.ast_tx_aggr_ok++; 4420 ath_tx_update_baw(sc, an, atid, bf); 4421 bf->bf_state.bfs_dobaw = 0; 4422 if (! bf->bf_state.bfs_addedbaw) 4423 device_printf(sc->sc_dev, 4424 "%s: wasn't added: seqno %d\n", 4425 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4426 bf->bf_next = NULL; 4427 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 4428 } else { 4429 sc->sc_stats.ast_tx_aggr_fail++; 4430 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 4431 drops++; 4432 bf->bf_next = NULL; 4433 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 4434 } 4435 nbad++; 4436 } 4437 bf = bf_next; 4438 } 4439 4440 /* 4441 * Now that the BAW updates have been done, unlock 4442 * 4443 * txseq is grabbed before the lock is released so we 4444 * have a consistent view of what -was- in the BAW. 4445 * Anything after this point will not yet have been 4446 * TXed. 4447 */ 4448 txseq = tap->txa_start; 4449 ATH_TX_UNLOCK(sc); 4450 4451 if (nframes != nf) 4452 device_printf(sc->sc_dev, 4453 "%s: num frames seen=%d; bf nframes=%d\n", 4454 __func__, nframes, nf); 4455 4456 /* 4457 * Now we know how many frames were bad, call the rate 4458 * control code. 4459 */ 4460 if (fail == 0) 4461 ath_tx_update_ratectrl(sc, ni, rc, &ts, pktlen, nframes, 4462 nbad); 4463 4464 /* 4465 * send bar if we dropped any frames 4466 */ 4467 if (drops) { 4468 /* Suspend the TX queue and get ready to send the BAR */ 4469 ATH_TX_LOCK(sc); 4470 ath_tx_tid_bar_suspend(sc, atid); 4471 ATH_TX_UNLOCK(sc); 4472 } 4473 4474 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4475 "%s: txa_start now %d\n", __func__, tap->txa_start); 4476 4477 ATH_TX_LOCK(sc); 4478 4479 /* Prepend all frames to the beginning of the queue */ 4480 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 4481 TAILQ_REMOVE(&bf_q, bf, bf_list); 4482 ATH_TID_INSERT_HEAD(atid, bf, bf_list); 4483 } 4484 4485 /* 4486 * Reschedule to grab some further frames. 4487 */ 4488 ath_tx_tid_sched(sc, atid); 4489 4490 /* 4491 * If the queue is filtered, re-schedule as required. 4492 * 4493 * This is required as there may be a subsequent TX descriptor 4494 * for this end-node that has CLRDMASK set, so it's quite possible 4495 * that a filtered frame will be followed by a non-filtered 4496 * (complete or otherwise) frame. 4497 * 4498 * XXX should we do this before we complete the frame? 4499 */ 4500 if (atid->isfiltered) 4501 ath_tx_tid_filt_comp_complete(sc, atid); 4502 4503finish_send_bar: 4504 4505 /* 4506 * Send BAR if required 4507 */ 4508 if (ath_tx_tid_bar_tx_ready(sc, atid)) 4509 ath_tx_tid_bar_tx(sc, atid); 4510 4511 ATH_TX_UNLOCK(sc); 4512 4513 /* Do deferred completion */ 4514 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 4515 TAILQ_REMOVE(&bf_cq, bf, bf_list); 4516 ath_tx_default_comp(sc, bf, 0); 4517 } 4518} 4519 4520/* 4521 * Handle completion of unaggregated frames in an ADDBA 4522 * session. 4523 * 4524 * Fail is set to 1 if the entry is being freed via a call to 4525 * ath_tx_draintxq(). 4526 */ 4527static void 4528ath_tx_aggr_comp_unaggr(struct ath_softc *sc, struct ath_buf *bf, int fail) 4529{ 4530 struct ieee80211_node *ni = bf->bf_node; 4531 struct ath_node *an = ATH_NODE(ni); 4532 int tid = bf->bf_state.bfs_tid; 4533 struct ath_tid *atid = &an->an_tid[tid]; 4534 struct ath_tx_status ts; 4535 int drops = 0; 4536 4537 /* 4538 * Take a copy of this; filtering/cloning the frame may free the 4539 * bf pointer. 4540 */ 4541 ts = bf->bf_status.ds_txstat; 4542 4543 /* 4544 * Update rate control status here, before we possibly 4545 * punt to retry or cleanup. 4546 * 4547 * Do it outside of the TXQ lock. 4548 */ 4549 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 4550 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 4551 &bf->bf_status.ds_txstat, 4552 bf->bf_state.bfs_pktlen, 4553 1, (ts.ts_status == 0) ? 0 : 1); 4554 4555 /* 4556 * This is called early so atid->hwq_depth can be tracked. 4557 * This unfortunately means that it's released and regrabbed 4558 * during retry and cleanup. That's rather inefficient. 4559 */ 4560 ATH_TX_LOCK(sc); 4561 4562 if (tid == IEEE80211_NONQOS_TID) 4563 device_printf(sc->sc_dev, "%s: TID=16!\n", __func__); 4564 4565 DPRINTF(sc, ATH_DEBUG_SW_TX, 4566 "%s: bf=%p: tid=%d, hwq_depth=%d, seqno=%d\n", 4567 __func__, bf, bf->bf_state.bfs_tid, atid->hwq_depth, 4568 SEQNO(bf->bf_state.bfs_seqno)); 4569 4570 atid->hwq_depth--; 4571 if (atid->hwq_depth < 0) 4572 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 4573 __func__, atid->hwq_depth); 4574 4575 /* 4576 * If the TID is filtered, handle completing the filter 4577 * transition before potentially kicking it to the cleanup 4578 * function. 4579 */ 4580 if (atid->isfiltered) 4581 ath_tx_tid_filt_comp_complete(sc, atid); 4582 4583 /* 4584 * If a cleanup is in progress, punt to comp_cleanup; 4585 * rather than handling it here. It's thus their 4586 * responsibility to clean up, call the completion 4587 * function in net80211, etc. 4588 */ 4589 if (atid->cleanup_inprogress) { 4590 if (atid->isfiltered) 4591 device_printf(sc->sc_dev, 4592 "%s: isfiltered=1, normal_comp?\n", 4593 __func__); 4594 ATH_TX_UNLOCK(sc); 4595 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: cleanup_unaggr\n", 4596 __func__); 4597 ath_tx_comp_cleanup_unaggr(sc, bf); 4598 return; 4599 } 4600 4601 /* 4602 * XXX TODO: how does cleanup, BAR and filtered frame handling 4603 * overlap? 4604 * 4605 * If the frame is filtered OR if it's any failure but 4606 * the TID is filtered, the frame must be added to the 4607 * filtered frame list. 4608 * 4609 * However - a busy buffer can't be added to the filtered 4610 * list as it will end up being recycled without having 4611 * been made available for the hardware. 4612 */ 4613 if ((ts.ts_status & HAL_TXERR_FILT) || 4614 (ts.ts_status != 0 && atid->isfiltered)) { 4615 int freeframe; 4616 4617 if (fail != 0) 4618 device_printf(sc->sc_dev, 4619 "%s: isfiltered=1, fail=%d\n", 4620 __func__, 4621 fail); 4622 freeframe = ath_tx_tid_filt_comp_single(sc, atid, bf); 4623 if (freeframe) { 4624 /* Remove from BAW */ 4625 if (bf->bf_state.bfs_addedbaw) 4626 drops++; 4627 if (bf->bf_state.bfs_dobaw) { 4628 ath_tx_update_baw(sc, an, atid, bf); 4629 if (! bf->bf_state.bfs_addedbaw) 4630 device_printf(sc->sc_dev, 4631 "%s: wasn't added: seqno %d\n", 4632 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4633 } 4634 bf->bf_state.bfs_dobaw = 0; 4635 } 4636 4637 /* 4638 * If the frame couldn't be filtered, treat it as a drop and 4639 * prepare to send a BAR. 4640 */ 4641 if (freeframe && drops) 4642 ath_tx_tid_bar_suspend(sc, atid); 4643 4644 /* 4645 * Send BAR if required 4646 */ 4647 if (ath_tx_tid_bar_tx_ready(sc, atid)) 4648 ath_tx_tid_bar_tx(sc, atid); 4649 4650 ATH_TX_UNLOCK(sc); 4651 /* 4652 * If freeframe is set, then the frame couldn't be 4653 * cloned and bf is still valid. Just complete/free it. 4654 */ 4655 if (freeframe) 4656 ath_tx_default_comp(sc, bf, fail); 4657 4658 4659 return; 4660 } 4661 /* 4662 * Don't bother with the retry check if all frames 4663 * are being failed (eg during queue deletion.) 4664 */ 4665#if 0 4666 if (fail == 0 && ts->ts_status & HAL_TXERR_XRETRY) { 4667#endif 4668 if (fail == 0 && ts.ts_status != 0) { 4669 ATH_TX_UNLOCK(sc); 4670 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: retry_unaggr\n", 4671 __func__); 4672 ath_tx_aggr_retry_unaggr(sc, bf); 4673 return; 4674 } 4675 4676 /* Success? Complete */ 4677 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: TID=%d, seqno %d\n", 4678 __func__, tid, SEQNO(bf->bf_state.bfs_seqno)); 4679 if (bf->bf_state.bfs_dobaw) { 4680 ath_tx_update_baw(sc, an, atid, bf); 4681 bf->bf_state.bfs_dobaw = 0; 4682 if (! bf->bf_state.bfs_addedbaw) 4683 device_printf(sc->sc_dev, 4684 "%s: wasn't added: seqno %d\n", 4685 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4686 } 4687 4688 /* 4689 * If the queue is filtered, re-schedule as required. 4690 * 4691 * This is required as there may be a subsequent TX descriptor 4692 * for this end-node that has CLRDMASK set, so it's quite possible 4693 * that a filtered frame will be followed by a non-filtered 4694 * (complete or otherwise) frame. 4695 * 4696 * XXX should we do this before we complete the frame? 4697 */ 4698 if (atid->isfiltered) 4699 ath_tx_tid_filt_comp_complete(sc, atid); 4700 4701 /* 4702 * Send BAR if required 4703 */ 4704 if (ath_tx_tid_bar_tx_ready(sc, atid)) 4705 ath_tx_tid_bar_tx(sc, atid); 4706 4707 ATH_TX_UNLOCK(sc); 4708 4709 ath_tx_default_comp(sc, bf, fail); 4710 /* bf is freed at this point */ 4711} 4712 4713void 4714ath_tx_aggr_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 4715{ 4716 if (bf->bf_state.bfs_aggr) 4717 ath_tx_aggr_comp_aggr(sc, bf, fail); 4718 else 4719 ath_tx_aggr_comp_unaggr(sc, bf, fail); 4720} 4721 4722/* 4723 * Schedule some packets from the given node/TID to the hardware. 4724 * 4725 * This is the aggregate version. 4726 */ 4727void 4728ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an, 4729 struct ath_tid *tid) 4730{ 4731 struct ath_buf *bf; 4732 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 4733 struct ieee80211_tx_ampdu *tap; 4734 ATH_AGGR_STATUS status; 4735 ath_bufhead bf_q; 4736 4737 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d\n", __func__, tid->tid); 4738 ATH_TX_LOCK_ASSERT(sc); 4739 4740 tap = ath_tx_get_tx_tid(an, tid->tid); 4741 4742 if (tid->tid == IEEE80211_NONQOS_TID) 4743 device_printf(sc->sc_dev, "%s: called for TID=NONQOS_TID?\n", 4744 __func__); 4745 4746 for (;;) { 4747 status = ATH_AGGR_DONE; 4748 4749 /* 4750 * If the upper layer has paused the TID, don't 4751 * queue any further packets. 4752 * 4753 * This can also occur from the completion task because 4754 * of packet loss; but as its serialised with this code, 4755 * it won't "appear" half way through queuing packets. 4756 */ 4757 if (tid->paused) 4758 break; 4759 4760 bf = ATH_TID_FIRST(tid); 4761 if (bf == NULL) { 4762 break; 4763 } 4764 4765 /* 4766 * If the packet doesn't fall within the BAW (eg a NULL 4767 * data frame), schedule it directly; continue. 4768 */ 4769 if (! bf->bf_state.bfs_dobaw) { 4770 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4771 "%s: non-baw packet\n", 4772 __func__); 4773 ATH_TID_REMOVE(tid, bf, bf_list); 4774 4775 if (bf->bf_state.bfs_nframes > 1) 4776 device_printf(sc->sc_dev, 4777 "%s: aggr=%d, nframes=%d\n", 4778 __func__, 4779 bf->bf_state.bfs_aggr, 4780 bf->bf_state.bfs_nframes); 4781 4782 /* 4783 * This shouldn't happen - such frames shouldn't 4784 * ever have been queued as an aggregate in the 4785 * first place. However, make sure the fields 4786 * are correctly setup just to be totally sure. 4787 */ 4788 bf->bf_state.bfs_aggr = 0; 4789 bf->bf_state.bfs_nframes = 1; 4790 4791 /* Update CLRDMASK just before this frame is queued */ 4792 ath_tx_update_clrdmask(sc, tid, bf); 4793 4794 ath_tx_do_ratelookup(sc, bf); 4795 ath_tx_calc_duration(sc, bf); 4796 ath_tx_calc_protection(sc, bf); 4797 ath_tx_set_rtscts(sc, bf); 4798 ath_tx_rate_fill_rcflags(sc, bf); 4799 ath_tx_setds(sc, bf); 4800 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 4801 4802 sc->sc_aggr_stats.aggr_nonbaw_pkt++; 4803 4804 /* Queue the packet; continue */ 4805 goto queuepkt; 4806 } 4807 4808 TAILQ_INIT(&bf_q); 4809 4810 /* 4811 * Do a rate control lookup on the first frame in the 4812 * list. The rate control code needs that to occur 4813 * before it can determine whether to TX. 4814 * It's inaccurate because the rate control code doesn't 4815 * really "do" aggregate lookups, so it only considers 4816 * the size of the first frame. 4817 */ 4818 ath_tx_do_ratelookup(sc, bf); 4819 bf->bf_state.bfs_rc[3].rix = 0; 4820 bf->bf_state.bfs_rc[3].tries = 0; 4821 4822 ath_tx_calc_duration(sc, bf); 4823 ath_tx_calc_protection(sc, bf); 4824 4825 ath_tx_set_rtscts(sc, bf); 4826 ath_tx_rate_fill_rcflags(sc, bf); 4827 4828 status = ath_tx_form_aggr(sc, an, tid, &bf_q); 4829 4830 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4831 "%s: ath_tx_form_aggr() status=%d\n", __func__, status); 4832 4833 /* 4834 * No frames to be picked up - out of BAW 4835 */ 4836 if (TAILQ_EMPTY(&bf_q)) 4837 break; 4838 4839 /* 4840 * This assumes that the descriptor list in the ath_bufhead 4841 * are already linked together via bf_next pointers. 4842 */ 4843 bf = TAILQ_FIRST(&bf_q); 4844 4845 if (status == ATH_AGGR_8K_LIMITED) 4846 sc->sc_aggr_stats.aggr_rts_aggr_limited++; 4847 4848 /* 4849 * If it's the only frame send as non-aggregate 4850 * assume that ath_tx_form_aggr() has checked 4851 * whether it's in the BAW and added it appropriately. 4852 */ 4853 if (bf->bf_state.bfs_nframes == 1) { 4854 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4855 "%s: single-frame aggregate\n", __func__); 4856 4857 /* Update CLRDMASK just before this frame is queued */ 4858 ath_tx_update_clrdmask(sc, tid, bf); 4859 4860 bf->bf_state.bfs_aggr = 0; 4861 bf->bf_state.bfs_ndelim = 0; 4862 ath_tx_setds(sc, bf); 4863 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 4864 if (status == ATH_AGGR_BAW_CLOSED) 4865 sc->sc_aggr_stats.aggr_baw_closed_single_pkt++; 4866 else 4867 sc->sc_aggr_stats.aggr_single_pkt++; 4868 } else { 4869 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4870 "%s: multi-frame aggregate: %d frames, " 4871 "length %d\n", 4872 __func__, bf->bf_state.bfs_nframes, 4873 bf->bf_state.bfs_al); 4874 bf->bf_state.bfs_aggr = 1; 4875 sc->sc_aggr_stats.aggr_pkts[bf->bf_state.bfs_nframes]++; 4876 sc->sc_aggr_stats.aggr_aggr_pkt++; 4877 4878 /* Update CLRDMASK just before this frame is queued */ 4879 ath_tx_update_clrdmask(sc, tid, bf); 4880 4881 /* 4882 * Calculate the duration/protection as required. 4883 */ 4884 ath_tx_calc_duration(sc, bf); 4885 ath_tx_calc_protection(sc, bf); 4886 4887 /* 4888 * Update the rate and rtscts information based on the 4889 * rate decision made by the rate control code; 4890 * the first frame in the aggregate needs it. 4891 */ 4892 ath_tx_set_rtscts(sc, bf); 4893 4894 /* 4895 * Setup the relevant descriptor fields 4896 * for aggregation. The first descriptor 4897 * already points to the rest in the chain. 4898 */ 4899 ath_tx_setds_11n(sc, bf); 4900 4901 } 4902 queuepkt: 4903 /* Set completion handler, multi-frame aggregate or not */ 4904 bf->bf_comp = ath_tx_aggr_comp; 4905 4906 if (bf->bf_state.bfs_tid == IEEE80211_NONQOS_TID) 4907 device_printf(sc->sc_dev, "%s: TID=16?\n", __func__); 4908 4909 /* Punt to txq */ 4910 ath_tx_handoff(sc, txq, bf); 4911 4912 /* Track outstanding buffer count to hardware */ 4913 /* aggregates are "one" buffer */ 4914 tid->hwq_depth++; 4915 4916 /* 4917 * Break out if ath_tx_form_aggr() indicated 4918 * there can't be any further progress (eg BAW is full.) 4919 * Checking for an empty txq is done above. 4920 * 4921 * XXX locking on txq here? 4922 */ 4923 if (txq->axq_aggr_depth >= sc->sc_hwq_limit || 4924 status == ATH_AGGR_BAW_CLOSED) 4925 break; 4926 } 4927} 4928 4929/* 4930 * Schedule some packets from the given node/TID to the hardware. 4931 */ 4932void 4933ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an, 4934 struct ath_tid *tid) 4935{ 4936 struct ath_buf *bf; 4937 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 4938 4939 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: node %p: TID %d: called\n", 4940 __func__, an, tid->tid); 4941 4942 ATH_TX_LOCK_ASSERT(sc); 4943 4944 /* Check - is AMPDU pending or running? then print out something */ 4945 if (ath_tx_ampdu_pending(sc, an, tid->tid)) 4946 device_printf(sc->sc_dev, "%s: tid=%d, ampdu pending?\n", 4947 __func__, tid->tid); 4948 if (ath_tx_ampdu_running(sc, an, tid->tid)) 4949 device_printf(sc->sc_dev, "%s: tid=%d, ampdu running?\n", 4950 __func__, tid->tid); 4951 4952 for (;;) { 4953 4954 /* 4955 * If the upper layers have paused the TID, don't 4956 * queue any further packets. 4957 */ 4958 if (tid->paused) 4959 break; 4960 4961 bf = ATH_TID_FIRST(tid); 4962 if (bf == NULL) { 4963 break; 4964 } 4965 4966 ATH_TID_REMOVE(tid, bf, bf_list); 4967 4968 /* Sanity check! */ 4969 if (tid->tid != bf->bf_state.bfs_tid) { 4970 device_printf(sc->sc_dev, "%s: bfs_tid %d !=" 4971 " tid %d\n", 4972 __func__, bf->bf_state.bfs_tid, tid->tid); 4973 } 4974 /* Normal completion handler */ 4975 bf->bf_comp = ath_tx_normal_comp; 4976 4977 /* 4978 * Override this for now, until the non-aggregate 4979 * completion handler correctly handles software retransmits. 4980 */ 4981 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 4982 4983 /* Update CLRDMASK just before this frame is queued */ 4984 ath_tx_update_clrdmask(sc, tid, bf); 4985 4986 /* Program descriptors + rate control */ 4987 ath_tx_do_ratelookup(sc, bf); 4988 ath_tx_calc_duration(sc, bf); 4989 ath_tx_calc_protection(sc, bf); 4990 ath_tx_set_rtscts(sc, bf); 4991 ath_tx_rate_fill_rcflags(sc, bf); 4992 ath_tx_setds(sc, bf); 4993 4994 /* Track outstanding buffer count to hardware */ 4995 /* aggregates are "one" buffer */ 4996 tid->hwq_depth++; 4997 4998 /* Punt to hardware or software txq */ 4999 ath_tx_handoff(sc, txq, bf); 5000 } 5001} 5002 5003/* 5004 * Schedule some packets to the given hardware queue. 5005 * 5006 * This function walks the list of TIDs (ie, ath_node TIDs 5007 * with queued traffic) and attempts to schedule traffic 5008 * from them. 5009 * 5010 * TID scheduling is implemented as a FIFO, with TIDs being 5011 * added to the end of the queue after some frames have been 5012 * scheduled. 5013 */ 5014void 5015ath_txq_sched(struct ath_softc *sc, struct ath_txq *txq) 5016{ 5017 struct ath_tid *tid, *next, *last; 5018 5019 ATH_TX_LOCK_ASSERT(sc); 5020 5021 /* 5022 * Don't schedule if the hardware queue is busy. 5023 * This (hopefully) gives some more time to aggregate 5024 * some packets in the aggregation queue. 5025 */ 5026 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 5027 sc->sc_aggr_stats.aggr_sched_nopkt++; 5028 return; 5029 } 5030 5031 last = TAILQ_LAST(&txq->axq_tidq, axq_t_s); 5032 5033 TAILQ_FOREACH_SAFE(tid, &txq->axq_tidq, axq_qelem, next) { 5034 /* 5035 * Suspend paused queues here; they'll be resumed 5036 * once the addba completes or times out. 5037 */ 5038 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, paused=%d\n", 5039 __func__, tid->tid, tid->paused); 5040 ath_tx_tid_unsched(sc, tid); 5041 if (tid->paused) { 5042 continue; 5043 } 5044 if (ath_tx_ampdu_running(sc, tid->an, tid->tid)) 5045 ath_tx_tid_hw_queue_aggr(sc, tid->an, tid); 5046 else 5047 ath_tx_tid_hw_queue_norm(sc, tid->an, tid); 5048 5049 /* Not empty? Re-schedule */ 5050 if (tid->axq_depth != 0) 5051 ath_tx_tid_sched(sc, tid); 5052 5053 /* Give the software queue time to aggregate more packets */ 5054 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 5055 break; 5056 } 5057 5058 /* 5059 * If this was the last entry on the original list, stop. 5060 * Otherwise nodes that have been rescheduled onto the end 5061 * of the TID FIFO list will just keep being rescheduled. 5062 */ 5063 if (tid == last) 5064 break; 5065 } 5066} 5067 5068/* 5069 * TX addba handling 5070 */ 5071 5072/* 5073 * Return net80211 TID struct pointer, or NULL for none 5074 */ 5075struct ieee80211_tx_ampdu * 5076ath_tx_get_tx_tid(struct ath_node *an, int tid) 5077{ 5078 struct ieee80211_node *ni = &an->an_node; 5079 struct ieee80211_tx_ampdu *tap; 5080 5081 if (tid == IEEE80211_NONQOS_TID) 5082 return NULL; 5083 5084 tap = &ni->ni_tx_ampdu[tid]; 5085 return tap; 5086} 5087 5088/* 5089 * Is AMPDU-TX running? 5090 */ 5091static int 5092ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, int tid) 5093{ 5094 struct ieee80211_tx_ampdu *tap; 5095 5096 if (tid == IEEE80211_NONQOS_TID) 5097 return 0; 5098 5099 tap = ath_tx_get_tx_tid(an, tid); 5100 if (tap == NULL) 5101 return 0; /* Not valid; default to not running */ 5102 5103 return !! (tap->txa_flags & IEEE80211_AGGR_RUNNING); 5104} 5105 5106/* 5107 * Is AMPDU-TX negotiation pending? 5108 */ 5109static int 5110ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid) 5111{ 5112 struct ieee80211_tx_ampdu *tap; 5113 5114 if (tid == IEEE80211_NONQOS_TID) 5115 return 0; 5116 5117 tap = ath_tx_get_tx_tid(an, tid); 5118 if (tap == NULL) 5119 return 0; /* Not valid; default to not pending */ 5120 5121 return !! (tap->txa_flags & IEEE80211_AGGR_XCHGPEND); 5122} 5123 5124/* 5125 * Is AMPDU-TX pending for the given TID? 5126 */ 5127 5128 5129/* 5130 * Method to handle sending an ADDBA request. 5131 * 5132 * We tap this so the relevant flags can be set to pause the TID 5133 * whilst waiting for the response. 5134 * 5135 * XXX there's no timeout handler we can override? 5136 */ 5137int 5138ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5139 int dialogtoken, int baparamset, int batimeout) 5140{ 5141 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5142 int tid = tap->txa_tid; 5143 struct ath_node *an = ATH_NODE(ni); 5144 struct ath_tid *atid = &an->an_tid[tid]; 5145 5146 /* 5147 * XXX danger Will Robinson! 5148 * 5149 * Although the taskqueue may be running and scheduling some more 5150 * packets, these should all be _before_ the addba sequence number. 5151 * However, net80211 will keep self-assigning sequence numbers 5152 * until addba has been negotiated. 5153 * 5154 * In the past, these packets would be "paused" (which still works 5155 * fine, as they're being scheduled to the driver in the same 5156 * serialised method which is calling the addba request routine) 5157 * and when the aggregation session begins, they'll be dequeued 5158 * as aggregate packets and added to the BAW. However, now there's 5159 * a "bf->bf_state.bfs_dobaw" flag, and this isn't set for these 5160 * packets. Thus they never get included in the BAW tracking and 5161 * this can cause the initial burst of packets after the addba 5162 * negotiation to "hang", as they quickly fall outside the BAW. 5163 * 5164 * The "eventual" solution should be to tag these packets with 5165 * dobaw. Although net80211 has given us a sequence number, 5166 * it'll be "after" the left edge of the BAW and thus it'll 5167 * fall within it. 5168 */ 5169 ATH_TX_LOCK(sc); 5170 /* 5171 * This is a bit annoying. Until net80211 HT code inherits some 5172 * (any) locking, we may have this called in parallel BUT only 5173 * one response/timeout will be called. Grr. 5174 */ 5175 if (atid->addba_tx_pending == 0) { 5176 ath_tx_tid_pause(sc, atid); 5177 atid->addba_tx_pending = 1; 5178 } 5179 ATH_TX_UNLOCK(sc); 5180 5181 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 5182 "%s: called; dialogtoken=%d, baparamset=%d, batimeout=%d\n", 5183 __func__, dialogtoken, baparamset, batimeout); 5184 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 5185 "%s: txa_start=%d, ni_txseqs=%d\n", 5186 __func__, tap->txa_start, ni->ni_txseqs[tid]); 5187 5188 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 5189 batimeout); 5190} 5191 5192/* 5193 * Handle an ADDBA response. 5194 * 5195 * We unpause the queue so TX'ing can resume. 5196 * 5197 * Any packets TX'ed from this point should be "aggregate" (whether 5198 * aggregate or not) so the BAW is updated. 5199 * 5200 * Note! net80211 keeps self-assigning sequence numbers until 5201 * ampdu is negotiated. This means the initially-negotiated BAW left 5202 * edge won't match the ni->ni_txseq. 5203 * 5204 * So, being very dirty, the BAW left edge is "slid" here to match 5205 * ni->ni_txseq. 5206 * 5207 * What likely SHOULD happen is that all packets subsequent to the 5208 * addba request should be tagged as aggregate and queued as non-aggregate 5209 * frames; thus updating the BAW. For now though, I'll just slide the 5210 * window. 5211 */ 5212int 5213ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5214 int status, int code, int batimeout) 5215{ 5216 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5217 int tid = tap->txa_tid; 5218 struct ath_node *an = ATH_NODE(ni); 5219 struct ath_tid *atid = &an->an_tid[tid]; 5220 int r; 5221 5222 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 5223 "%s: called; status=%d, code=%d, batimeout=%d\n", __func__, 5224 status, code, batimeout); 5225 5226 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 5227 "%s: txa_start=%d, ni_txseqs=%d\n", 5228 __func__, tap->txa_start, ni->ni_txseqs[tid]); 5229 5230 /* 5231 * Call this first, so the interface flags get updated 5232 * before the TID is unpaused. Otherwise a race condition 5233 * exists where the unpaused TID still doesn't yet have 5234 * IEEE80211_AGGR_RUNNING set. 5235 */ 5236 r = sc->sc_addba_response(ni, tap, status, code, batimeout); 5237 5238 ATH_TX_LOCK(sc); 5239 atid->addba_tx_pending = 0; 5240 /* 5241 * XXX dirty! 5242 * Slide the BAW left edge to wherever net80211 left it for us. 5243 * Read above for more information. 5244 */ 5245 tap->txa_start = ni->ni_txseqs[tid]; 5246 ath_tx_tid_resume(sc, atid); 5247 ATH_TX_UNLOCK(sc); 5248 return r; 5249} 5250 5251 5252/* 5253 * Stop ADDBA on a queue. 5254 * 5255 * This can be called whilst BAR TX is currently active on the queue, 5256 * so make sure this is unblocked before continuing. 5257 */ 5258void 5259ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 5260{ 5261 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5262 int tid = tap->txa_tid; 5263 struct ath_node *an = ATH_NODE(ni); 5264 struct ath_tid *atid = &an->an_tid[tid]; 5265 5266 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: called\n", __func__); 5267 5268 /* 5269 * Pause TID traffic early, so there aren't any races 5270 * Unblock the pending BAR held traffic, if it's currently paused. 5271 */ 5272 ATH_TX_LOCK(sc); 5273 ath_tx_tid_pause(sc, atid); 5274 if (atid->bar_wait) { 5275 /* 5276 * bar_unsuspend() expects bar_tx == 1, as it should be 5277 * called from the TX completion path. This quietens 5278 * the warning. It's cleared for us anyway. 5279 */ 5280 atid->bar_tx = 1; 5281 ath_tx_tid_bar_unsuspend(sc, atid); 5282 } 5283 ATH_TX_UNLOCK(sc); 5284 5285 /* There's no need to hold the TXQ lock here */ 5286 sc->sc_addba_stop(ni, tap); 5287 5288 /* 5289 * ath_tx_tid_cleanup will resume the TID if possible, otherwise 5290 * it'll set the cleanup flag, and it'll be unpaused once 5291 * things have been cleaned up. 5292 */ 5293 ath_tx_tid_cleanup(sc, an, tid); 5294} 5295 5296/* 5297 * Note: net80211 bar_timeout() doesn't call this function on BAR failure; 5298 * it simply tears down the aggregation session. Ew. 5299 * 5300 * It however will call ieee80211_ampdu_stop() which will call 5301 * ic->ic_addba_stop(). 5302 * 5303 * XXX This uses a hard-coded max BAR count value; the whole 5304 * XXX BAR TX success or failure should be better handled! 5305 */ 5306void 5307ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5308 int status) 5309{ 5310 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5311 int tid = tap->txa_tid; 5312 struct ath_node *an = ATH_NODE(ni); 5313 struct ath_tid *atid = &an->an_tid[tid]; 5314 int attempts = tap->txa_attempts; 5315 5316 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 5317 "%s: called; tap=%p, atid=%p, txa_tid=%d, atid->tid=%d, status=%d, attempts=%d\n", 5318 __func__, 5319 tap, 5320 atid, 5321 tap->txa_tid, 5322 atid->tid, 5323 status, 5324 attempts); 5325 5326 /* Note: This may update the BAW details */ 5327 sc->sc_bar_response(ni, tap, status); 5328 5329 /* Unpause the TID */ 5330 /* 5331 * XXX if this is attempt=50, the TID will be downgraded 5332 * XXX to a non-aggregate session. So we must unpause the 5333 * XXX TID here or it'll never be done. 5334 * 5335 * Also, don't call it if bar_tx/bar_wait are 0; something 5336 * has beaten us to the punch? (XXX figure out what?) 5337 */ 5338 if (status == 0 || attempts == 50) { 5339 ATH_TX_LOCK(sc); 5340 if (atid->bar_tx == 0 || atid->bar_wait == 0) 5341 device_printf(sc->sc_dev, 5342 "%s: huh? bar_tx=%d, bar_wait=%d\n", 5343 __func__, 5344 atid->bar_tx, atid->bar_wait); 5345 else 5346 ath_tx_tid_bar_unsuspend(sc, atid); 5347 ATH_TX_UNLOCK(sc); 5348 } 5349} 5350 5351/* 5352 * This is called whenever the pending ADDBA request times out. 5353 * Unpause and reschedule the TID. 5354 */ 5355void 5356ath_addba_response_timeout(struct ieee80211_node *ni, 5357 struct ieee80211_tx_ampdu *tap) 5358{ 5359 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5360 int tid = tap->txa_tid; 5361 struct ath_node *an = ATH_NODE(ni); 5362 struct ath_tid *atid = &an->an_tid[tid]; 5363 5364 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 5365 "%s: called; resuming\n", __func__); 5366 5367 ATH_TX_LOCK(sc); 5368 atid->addba_tx_pending = 0; 5369 ATH_TX_UNLOCK(sc); 5370 5371 /* Note: This updates the aggregate state to (again) pending */ 5372 sc->sc_addba_response_timeout(ni, tap); 5373 5374 /* Unpause the TID; which reschedules it */ 5375 ATH_TX_LOCK(sc); 5376 ath_tx_tid_resume(sc, atid); 5377 ATH_TX_UNLOCK(sc); 5378} 5379 5380/* 5381 * Check if a node is asleep or not. 5382 */ 5383int 5384ath_tx_node_is_asleep(struct ath_softc *sc, struct ath_node *an) 5385{ 5386 5387 ATH_NODE_LOCK_ASSERT(an); 5388 5389 return (an->an_is_powersave); 5390} 5391 5392/* 5393 * Mark a node as currently "in powersaving." 5394 * This suspends all traffic on the node. 5395 * 5396 * This must be called with the node/tx locks free. 5397 * 5398 * XXX TODO: the locking silliness below is due to how the node 5399 * locking currently works. Right now, the node lock is grabbed 5400 * to do rate control lookups and these are done with the TX 5401 * queue lock held. This means the node lock can't be grabbed 5402 * first here or a LOR will occur. 5403 * 5404 * Eventually (hopefully!) the TX path code will only grab 5405 * the TXQ lock when transmitting and the ath_node lock when 5406 * doing node/TID operations. There are other complications - 5407 * the sched/unsched operations involve walking the per-txq 5408 * 'active tid' list and this requires both locks to be held. 5409 */ 5410void 5411ath_tx_node_sleep(struct ath_softc *sc, struct ath_node *an) 5412{ 5413 struct ath_tid *atid; 5414 struct ath_txq *txq; 5415 int tid; 5416 5417 ATH_NODE_UNLOCK_ASSERT(an); 5418 5419 /* 5420 * It's possible that a parallel call to ath_tx_node_wakeup() 5421 * will unpause these queues. 5422 * 5423 * The node lock can't just be grabbed here, as there's places 5424 * in the driver where the node lock is grabbed _within_ a 5425 * TXQ lock. 5426 * So, we do this delicately and unwind state if needed. 5427 * 5428 * + Pause all the queues 5429 * + Grab the node lock 5430 * + If the queue is already asleep, unpause and quit 5431 * + else just mark as asleep. 5432 * 5433 * A parallel sleep() call will just pause and then 5434 * find they're already paused, so undo it. 5435 * 5436 * A parallel wakeup() call will check if asleep is 1 5437 * and if it's not (ie, it's 0), it'll treat it as already 5438 * being awake. If it's 1, it'll mark it as 0 and then 5439 * unpause everything. 5440 * 5441 * (Talk about a delicate hack.) 5442 */ 5443 5444 /* Suspend all traffic on the node */ 5445 ATH_TX_LOCK(sc); 5446 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 5447 atid = &an->an_tid[tid]; 5448 txq = sc->sc_ac2q[atid->ac]; 5449 5450 ath_tx_tid_pause(sc, atid); 5451 } 5452 ATH_TX_UNLOCK(sc); 5453 5454 ATH_NODE_LOCK(an); 5455 5456 /* In case of concurrency races from net80211.. */ 5457 if (an->an_is_powersave == 1) { 5458 ATH_NODE_UNLOCK(an); 5459 device_printf(sc->sc_dev, 5460 "%s: an=%p: node was already asleep\n", 5461 __func__, an); 5462 ATH_TX_LOCK(sc); 5463 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 5464 atid = &an->an_tid[tid]; 5465 txq = sc->sc_ac2q[atid->ac]; 5466 5467 ath_tx_tid_resume(sc, atid); 5468 } 5469 ATH_TX_UNLOCK(sc); 5470 return; 5471 } 5472 5473 /* Mark node as in powersaving */ 5474 an->an_is_powersave = 1; 5475 5476 ATH_NODE_UNLOCK(an); 5477} 5478 5479/* 5480 * Mark a node as currently "awake." 5481 * This resumes all traffic to the node. 5482 */ 5483void 5484ath_tx_node_wakeup(struct ath_softc *sc, struct ath_node *an) 5485{ 5486 struct ath_tid *atid; 5487 struct ath_txq *txq; 5488 int tid; 5489 5490 ATH_NODE_UNLOCK_ASSERT(an); 5491 ATH_NODE_LOCK(an); 5492 5493 /* In case of concurrency races from net80211.. */ 5494 if (an->an_is_powersave == 0) { 5495 ATH_NODE_UNLOCK(an); 5496 device_printf(sc->sc_dev, 5497 "%s: an=%p: node was already awake\n", 5498 __func__, an); 5499 return; 5500 } 5501 5502 /* Mark node as awake */ 5503 an->an_is_powersave = 0; 5504 5505 ATH_NODE_UNLOCK(an); 5506 5507 ATH_TX_LOCK(sc); 5508 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 5509 atid = &an->an_tid[tid]; 5510 txq = sc->sc_ac2q[atid->ac]; 5511 5512 ath_tx_tid_resume(sc, atid); 5513 } 5514 ATH_TX_UNLOCK(sc); 5515} 5516 5517static int 5518ath_legacy_dma_txsetup(struct ath_softc *sc) 5519{ 5520 5521 /* nothing new needed */ 5522 return (0); 5523} 5524 5525static int 5526ath_legacy_dma_txteardown(struct ath_softc *sc) 5527{ 5528 5529 /* nothing new needed */ 5530 return (0); 5531} 5532 5533void 5534ath_xmit_setup_legacy(struct ath_softc *sc) 5535{ 5536 /* 5537 * For now, just set the descriptor length to sizeof(ath_desc); 5538 * worry about extracting the real length out of the HAL later. 5539 */ 5540 sc->sc_tx_desclen = sizeof(struct ath_desc); 5541 sc->sc_tx_statuslen = sizeof(struct ath_desc); 5542 sc->sc_tx_nmaps = 1; /* only one buffer per TX desc */ 5543 5544 sc->sc_tx.xmit_setup = ath_legacy_dma_txsetup; 5545 sc->sc_tx.xmit_teardown = ath_legacy_dma_txteardown; 5546 sc->sc_tx.xmit_attach_comp_func = ath_legacy_attach_comp_func; 5547 5548 sc->sc_tx.xmit_dma_restart = ath_legacy_tx_dma_restart; 5549 sc->sc_tx.xmit_handoff = ath_legacy_xmit_handoff; 5550 5551 sc->sc_tx.xmit_drain = ath_legacy_tx_drain; 5552} 5553