if_ath_tx.c revision 240722
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2010-2012 Adrian Chadd, Xenion Pty Ltd 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_tx.c 240722 2012-09-20 03:04:19Z adrian $"); 33 34/* 35 * Driver for the Atheros Wireless LAN controller. 36 * 37 * This software is derived from work of Atsushi Onoe; his contribution 38 * is greatly appreciated. 39 */ 40 41#include "opt_inet.h" 42#include "opt_ath.h" 43#include "opt_wlan.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/sysctl.h> 48#include <sys/mbuf.h> 49#include <sys/malloc.h> 50#include <sys/lock.h> 51#include <sys/mutex.h> 52#include <sys/kernel.h> 53#include <sys/socket.h> 54#include <sys/sockio.h> 55#include <sys/errno.h> 56#include <sys/callout.h> 57#include <sys/bus.h> 58#include <sys/endian.h> 59#include <sys/kthread.h> 60#include <sys/taskqueue.h> 61#include <sys/priv.h> 62 63#include <machine/bus.h> 64 65#include <net/if.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68#include <net/if_types.h> 69#include <net/if_arp.h> 70#include <net/ethernet.h> 71#include <net/if_llc.h> 72 73#include <net80211/ieee80211_var.h> 74#include <net80211/ieee80211_regdomain.h> 75#ifdef IEEE80211_SUPPORT_SUPERG 76#include <net80211/ieee80211_superg.h> 77#endif 78#ifdef IEEE80211_SUPPORT_TDMA 79#include <net80211/ieee80211_tdma.h> 80#endif 81#include <net80211/ieee80211_ht.h> 82 83#include <net/bpf.h> 84 85#ifdef INET 86#include <netinet/in.h> 87#include <netinet/if_ether.h> 88#endif 89 90#include <dev/ath/if_athvar.h> 91#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 92#include <dev/ath/ath_hal/ah_diagcodes.h> 93 94#include <dev/ath/if_ath_debug.h> 95 96#ifdef ATH_TX99_DIAG 97#include <dev/ath/ath_tx99/ath_tx99.h> 98#endif 99 100#include <dev/ath/if_ath_misc.h> 101#include <dev/ath/if_ath_tx.h> 102#include <dev/ath/if_ath_tx_ht.h> 103 104/* 105 * How many retries to perform in software 106 */ 107#define SWMAX_RETRIES 10 108 109static int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, 110 int tid); 111static int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, 112 int tid); 113static ieee80211_seq ath_tx_tid_seqno_assign(struct ath_softc *sc, 114 struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0); 115static int ath_tx_action_frame_override_queue(struct ath_softc *sc, 116 struct ieee80211_node *ni, struct mbuf *m0, int *tid); 117static struct ath_buf * 118ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an, 119 struct ath_tid *tid, struct ath_buf *bf); 120 121/* 122 * Whether to use the 11n rate scenario functions or not 123 */ 124static inline int 125ath_tx_is_11n(struct ath_softc *sc) 126{ 127 return ((sc->sc_ah->ah_magic == 0x20065416) || 128 (sc->sc_ah->ah_magic == 0x19741014)); 129} 130 131/* 132 * Obtain the current TID from the given frame. 133 * 134 * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.) 135 * This has implications for which AC/priority the packet is placed 136 * in. 137 */ 138static int 139ath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0) 140{ 141 const struct ieee80211_frame *wh; 142 int pri = M_WME_GETAC(m0); 143 144 wh = mtod(m0, const struct ieee80211_frame *); 145 if (! IEEE80211_QOS_HAS_SEQ(wh)) 146 return IEEE80211_NONQOS_TID; 147 else 148 return WME_AC_TO_TID(pri); 149} 150 151static void 152ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) 153{ 154 struct ieee80211_frame *wh; 155 156 wh = mtod(bf->bf_m, struct ieee80211_frame *); 157 /* Only update/resync if needed */ 158 if (bf->bf_state.bfs_isretried == 0) { 159 wh->i_fc[1] |= IEEE80211_FC1_RETRY; 160 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 161 BUS_DMASYNC_PREWRITE); 162 } 163 bf->bf_state.bfs_isretried = 1; 164 bf->bf_state.bfs_retries ++; 165} 166 167/* 168 * Determine what the correct AC queue for the given frame 169 * should be. 170 * 171 * This code assumes that the TIDs map consistently to 172 * the underlying hardware (or software) ath_txq. 173 * Since the sender may try to set an AC which is 174 * arbitrary, non-QoS TIDs may end up being put on 175 * completely different ACs. There's no way to put a 176 * TID into multiple ath_txq's for scheduling, so 177 * for now we override the AC/TXQ selection and set 178 * non-QOS TID frames into the BE queue. 179 * 180 * This may be completely incorrect - specifically, 181 * some management frames may end up out of order 182 * compared to the QoS traffic they're controlling. 183 * I'll look into this later. 184 */ 185static int 186ath_tx_getac(struct ath_softc *sc, const struct mbuf *m0) 187{ 188 const struct ieee80211_frame *wh; 189 int pri = M_WME_GETAC(m0); 190 wh = mtod(m0, const struct ieee80211_frame *); 191 if (IEEE80211_QOS_HAS_SEQ(wh)) 192 return pri; 193 194 return WME_AC_BE; 195} 196 197void 198ath_txfrag_cleanup(struct ath_softc *sc, 199 ath_bufhead *frags, struct ieee80211_node *ni) 200{ 201 struct ath_buf *bf, *next; 202 203 ATH_TXBUF_LOCK_ASSERT(sc); 204 205 TAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 206 /* NB: bf assumed clean */ 207 TAILQ_REMOVE(frags, bf, bf_list); 208 ath_returnbuf_head(sc, bf); 209 ieee80211_node_decref(ni); 210 } 211} 212 213/* 214 * Setup xmit of a fragmented frame. Allocate a buffer 215 * for each frag and bump the node reference count to 216 * reflect the held reference to be setup by ath_tx_start. 217 */ 218int 219ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 220 struct mbuf *m0, struct ieee80211_node *ni) 221{ 222 struct mbuf *m; 223 struct ath_buf *bf; 224 225 ATH_TXBUF_LOCK(sc); 226 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 227 /* XXX non-management? */ 228 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL); 229 if (bf == NULL) { /* out of buffers, cleanup */ 230 device_printf(sc->sc_dev, "%s: no buffer?\n", 231 __func__); 232 ath_txfrag_cleanup(sc, frags, ni); 233 break; 234 } 235 ieee80211_node_incref(ni); 236 TAILQ_INSERT_TAIL(frags, bf, bf_list); 237 } 238 ATH_TXBUF_UNLOCK(sc); 239 240 return !TAILQ_EMPTY(frags); 241} 242 243/* 244 * Reclaim mbuf resources. For fragmented frames we 245 * need to claim each frag chained with m_nextpkt. 246 */ 247void 248ath_freetx(struct mbuf *m) 249{ 250 struct mbuf *next; 251 252 do { 253 next = m->m_nextpkt; 254 m->m_nextpkt = NULL; 255 m_freem(m); 256 } while ((m = next) != NULL); 257} 258 259static int 260ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 261{ 262 struct mbuf *m; 263 int error; 264 265 /* 266 * Load the DMA map so any coalescing is done. This 267 * also calculates the number of descriptors we need. 268 */ 269 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 270 bf->bf_segs, &bf->bf_nseg, 271 BUS_DMA_NOWAIT); 272 if (error == EFBIG) { 273 /* XXX packet requires too many descriptors */ 274 bf->bf_nseg = ATH_TXDESC+1; 275 } else if (error != 0) { 276 sc->sc_stats.ast_tx_busdma++; 277 ath_freetx(m0); 278 return error; 279 } 280 /* 281 * Discard null packets and check for packets that 282 * require too many TX descriptors. We try to convert 283 * the latter to a cluster. 284 */ 285 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 286 sc->sc_stats.ast_tx_linear++; 287 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC); 288 if (m == NULL) { 289 ath_freetx(m0); 290 sc->sc_stats.ast_tx_nombuf++; 291 return ENOMEM; 292 } 293 m0 = m; 294 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 295 bf->bf_segs, &bf->bf_nseg, 296 BUS_DMA_NOWAIT); 297 if (error != 0) { 298 sc->sc_stats.ast_tx_busdma++; 299 ath_freetx(m0); 300 return error; 301 } 302 KASSERT(bf->bf_nseg <= ATH_TXDESC, 303 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 304 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 305 sc->sc_stats.ast_tx_nodata++; 306 ath_freetx(m0); 307 return EIO; 308 } 309 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 310 __func__, m0, m0->m_pkthdr.len); 311 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 312 bf->bf_m = m0; 313 314 return 0; 315} 316 317/* 318 * Chain together segments+descriptors for a non-11n frame. 319 */ 320static void 321ath_tx_chaindesclist(struct ath_softc *sc, struct ath_buf *bf) 322{ 323 struct ath_hal *ah = sc->sc_ah; 324 char *ds, *ds0; 325 int i, bp, dsp; 326 HAL_DMA_ADDR bufAddrList[4]; 327 uint32_t segLenList[4]; 328 int numTxMaps = 1; 329 int isFirstDesc = 1; 330 int qnum; 331 332 /* 333 * XXX There's txdma and txdma_mgmt; the descriptor 334 * sizes must match. 335 */ 336 struct ath_descdma *dd = &sc->sc_txdma; 337 338 /* 339 * Fillin the remainder of the descriptor info. 340 */ 341 342 /* 343 * For now the HAL doesn't implement halNumTxMaps for non-EDMA 344 * (ie it's 0.) So just work around it. 345 * 346 * XXX TODO: populate halNumTxMaps for each HAL chip and 347 * then undo this hack. 348 */ 349 if (sc->sc_ah->ah_magic == 0x19741014) 350 numTxMaps = 4; 351 352 /* 353 * For EDMA and later chips ensure the TX map is fully populated 354 * before advancing to the next descriptor. 355 */ 356 ds0 = ds = (char *) bf->bf_desc; 357 bp = dsp = 0; 358 bzero(bufAddrList, sizeof(bufAddrList)); 359 bzero(segLenList, sizeof(segLenList)); 360 for (i = 0; i < bf->bf_nseg; i++) { 361 bufAddrList[bp] = bf->bf_segs[i].ds_addr; 362 segLenList[bp] = bf->bf_segs[i].ds_len; 363 bp++; 364 365 /* 366 * Go to the next segment if this isn't the last segment 367 * and there's space in the current TX map. 368 */ 369 if ((i != bf->bf_nseg - 1) && (bp < numTxMaps)) 370 continue; 371 372 /* 373 * Last segment or we're out of buffer pointers. 374 */ 375 bp = 0; 376 377 if (i == bf->bf_nseg - 1) 378 ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 0); 379 else 380 ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 381 bf->bf_daddr + dd->dd_descsize * (dsp + 1)); 382 383 /* 384 * XXX this assumes that bfs_txq is the actual destination 385 * hardware queue at this point. It may not have been assigned, 386 * it may actually be pointing to the multicast software 387 * TXQ id. These must be fixed! 388 */ 389 qnum = bf->bf_state.bfs_txq->axq_qnum; 390 391 ath_hal_filltxdesc(ah, (struct ath_desc *) ds 392 , bufAddrList 393 , segLenList 394 , bf->bf_descid /* XXX desc id */ 395 , qnum 396 , isFirstDesc /* first segment */ 397 , i == bf->bf_nseg - 1 /* last segment */ 398 , (struct ath_desc *) ds0 /* first descriptor */ 399 ); 400 401 /* Make sure the 11n aggregate fields are cleared */ 402 if (ath_tx_is_11n(sc)) 403 ath_hal_clr11n_aggr(sc->sc_ah, (struct ath_desc *) ds); 404 405 isFirstDesc = 0; 406#ifdef ATH_DEBUG 407 if (sc->sc_debug & ATH_DEBUG_XMIT) 408 ath_printtxbuf(sc, bf, qnum, 0, 0); 409#endif 410 bf->bf_lastds = (struct ath_desc *) ds; 411 412 /* 413 * Don't forget to skip to the next descriptor. 414 */ 415 ds += sc->sc_tx_desclen; 416 dsp++; 417 418 /* 419 * .. and don't forget to blank these out! 420 */ 421 bzero(bufAddrList, sizeof(bufAddrList)); 422 bzero(segLenList, sizeof(segLenList)); 423 } 424 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 425} 426 427/* 428 * Fill in the descriptor list for a aggregate subframe. 429 * 430 * The subframe is returned with the ds_link field in the last subframe 431 * pointing to 0. 432 */ 433static void 434ath_tx_chaindesclist_subframe(struct ath_softc *sc, struct ath_buf *bf) 435{ 436 struct ath_hal *ah = sc->sc_ah; 437 struct ath_desc *ds, *ds0; 438 int i; 439 HAL_DMA_ADDR bufAddrList[4]; 440 uint32_t segLenList[4]; 441 442 /* 443 * XXX There's txdma and txdma_mgmt; the descriptor 444 * sizes must match. 445 */ 446 struct ath_descdma *dd = &sc->sc_txdma; 447 448 ds0 = ds = bf->bf_desc; 449 450 /* 451 * There's no need to call ath_hal_setupfirsttxdesc here; 452 * That's only going to occur for the first frame in an aggregate. 453 */ 454 for (i = 0; i < bf->bf_nseg; i++, ds++) { 455 bzero(bufAddrList, sizeof(bufAddrList)); 456 bzero(segLenList, sizeof(segLenList)); 457 if (i == bf->bf_nseg - 1) 458 ath_hal_settxdesclink(ah, ds, 0); 459 else 460 ath_hal_settxdesclink(ah, ds, 461 bf->bf_daddr + dd->dd_descsize * (i + 1)); 462 463 bufAddrList[0] = bf->bf_segs[i].ds_addr; 464 segLenList[0] = bf->bf_segs[i].ds_len; 465 466 /* 467 * This performs the setup for an aggregate frame. 468 * This includes enabling the aggregate flags if needed. 469 */ 470 ath_hal_chaintxdesc(ah, ds, 471 bufAddrList, 472 segLenList, 473 bf->bf_state.bfs_pktlen, 474 bf->bf_state.bfs_hdrlen, 475 HAL_PKT_TYPE_AMPDU, /* forces aggregate bits to be set */ 476 bf->bf_state.bfs_keyix, 477 0, /* cipher, calculated from keyix */ 478 bf->bf_state.bfs_ndelim, 479 i == 0, /* first segment */ 480 i == bf->bf_nseg - 1, /* last segment */ 481 bf->bf_next == NULL /* last sub-frame in aggr */ 482 ); 483 484 DPRINTF(sc, ATH_DEBUG_XMIT, 485 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 486 __func__, i, ds->ds_link, ds->ds_data, 487 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 488 bf->bf_lastds = ds; 489 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 490 BUS_DMASYNC_PREWRITE); 491 } 492} 493 494/* 495 * Set the rate control fields in the given descriptor based on 496 * the bf_state fields and node state. 497 * 498 * The bfs fields should already be set with the relevant rate 499 * control information, including whether MRR is to be enabled. 500 * 501 * Since the FreeBSD HAL currently sets up the first TX rate 502 * in ath_hal_setuptxdesc(), this will setup the MRR 503 * conditionally for the pre-11n chips, and call ath_buf_set_rate 504 * unconditionally for 11n chips. These require the 11n rate 505 * scenario to be set if MCS rates are enabled, so it's easier 506 * to just always call it. The caller can then only set rates 2, 3 507 * and 4 if multi-rate retry is needed. 508 */ 509static void 510ath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 511 struct ath_buf *bf) 512{ 513 struct ath_rc_series *rc = bf->bf_state.bfs_rc; 514 515 /* If mrr is disabled, blank tries 1, 2, 3 */ 516 if (! bf->bf_state.bfs_ismrr) 517 rc[1].tries = rc[2].tries = rc[3].tries = 0; 518 519 /* 520 * Always call - that way a retried descriptor will 521 * have the MRR fields overwritten. 522 * 523 * XXX TODO: see if this is really needed - setting up 524 * the first descriptor should set the MRR fields to 0 525 * for us anyway. 526 */ 527 if (ath_tx_is_11n(sc)) { 528 ath_buf_set_rate(sc, ni, bf); 529 } else { 530 ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc 531 , rc[1].ratecode, rc[1].tries 532 , rc[2].ratecode, rc[2].tries 533 , rc[3].ratecode, rc[3].tries 534 ); 535 } 536} 537 538/* 539 * Setup segments+descriptors for an 11n aggregate. 540 * bf_first is the first buffer in the aggregate. 541 * The descriptor list must already been linked together using 542 * bf->bf_next. 543 */ 544static void 545ath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first) 546{ 547 struct ath_buf *bf, *bf_prev = NULL; 548 549 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n", 550 __func__, bf_first->bf_state.bfs_nframes, 551 bf_first->bf_state.bfs_al); 552 553 /* 554 * Setup all descriptors of all subframes. 555 */ 556 bf = bf_first; 557 while (bf != NULL) { 558 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 559 "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n", 560 __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen, 561 SEQNO(bf->bf_state.bfs_seqno)); 562 563 /* Sub-frame setup */ 564 ath_tx_chaindesclist_subframe(sc, bf); 565 566 /* 567 * Link the last descriptor of the previous frame 568 * to the beginning descriptor of this frame. 569 */ 570 if (bf_prev != NULL) 571 ath_hal_settxdesclink(sc->sc_ah, bf_prev->bf_lastds, 572 bf->bf_daddr); 573 574 /* Save a copy so we can link the next descriptor in */ 575 bf_prev = bf; 576 bf = bf->bf_next; 577 } 578 579 /* 580 * Setup first descriptor of first frame. 581 * chaintxdesc() overwrites the descriptor entries; 582 * setupfirsttxdesc() merges in things. 583 * Otherwise various fields aren't set correctly (eg flags). 584 */ 585 ath_hal_setupfirsttxdesc(sc->sc_ah, 586 bf_first->bf_desc, 587 bf_first->bf_state.bfs_al, 588 bf_first->bf_state.bfs_txflags | HAL_TXDESC_INTREQ, 589 bf_first->bf_state.bfs_txpower, 590 bf_first->bf_state.bfs_txrate0, 591 bf_first->bf_state.bfs_try0, 592 bf_first->bf_state.bfs_txantenna, 593 bf_first->bf_state.bfs_ctsrate, 594 bf_first->bf_state.bfs_ctsduration); 595 596 /* 597 * Set the first descriptor bf_lastds field to point to 598 * the last descriptor in the last subframe, that's where 599 * the status update will occur. 600 */ 601 bf_first->bf_lastds = bf_prev->bf_lastds; 602 603 /* 604 * And bf_last in the first descriptor points to the end of 605 * the aggregate list. 606 */ 607 bf_first->bf_last = bf_prev; 608 609 /* 610 * setup first desc with rate and aggr info 611 */ 612 ath_tx_set_ratectrl(sc, bf_first->bf_node, bf_first); 613 614 /* 615 * Setup the last descriptor in the list. 616 * 617 * bf_first->bf_lastds already points to it; the rate 618 * control information needs to be squirreled away here 619 * as well ans clearing the moreaggr/paddelim fields. 620 */ 621 ath_hal_setuplasttxdesc(sc->sc_ah, bf_first->bf_lastds, 622 bf_first->bf_desc); 623 624 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__); 625} 626 627/* 628 * Hand-off a frame to the multicast TX queue. 629 * 630 * This is a software TXQ which will be appended to the CAB queue 631 * during the beacon setup code. 632 * 633 * XXX TODO: since the AR9300 EDMA TX queue support wants the QCU ID 634 * as part of the TX descriptor, bf_state.bfs_txq must be updated 635 * with the actual hardware txq, or all of this will fall apart. 636 * 637 * XXX It may not be a bad idea to just stuff the QCU ID into bf_state 638 * and retire bfs_txq; then make sure the CABQ QCU ID is populated 639 * correctly. 640 */ 641static void 642ath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq, 643 struct ath_buf *bf) 644{ 645 ATH_TXQ_LOCK_ASSERT(txq); 646 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 647 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 648 if (txq->axq_link != NULL) { 649 struct ath_buf *last = ATH_TXQ_LAST(txq, axq_q_s); 650 struct ieee80211_frame *wh; 651 652 /* mark previous frame */ 653 wh = mtod(last->bf_m, struct ieee80211_frame *); 654 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 655 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 656 BUS_DMASYNC_PREWRITE); 657 658 /* link descriptor */ 659 *txq->axq_link = bf->bf_daddr; 660 } 661 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 662 ath_hal_gettxdesclinkptr(sc->sc_ah, bf->bf_lastds, &txq->axq_link); 663} 664 665/* 666 * Hand-off packet to a hardware queue. 667 */ 668static void 669ath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq, 670 struct ath_buf *bf) 671{ 672 struct ath_hal *ah = sc->sc_ah; 673 674 /* 675 * Insert the frame on the outbound list and pass it on 676 * to the hardware. Multicast frames buffered for power 677 * save stations and transmit from the CAB queue are stored 678 * on a s/w only queue and loaded on to the CAB queue in 679 * the SWBA handler since frames only go out on DTIM and 680 * to avoid possible races. 681 */ 682 ATH_TXQ_LOCK_ASSERT(txq); 683 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 684 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 685 KASSERT(txq->axq_qnum != ATH_TXQ_SWQ, 686 ("ath_tx_handoff_hw called for mcast queue")); 687 688#if 0 689 /* 690 * This causes a LOR. Find out where the PCU lock is being 691 * held whilst the TXQ lock is grabbed - that shouldn't 692 * be occuring. 693 */ 694 ATH_PCU_LOCK(sc); 695 if (sc->sc_inreset_cnt) { 696 ATH_PCU_UNLOCK(sc); 697 DPRINTF(sc, ATH_DEBUG_RESET, 698 "%s: called with sc_in_reset != 0\n", 699 __func__); 700 DPRINTF(sc, ATH_DEBUG_XMIT, 701 "%s: queued: TXDP[%u] = %p (%p) depth %d\n", 702 __func__, txq->axq_qnum, 703 (caddr_t)bf->bf_daddr, bf->bf_desc, 704 txq->axq_depth); 705 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 706 if (bf->bf_state.bfs_aggr) 707 txq->axq_aggr_depth++; 708 /* 709 * There's no need to update axq_link; the hardware 710 * is in reset and once the reset is complete, any 711 * non-empty queues will simply have DMA restarted. 712 */ 713 return; 714 } 715 ATH_PCU_UNLOCK(sc); 716#endif 717 718 /* For now, so not to generate whitespace diffs */ 719 if (1) { 720#ifdef IEEE80211_SUPPORT_TDMA 721 int qbusy; 722 723 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 724 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 725 if (txq->axq_link == NULL) { 726 /* 727 * Be careful writing the address to TXDP. If 728 * the tx q is enabled then this write will be 729 * ignored. Normally this is not an issue but 730 * when tdma is in use and the q is beacon gated 731 * this race can occur. If the q is busy then 732 * defer the work to later--either when another 733 * packet comes along or when we prepare a beacon 734 * frame at SWBA. 735 */ 736 if (!qbusy) { 737 ath_hal_puttxbuf(ah, txq->axq_qnum, 738 bf->bf_daddr); 739 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 740 DPRINTF(sc, ATH_DEBUG_XMIT, 741 "%s: TXDP[%u] = %p (%p) depth %d\n", 742 __func__, txq->axq_qnum, 743 (caddr_t)bf->bf_daddr, bf->bf_desc, 744 txq->axq_depth); 745 } else { 746 txq->axq_flags |= ATH_TXQ_PUTPENDING; 747 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 748 "%s: Q%u busy, defer enable\n", __func__, 749 txq->axq_qnum); 750 } 751 } else { 752 *txq->axq_link = bf->bf_daddr; 753 DPRINTF(sc, ATH_DEBUG_XMIT, 754 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 755 txq->axq_qnum, txq->axq_link, 756 (caddr_t)bf->bf_daddr, bf->bf_desc, 757 txq->axq_depth); 758 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) { 759 /* 760 * The q was busy when we previously tried 761 * to write the address of the first buffer 762 * in the chain. Since it's not busy now 763 * handle this chore. We are certain the 764 * buffer at the front is the right one since 765 * axq_link is NULL only when the buffer list 766 * is/was empty. 767 */ 768 ath_hal_puttxbuf(ah, txq->axq_qnum, 769 TAILQ_FIRST(&txq->axq_q)->bf_daddr); 770 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 771 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 772 "%s: Q%u restarted\n", __func__, 773 txq->axq_qnum); 774 } 775 } 776#else 777 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 778 if (txq->axq_link == NULL) { 779 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 780 DPRINTF(sc, ATH_DEBUG_XMIT, 781 "%s: TXDP[%u] = %p (%p) depth %d\n", 782 __func__, txq->axq_qnum, 783 (caddr_t)bf->bf_daddr, bf->bf_desc, 784 txq->axq_depth); 785 } else { 786 *txq->axq_link = bf->bf_daddr; 787 DPRINTF(sc, ATH_DEBUG_XMIT, 788 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 789 txq->axq_qnum, txq->axq_link, 790 (caddr_t)bf->bf_daddr, bf->bf_desc, 791 txq->axq_depth); 792 } 793#endif /* IEEE80211_SUPPORT_TDMA */ 794 if (bf->bf_state.bfs_aggr) 795 txq->axq_aggr_depth++; 796 ath_hal_gettxdesclinkptr(ah, bf->bf_lastds, &txq->axq_link); 797 ath_hal_txstart(ah, txq->axq_qnum); 798 } 799} 800 801/* 802 * Restart TX DMA for the given TXQ. 803 * 804 * This must be called whether the queue is empty or not. 805 */ 806static void 807ath_legacy_tx_dma_restart(struct ath_softc *sc, struct ath_txq *txq) 808{ 809 struct ath_hal *ah = sc->sc_ah; 810 struct ath_buf *bf, *bf_last; 811 812 ATH_TXQ_LOCK_ASSERT(txq); 813 814 /* This is always going to be cleared, empty or not */ 815 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 816 817 /* XXX make this ATH_TXQ_FIRST */ 818 bf = TAILQ_FIRST(&txq->axq_q); 819 bf_last = ATH_TXQ_LAST(txq, axq_q_s); 820 821 if (bf == NULL) 822 return; 823 824 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 825 ath_hal_gettxdesclinkptr(ah, bf_last->bf_lastds, &txq->axq_link); 826 ath_hal_txstart(ah, txq->axq_qnum); 827} 828 829/* 830 * Hand off a packet to the hardware (or mcast queue.) 831 * 832 * The relevant hardware txq should be locked. 833 */ 834static void 835ath_legacy_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq, 836 struct ath_buf *bf) 837{ 838 ATH_TXQ_LOCK_ASSERT(txq); 839 840 if (txq->axq_qnum == ATH_TXQ_SWQ) 841 ath_tx_handoff_mcast(sc, txq, bf); 842 else 843 ath_tx_handoff_hw(sc, txq, bf); 844} 845 846static int 847ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni, 848 struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen, 849 int *keyix) 850{ 851 DPRINTF(sc, ATH_DEBUG_XMIT, 852 "%s: hdrlen=%d, pktlen=%d, isfrag=%d, iswep=%d, m0=%p\n", 853 __func__, 854 *hdrlen, 855 *pktlen, 856 isfrag, 857 iswep, 858 m0); 859 860 if (iswep) { 861 const struct ieee80211_cipher *cip; 862 struct ieee80211_key *k; 863 864 /* 865 * Construct the 802.11 header+trailer for an encrypted 866 * frame. The only reason this can fail is because of an 867 * unknown or unsupported cipher/key type. 868 */ 869 k = ieee80211_crypto_encap(ni, m0); 870 if (k == NULL) { 871 /* 872 * This can happen when the key is yanked after the 873 * frame was queued. Just discard the frame; the 874 * 802.11 layer counts failures and provides 875 * debugging/diagnostics. 876 */ 877 return (0); 878 } 879 /* 880 * Adjust the packet + header lengths for the crypto 881 * additions and calculate the h/w key index. When 882 * a s/w mic is done the frame will have had any mic 883 * added to it prior to entry so m0->m_pkthdr.len will 884 * account for it. Otherwise we need to add it to the 885 * packet length. 886 */ 887 cip = k->wk_cipher; 888 (*hdrlen) += cip->ic_header; 889 (*pktlen) += cip->ic_header + cip->ic_trailer; 890 /* NB: frags always have any TKIP MIC done in s/w */ 891 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 892 (*pktlen) += cip->ic_miclen; 893 (*keyix) = k->wk_keyix; 894 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 895 /* 896 * Use station key cache slot, if assigned. 897 */ 898 (*keyix) = ni->ni_ucastkey.wk_keyix; 899 if ((*keyix) == IEEE80211_KEYIX_NONE) 900 (*keyix) = HAL_TXKEYIX_INVALID; 901 } else 902 (*keyix) = HAL_TXKEYIX_INVALID; 903 904 return (1); 905} 906 907/* 908 * Calculate whether interoperability protection is required for 909 * this frame. 910 * 911 * This requires the rate control information be filled in, 912 * as the protection requirement depends upon the current 913 * operating mode / PHY. 914 */ 915static void 916ath_tx_calc_protection(struct ath_softc *sc, struct ath_buf *bf) 917{ 918 struct ieee80211_frame *wh; 919 uint8_t rix; 920 uint16_t flags; 921 int shortPreamble; 922 const HAL_RATE_TABLE *rt = sc->sc_currates; 923 struct ifnet *ifp = sc->sc_ifp; 924 struct ieee80211com *ic = ifp->if_l2com; 925 926 flags = bf->bf_state.bfs_txflags; 927 rix = bf->bf_state.bfs_rc[0].rix; 928 shortPreamble = bf->bf_state.bfs_shpream; 929 wh = mtod(bf->bf_m, struct ieee80211_frame *); 930 931 /* 932 * If 802.11g protection is enabled, determine whether 933 * to use RTS/CTS or just CTS. Note that this is only 934 * done for OFDM unicast frames. 935 */ 936 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 937 rt->info[rix].phy == IEEE80211_T_OFDM && 938 (flags & HAL_TXDESC_NOACK) == 0) { 939 bf->bf_state.bfs_doprot = 1; 940 /* XXX fragments must use CCK rates w/ protection */ 941 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 942 flags |= HAL_TXDESC_RTSENA; 943 } else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 944 flags |= HAL_TXDESC_CTSENA; 945 } 946 /* 947 * For frags it would be desirable to use the 948 * highest CCK rate for RTS/CTS. But stations 949 * farther away may detect it at a lower CCK rate 950 * so use the configured protection rate instead 951 * (for now). 952 */ 953 sc->sc_stats.ast_tx_protect++; 954 } 955 956 /* 957 * If 11n protection is enabled and it's a HT frame, 958 * enable RTS. 959 * 960 * XXX ic_htprotmode or ic_curhtprotmode? 961 * XXX should it_htprotmode only matter if ic_curhtprotmode 962 * XXX indicates it's not a HT pure environment? 963 */ 964 if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) && 965 rt->info[rix].phy == IEEE80211_T_HT && 966 (flags & HAL_TXDESC_NOACK) == 0) { 967 flags |= HAL_TXDESC_RTSENA; 968 sc->sc_stats.ast_tx_htprotect++; 969 } 970 bf->bf_state.bfs_txflags = flags; 971} 972 973/* 974 * Update the frame duration given the currently selected rate. 975 * 976 * This also updates the frame duration value, so it will require 977 * a DMA flush. 978 */ 979static void 980ath_tx_calc_duration(struct ath_softc *sc, struct ath_buf *bf) 981{ 982 struct ieee80211_frame *wh; 983 uint8_t rix; 984 uint16_t flags; 985 int shortPreamble; 986 struct ath_hal *ah = sc->sc_ah; 987 const HAL_RATE_TABLE *rt = sc->sc_currates; 988 int isfrag = bf->bf_m->m_flags & M_FRAG; 989 990 flags = bf->bf_state.bfs_txflags; 991 rix = bf->bf_state.bfs_rc[0].rix; 992 shortPreamble = bf->bf_state.bfs_shpream; 993 wh = mtod(bf->bf_m, struct ieee80211_frame *); 994 995 /* 996 * Calculate duration. This logically belongs in the 802.11 997 * layer but it lacks sufficient information to calculate it. 998 */ 999 if ((flags & HAL_TXDESC_NOACK) == 0 && 1000 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 1001 u_int16_t dur; 1002 if (shortPreamble) 1003 dur = rt->info[rix].spAckDuration; 1004 else 1005 dur = rt->info[rix].lpAckDuration; 1006 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 1007 dur += dur; /* additional SIFS+ACK */ 1008 KASSERT(bf->bf_m->m_nextpkt != NULL, ("no fragment")); 1009 /* 1010 * Include the size of next fragment so NAV is 1011 * updated properly. The last fragment uses only 1012 * the ACK duration 1013 */ 1014 dur += ath_hal_computetxtime(ah, rt, 1015 bf->bf_m->m_nextpkt->m_pkthdr.len, 1016 rix, shortPreamble); 1017 } 1018 if (isfrag) { 1019 /* 1020 * Force hardware to use computed duration for next 1021 * fragment by disabling multi-rate retry which updates 1022 * duration based on the multi-rate duration table. 1023 */ 1024 bf->bf_state.bfs_ismrr = 0; 1025 bf->bf_state.bfs_try0 = ATH_TXMGTTRY; 1026 /* XXX update bfs_rc[0].try? */ 1027 } 1028 1029 /* Update the duration field itself */ 1030 *(u_int16_t *)wh->i_dur = htole16(dur); 1031 } 1032} 1033 1034static uint8_t 1035ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt, 1036 int cix, int shortPreamble) 1037{ 1038 uint8_t ctsrate; 1039 1040 /* 1041 * CTS transmit rate is derived from the transmit rate 1042 * by looking in the h/w rate table. We must also factor 1043 * in whether or not a short preamble is to be used. 1044 */ 1045 /* NB: cix is set above where RTS/CTS is enabled */ 1046 KASSERT(cix != 0xff, ("cix not setup")); 1047 ctsrate = rt->info[cix].rateCode; 1048 1049 /* XXX this should only matter for legacy rates */ 1050 if (shortPreamble) 1051 ctsrate |= rt->info[cix].shortPreamble; 1052 1053 return (ctsrate); 1054} 1055 1056/* 1057 * Calculate the RTS/CTS duration for legacy frames. 1058 */ 1059static int 1060ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix, 1061 int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt, 1062 int flags) 1063{ 1064 int ctsduration = 0; 1065 1066 /* This mustn't be called for HT modes */ 1067 if (rt->info[cix].phy == IEEE80211_T_HT) { 1068 printf("%s: HT rate where it shouldn't be (0x%x)\n", 1069 __func__, rt->info[cix].rateCode); 1070 return (-1); 1071 } 1072 1073 /* 1074 * Compute the transmit duration based on the frame 1075 * size and the size of an ACK frame. We call into the 1076 * HAL to do the computation since it depends on the 1077 * characteristics of the actual PHY being used. 1078 * 1079 * NB: CTS is assumed the same size as an ACK so we can 1080 * use the precalculated ACK durations. 1081 */ 1082 if (shortPreamble) { 1083 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 1084 ctsduration += rt->info[cix].spAckDuration; 1085 ctsduration += ath_hal_computetxtime(ah, 1086 rt, pktlen, rix, AH_TRUE); 1087 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 1088 ctsduration += rt->info[rix].spAckDuration; 1089 } else { 1090 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 1091 ctsduration += rt->info[cix].lpAckDuration; 1092 ctsduration += ath_hal_computetxtime(ah, 1093 rt, pktlen, rix, AH_FALSE); 1094 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 1095 ctsduration += rt->info[rix].lpAckDuration; 1096 } 1097 1098 return (ctsduration); 1099} 1100 1101/* 1102 * Update the given ath_buf with updated rts/cts setup and duration 1103 * values. 1104 * 1105 * To support rate lookups for each software retry, the rts/cts rate 1106 * and cts duration must be re-calculated. 1107 * 1108 * This function assumes the RTS/CTS flags have been set as needed; 1109 * mrr has been disabled; and the rate control lookup has been done. 1110 * 1111 * XXX TODO: MRR need only be disabled for the pre-11n NICs. 1112 * XXX The 11n NICs support per-rate RTS/CTS configuration. 1113 */ 1114static void 1115ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf) 1116{ 1117 uint16_t ctsduration = 0; 1118 uint8_t ctsrate = 0; 1119 uint8_t rix = bf->bf_state.bfs_rc[0].rix; 1120 uint8_t cix = 0; 1121 const HAL_RATE_TABLE *rt = sc->sc_currates; 1122 1123 /* 1124 * No RTS/CTS enabled? Don't bother. 1125 */ 1126 if ((bf->bf_state.bfs_txflags & 1127 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) { 1128 /* XXX is this really needed? */ 1129 bf->bf_state.bfs_ctsrate = 0; 1130 bf->bf_state.bfs_ctsduration = 0; 1131 return; 1132 } 1133 1134 /* 1135 * If protection is enabled, use the protection rix control 1136 * rate. Otherwise use the rate0 control rate. 1137 */ 1138 if (bf->bf_state.bfs_doprot) 1139 rix = sc->sc_protrix; 1140 else 1141 rix = bf->bf_state.bfs_rc[0].rix; 1142 1143 /* 1144 * If the raw path has hard-coded ctsrate0 to something, 1145 * use it. 1146 */ 1147 if (bf->bf_state.bfs_ctsrate0 != 0) 1148 cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0); 1149 else 1150 /* Control rate from above */ 1151 cix = rt->info[rix].controlRate; 1152 1153 /* Calculate the rtscts rate for the given cix */ 1154 ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix, 1155 bf->bf_state.bfs_shpream); 1156 1157 /* The 11n chipsets do ctsduration calculations for you */ 1158 if (! ath_tx_is_11n(sc)) 1159 ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix, 1160 bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen, 1161 rt, bf->bf_state.bfs_txflags); 1162 1163 /* Squirrel away in ath_buf */ 1164 bf->bf_state.bfs_ctsrate = ctsrate; 1165 bf->bf_state.bfs_ctsduration = ctsduration; 1166 1167 /* 1168 * Must disable multi-rate retry when using RTS/CTS. 1169 */ 1170 if (!sc->sc_mrrprot) { 1171 bf->bf_state.bfs_ismrr = 0; 1172 bf->bf_state.bfs_try0 = 1173 bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */ 1174 } 1175} 1176 1177/* 1178 * Setup the descriptor chain for a normal or fast-frame 1179 * frame. 1180 * 1181 * XXX TODO: extend to include the destination hardware QCU ID. 1182 * Make sure that is correct. Make sure that when being added 1183 * to the mcastq, the CABQ QCUID is set or things will get a bit 1184 * odd. 1185 */ 1186static void 1187ath_tx_setds(struct ath_softc *sc, struct ath_buf *bf) 1188{ 1189 struct ath_desc *ds = bf->bf_desc; 1190 struct ath_hal *ah = sc->sc_ah; 1191 1192 ath_hal_setuptxdesc(ah, ds 1193 , bf->bf_state.bfs_pktlen /* packet length */ 1194 , bf->bf_state.bfs_hdrlen /* header length */ 1195 , bf->bf_state.bfs_atype /* Atheros packet type */ 1196 , bf->bf_state.bfs_txpower /* txpower */ 1197 , bf->bf_state.bfs_txrate0 1198 , bf->bf_state.bfs_try0 /* series 0 rate/tries */ 1199 , bf->bf_state.bfs_keyix /* key cache index */ 1200 , bf->bf_state.bfs_txantenna /* antenna mode */ 1201 , bf->bf_state.bfs_txflags /* flags */ 1202 , bf->bf_state.bfs_ctsrate /* rts/cts rate */ 1203 , bf->bf_state.bfs_ctsduration /* rts/cts duration */ 1204 ); 1205 1206 /* 1207 * This will be overriden when the descriptor chain is written. 1208 */ 1209 bf->bf_lastds = ds; 1210 bf->bf_last = bf; 1211 1212 /* Set rate control and descriptor chain for this frame */ 1213 ath_tx_set_ratectrl(sc, bf->bf_node, bf); 1214 ath_tx_chaindesclist(sc, bf); 1215} 1216 1217/* 1218 * Do a rate lookup. 1219 * 1220 * This performs a rate lookup for the given ath_buf only if it's required. 1221 * Non-data frames and raw frames don't require it. 1222 * 1223 * This populates the primary and MRR entries; MRR values are 1224 * then disabled later on if something requires it (eg RTS/CTS on 1225 * pre-11n chipsets. 1226 * 1227 * This needs to be done before the RTS/CTS fields are calculated 1228 * as they may depend upon the rate chosen. 1229 */ 1230static void 1231ath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf) 1232{ 1233 uint8_t rate, rix; 1234 int try0; 1235 1236 if (! bf->bf_state.bfs_doratelookup) 1237 return; 1238 1239 /* Get rid of any previous state */ 1240 bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1241 1242 ATH_NODE_LOCK(ATH_NODE(bf->bf_node)); 1243 ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream, 1244 bf->bf_state.bfs_pktlen, &rix, &try0, &rate); 1245 1246 /* In case MRR is disabled, make sure rc[0] is setup correctly */ 1247 bf->bf_state.bfs_rc[0].rix = rix; 1248 bf->bf_state.bfs_rc[0].ratecode = rate; 1249 bf->bf_state.bfs_rc[0].tries = try0; 1250 1251 if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY) 1252 ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix, 1253 bf->bf_state.bfs_rc); 1254 ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node)); 1255 1256 sc->sc_txrix = rix; /* for LED blinking */ 1257 sc->sc_lastdatarix = rix; /* for fast frames */ 1258 bf->bf_state.bfs_try0 = try0; 1259 bf->bf_state.bfs_txrate0 = rate; 1260} 1261 1262/* 1263 * Transmit the given frame to the hardware. 1264 * 1265 * The frame must already be setup; rate control must already have 1266 * been done. 1267 * 1268 * XXX since the TXQ lock is being held here (and I dislike holding 1269 * it for this long when not doing software aggregation), later on 1270 * break this function into "setup_normal" and "xmit_normal". The 1271 * lock only needs to be held for the ath_tx_handoff call. 1272 */ 1273static void 1274ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq, 1275 struct ath_buf *bf) 1276{ 1277 1278 ATH_TXQ_LOCK_ASSERT(txq); 1279 1280 /* Setup the descriptor before handoff */ 1281 ath_tx_do_ratelookup(sc, bf); 1282 ath_tx_calc_duration(sc, bf); 1283 ath_tx_calc_protection(sc, bf); 1284 ath_tx_set_rtscts(sc, bf); 1285 ath_tx_rate_fill_rcflags(sc, bf); 1286 ath_tx_setds(sc, bf); 1287 1288 /* Hand off to hardware */ 1289 ath_tx_handoff(sc, txq, bf); 1290} 1291 1292/* 1293 * Do the basic frame setup stuff that's required before the frame 1294 * is added to a software queue. 1295 * 1296 * All frames get mostly the same treatment and it's done once. 1297 * Retransmits fiddle with things like the rate control setup, 1298 * setting the retransmit bit in the packet; doing relevant DMA/bus 1299 * syncing and relinking it (back) into the hardware TX queue. 1300 * 1301 * Note that this may cause the mbuf to be reallocated, so 1302 * m0 may not be valid. 1303 */ 1304static int 1305ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni, 1306 struct ath_buf *bf, struct mbuf *m0, struct ath_txq *txq) 1307{ 1308 struct ieee80211vap *vap = ni->ni_vap; 1309 struct ath_hal *ah = sc->sc_ah; 1310 struct ifnet *ifp = sc->sc_ifp; 1311 struct ieee80211com *ic = ifp->if_l2com; 1312 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 1313 int error, iswep, ismcast, isfrag, ismrr; 1314 int keyix, hdrlen, pktlen, try0 = 0; 1315 u_int8_t rix = 0, txrate = 0; 1316 struct ath_desc *ds; 1317 struct ieee80211_frame *wh; 1318 u_int subtype, flags; 1319 HAL_PKT_TYPE atype; 1320 const HAL_RATE_TABLE *rt; 1321 HAL_BOOL shortPreamble; 1322 struct ath_node *an; 1323 u_int pri; 1324 1325 /* 1326 * To ensure that both sequence numbers and the CCMP PN handling 1327 * is "correct", make sure that the relevant TID queue is locked. 1328 * Otherwise the CCMP PN and seqno may appear out of order, causing 1329 * re-ordered frames to have out of order CCMP PN's, resulting 1330 * in many, many frame drops. 1331 */ 1332 ATH_TXQ_LOCK_ASSERT(txq); 1333 1334 wh = mtod(m0, struct ieee80211_frame *); 1335 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1336 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1337 isfrag = m0->m_flags & M_FRAG; 1338 hdrlen = ieee80211_anyhdrsize(wh); 1339 /* 1340 * Packet length must not include any 1341 * pad bytes; deduct them here. 1342 */ 1343 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 1344 1345 /* Handle encryption twiddling if needed */ 1346 if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen, 1347 &pktlen, &keyix)) { 1348 ath_freetx(m0); 1349 return EIO; 1350 } 1351 1352 /* packet header may have moved, reset our local pointer */ 1353 wh = mtod(m0, struct ieee80211_frame *); 1354 1355 pktlen += IEEE80211_CRC_LEN; 1356 1357 /* 1358 * Load the DMA map so any coalescing is done. This 1359 * also calculates the number of descriptors we need. 1360 */ 1361 error = ath_tx_dmasetup(sc, bf, m0); 1362 if (error != 0) 1363 return error; 1364 bf->bf_node = ni; /* NB: held reference */ 1365 m0 = bf->bf_m; /* NB: may have changed */ 1366 wh = mtod(m0, struct ieee80211_frame *); 1367 1368 /* setup descriptors */ 1369 ds = bf->bf_desc; 1370 rt = sc->sc_currates; 1371 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1372 1373 /* 1374 * NB: the 802.11 layer marks whether or not we should 1375 * use short preamble based on the current mode and 1376 * negotiated parameters. 1377 */ 1378 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1379 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 1380 shortPreamble = AH_TRUE; 1381 sc->sc_stats.ast_tx_shortpre++; 1382 } else { 1383 shortPreamble = AH_FALSE; 1384 } 1385 1386 an = ATH_NODE(ni); 1387 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1388 ismrr = 0; /* default no multi-rate retry*/ 1389 pri = M_WME_GETAC(m0); /* honor classification */ 1390 /* XXX use txparams instead of fixed values */ 1391 /* 1392 * Calculate Atheros packet type from IEEE80211 packet header, 1393 * setup for rate calculations, and select h/w transmit queue. 1394 */ 1395 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1396 case IEEE80211_FC0_TYPE_MGT: 1397 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1398 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1399 atype = HAL_PKT_TYPE_BEACON; 1400 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1401 atype = HAL_PKT_TYPE_PROBE_RESP; 1402 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1403 atype = HAL_PKT_TYPE_ATIM; 1404 else 1405 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 1406 rix = an->an_mgmtrix; 1407 txrate = rt->info[rix].rateCode; 1408 if (shortPreamble) 1409 txrate |= rt->info[rix].shortPreamble; 1410 try0 = ATH_TXMGTTRY; 1411 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1412 break; 1413 case IEEE80211_FC0_TYPE_CTL: 1414 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 1415 rix = an->an_mgmtrix; 1416 txrate = rt->info[rix].rateCode; 1417 if (shortPreamble) 1418 txrate |= rt->info[rix].shortPreamble; 1419 try0 = ATH_TXMGTTRY; 1420 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1421 break; 1422 case IEEE80211_FC0_TYPE_DATA: 1423 atype = HAL_PKT_TYPE_NORMAL; /* default */ 1424 /* 1425 * Data frames: multicast frames go out at a fixed rate, 1426 * EAPOL frames use the mgmt frame rate; otherwise consult 1427 * the rate control module for the rate to use. 1428 */ 1429 if (ismcast) { 1430 rix = an->an_mcastrix; 1431 txrate = rt->info[rix].rateCode; 1432 if (shortPreamble) 1433 txrate |= rt->info[rix].shortPreamble; 1434 try0 = 1; 1435 } else if (m0->m_flags & M_EAPOL) { 1436 /* XXX? maybe always use long preamble? */ 1437 rix = an->an_mgmtrix; 1438 txrate = rt->info[rix].rateCode; 1439 if (shortPreamble) 1440 txrate |= rt->info[rix].shortPreamble; 1441 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 1442 } else { 1443 /* 1444 * Do rate lookup on each TX, rather than using 1445 * the hard-coded TX information decided here. 1446 */ 1447 ismrr = 1; 1448 bf->bf_state.bfs_doratelookup = 1; 1449 } 1450 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 1451 flags |= HAL_TXDESC_NOACK; 1452 break; 1453 default: 1454 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 1455 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1456 /* XXX statistic */ 1457 ath_freetx(m0); 1458 return EIO; 1459 } 1460 1461 /* 1462 * There are two known scenarios where the frame AC doesn't match 1463 * what the destination TXQ is. 1464 * 1465 * + non-QoS frames (eg management?) that the net80211 stack has 1466 * assigned a higher AC to, but since it's a non-QoS TID, it's 1467 * being thrown into TID 16. TID 16 gets the AC_BE queue. 1468 * It's quite possible that management frames should just be 1469 * direct dispatched to hardware rather than go via the software 1470 * queue; that should be investigated in the future. There are 1471 * some specific scenarios where this doesn't make sense, mostly 1472 * surrounding ADDBA request/response - hence why that is special 1473 * cased. 1474 * 1475 * + Multicast frames going into the VAP mcast queue. That shows up 1476 * as "TXQ 11". 1477 * 1478 * This driver should eventually support separate TID and TXQ locking, 1479 * allowing for arbitrary AC frames to appear on arbitrary software 1480 * queues, being queued to the "correct" hardware queue when needed. 1481 */ 1482#if 0 1483 if (txq != sc->sc_ac2q[pri]) { 1484 device_printf(sc->sc_dev, 1485 "%s: txq=%p (%d), pri=%d, pri txq=%p (%d)\n", 1486 __func__, 1487 txq, 1488 txq->axq_qnum, 1489 pri, 1490 sc->sc_ac2q[pri], 1491 sc->sc_ac2q[pri]->axq_qnum); 1492 } 1493#endif 1494 1495 /* 1496 * Calculate miscellaneous flags. 1497 */ 1498 if (ismcast) { 1499 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 1500 } else if (pktlen > vap->iv_rtsthreshold && 1501 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 1502 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 1503 sc->sc_stats.ast_tx_rts++; 1504 } 1505 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 1506 sc->sc_stats.ast_tx_noack++; 1507#ifdef IEEE80211_SUPPORT_TDMA 1508 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 1509 DPRINTF(sc, ATH_DEBUG_TDMA, 1510 "%s: discard frame, ACK required w/ TDMA\n", __func__); 1511 sc->sc_stats.ast_tdma_ack++; 1512 ath_freetx(m0); 1513 return EIO; 1514 } 1515#endif 1516 1517 /* 1518 * Determine if a tx interrupt should be generated for 1519 * this descriptor. We take a tx interrupt to reap 1520 * descriptors when the h/w hits an EOL condition or 1521 * when the descriptor is specifically marked to generate 1522 * an interrupt. We periodically mark descriptors in this 1523 * way to insure timely replenishing of the supply needed 1524 * for sending frames. Defering interrupts reduces system 1525 * load and potentially allows more concurrent work to be 1526 * done but if done to aggressively can cause senders to 1527 * backup. 1528 * 1529 * NB: use >= to deal with sc_txintrperiod changing 1530 * dynamically through sysctl. 1531 */ 1532 if (flags & HAL_TXDESC_INTREQ) { 1533 txq->axq_intrcnt = 0; 1534 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 1535 flags |= HAL_TXDESC_INTREQ; 1536 txq->axq_intrcnt = 0; 1537 } 1538 1539 /* This point forward is actual TX bits */ 1540 1541 /* 1542 * At this point we are committed to sending the frame 1543 * and we don't need to look at m_nextpkt; clear it in 1544 * case this frame is part of frag chain. 1545 */ 1546 m0->m_nextpkt = NULL; 1547 1548 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1549 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len, 1550 sc->sc_hwmap[rix].ieeerate, -1); 1551 1552 if (ieee80211_radiotap_active_vap(vap)) { 1553 u_int64_t tsf = ath_hal_gettsf64(ah); 1554 1555 sc->sc_tx_th.wt_tsf = htole64(tsf); 1556 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1557 if (iswep) 1558 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1559 if (isfrag) 1560 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1561 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1562 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 1563 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1564 1565 ieee80211_radiotap_tx(vap, m0); 1566 } 1567 1568 /* Blank the legacy rate array */ 1569 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1570 1571 /* 1572 * ath_buf_set_rate needs at least one rate/try to setup 1573 * the rate scenario. 1574 */ 1575 bf->bf_state.bfs_rc[0].rix = rix; 1576 bf->bf_state.bfs_rc[0].tries = try0; 1577 bf->bf_state.bfs_rc[0].ratecode = txrate; 1578 1579 /* Store the decided rate index values away */ 1580 bf->bf_state.bfs_pktlen = pktlen; 1581 bf->bf_state.bfs_hdrlen = hdrlen; 1582 bf->bf_state.bfs_atype = atype; 1583 bf->bf_state.bfs_txpower = ni->ni_txpower; 1584 bf->bf_state.bfs_txrate0 = txrate; 1585 bf->bf_state.bfs_try0 = try0; 1586 bf->bf_state.bfs_keyix = keyix; 1587 bf->bf_state.bfs_txantenna = sc->sc_txantenna; 1588 bf->bf_state.bfs_txflags = flags; 1589 bf->bf_state.bfs_shpream = shortPreamble; 1590 1591 /* XXX this should be done in ath_tx_setrate() */ 1592 bf->bf_state.bfs_ctsrate0 = 0; /* ie, no hard-coded ctsrate */ 1593 bf->bf_state.bfs_ctsrate = 0; /* calculated later */ 1594 bf->bf_state.bfs_ctsduration = 0; 1595 bf->bf_state.bfs_ismrr = ismrr; 1596 1597 return 0; 1598} 1599 1600/* 1601 * Direct-dispatch the current frame to the hardware. 1602 * 1603 * This can be called by the net80211 code. 1604 * 1605 * XXX what about locking? Or, push the seqno assign into the 1606 * XXX aggregate scheduler so its serialised? 1607 */ 1608int 1609ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, 1610 struct ath_buf *bf, struct mbuf *m0) 1611{ 1612 struct ieee80211vap *vap = ni->ni_vap; 1613 struct ath_vap *avp = ATH_VAP(vap); 1614 int r = 0; 1615 u_int pri; 1616 int tid; 1617 struct ath_txq *txq; 1618 int ismcast; 1619 const struct ieee80211_frame *wh; 1620 int is_ampdu, is_ampdu_tx, is_ampdu_pending; 1621 ieee80211_seq seqno; 1622 uint8_t type, subtype; 1623 1624 /* 1625 * Determine the target hardware queue. 1626 * 1627 * For multicast frames, the txq gets overridden appropriately 1628 * depending upon the state of PS. 1629 * 1630 * For any other frame, we do a TID/QoS lookup inside the frame 1631 * to see what the TID should be. If it's a non-QoS frame, the 1632 * AC and TID are overridden. The TID/TXQ code assumes the 1633 * TID is on a predictable hardware TXQ, so we don't support 1634 * having a node TID queued to multiple hardware TXQs. 1635 * This may change in the future but would require some locking 1636 * fudgery. 1637 */ 1638 pri = ath_tx_getac(sc, m0); 1639 tid = ath_tx_gettid(sc, m0); 1640 1641 txq = sc->sc_ac2q[pri]; 1642 wh = mtod(m0, struct ieee80211_frame *); 1643 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1644 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1645 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1646 1647 /* 1648 * Enforce how deep the multicast queue can grow. 1649 * 1650 * XXX duplicated in ath_raw_xmit(). 1651 */ 1652 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1653 ATH_TXQ_LOCK(sc->sc_cabq); 1654 1655 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 1656 sc->sc_stats.ast_tx_mcastq_overflow++; 1657 r = ENOBUFS; 1658 } 1659 1660 ATH_TXQ_UNLOCK(sc->sc_cabq); 1661 1662 if (r != 0) { 1663 m_freem(m0); 1664 return r; 1665 } 1666 } 1667 1668 /* A-MPDU TX */ 1669 is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid); 1670 is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid); 1671 is_ampdu = is_ampdu_tx | is_ampdu_pending; 1672 1673 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, ac=%d, is_ampdu=%d\n", 1674 __func__, tid, pri, is_ampdu); 1675 1676 /* Set local packet state, used to queue packets to hardware */ 1677 bf->bf_state.bfs_tid = tid; 1678 bf->bf_state.bfs_txq = txq; 1679 bf->bf_state.bfs_pri = pri; 1680 1681 /* 1682 * When servicing one or more stations in power-save mode 1683 * (or) if there is some mcast data waiting on the mcast 1684 * queue (to prevent out of order delivery) multicast frames 1685 * must be bufferd until after the beacon. 1686 * 1687 * TODO: we should lock the mcastq before we check the length. 1688 */ 1689 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) { 1690 txq = &avp->av_mcastq; 1691 /* 1692 * Mark the frame as eventually belonging on the CAB 1693 * queue, so the descriptor setup functions will 1694 * correctly initialise the descriptor 'qcuId' field. 1695 */ 1696 bf->bf_state.bfs_txq = sc->sc_cabq; 1697 } 1698 1699 /* Do the generic frame setup */ 1700 /* XXX should just bzero the bf_state? */ 1701 bf->bf_state.bfs_dobaw = 0; 1702 1703 /* 1704 * Acquire the TXQ lock early, so both the encap and seqno 1705 * are allocated together. 1706 * 1707 * XXX should TXQ for CABQ traffic be the multicast queue, 1708 * or the TXQ the given PRI would allocate from? (eg for 1709 * sequence number allocation locking.) 1710 */ 1711 ATH_TXQ_LOCK(txq); 1712 1713 /* A-MPDU TX? Manually set sequence number */ 1714 /* 1715 * Don't do it whilst pending; the net80211 layer still 1716 * assigns them. 1717 */ 1718 if (is_ampdu_tx) { 1719 /* 1720 * Always call; this function will 1721 * handle making sure that null data frames 1722 * don't get a sequence number from the current 1723 * TID and thus mess with the BAW. 1724 */ 1725 seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0); 1726 1727 /* 1728 * Don't add QoS NULL frames to the BAW. 1729 */ 1730 if (IEEE80211_QOS_HAS_SEQ(wh) && 1731 subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL) { 1732 bf->bf_state.bfs_dobaw = 1; 1733 } 1734 } 1735 1736 /* 1737 * If needed, the sequence number has been assigned. 1738 * Squirrel it away somewhere easy to get to. 1739 */ 1740 bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT; 1741 1742 /* Is ampdu pending? fetch the seqno and print it out */ 1743 if (is_ampdu_pending) 1744 DPRINTF(sc, ATH_DEBUG_SW_TX, 1745 "%s: tid %d: ampdu pending, seqno %d\n", 1746 __func__, tid, M_SEQNO_GET(m0)); 1747 1748 /* This also sets up the DMA map */ 1749 r = ath_tx_normal_setup(sc, ni, bf, m0, txq); 1750 1751 if (r != 0) 1752 goto done; 1753 1754 /* At this point m0 could have changed! */ 1755 m0 = bf->bf_m; 1756 1757#if 1 1758 /* 1759 * If it's a multicast frame, do a direct-dispatch to the 1760 * destination hardware queue. Don't bother software 1761 * queuing it. 1762 */ 1763 /* 1764 * If it's a BAR frame, do a direct dispatch to the 1765 * destination hardware queue. Don't bother software 1766 * queuing it, as the TID will now be paused. 1767 * Sending a BAR frame can occur from the net80211 txa timer 1768 * (ie, retries) or from the ath txtask (completion call.) 1769 * It queues directly to hardware because the TID is paused 1770 * at this point (and won't be unpaused until the BAR has 1771 * either been TXed successfully or max retries has been 1772 * reached.) 1773 */ 1774 if (txq == &avp->av_mcastq) { 1775 DPRINTF(sc, ATH_DEBUG_SW_TX, 1776 "%s: bf=%p: mcastq: TX'ing\n", __func__, bf); 1777 ath_tx_xmit_normal(sc, txq, bf); 1778 } else if (type == IEEE80211_FC0_TYPE_CTL && 1779 subtype == IEEE80211_FC0_SUBTYPE_BAR) { 1780 DPRINTF(sc, ATH_DEBUG_SW_TX, 1781 "%s: BAR: TX'ing direct\n", __func__); 1782 ath_tx_xmit_normal(sc, txq, bf); 1783 } else { 1784 /* add to software queue */ 1785 DPRINTF(sc, ATH_DEBUG_SW_TX, 1786 "%s: bf=%p: swq: TX'ing\n", __func__, bf); 1787 ath_tx_swq(sc, ni, txq, bf); 1788 } 1789#else 1790 /* 1791 * For now, since there's no software queue, 1792 * direct-dispatch to the hardware. 1793 */ 1794 ath_tx_xmit_normal(sc, txq, bf); 1795#endif 1796done: 1797 ATH_TXQ_UNLOCK(txq); 1798 1799 return 0; 1800} 1801 1802static int 1803ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 1804 struct ath_buf *bf, struct mbuf *m0, 1805 const struct ieee80211_bpf_params *params) 1806{ 1807 struct ifnet *ifp = sc->sc_ifp; 1808 struct ieee80211com *ic = ifp->if_l2com; 1809 struct ath_hal *ah = sc->sc_ah; 1810 struct ieee80211vap *vap = ni->ni_vap; 1811 int error, ismcast, ismrr; 1812 int keyix, hdrlen, pktlen, try0, txantenna; 1813 u_int8_t rix, txrate; 1814 struct ieee80211_frame *wh; 1815 u_int flags; 1816 HAL_PKT_TYPE atype; 1817 const HAL_RATE_TABLE *rt; 1818 struct ath_desc *ds; 1819 u_int pri; 1820 int o_tid = -1; 1821 int do_override; 1822 1823 wh = mtod(m0, struct ieee80211_frame *); 1824 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1825 hdrlen = ieee80211_anyhdrsize(wh); 1826 /* 1827 * Packet length must not include any 1828 * pad bytes; deduct them here. 1829 */ 1830 /* XXX honor IEEE80211_BPF_DATAPAD */ 1831 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 1832 1833 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n", 1834 __func__, ismcast); 1835 1836 pri = params->ibp_pri & 3; 1837 /* Override pri if the frame isn't a QoS one */ 1838 if (! IEEE80211_QOS_HAS_SEQ(wh)) 1839 pri = ath_tx_getac(sc, m0); 1840 1841 /* XXX If it's an ADDBA, override the correct queue */ 1842 do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid); 1843 1844 /* Map ADDBA to the correct priority */ 1845 if (do_override) { 1846#if 0 1847 device_printf(sc->sc_dev, 1848 "%s: overriding tid %d pri %d -> %d\n", 1849 __func__, o_tid, pri, TID_TO_WME_AC(o_tid)); 1850#endif 1851 pri = TID_TO_WME_AC(o_tid); 1852 } 1853 1854 ATH_TXQ_LOCK(sc->sc_ac2q[pri]); 1855 1856 /* Handle encryption twiddling if needed */ 1857 if (! ath_tx_tag_crypto(sc, ni, 1858 m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0, 1859 &hdrlen, &pktlen, &keyix)) { 1860 ath_freetx(m0); 1861 return EIO; 1862 } 1863 /* packet header may have moved, reset our local pointer */ 1864 wh = mtod(m0, struct ieee80211_frame *); 1865 1866 /* Do the generic frame setup */ 1867 /* XXX should just bzero the bf_state? */ 1868 bf->bf_state.bfs_dobaw = 0; 1869 1870 error = ath_tx_dmasetup(sc, bf, m0); 1871 if (error != 0) 1872 return error; 1873 m0 = bf->bf_m; /* NB: may have changed */ 1874 wh = mtod(m0, struct ieee80211_frame *); 1875 bf->bf_node = ni; /* NB: held reference */ 1876 1877 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1878 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1879 if (params->ibp_flags & IEEE80211_BPF_RTS) 1880 flags |= HAL_TXDESC_RTSENA; 1881 else if (params->ibp_flags & IEEE80211_BPF_CTS) { 1882 /* XXX assume 11g/11n protection? */ 1883 bf->bf_state.bfs_doprot = 1; 1884 flags |= HAL_TXDESC_CTSENA; 1885 } 1886 /* XXX leave ismcast to injector? */ 1887 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 1888 flags |= HAL_TXDESC_NOACK; 1889 1890 rt = sc->sc_currates; 1891 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1892 rix = ath_tx_findrix(sc, params->ibp_rate0); 1893 txrate = rt->info[rix].rateCode; 1894 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 1895 txrate |= rt->info[rix].shortPreamble; 1896 sc->sc_txrix = rix; 1897 try0 = params->ibp_try0; 1898 ismrr = (params->ibp_try1 != 0); 1899 txantenna = params->ibp_pri >> 2; 1900 if (txantenna == 0) /* XXX? */ 1901 txantenna = sc->sc_txantenna; 1902 1903 /* 1904 * Since ctsrate is fixed, store it away for later 1905 * use when the descriptor fields are being set. 1906 */ 1907 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) 1908 bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate; 1909 1910 /* 1911 * NB: we mark all packets as type PSPOLL so the h/w won't 1912 * set the sequence number, duration, etc. 1913 */ 1914 atype = HAL_PKT_TYPE_PSPOLL; 1915 1916 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1917 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 1918 sc->sc_hwmap[rix].ieeerate, -1); 1919 1920 if (ieee80211_radiotap_active_vap(vap)) { 1921 u_int64_t tsf = ath_hal_gettsf64(ah); 1922 1923 sc->sc_tx_th.wt_tsf = htole64(tsf); 1924 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1925 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1926 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1927 if (m0->m_flags & M_FRAG) 1928 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1929 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1930 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 1931 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1932 1933 ieee80211_radiotap_tx(vap, m0); 1934 } 1935 1936 /* 1937 * Formulate first tx descriptor with tx controls. 1938 */ 1939 ds = bf->bf_desc; 1940 /* XXX check return value? */ 1941 1942 /* Store the decided rate index values away */ 1943 bf->bf_state.bfs_pktlen = pktlen; 1944 bf->bf_state.bfs_hdrlen = hdrlen; 1945 bf->bf_state.bfs_atype = atype; 1946 bf->bf_state.bfs_txpower = params->ibp_power; 1947 bf->bf_state.bfs_txrate0 = txrate; 1948 bf->bf_state.bfs_try0 = try0; 1949 bf->bf_state.bfs_keyix = keyix; 1950 bf->bf_state.bfs_txantenna = txantenna; 1951 bf->bf_state.bfs_txflags = flags; 1952 bf->bf_state.bfs_shpream = 1953 !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE); 1954 1955 /* Set local packet state, used to queue packets to hardware */ 1956 bf->bf_state.bfs_tid = WME_AC_TO_TID(pri); 1957 bf->bf_state.bfs_txq = sc->sc_ac2q[pri]; 1958 bf->bf_state.bfs_pri = pri; 1959 1960 /* XXX this should be done in ath_tx_setrate() */ 1961 bf->bf_state.bfs_ctsrate = 0; 1962 bf->bf_state.bfs_ctsduration = 0; 1963 bf->bf_state.bfs_ismrr = ismrr; 1964 1965 /* Blank the legacy rate array */ 1966 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1967 1968 bf->bf_state.bfs_rc[0].rix = 1969 ath_tx_findrix(sc, params->ibp_rate0); 1970 bf->bf_state.bfs_rc[0].tries = try0; 1971 bf->bf_state.bfs_rc[0].ratecode = txrate; 1972 1973 if (ismrr) { 1974 int rix; 1975 1976 rix = ath_tx_findrix(sc, params->ibp_rate1); 1977 bf->bf_state.bfs_rc[1].rix = rix; 1978 bf->bf_state.bfs_rc[1].tries = params->ibp_try1; 1979 1980 rix = ath_tx_findrix(sc, params->ibp_rate2); 1981 bf->bf_state.bfs_rc[2].rix = rix; 1982 bf->bf_state.bfs_rc[2].tries = params->ibp_try2; 1983 1984 rix = ath_tx_findrix(sc, params->ibp_rate3); 1985 bf->bf_state.bfs_rc[3].rix = rix; 1986 bf->bf_state.bfs_rc[3].tries = params->ibp_try3; 1987 } 1988 /* 1989 * All the required rate control decisions have been made; 1990 * fill in the rc flags. 1991 */ 1992 ath_tx_rate_fill_rcflags(sc, bf); 1993 1994 /* NB: no buffered multicast in power save support */ 1995 1996 /* 1997 * If we're overiding the ADDBA destination, dump directly 1998 * into the hardware queue, right after any pending 1999 * frames to that node are. 2000 */ 2001 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n", 2002 __func__, do_override); 2003 2004 if (do_override) { 2005 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf); 2006 } else { 2007 /* Queue to software queue */ 2008 ath_tx_swq(sc, ni, sc->sc_ac2q[pri], bf); 2009 } 2010 ATH_TXQ_UNLOCK(sc->sc_ac2q[pri]); 2011 2012 return 0; 2013} 2014 2015/* 2016 * Send a raw frame. 2017 * 2018 * This can be called by net80211. 2019 */ 2020int 2021ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2022 const struct ieee80211_bpf_params *params) 2023{ 2024 struct ieee80211com *ic = ni->ni_ic; 2025 struct ifnet *ifp = ic->ic_ifp; 2026 struct ath_softc *sc = ifp->if_softc; 2027 struct ath_buf *bf; 2028 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2029 int error = 0; 2030 2031 ATH_PCU_LOCK(sc); 2032 if (sc->sc_inreset_cnt > 0) { 2033 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; bailing\n", 2034 __func__); 2035 error = EIO; 2036 ATH_PCU_UNLOCK(sc); 2037 goto bad0; 2038 } 2039 sc->sc_txstart_cnt++; 2040 ATH_PCU_UNLOCK(sc); 2041 2042 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 2043 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 2044 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ? 2045 "!running" : "invalid"); 2046 m_freem(m); 2047 error = ENETDOWN; 2048 goto bad; 2049 } 2050 2051 /* 2052 * Enforce how deep the multicast queue can grow. 2053 * 2054 * XXX duplicated in ath_tx_start(). 2055 */ 2056 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2057 ATH_TXQ_LOCK(sc->sc_cabq); 2058 2059 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 2060 sc->sc_stats.ast_tx_mcastq_overflow++; 2061 error = ENOBUFS; 2062 } 2063 2064 ATH_TXQ_UNLOCK(sc->sc_cabq); 2065 2066 if (error != 0) { 2067 m_freem(m); 2068 goto bad; 2069 } 2070 } 2071 2072 /* 2073 * Grab a TX buffer and associated resources. 2074 */ 2075 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT); 2076 if (bf == NULL) { 2077 sc->sc_stats.ast_tx_nobuf++; 2078 m_freem(m); 2079 error = ENOBUFS; 2080 goto bad; 2081 } 2082 2083 if (params == NULL) { 2084 /* 2085 * Legacy path; interpret frame contents to decide 2086 * precisely how to send the frame. 2087 */ 2088 if (ath_tx_start(sc, ni, bf, m)) { 2089 error = EIO; /* XXX */ 2090 goto bad2; 2091 } 2092 } else { 2093 /* 2094 * Caller supplied explicit parameters to use in 2095 * sending the frame. 2096 */ 2097 if (ath_tx_raw_start(sc, ni, bf, m, params)) { 2098 error = EIO; /* XXX */ 2099 goto bad2; 2100 } 2101 } 2102 sc->sc_wd_timer = 5; 2103 ifp->if_opackets++; 2104 sc->sc_stats.ast_tx_raw++; 2105 2106 ATH_PCU_LOCK(sc); 2107 sc->sc_txstart_cnt--; 2108 ATH_PCU_UNLOCK(sc); 2109 2110 return 0; 2111bad2: 2112 ATH_TXBUF_LOCK(sc); 2113 ath_returnbuf_head(sc, bf); 2114 ATH_TXBUF_UNLOCK(sc); 2115bad: 2116 ATH_PCU_LOCK(sc); 2117 sc->sc_txstart_cnt--; 2118 ATH_PCU_UNLOCK(sc); 2119bad0: 2120 ifp->if_oerrors++; 2121 sc->sc_stats.ast_tx_raw_fail++; 2122 ieee80211_free_node(ni); 2123 2124 return error; 2125} 2126 2127/* Some helper functions */ 2128 2129/* 2130 * ADDBA (and potentially others) need to be placed in the same 2131 * hardware queue as the TID/node it's relating to. This is so 2132 * it goes out after any pending non-aggregate frames to the 2133 * same node/TID. 2134 * 2135 * If this isn't done, the ADDBA can go out before the frames 2136 * queued in hardware. Even though these frames have a sequence 2137 * number -earlier- than the ADDBA can be transmitted (but 2138 * no frames whose sequence numbers are after the ADDBA should 2139 * be!) they'll arrive after the ADDBA - and the receiving end 2140 * will simply drop them as being out of the BAW. 2141 * 2142 * The frames can't be appended to the TID software queue - it'll 2143 * never be sent out. So these frames have to be directly 2144 * dispatched to the hardware, rather than queued in software. 2145 * So if this function returns true, the TXQ has to be 2146 * overridden and it has to be directly dispatched. 2147 * 2148 * It's a dirty hack, but someone's gotta do it. 2149 */ 2150 2151/* 2152 * XXX doesn't belong here! 2153 */ 2154static int 2155ieee80211_is_action(struct ieee80211_frame *wh) 2156{ 2157 /* Type: Management frame? */ 2158 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 2159 IEEE80211_FC0_TYPE_MGT) 2160 return 0; 2161 2162 /* Subtype: Action frame? */ 2163 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) != 2164 IEEE80211_FC0_SUBTYPE_ACTION) 2165 return 0; 2166 2167 return 1; 2168} 2169 2170#define MS(_v, _f) (((_v) & _f) >> _f##_S) 2171/* 2172 * Return an alternate TID for ADDBA request frames. 2173 * 2174 * Yes, this likely should be done in the net80211 layer. 2175 */ 2176static int 2177ath_tx_action_frame_override_queue(struct ath_softc *sc, 2178 struct ieee80211_node *ni, 2179 struct mbuf *m0, int *tid) 2180{ 2181 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 2182 struct ieee80211_action_ba_addbarequest *ia; 2183 uint8_t *frm; 2184 uint16_t baparamset; 2185 2186 /* Not action frame? Bail */ 2187 if (! ieee80211_is_action(wh)) 2188 return 0; 2189 2190 /* XXX Not needed for frames we send? */ 2191#if 0 2192 /* Correct length? */ 2193 if (! ieee80211_parse_action(ni, m)) 2194 return 0; 2195#endif 2196 2197 /* Extract out action frame */ 2198 frm = (u_int8_t *)&wh[1]; 2199 ia = (struct ieee80211_action_ba_addbarequest *) frm; 2200 2201 /* Not ADDBA? Bail */ 2202 if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA) 2203 return 0; 2204 if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST) 2205 return 0; 2206 2207 /* Extract TID, return it */ 2208 baparamset = le16toh(ia->rq_baparamset); 2209 *tid = (int) MS(baparamset, IEEE80211_BAPS_TID); 2210 2211 return 1; 2212} 2213#undef MS 2214 2215/* Per-node software queue operations */ 2216 2217/* 2218 * Add the current packet to the given BAW. 2219 * It is assumed that the current packet 2220 * 2221 * + fits inside the BAW; 2222 * + already has had a sequence number allocated. 2223 * 2224 * Since the BAW status may be modified by both the ath task and 2225 * the net80211/ifnet contexts, the TID must be locked. 2226 */ 2227void 2228ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an, 2229 struct ath_tid *tid, struct ath_buf *bf) 2230{ 2231 int index, cindex; 2232 struct ieee80211_tx_ampdu *tap; 2233 2234 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2235 ATH_TID_LOCK_ASSERT(sc, tid); 2236 2237 if (bf->bf_state.bfs_isretried) 2238 return; 2239 2240 tap = ath_tx_get_tx_tid(an, tid->tid); 2241 2242 if (! bf->bf_state.bfs_dobaw) { 2243 device_printf(sc->sc_dev, 2244 "%s: dobaw=0, seqno=%d, window %d:%d\n", 2245 __func__, 2246 SEQNO(bf->bf_state.bfs_seqno), 2247 tap->txa_start, 2248 tap->txa_wnd); 2249 } 2250 2251 if (bf->bf_state.bfs_addedbaw) 2252 device_printf(sc->sc_dev, 2253 "%s: re-added? tid=%d, seqno %d; window %d:%d; " 2254 "baw head=%d tail=%d\n", 2255 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2256 tap->txa_start, tap->txa_wnd, tid->baw_head, 2257 tid->baw_tail); 2258 2259 /* 2260 * Verify that the given sequence number is not outside of the 2261 * BAW. Complain loudly if that's the case. 2262 */ 2263 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2264 SEQNO(bf->bf_state.bfs_seqno))) { 2265 device_printf(sc->sc_dev, 2266 "%s: bf=%p: outside of BAW?? tid=%d, seqno %d; window %d:%d; " 2267 "baw head=%d tail=%d\n", 2268 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2269 tap->txa_start, tap->txa_wnd, tid->baw_head, 2270 tid->baw_tail); 2271 } 2272 2273 /* 2274 * ni->ni_txseqs[] is the currently allocated seqno. 2275 * the txa state contains the current baw start. 2276 */ 2277 index = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno)); 2278 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2279 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2280 "%s: tid=%d, seqno %d; window %d:%d; index=%d cindex=%d " 2281 "baw head=%d tail=%d\n", 2282 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2283 tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head, 2284 tid->baw_tail); 2285 2286 2287#if 0 2288 assert(tid->tx_buf[cindex] == NULL); 2289#endif 2290 if (tid->tx_buf[cindex] != NULL) { 2291 device_printf(sc->sc_dev, 2292 "%s: ba packet dup (index=%d, cindex=%d, " 2293 "head=%d, tail=%d)\n", 2294 __func__, index, cindex, tid->baw_head, tid->baw_tail); 2295 device_printf(sc->sc_dev, 2296 "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n", 2297 __func__, 2298 tid->tx_buf[cindex], 2299 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno), 2300 bf, 2301 SEQNO(bf->bf_state.bfs_seqno) 2302 ); 2303 } 2304 tid->tx_buf[cindex] = bf; 2305 2306 if (index >= ((tid->baw_tail - tid->baw_head) & 2307 (ATH_TID_MAX_BUFS - 1))) { 2308 tid->baw_tail = cindex; 2309 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 2310 } 2311} 2312 2313/* 2314 * Flip the BAW buffer entry over from the existing one to the new one. 2315 * 2316 * When software retransmitting a (sub-)frame, it is entirely possible that 2317 * the frame ath_buf is marked as BUSY and can't be immediately reused. 2318 * In that instance the buffer is cloned and the new buffer is used for 2319 * retransmit. We thus need to update the ath_buf slot in the BAW buf 2320 * tracking array to maintain consistency. 2321 */ 2322static void 2323ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an, 2324 struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf) 2325{ 2326 int index, cindex; 2327 struct ieee80211_tx_ampdu *tap; 2328 int seqno = SEQNO(old_bf->bf_state.bfs_seqno); 2329 2330 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2331 ATH_TID_LOCK_ASSERT(sc, tid); 2332 2333 tap = ath_tx_get_tx_tid(an, tid->tid); 2334 index = ATH_BA_INDEX(tap->txa_start, seqno); 2335 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2336 2337 /* 2338 * Just warn for now; if it happens then we should find out 2339 * about it. It's highly likely the aggregation session will 2340 * soon hang. 2341 */ 2342 if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) { 2343 device_printf(sc->sc_dev, "%s: retransmitted buffer" 2344 " has mismatching seqno's, BA session may hang.\n", 2345 __func__); 2346 device_printf(sc->sc_dev, "%s: old seqno=%d, new_seqno=%d\n", 2347 __func__, 2348 old_bf->bf_state.bfs_seqno, 2349 new_bf->bf_state.bfs_seqno); 2350 } 2351 2352 if (tid->tx_buf[cindex] != old_bf) { 2353 device_printf(sc->sc_dev, "%s: ath_buf pointer incorrect; " 2354 " has m BA session may hang.\n", 2355 __func__); 2356 device_printf(sc->sc_dev, "%s: old bf=%p, new bf=%p\n", 2357 __func__, 2358 old_bf, new_bf); 2359 } 2360 2361 tid->tx_buf[cindex] = new_bf; 2362} 2363 2364/* 2365 * seq_start - left edge of BAW 2366 * seq_next - current/next sequence number to allocate 2367 * 2368 * Since the BAW status may be modified by both the ath task and 2369 * the net80211/ifnet contexts, the TID must be locked. 2370 */ 2371static void 2372ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an, 2373 struct ath_tid *tid, const struct ath_buf *bf) 2374{ 2375 int index, cindex; 2376 struct ieee80211_tx_ampdu *tap; 2377 int seqno = SEQNO(bf->bf_state.bfs_seqno); 2378 2379 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2380 ATH_TID_LOCK_ASSERT(sc, tid); 2381 2382 tap = ath_tx_get_tx_tid(an, tid->tid); 2383 index = ATH_BA_INDEX(tap->txa_start, seqno); 2384 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2385 2386 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2387 "%s: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, " 2388 "baw head=%d, tail=%d\n", 2389 __func__, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index, 2390 cindex, tid->baw_head, tid->baw_tail); 2391 2392 /* 2393 * If this occurs then we have a big problem - something else 2394 * has slid tap->txa_start along without updating the BAW 2395 * tracking start/end pointers. Thus the TX BAW state is now 2396 * completely busted. 2397 * 2398 * But for now, since I haven't yet fixed TDMA and buffer cloning, 2399 * it's quite possible that a cloned buffer is making its way 2400 * here and causing it to fire off. Disable TDMA for now. 2401 */ 2402 if (tid->tx_buf[cindex] != bf) { 2403 device_printf(sc->sc_dev, 2404 "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n", 2405 __func__, 2406 bf, SEQNO(bf->bf_state.bfs_seqno), 2407 tid->tx_buf[cindex], 2408 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno)); 2409 } 2410 2411 tid->tx_buf[cindex] = NULL; 2412 2413 while (tid->baw_head != tid->baw_tail && 2414 !tid->tx_buf[tid->baw_head]) { 2415 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 2416 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 2417 } 2418 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2419 "%s: baw is now %d:%d, baw head=%d\n", 2420 __func__, tap->txa_start, tap->txa_wnd, tid->baw_head); 2421} 2422 2423/* 2424 * Mark the current node/TID as ready to TX. 2425 * 2426 * This is done to make it easy for the software scheduler to 2427 * find which nodes have data to send. 2428 * 2429 * The TXQ lock must be held. 2430 */ 2431static void 2432ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid) 2433{ 2434 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2435 2436 ATH_TXQ_LOCK_ASSERT(txq); 2437 2438 if (tid->paused) 2439 return; /* paused, can't schedule yet */ 2440 2441 if (tid->sched) 2442 return; /* already scheduled */ 2443 2444 tid->sched = 1; 2445 2446 TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem); 2447} 2448 2449/* 2450 * Mark the current node as no longer needing to be polled for 2451 * TX packets. 2452 * 2453 * The TXQ lock must be held. 2454 */ 2455static void 2456ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid) 2457{ 2458 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2459 2460 ATH_TXQ_LOCK_ASSERT(txq); 2461 2462 if (tid->sched == 0) 2463 return; 2464 2465 tid->sched = 0; 2466 TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem); 2467} 2468 2469/* 2470 * Assign a sequence number manually to the given frame. 2471 * 2472 * This should only be called for A-MPDU TX frames. 2473 */ 2474static ieee80211_seq 2475ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni, 2476 struct ath_buf *bf, struct mbuf *m0) 2477{ 2478 struct ieee80211_frame *wh; 2479 int tid, pri; 2480 ieee80211_seq seqno; 2481 uint8_t subtype; 2482 2483 /* TID lookup */ 2484 wh = mtod(m0, struct ieee80211_frame *); 2485 pri = M_WME_GETAC(m0); /* honor classification */ 2486 tid = WME_AC_TO_TID(pri); 2487 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pri=%d, tid=%d, qos has seq=%d\n", 2488 __func__, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2489 2490 /* XXX Is it a control frame? Ignore */ 2491 2492 /* Does the packet require a sequence number? */ 2493 if (! IEEE80211_QOS_HAS_SEQ(wh)) 2494 return -1; 2495 2496 ATH_TID_LOCK_ASSERT(sc, &(ATH_NODE(ni)->an_tid[tid])); 2497 2498 /* 2499 * Is it a QOS NULL Data frame? Give it a sequence number from 2500 * the default TID (IEEE80211_NONQOS_TID.) 2501 * 2502 * The RX path of everything I've looked at doesn't include the NULL 2503 * data frame sequence number in the aggregation state updates, so 2504 * assigning it a sequence number there will cause a BAW hole on the 2505 * RX side. 2506 */ 2507 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2508 if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) { 2509 /* XXX no locking for this TID? This is a bit of a problem. */ 2510 seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID]; 2511 INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE); 2512 } else { 2513 /* Manually assign sequence number */ 2514 seqno = ni->ni_txseqs[tid]; 2515 INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE); 2516 } 2517 *(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 2518 M_SEQNO_SET(m0, seqno); 2519 2520 /* Return so caller can do something with it if needed */ 2521 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: -> seqno=%d\n", __func__, seqno); 2522 return seqno; 2523} 2524 2525/* 2526 * Attempt to direct dispatch an aggregate frame to hardware. 2527 * If the frame is out of BAW, queue. 2528 * Otherwise, schedule it as a single frame. 2529 */ 2530static void 2531ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an, 2532 struct ath_txq *txq, struct ath_buf *bf) 2533{ 2534 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid]; 2535// struct ath_txq *txq = bf->bf_state.bfs_txq; 2536 struct ieee80211_tx_ampdu *tap; 2537 2538 if (txq != bf->bf_state.bfs_txq) { 2539 device_printf(sc->sc_dev, "%s: txq %d != bfs_txq %d!\n", 2540 __func__, 2541 txq->axq_qnum, 2542 bf->bf_state.bfs_txq->axq_qnum); 2543 } 2544 2545 ATH_TXQ_LOCK_ASSERT(txq); 2546 ATH_TID_LOCK_ASSERT(sc, tid); 2547 2548 tap = ath_tx_get_tx_tid(an, tid->tid); 2549 2550 /* paused? queue */ 2551 if (tid->paused) { 2552 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 2553 /* XXX don't sched - we're paused! */ 2554 return; 2555 } 2556 2557 /* outside baw? queue */ 2558 if (bf->bf_state.bfs_dobaw && 2559 (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2560 SEQNO(bf->bf_state.bfs_seqno)))) { 2561 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 2562 ath_tx_tid_sched(sc, tid); 2563 return; 2564 } 2565 2566 /* 2567 * This is a temporary check and should be removed once 2568 * all the relevant code paths have been fixed. 2569 * 2570 * During aggregate retries, it's possible that the head 2571 * frame will fail (which has the bfs_aggr and bfs_nframes 2572 * fields set for said aggregate) and will be retried as 2573 * a single frame. In this instance, the values should 2574 * be reset or the completion code will get upset with you. 2575 */ 2576 if (bf->bf_state.bfs_aggr != 0 || bf->bf_state.bfs_nframes > 1) { 2577 device_printf(sc->sc_dev, "%s: bfs_aggr=%d, bfs_nframes=%d\n", 2578 __func__, 2579 bf->bf_state.bfs_aggr, 2580 bf->bf_state.bfs_nframes); 2581 bf->bf_state.bfs_aggr = 0; 2582 bf->bf_state.bfs_nframes = 1; 2583 } 2584 2585 /* Direct dispatch to hardware */ 2586 ath_tx_do_ratelookup(sc, bf); 2587 ath_tx_calc_duration(sc, bf); 2588 ath_tx_calc_protection(sc, bf); 2589 ath_tx_set_rtscts(sc, bf); 2590 ath_tx_rate_fill_rcflags(sc, bf); 2591 ath_tx_setds(sc, bf); 2592 2593 /* Statistics */ 2594 sc->sc_aggr_stats.aggr_low_hwq_single_pkt++; 2595 2596 /* Track per-TID hardware queue depth correctly */ 2597 tid->hwq_depth++; 2598 2599 /* Add to BAW */ 2600 if (bf->bf_state.bfs_dobaw) { 2601 ath_tx_addto_baw(sc, an, tid, bf); 2602 bf->bf_state.bfs_addedbaw = 1; 2603 } 2604 2605 /* Set completion handler, multi-frame aggregate or not */ 2606 bf->bf_comp = ath_tx_aggr_comp; 2607 2608 /* Hand off to hardware */ 2609 ath_tx_handoff(sc, txq, bf); 2610} 2611 2612/* 2613 * Attempt to send the packet. 2614 * If the queue isn't busy, direct-dispatch. 2615 * If the queue is busy enough, queue the given packet on the 2616 * relevant software queue. 2617 */ 2618void 2619ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_txq *txq, 2620 struct ath_buf *bf) 2621{ 2622 struct ath_node *an = ATH_NODE(ni); 2623 struct ieee80211_frame *wh; 2624 struct ath_tid *atid; 2625 int pri, tid; 2626 struct mbuf *m0 = bf->bf_m; 2627 2628 ATH_TXQ_LOCK_ASSERT(txq); 2629 2630 /* Fetch the TID - non-QoS frames get assigned to TID 16 */ 2631 wh = mtod(m0, struct ieee80211_frame *); 2632 pri = ath_tx_getac(sc, m0); 2633 tid = ath_tx_gettid(sc, m0); 2634 atid = &an->an_tid[tid]; 2635 2636 ATH_TID_LOCK_ASSERT(sc, atid); 2637 2638 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d\n", 2639 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2640 2641 /* Set local packet state, used to queue packets to hardware */ 2642 /* XXX potentially duplicate info, re-check */ 2643 /* XXX remember, txq must be the hardware queue, not the av_mcastq */ 2644 bf->bf_state.bfs_tid = tid; 2645 bf->bf_state.bfs_txq = txq; 2646 bf->bf_state.bfs_pri = pri; 2647 2648 /* 2649 * If the hardware queue isn't busy, queue it directly. 2650 * If the hardware queue is busy, queue it. 2651 * If the TID is paused or the traffic it outside BAW, software 2652 * queue it. 2653 */ 2654 if (atid->paused) { 2655 /* TID is paused, queue */ 2656 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: paused\n", __func__); 2657 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2658 } else if (ath_tx_ampdu_pending(sc, an, tid)) { 2659 /* AMPDU pending; queue */ 2660 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pending\n", __func__); 2661 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2662 /* XXX sched? */ 2663 } else if (ath_tx_ampdu_running(sc, an, tid)) { 2664 /* AMPDU running, attempt direct dispatch if possible */ 2665 2666 /* 2667 * Always queue the frame to the tail of the list. 2668 */ 2669 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2670 2671 /* 2672 * If the hardware queue isn't busy, direct dispatch 2673 * the head frame in the list. Don't schedule the 2674 * TID - let it build some more frames first? 2675 * 2676 * Otherwise, schedule the TID. 2677 */ 2678 if (txq->axq_depth < sc->sc_hwq_limit) { 2679 bf = TAILQ_FIRST(&atid->axq_q); 2680 ATH_TXQ_REMOVE(atid, bf, bf_list); 2681 2682 /* 2683 * Ensure it's definitely treated as a non-AMPDU 2684 * frame - this information may have been left 2685 * over from a previous attempt. 2686 */ 2687 bf->bf_state.bfs_aggr = 0; 2688 bf->bf_state.bfs_nframes = 1; 2689 2690 /* Queue to the hardware */ 2691 ath_tx_xmit_aggr(sc, an, txq, bf); 2692 DPRINTF(sc, ATH_DEBUG_SW_TX, 2693 "%s: xmit_aggr\n", 2694 __func__); 2695 } else { 2696 DPRINTF(sc, ATH_DEBUG_SW_TX, 2697 "%s: ampdu; swq'ing\n", 2698 __func__); 2699 ath_tx_tid_sched(sc, atid); 2700 } 2701 } else if (txq->axq_depth < sc->sc_hwq_limit) { 2702 /* AMPDU not running, attempt direct dispatch */ 2703 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: xmit_normal\n", __func__); 2704 ath_tx_xmit_normal(sc, txq, bf); 2705 } else { 2706 /* Busy; queue */ 2707 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: swq'ing\n", __func__); 2708 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2709 ath_tx_tid_sched(sc, atid); 2710 } 2711} 2712 2713/* 2714 * Configure the per-TID node state. 2715 * 2716 * This likely belongs in if_ath_node.c but I can't think of anywhere 2717 * else to put it just yet. 2718 * 2719 * This sets up the SLISTs and the mutex as appropriate. 2720 */ 2721void 2722ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an) 2723{ 2724 int i, j; 2725 struct ath_tid *atid; 2726 2727 for (i = 0; i < IEEE80211_TID_SIZE; i++) { 2728 atid = &an->an_tid[i]; 2729 2730 /* XXX now with this bzer(), is the field 0'ing needed? */ 2731 bzero(atid, sizeof(*atid)); 2732 2733 TAILQ_INIT(&atid->axq_q); 2734 TAILQ_INIT(&atid->filtq.axq_q); 2735 atid->tid = i; 2736 atid->an = an; 2737 for (j = 0; j < ATH_TID_MAX_BUFS; j++) 2738 atid->tx_buf[j] = NULL; 2739 atid->baw_head = atid->baw_tail = 0; 2740 atid->paused = 0; 2741 atid->sched = 0; 2742 atid->hwq_depth = 0; 2743 atid->cleanup_inprogress = 0; 2744 atid->clrdmask = 1; /* Always start by setting this bit */ 2745 if (i == IEEE80211_NONQOS_TID) 2746 atid->ac = WME_AC_BE; 2747 else 2748 atid->ac = TID_TO_WME_AC(i); 2749 } 2750} 2751 2752/* 2753 * Pause the current TID. This stops packets from being transmitted 2754 * on it. 2755 * 2756 * Since this is also called from upper layers as well as the driver, 2757 * it will get the TID lock. 2758 */ 2759static void 2760ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid) 2761{ 2762 2763 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2764 tid->paused++; 2765 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n", 2766 __func__, tid->paused); 2767} 2768 2769/* 2770 * Unpause the current TID, and schedule it if needed. 2771 */ 2772static void 2773ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid) 2774{ 2775 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2776 2777 tid->paused--; 2778 2779 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n", 2780 __func__, tid->paused); 2781 2782 if (tid->paused || tid->axq_depth == 0) { 2783 return; 2784 } 2785 2786 /* XXX isfiltered shouldn't ever be 0 at this point */ 2787 if (tid->isfiltered == 1) { 2788 device_printf(sc->sc_dev, "%s: filtered?!\n", __func__); 2789 return; 2790 } 2791 2792 ath_tx_tid_sched(sc, tid); 2793 /* Punt some frames to the hardware if needed */ 2794 //ath_txq_sched(sc, sc->sc_ac2q[tid->ac]); 2795 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask); 2796} 2797 2798/* 2799 * Add the given ath_buf to the TID filtered frame list. 2800 * This requires the TID be filtered. 2801 */ 2802static void 2803ath_tx_tid_filt_addbuf(struct ath_softc *sc, struct ath_tid *tid, 2804 struct ath_buf *bf) 2805{ 2806 2807 ATH_TID_LOCK_ASSERT(sc, tid); 2808 if (! tid->isfiltered) 2809 device_printf(sc->sc_dev, "%s: not filtered?!\n", __func__); 2810 2811 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: bf=%p\n", __func__, bf); 2812 2813 /* Set the retry bit and bump the retry counter */ 2814 ath_tx_set_retry(sc, bf); 2815 sc->sc_stats.ast_tx_swfiltered++; 2816 2817 ATH_TXQ_INSERT_TAIL(&tid->filtq, bf, bf_list); 2818} 2819 2820/* 2821 * Handle a completed filtered frame from the given TID. 2822 * This just enables/pauses the filtered frame state if required 2823 * and appends the filtered frame to the filtered queue. 2824 */ 2825static void 2826ath_tx_tid_filt_comp_buf(struct ath_softc *sc, struct ath_tid *tid, 2827 struct ath_buf *bf) 2828{ 2829 2830 ATH_TID_LOCK_ASSERT(sc, tid); 2831 2832 if (! tid->isfiltered) { 2833 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: filter transition\n", 2834 __func__); 2835 tid->isfiltered = 1; 2836 ath_tx_tid_pause(sc, tid); 2837 } 2838 2839 /* Add the frame to the filter queue */ 2840 ath_tx_tid_filt_addbuf(sc, tid, bf); 2841} 2842 2843/* 2844 * Complete the filtered frame TX completion. 2845 * 2846 * If there are no more frames in the hardware queue, unpause/unfilter 2847 * the TID if applicable. Otherwise we will wait for a node PS transition 2848 * to unfilter. 2849 */ 2850static void 2851ath_tx_tid_filt_comp_complete(struct ath_softc *sc, struct ath_tid *tid) 2852{ 2853 struct ath_buf *bf; 2854 2855 ATH_TID_LOCK_ASSERT(sc, tid); 2856 2857 if (tid->hwq_depth != 0) 2858 return; 2859 2860 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: hwq=0, transition back\n", 2861 __func__); 2862 tid->isfiltered = 0; 2863 tid->clrdmask = 1; 2864 2865 /* XXX this is really quite inefficient */ 2866 while ((bf = TAILQ_LAST(&tid->filtq.axq_q, ath_bufhead_s)) != NULL) { 2867 ATH_TXQ_REMOVE(&tid->filtq, bf, bf_list); 2868 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 2869 } 2870 2871 ath_tx_tid_resume(sc, tid); 2872} 2873 2874/* 2875 * Called when a single (aggregate or otherwise) frame is completed. 2876 * 2877 * Returns 1 if the buffer could be added to the filtered list 2878 * (cloned or otherwise), 0 if the buffer couldn't be added to the 2879 * filtered list (failed clone; expired retry) and the caller should 2880 * free it and handle it like a failure (eg by sending a BAR.) 2881 */ 2882static int 2883ath_tx_tid_filt_comp_single(struct ath_softc *sc, struct ath_tid *tid, 2884 struct ath_buf *bf) 2885{ 2886 struct ath_buf *nbf; 2887 int retval; 2888 2889 ATH_TID_LOCK_ASSERT(sc, tid); 2890 2891 /* 2892 * Don't allow a filtered frame to live forever. 2893 */ 2894 if (bf->bf_state.bfs_retries > SWMAX_RETRIES) { 2895 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 2896 "%s: bf=%p, seqno=%d, exceeded retries\n", 2897 __func__, 2898 bf, 2899 bf->bf_state.bfs_seqno); 2900 return (0); 2901 } 2902 2903 /* 2904 * A busy buffer can't be added to the retry list. 2905 * It needs to be cloned. 2906 */ 2907 if (bf->bf_flags & ATH_BUF_BUSY) { 2908 nbf = ath_tx_retry_clone(sc, tid->an, tid, bf); 2909 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 2910 "%s: busy buffer clone: %p -> %p\n", 2911 __func__, bf, nbf); 2912 } else { 2913 nbf = bf; 2914 } 2915 2916 if (nbf == NULL) { 2917 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 2918 "%s: busy buffer couldn't be cloned (%p)!\n", 2919 __func__, bf); 2920 retval = 1; 2921 } else { 2922 ath_tx_tid_filt_comp_buf(sc, tid, nbf); 2923 retval = 0; 2924 } 2925 ath_tx_tid_filt_comp_complete(sc, tid); 2926 2927 return (retval); 2928} 2929 2930static void 2931ath_tx_tid_filt_comp_aggr(struct ath_softc *sc, struct ath_tid *tid, 2932 struct ath_buf *bf_first, ath_bufhead *bf_q) 2933{ 2934 struct ath_buf *bf, *bf_next, *nbf; 2935 2936 ATH_TID_LOCK_ASSERT(sc, tid); 2937 2938 bf = bf_first; 2939 while (bf) { 2940 bf_next = bf->bf_next; 2941 bf->bf_next = NULL; /* Remove it from the aggr list */ 2942 2943 /* 2944 * Don't allow a filtered frame to live forever. 2945 */ 2946 if (bf->bf_state.bfs_retries > SWMAX_RETRIES) { 2947 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 2948 "%s: bf=%p, seqno=%d, exceeded retries\n", 2949 __func__, 2950 bf, 2951 bf->bf_state.bfs_seqno); 2952 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 2953 goto next; 2954 } 2955 2956 if (bf->bf_flags & ATH_BUF_BUSY) { 2957 nbf = ath_tx_retry_clone(sc, tid->an, tid, bf); 2958 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 2959 "%s: busy buffer cloned: %p -> %p", 2960 __func__, bf, nbf); 2961 } else { 2962 nbf = bf; 2963 } 2964 2965 /* 2966 * If the buffer couldn't be cloned, add it to bf_q; 2967 * the caller will free the buffer(s) as required. 2968 */ 2969 if (nbf == NULL) { 2970 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 2971 "%s: buffer couldn't be cloned! (%p)\n", 2972 __func__, bf); 2973 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 2974 } else { 2975 ath_tx_tid_filt_comp_buf(sc, tid, nbf); 2976 } 2977next: 2978 bf = bf_next; 2979 } 2980 2981 ath_tx_tid_filt_comp_complete(sc, tid); 2982} 2983 2984/* 2985 * Suspend the queue because we need to TX a BAR. 2986 */ 2987static void 2988ath_tx_tid_bar_suspend(struct ath_softc *sc, struct ath_tid *tid) 2989{ 2990 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2991 2992 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2993 "%s: tid=%p, bar_wait=%d, bar_tx=%d, called\n", 2994 __func__, 2995 tid, 2996 tid->bar_wait, 2997 tid->bar_tx); 2998 2999 /* We shouldn't be called when bar_tx is 1 */ 3000 if (tid->bar_tx) { 3001 device_printf(sc->sc_dev, "%s: bar_tx is 1?!\n", 3002 __func__); 3003 } 3004 3005 /* If we've already been called, just be patient. */ 3006 if (tid->bar_wait) 3007 return; 3008 3009 /* Wait! */ 3010 tid->bar_wait = 1; 3011 3012 /* Only one pause, no matter how many frames fail */ 3013 ath_tx_tid_pause(sc, tid); 3014} 3015 3016/* 3017 * We've finished with BAR handling - either we succeeded or 3018 * failed. Either way, unsuspend TX. 3019 */ 3020static void 3021ath_tx_tid_bar_unsuspend(struct ath_softc *sc, struct ath_tid *tid) 3022{ 3023 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 3024 3025 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3026 "%s: tid=%p, called\n", 3027 __func__, 3028 tid); 3029 3030 if (tid->bar_tx == 0 || tid->bar_wait == 0) { 3031 device_printf(sc->sc_dev, "%s: bar_tx=%d, bar_wait=%d: ?\n", 3032 __func__, tid->bar_tx, tid->bar_wait); 3033 } 3034 3035 tid->bar_tx = tid->bar_wait = 0; 3036 ath_tx_tid_resume(sc, tid); 3037} 3038 3039/* 3040 * Return whether we're ready to TX a BAR frame. 3041 * 3042 * Requires the TID lock be held. 3043 */ 3044static int 3045ath_tx_tid_bar_tx_ready(struct ath_softc *sc, struct ath_tid *tid) 3046{ 3047 3048 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 3049 3050 if (tid->bar_wait == 0 || tid->hwq_depth > 0) 3051 return (0); 3052 3053 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, "%s: tid=%p (%d), bar ready\n", 3054 __func__, tid, tid->tid); 3055 3056 return (1); 3057} 3058 3059/* 3060 * Check whether the current TID is ready to have a BAR 3061 * TXed and if so, do the TX. 3062 * 3063 * Since the TID/TXQ lock can't be held during a call to 3064 * ieee80211_send_bar(), we have to do the dirty thing of unlocking it, 3065 * sending the BAR and locking it again. 3066 * 3067 * Eventually, the code to send the BAR should be broken out 3068 * from this routine so the lock doesn't have to be reacquired 3069 * just to be immediately dropped by the caller. 3070 */ 3071static void 3072ath_tx_tid_bar_tx(struct ath_softc *sc, struct ath_tid *tid) 3073{ 3074 struct ieee80211_tx_ampdu *tap; 3075 3076 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 3077 3078 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3079 "%s: tid=%p, called\n", 3080 __func__, 3081 tid); 3082 3083 tap = ath_tx_get_tx_tid(tid->an, tid->tid); 3084 3085 /* 3086 * This is an error condition! 3087 */ 3088 if (tid->bar_wait == 0 || tid->bar_tx == 1) { 3089 device_printf(sc->sc_dev, 3090 "%s: tid=%p, bar_tx=%d, bar_wait=%d: ?\n", 3091 __func__, 3092 tid, 3093 tid->bar_tx, 3094 tid->bar_wait); 3095 return; 3096 } 3097 3098 /* Don't do anything if we still have pending frames */ 3099 if (tid->hwq_depth > 0) { 3100 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3101 "%s: tid=%p, hwq_depth=%d, waiting\n", 3102 __func__, 3103 tid, 3104 tid->hwq_depth); 3105 return; 3106 } 3107 3108 /* We're now about to TX */ 3109 tid->bar_tx = 1; 3110 3111 /* 3112 * Calculate new BAW left edge, now that all frames have either 3113 * succeeded or failed. 3114 * 3115 * XXX verify this is _actually_ the valid value to begin at! 3116 */ 3117 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3118 "%s: tid=%p, new BAW left edge=%d\n", 3119 __func__, 3120 tid, 3121 tap->txa_start); 3122 3123 /* Try sending the BAR frame */ 3124 /* We can't hold the lock here! */ 3125 3126 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]); 3127 if (ieee80211_send_bar(&tid->an->an_node, tap, tap->txa_start) == 0) { 3128 /* Success? Now we wait for notification that it's done */ 3129 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 3130 return; 3131 } 3132 3133 /* Failure? For now, warn loudly and continue */ 3134 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 3135 device_printf(sc->sc_dev, "%s: tid=%p, failed to TX BAR, continue!\n", 3136 __func__, tid); 3137 ath_tx_tid_bar_unsuspend(sc, tid); 3138} 3139 3140static void 3141ath_tx_tid_drain_pkt(struct ath_softc *sc, struct ath_node *an, 3142 struct ath_tid *tid, ath_bufhead *bf_cq, struct ath_buf *bf) 3143{ 3144 3145 ATH_TID_LOCK_ASSERT(sc, tid); 3146 3147 /* 3148 * If the current TID is running AMPDU, update 3149 * the BAW. 3150 */ 3151 if (ath_tx_ampdu_running(sc, an, tid->tid) && 3152 bf->bf_state.bfs_dobaw) { 3153 /* 3154 * Only remove the frame from the BAW if it's 3155 * been transmitted at least once; this means 3156 * the frame was in the BAW to begin with. 3157 */ 3158 if (bf->bf_state.bfs_retries > 0) { 3159 ath_tx_update_baw(sc, an, tid, bf); 3160 bf->bf_state.bfs_dobaw = 0; 3161 } 3162 /* 3163 * This has become a non-fatal error now 3164 */ 3165 if (! bf->bf_state.bfs_addedbaw) 3166 device_printf(sc->sc_dev, 3167 "%s: wasn't added: seqno %d\n", 3168 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3169 } 3170 TAILQ_INSERT_TAIL(bf_cq, bf, bf_list); 3171} 3172 3173static void 3174ath_tx_tid_drain_print(struct ath_softc *sc, struct ath_node *an, 3175 struct ath_tid *tid, struct ath_buf *bf) 3176{ 3177 struct ieee80211_node *ni = &an->an_node; 3178 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 3179 struct ieee80211_tx_ampdu *tap; 3180 3181 tap = ath_tx_get_tx_tid(an, tid->tid); 3182 3183 device_printf(sc->sc_dev, 3184 "%s: node %p: bf=%p: addbaw=%d, dobaw=%d, " 3185 "seqno=%d, retry=%d\n", 3186 __func__, ni, bf, 3187 bf->bf_state.bfs_addedbaw, 3188 bf->bf_state.bfs_dobaw, 3189 SEQNO(bf->bf_state.bfs_seqno), 3190 bf->bf_state.bfs_retries); 3191 device_printf(sc->sc_dev, 3192 "%s: node %p: bf=%p: tid txq_depth=%d hwq_depth=%d, bar_wait=%d, isfiltered=%d\n", 3193 __func__, ni, bf, 3194 tid->axq_depth, 3195 tid->hwq_depth, 3196 tid->bar_wait, 3197 tid->isfiltered); 3198 device_printf(sc->sc_dev, 3199 "%s: node %p: tid %d: txq_depth=%d, " 3200 "txq_aggr_depth=%d, sched=%d, paused=%d, " 3201 "hwq_depth=%d, incomp=%d, baw_head=%d, " 3202 "baw_tail=%d txa_start=%d, ni_txseqs=%d\n", 3203 __func__, ni, tid->tid, txq->axq_depth, 3204 txq->axq_aggr_depth, tid->sched, tid->paused, 3205 tid->hwq_depth, tid->incomp, tid->baw_head, 3206 tid->baw_tail, tap == NULL ? -1 : tap->txa_start, 3207 ni->ni_txseqs[tid->tid]); 3208 3209 /* XXX Dump the frame, see what it is? */ 3210 ieee80211_dump_pkt(ni->ni_ic, 3211 mtod(bf->bf_m, const uint8_t *), 3212 bf->bf_m->m_len, 0, -1); 3213} 3214 3215/* 3216 * Free any packets currently pending in the software TX queue. 3217 * 3218 * This will be called when a node is being deleted. 3219 * 3220 * It can also be called on an active node during an interface 3221 * reset or state transition. 3222 * 3223 * (From Linux/reference): 3224 * 3225 * TODO: For frame(s) that are in the retry state, we will reuse the 3226 * sequence number(s) without setting the retry bit. The 3227 * alternative is to give up on these and BAR the receiver's window 3228 * forward. 3229 */ 3230static void 3231ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an, 3232 struct ath_tid *tid, ath_bufhead *bf_cq) 3233{ 3234 struct ath_buf *bf; 3235 struct ieee80211_tx_ampdu *tap; 3236 struct ieee80211_node *ni = &an->an_node; 3237 int t; 3238 3239 tap = ath_tx_get_tx_tid(an, tid->tid); 3240 3241 ATH_TID_LOCK_ASSERT(sc, tid); 3242 3243 /* Walk the queue, free frames */ 3244 t = 0; 3245 for (;;) { 3246 bf = TAILQ_FIRST(&tid->axq_q); 3247 if (bf == NULL) { 3248 break; 3249 } 3250 3251 if (t == 0) { 3252 ath_tx_tid_drain_print(sc, an, tid, bf); 3253 t = 1; 3254 } 3255 3256 ATH_TXQ_REMOVE(tid, bf, bf_list); 3257 ath_tx_tid_drain_pkt(sc, an, tid, bf_cq, bf); 3258 } 3259 3260 /* And now, drain the filtered frame queue */ 3261 t = 0; 3262 for (;;) { 3263 bf = TAILQ_FIRST(&tid->filtq.axq_q); 3264 if (bf == NULL) 3265 break; 3266 3267 if (t == 0) { 3268 ath_tx_tid_drain_print(sc, an, tid, bf); 3269 t = 1; 3270 } 3271 3272 ATH_TXQ_REMOVE(&tid->filtq, bf, bf_list); 3273 ath_tx_tid_drain_pkt(sc, an, tid, bf_cq, bf); 3274 } 3275 3276 /* 3277 * Now that it's completed, grab the TID lock and update 3278 * the sequence number and BAW window. 3279 * Because sequence numbers have been assigned to frames 3280 * that haven't been sent yet, it's entirely possible 3281 * we'll be called with some pending frames that have not 3282 * been transmitted. 3283 * 3284 * The cleaner solution is to do the sequence number allocation 3285 * when the packet is first transmitted - and thus the "retries" 3286 * check above would be enough to update the BAW/seqno. 3287 */ 3288 3289 /* But don't do it for non-QoS TIDs */ 3290 if (tap) { 3291#if 0 3292 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3293 "%s: node %p: TID %d: sliding BAW left edge to %d\n", 3294 __func__, an, tid->tid, tap->txa_start); 3295#endif 3296 ni->ni_txseqs[tid->tid] = tap->txa_start; 3297 tid->baw_tail = tid->baw_head; 3298 } 3299} 3300 3301/* 3302 * Flush all software queued packets for the given node. 3303 * 3304 * This occurs when a completion handler frees the last buffer 3305 * for a node, and the node is thus freed. This causes the node 3306 * to be cleaned up, which ends up calling ath_tx_node_flush. 3307 */ 3308void 3309ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an) 3310{ 3311 int tid; 3312 ath_bufhead bf_cq; 3313 struct ath_buf *bf; 3314 3315 TAILQ_INIT(&bf_cq); 3316 3317 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 3318 struct ath_tid *atid = &an->an_tid[tid]; 3319 struct ath_txq *txq = sc->sc_ac2q[atid->ac]; 3320 3321 /* Remove this tid from the list of active tids */ 3322 ATH_TXQ_LOCK(txq); 3323 ath_tx_tid_unsched(sc, atid); 3324 3325 /* Free packets */ 3326 ath_tx_tid_drain(sc, an, atid, &bf_cq); 3327 ATH_TXQ_UNLOCK(txq); 3328 } 3329 3330 /* Handle completed frames */ 3331 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3332 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3333 ath_tx_default_comp(sc, bf, 0); 3334 } 3335} 3336 3337/* 3338 * Drain all the software TXQs currently with traffic queued. 3339 */ 3340void 3341ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq) 3342{ 3343 struct ath_tid *tid; 3344 ath_bufhead bf_cq; 3345 struct ath_buf *bf; 3346 3347 TAILQ_INIT(&bf_cq); 3348 ATH_TXQ_LOCK(txq); 3349 3350 /* 3351 * Iterate over all active tids for the given txq, 3352 * flushing and unsched'ing them 3353 */ 3354 while (! TAILQ_EMPTY(&txq->axq_tidq)) { 3355 tid = TAILQ_FIRST(&txq->axq_tidq); 3356 ath_tx_tid_drain(sc, tid->an, tid, &bf_cq); 3357 ath_tx_tid_unsched(sc, tid); 3358 } 3359 3360 ATH_TXQ_UNLOCK(txq); 3361 3362 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3363 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3364 ath_tx_default_comp(sc, bf, 0); 3365 } 3366} 3367 3368/* 3369 * Handle completion of non-aggregate session frames. 3370 */ 3371void 3372ath_tx_normal_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3373{ 3374 struct ieee80211_node *ni = bf->bf_node; 3375 struct ath_node *an = ATH_NODE(ni); 3376 int tid = bf->bf_state.bfs_tid; 3377 struct ath_tid *atid = &an->an_tid[tid]; 3378 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3379 3380 /* The TID state is protected behind the TXQ lock */ 3381 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3382 3383 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: fail=%d, hwq_depth now %d\n", 3384 __func__, bf, fail, atid->hwq_depth - 1); 3385 3386 atid->hwq_depth--; 3387 3388 if (atid->isfiltered) 3389 device_printf(sc->sc_dev, "%s: isfiltered=1, normal_comp?\n", 3390 __func__); 3391 3392 if (atid->hwq_depth < 0) 3393 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3394 __func__, atid->hwq_depth); 3395 3396 /* 3397 * If the queue is filtered, potentially mark it as complete 3398 * and reschedule it as needed. 3399 * 3400 * This is required as there may be a subsequent TX descriptor 3401 * for this end-node that has CLRDMASK set, so it's quite possible 3402 * that a filtered frame will be followed by a non-filtered 3403 * (complete or otherwise) frame. 3404 * 3405 * XXX should we do this before we complete the frame? 3406 */ 3407 if (atid->isfiltered) 3408 ath_tx_tid_filt_comp_complete(sc, atid); 3409 3410 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3411 3412 /* 3413 * punt to rate control if we're not being cleaned up 3414 * during a hw queue drain and the frame wanted an ACK. 3415 */ 3416 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 3417 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 3418 ts, bf->bf_state.bfs_pktlen, 3419 1, (ts->ts_status == 0) ? 0 : 1); 3420 3421 ath_tx_default_comp(sc, bf, fail); 3422} 3423 3424/* 3425 * Handle cleanup of aggregate session packets that aren't 3426 * an A-MPDU. 3427 * 3428 * There's no need to update the BAW here - the session is being 3429 * torn down. 3430 */ 3431static void 3432ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3433{ 3434 struct ieee80211_node *ni = bf->bf_node; 3435 struct ath_node *an = ATH_NODE(ni); 3436 int tid = bf->bf_state.bfs_tid; 3437 struct ath_tid *atid = &an->an_tid[tid]; 3438 3439 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: TID %d: incomp=%d\n", 3440 __func__, tid, atid->incomp); 3441 3442 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3443 atid->incomp--; 3444 if (atid->incomp == 0) { 3445 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3446 "%s: TID %d: cleaned up! resume!\n", 3447 __func__, tid); 3448 atid->cleanup_inprogress = 0; 3449 ath_tx_tid_resume(sc, atid); 3450 } 3451 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3452 3453 ath_tx_default_comp(sc, bf, 0); 3454} 3455 3456/* 3457 * Performs transmit side cleanup when TID changes from aggregated to 3458 * unaggregated. 3459 * 3460 * - Discard all retry frames from the s/w queue. 3461 * - Fix the tx completion function for all buffers in s/w queue. 3462 * - Count the number of unacked frames, and let transmit completion 3463 * handle it later. 3464 * 3465 * The caller is responsible for pausing the TID. 3466 */ 3467static void 3468ath_tx_tid_cleanup(struct ath_softc *sc, struct ath_node *an, int tid) 3469{ 3470 struct ath_tid *atid = &an->an_tid[tid]; 3471 struct ieee80211_tx_ampdu *tap; 3472 struct ath_buf *bf, *bf_next; 3473 ath_bufhead bf_cq; 3474 3475 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 3476 "%s: TID %d: called\n", __func__, tid); 3477 3478 TAILQ_INIT(&bf_cq); 3479 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3480 3481 /* 3482 * Move the filtered frames to the TX queue, before 3483 * we run off and discard/process things. 3484 */ 3485 /* XXX this is really quite inefficient */ 3486 while ((bf = TAILQ_LAST(&atid->filtq.axq_q, ath_bufhead_s)) != NULL) { 3487 ATH_TXQ_REMOVE(&atid->filtq, bf, bf_list); 3488 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list); 3489 } 3490 3491 /* 3492 * Update the frames in the software TX queue: 3493 * 3494 * + Discard retry frames in the queue 3495 * + Fix the completion function to be non-aggregate 3496 */ 3497 bf = TAILQ_FIRST(&atid->axq_q); 3498 while (bf) { 3499 if (bf->bf_state.bfs_isretried) { 3500 bf_next = TAILQ_NEXT(bf, bf_list); 3501 TAILQ_REMOVE(&atid->axq_q, bf, bf_list); 3502 atid->axq_depth--; 3503 if (bf->bf_state.bfs_dobaw) { 3504 ath_tx_update_baw(sc, an, atid, bf); 3505 if (! bf->bf_state.bfs_addedbaw) 3506 device_printf(sc->sc_dev, 3507 "%s: wasn't added: seqno %d\n", 3508 __func__, 3509 SEQNO(bf->bf_state.bfs_seqno)); 3510 } 3511 bf->bf_state.bfs_dobaw = 0; 3512 /* 3513 * Call the default completion handler with "fail" just 3514 * so upper levels are suitably notified about this. 3515 */ 3516 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3517 bf = bf_next; 3518 continue; 3519 } 3520 /* Give these the default completion handler */ 3521 bf->bf_comp = ath_tx_normal_comp; 3522 bf = TAILQ_NEXT(bf, bf_list); 3523 } 3524 3525 /* The caller is required to pause the TID */ 3526#if 0 3527 /* Pause the TID */ 3528 ath_tx_tid_pause(sc, atid); 3529#endif 3530 3531 /* 3532 * Calculate what hardware-queued frames exist based 3533 * on the current BAW size. Ie, what frames have been 3534 * added to the TX hardware queue for this TID but 3535 * not yet ACKed. 3536 */ 3537 tap = ath_tx_get_tx_tid(an, tid); 3538 /* Need the lock - fiddling with BAW */ 3539 while (atid->baw_head != atid->baw_tail) { 3540 if (atid->tx_buf[atid->baw_head]) { 3541 atid->incomp++; 3542 atid->cleanup_inprogress = 1; 3543 atid->tx_buf[atid->baw_head] = NULL; 3544 } 3545 INCR(atid->baw_head, ATH_TID_MAX_BUFS); 3546 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 3547 } 3548 3549 /* 3550 * If cleanup is required, defer TID scheduling 3551 * until all the HW queued packets have been 3552 * sent. 3553 */ 3554 if (! atid->cleanup_inprogress) 3555 ath_tx_tid_resume(sc, atid); 3556 3557 if (atid->cleanup_inprogress) 3558 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3559 "%s: TID %d: cleanup needed: %d packets\n", 3560 __func__, tid, atid->incomp); 3561 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3562 3563 /* Handle completing frames and fail them */ 3564 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3565 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3566 ath_tx_default_comp(sc, bf, 1); 3567 } 3568} 3569 3570static struct ath_buf * 3571ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an, 3572 struct ath_tid *tid, struct ath_buf *bf) 3573{ 3574 struct ath_buf *nbf; 3575 int error; 3576 3577 nbf = ath_buf_clone(sc, bf); 3578 3579#if 0 3580 device_printf(sc->sc_dev, "%s: ATH_BUF_BUSY; cloning\n", 3581 __func__); 3582#endif 3583 3584 if (nbf == NULL) { 3585 /* Failed to clone */ 3586 device_printf(sc->sc_dev, 3587 "%s: failed to clone a busy buffer\n", 3588 __func__); 3589 return NULL; 3590 } 3591 3592 /* Setup the dma for the new buffer */ 3593 error = ath_tx_dmasetup(sc, nbf, nbf->bf_m); 3594 if (error != 0) { 3595 device_printf(sc->sc_dev, 3596 "%s: failed to setup dma for clone\n", 3597 __func__); 3598 /* 3599 * Put this at the head of the list, not tail; 3600 * that way it doesn't interfere with the 3601 * busy buffer logic (which uses the tail of 3602 * the list.) 3603 */ 3604 ATH_TXBUF_LOCK(sc); 3605 ath_returnbuf_head(sc, nbf); 3606 ATH_TXBUF_UNLOCK(sc); 3607 return NULL; 3608 } 3609 3610 /* Update BAW if required, before we free the original buf */ 3611 if (bf->bf_state.bfs_dobaw) 3612 ath_tx_switch_baw_buf(sc, an, tid, bf, nbf); 3613 3614 /* Free current buffer; return the older buffer */ 3615 bf->bf_m = NULL; 3616 bf->bf_node = NULL; 3617 ath_freebuf(sc, bf); 3618 3619 return nbf; 3620} 3621 3622/* 3623 * Handle retrying an unaggregate frame in an aggregate 3624 * session. 3625 * 3626 * If too many retries occur, pause the TID, wait for 3627 * any further retransmits (as there's no reason why 3628 * non-aggregate frames in an aggregate session are 3629 * transmitted in-order; they just have to be in-BAW) 3630 * and then queue a BAR. 3631 */ 3632static void 3633ath_tx_aggr_retry_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3634{ 3635 struct ieee80211_node *ni = bf->bf_node; 3636 struct ath_node *an = ATH_NODE(ni); 3637 int tid = bf->bf_state.bfs_tid; 3638 struct ath_tid *atid = &an->an_tid[tid]; 3639 struct ieee80211_tx_ampdu *tap; 3640 3641 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3642 3643 tap = ath_tx_get_tx_tid(an, tid); 3644 3645 /* 3646 * If the buffer is marked as busy, we can't directly 3647 * reuse it. Instead, try to clone the buffer. 3648 * If the clone is successful, recycle the old buffer. 3649 * If the clone is unsuccessful, set bfs_retries to max 3650 * to force the next bit of code to free the buffer 3651 * for us. 3652 */ 3653 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3654 (bf->bf_flags & ATH_BUF_BUSY)) { 3655 struct ath_buf *nbf; 3656 nbf = ath_tx_retry_clone(sc, an, atid, bf); 3657 if (nbf) 3658 /* bf has been freed at this point */ 3659 bf = nbf; 3660 else 3661 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3662 } 3663 3664 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3665 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3666 "%s: exceeded retries; seqno %d\n", 3667 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3668 sc->sc_stats.ast_tx_swretrymax++; 3669 3670 /* Update BAW anyway */ 3671 if (bf->bf_state.bfs_dobaw) { 3672 ath_tx_update_baw(sc, an, atid, bf); 3673 if (! bf->bf_state.bfs_addedbaw) 3674 device_printf(sc->sc_dev, 3675 "%s: wasn't added: seqno %d\n", 3676 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3677 } 3678 bf->bf_state.bfs_dobaw = 0; 3679 3680 /* Suspend the TX queue and get ready to send the BAR */ 3681 ath_tx_tid_bar_suspend(sc, atid); 3682 3683 /* Send the BAR if there are no other frames waiting */ 3684 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3685 ath_tx_tid_bar_tx(sc, atid); 3686 3687 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3688 3689 /* Free buffer, bf is free after this call */ 3690 ath_tx_default_comp(sc, bf, 0); 3691 return; 3692 } 3693 3694 /* 3695 * This increments the retry counter as well as 3696 * sets the retry flag in the ath_buf and packet 3697 * body. 3698 */ 3699 ath_tx_set_retry(sc, bf); 3700 sc->sc_stats.ast_tx_swretries++; 3701 3702 /* 3703 * Insert this at the head of the queue, so it's 3704 * retried before any current/subsequent frames. 3705 */ 3706 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list); 3707 ath_tx_tid_sched(sc, atid); 3708 /* Send the BAR if there are no other frames waiting */ 3709 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3710 ath_tx_tid_bar_tx(sc, atid); 3711 3712 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3713} 3714 3715/* 3716 * Common code for aggregate excessive retry/subframe retry. 3717 * If retrying, queues buffers to bf_q. If not, frees the 3718 * buffers. 3719 * 3720 * XXX should unify this with ath_tx_aggr_retry_unaggr() 3721 */ 3722static int 3723ath_tx_retry_subframe(struct ath_softc *sc, struct ath_buf *bf, 3724 ath_bufhead *bf_q) 3725{ 3726 struct ieee80211_node *ni = bf->bf_node; 3727 struct ath_node *an = ATH_NODE(ni); 3728 int tid = bf->bf_state.bfs_tid; 3729 struct ath_tid *atid = &an->an_tid[tid]; 3730 3731 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[atid->ac]); 3732 3733 /* XXX clr11naggr should be done for all subframes */ 3734 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 3735 ath_hal_set11nburstduration(sc->sc_ah, bf->bf_desc, 0); 3736 3737 /* ath_hal_set11n_virtualmorefrag(sc->sc_ah, bf->bf_desc, 0); */ 3738 3739 /* 3740 * If the buffer is marked as busy, we can't directly 3741 * reuse it. Instead, try to clone the buffer. 3742 * If the clone is successful, recycle the old buffer. 3743 * If the clone is unsuccessful, set bfs_retries to max 3744 * to force the next bit of code to free the buffer 3745 * for us. 3746 */ 3747 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3748 (bf->bf_flags & ATH_BUF_BUSY)) { 3749 struct ath_buf *nbf; 3750 nbf = ath_tx_retry_clone(sc, an, atid, bf); 3751 if (nbf) 3752 /* bf has been freed at this point */ 3753 bf = nbf; 3754 else 3755 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3756 } 3757 3758 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3759 sc->sc_stats.ast_tx_swretrymax++; 3760 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3761 "%s: max retries: seqno %d\n", 3762 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3763 ath_tx_update_baw(sc, an, atid, bf); 3764 if (! bf->bf_state.bfs_addedbaw) 3765 device_printf(sc->sc_dev, 3766 "%s: wasn't added: seqno %d\n", 3767 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3768 bf->bf_state.bfs_dobaw = 0; 3769 return 1; 3770 } 3771 3772 ath_tx_set_retry(sc, bf); 3773 sc->sc_stats.ast_tx_swretries++; 3774 bf->bf_next = NULL; /* Just to make sure */ 3775 3776 /* Clear the aggregate state */ 3777 bf->bf_state.bfs_aggr = 0; 3778 bf->bf_state.bfs_ndelim = 0; /* ??? needed? */ 3779 bf->bf_state.bfs_nframes = 1; 3780 3781 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 3782 return 0; 3783} 3784 3785/* 3786 * error pkt completion for an aggregate destination 3787 */ 3788static void 3789ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first, 3790 struct ath_tid *tid) 3791{ 3792 struct ieee80211_node *ni = bf_first->bf_node; 3793 struct ath_node *an = ATH_NODE(ni); 3794 struct ath_buf *bf_next, *bf; 3795 ath_bufhead bf_q; 3796 int drops = 0; 3797 struct ieee80211_tx_ampdu *tap; 3798 ath_bufhead bf_cq; 3799 3800 TAILQ_INIT(&bf_q); 3801 TAILQ_INIT(&bf_cq); 3802 3803 /* 3804 * Update rate control - all frames have failed. 3805 * 3806 * XXX use the length in the first frame in the series; 3807 * XXX just so things are consistent for now. 3808 */ 3809 ath_tx_update_ratectrl(sc, ni, bf_first->bf_state.bfs_rc, 3810 &bf_first->bf_status.ds_txstat, 3811 bf_first->bf_state.bfs_pktlen, 3812 bf_first->bf_state.bfs_nframes, bf_first->bf_state.bfs_nframes); 3813 3814 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 3815 tap = ath_tx_get_tx_tid(an, tid->tid); 3816 sc->sc_stats.ast_tx_aggr_failall++; 3817 3818 /* Retry all subframes */ 3819 bf = bf_first; 3820 while (bf) { 3821 bf_next = bf->bf_next; 3822 bf->bf_next = NULL; /* Remove it from the aggr list */ 3823 sc->sc_stats.ast_tx_aggr_fail++; 3824 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 3825 drops++; 3826 bf->bf_next = NULL; 3827 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3828 } 3829 bf = bf_next; 3830 } 3831 3832 /* Prepend all frames to the beginning of the queue */ 3833 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 3834 TAILQ_REMOVE(&bf_q, bf, bf_list); 3835 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 3836 } 3837 3838 /* 3839 * Schedule the TID to be re-tried. 3840 */ 3841 ath_tx_tid_sched(sc, tid); 3842 3843 /* 3844 * send bar if we dropped any frames 3845 * 3846 * Keep the txq lock held for now, as we need to ensure 3847 * that ni_txseqs[] is consistent (as it's being updated 3848 * in the ifnet TX context or raw TX context.) 3849 */ 3850 if (drops) { 3851 /* Suspend the TX queue and get ready to send the BAR */ 3852 ath_tx_tid_bar_suspend(sc, tid); 3853 } 3854 3855 /* 3856 * Send BAR if required 3857 */ 3858 if (ath_tx_tid_bar_tx_ready(sc, tid)) 3859 ath_tx_tid_bar_tx(sc, tid); 3860 3861 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]); 3862 3863 /* Complete frames which errored out */ 3864 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3865 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3866 ath_tx_default_comp(sc, bf, 0); 3867 } 3868} 3869 3870/* 3871 * Handle clean-up of packets from an aggregate list. 3872 * 3873 * There's no need to update the BAW here - the session is being 3874 * torn down. 3875 */ 3876static void 3877ath_tx_comp_cleanup_aggr(struct ath_softc *sc, struct ath_buf *bf_first) 3878{ 3879 struct ath_buf *bf, *bf_next; 3880 struct ieee80211_node *ni = bf_first->bf_node; 3881 struct ath_node *an = ATH_NODE(ni); 3882 int tid = bf_first->bf_state.bfs_tid; 3883 struct ath_tid *atid = &an->an_tid[tid]; 3884 3885 bf = bf_first; 3886 3887 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3888 3889 /* update incomp */ 3890 while (bf) { 3891 atid->incomp--; 3892 bf = bf->bf_next; 3893 } 3894 3895 if (atid->incomp == 0) { 3896 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3897 "%s: TID %d: cleaned up! resume!\n", 3898 __func__, tid); 3899 atid->cleanup_inprogress = 0; 3900 ath_tx_tid_resume(sc, atid); 3901 } 3902 3903 /* Send BAR if required */ 3904 /* XXX why would we send a BAR when transitioning to non-aggregation? */ 3905 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3906 ath_tx_tid_bar_tx(sc, atid); 3907 3908 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3909 3910 /* Handle frame completion */ 3911 while (bf) { 3912 bf_next = bf->bf_next; 3913 ath_tx_default_comp(sc, bf, 1); 3914 bf = bf_next; 3915 } 3916} 3917 3918/* 3919 * Handle completion of an set of aggregate frames. 3920 * 3921 * XXX for now, simply complete each sub-frame. 3922 * 3923 * Note: the completion handler is the last descriptor in the aggregate, 3924 * not the last descriptor in the first frame. 3925 */ 3926static void 3927ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first, 3928 int fail) 3929{ 3930 //struct ath_desc *ds = bf->bf_lastds; 3931 struct ieee80211_node *ni = bf_first->bf_node; 3932 struct ath_node *an = ATH_NODE(ni); 3933 int tid = bf_first->bf_state.bfs_tid; 3934 struct ath_tid *atid = &an->an_tid[tid]; 3935 struct ath_tx_status ts; 3936 struct ieee80211_tx_ampdu *tap; 3937 ath_bufhead bf_q; 3938 ath_bufhead bf_cq; 3939 int seq_st, tx_ok; 3940 int hasba, isaggr; 3941 uint32_t ba[2]; 3942 struct ath_buf *bf, *bf_next; 3943 int ba_index; 3944 int drops = 0; 3945 int nframes = 0, nbad = 0, nf; 3946 int pktlen; 3947 /* XXX there's too much on the stack? */ 3948 struct ath_rc_series rc[ATH_RC_NUM]; 3949 int txseq; 3950 3951 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: called; hwq_depth=%d\n", 3952 __func__, atid->hwq_depth); 3953 3954 /* 3955 * Take a copy; this may be needed -after- bf_first 3956 * has been completed and freed. 3957 */ 3958 ts = bf_first->bf_status.ds_txstat; 3959 3960 TAILQ_INIT(&bf_q); 3961 TAILQ_INIT(&bf_cq); 3962 3963 /* The TID state is kept behind the TXQ lock */ 3964 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3965 3966 atid->hwq_depth--; 3967 if (atid->hwq_depth < 0) 3968 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3969 __func__, atid->hwq_depth); 3970 3971 /* 3972 * If the TID is filtered, handle completing the filter 3973 * transition before potentially kicking it to the cleanup 3974 * function. 3975 * 3976 * XXX this is duplicate work, ew. 3977 */ 3978 if (atid->isfiltered) 3979 ath_tx_tid_filt_comp_complete(sc, atid); 3980 3981 /* 3982 * Punt cleanup to the relevant function, not our problem now 3983 */ 3984 if (atid->cleanup_inprogress) { 3985 if (atid->isfiltered) 3986 device_printf(sc->sc_dev, 3987 "%s: isfiltered=1, normal_comp?\n", 3988 __func__); 3989 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3990 ath_tx_comp_cleanup_aggr(sc, bf_first); 3991 return; 3992 } 3993 3994 /* 3995 * If the frame is filtered, transition to filtered frame 3996 * mode and add this to the filtered frame list. 3997 * 3998 * XXX TODO: figure out how this interoperates with 3999 * BAR, pause and cleanup states. 4000 */ 4001 if ((ts.ts_status & HAL_TXERR_FILT) || 4002 (ts.ts_status != 0 && atid->isfiltered)) { 4003 if (fail != 0) 4004 device_printf(sc->sc_dev, 4005 "%s: isfiltered=1, fail=%d\n", __func__, fail); 4006 ath_tx_tid_filt_comp_aggr(sc, atid, bf_first, &bf_cq); 4007 4008 /* Remove from BAW */ 4009 TAILQ_FOREACH_SAFE(bf, &bf_cq, bf_list, bf_next) { 4010 if (bf->bf_state.bfs_addedbaw) 4011 drops++; 4012 if (bf->bf_state.bfs_dobaw) { 4013 ath_tx_update_baw(sc, an, atid, bf); 4014 if (! bf->bf_state.bfs_addedbaw) 4015 device_printf(sc->sc_dev, 4016 "%s: wasn't added: seqno %d\n", 4017 __func__, 4018 SEQNO(bf->bf_state.bfs_seqno)); 4019 } 4020 bf->bf_state.bfs_dobaw = 0; 4021 } 4022 /* 4023 * If any intermediate frames in the BAW were dropped when 4024 * handling filtering things, send a BAR. 4025 */ 4026 if (drops) 4027 ath_tx_tid_bar_suspend(sc, atid); 4028 4029 /* 4030 * Finish up by sending a BAR if required and freeing 4031 * the frames outside of the TX lock. 4032 */ 4033 goto finish_send_bar; 4034 } 4035 4036 /* 4037 * XXX for now, use the first frame in the aggregate for 4038 * XXX rate control completion; it's at least consistent. 4039 */ 4040 pktlen = bf_first->bf_state.bfs_pktlen; 4041 4042 /* 4043 * Handle errors first! 4044 * 4045 * Here, handle _any_ error as a "exceeded retries" error. 4046 * Later on (when filtered frames are to be specially handled) 4047 * it'll have to be expanded. 4048 */ 4049#if 0 4050 if (ts.ts_status & HAL_TXERR_XRETRY) { 4051#endif 4052 if (ts.ts_status != 0) { 4053 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4054 ath_tx_comp_aggr_error(sc, bf_first, atid); 4055 return; 4056 } 4057 4058 tap = ath_tx_get_tx_tid(an, tid); 4059 4060 /* 4061 * extract starting sequence and block-ack bitmap 4062 */ 4063 /* XXX endian-ness of seq_st, ba? */ 4064 seq_st = ts.ts_seqnum; 4065 hasba = !! (ts.ts_flags & HAL_TX_BA); 4066 tx_ok = (ts.ts_status == 0); 4067 isaggr = bf_first->bf_state.bfs_aggr; 4068 ba[0] = ts.ts_ba_low; 4069 ba[1] = ts.ts_ba_high; 4070 4071 /* 4072 * Copy the TX completion status and the rate control 4073 * series from the first descriptor, as it may be freed 4074 * before the rate control code can get its grubby fingers 4075 * into things. 4076 */ 4077 memcpy(rc, bf_first->bf_state.bfs_rc, sizeof(rc)); 4078 4079 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4080 "%s: txa_start=%d, tx_ok=%d, status=%.8x, flags=%.8x, " 4081 "isaggr=%d, seq_st=%d, hasba=%d, ba=%.8x, %.8x\n", 4082 __func__, tap->txa_start, tx_ok, ts.ts_status, ts.ts_flags, 4083 isaggr, seq_st, hasba, ba[0], ba[1]); 4084 4085 /* Occasionally, the MAC sends a tx status for the wrong TID. */ 4086 if (tid != ts.ts_tid) { 4087 device_printf(sc->sc_dev, "%s: tid %d != hw tid %d\n", 4088 __func__, tid, ts.ts_tid); 4089 tx_ok = 0; 4090 } 4091 4092 /* AR5416 BA bug; this requires an interface reset */ 4093 if (isaggr && tx_ok && (! hasba)) { 4094 device_printf(sc->sc_dev, 4095 "%s: AR5416 bug: hasba=%d; txok=%d, isaggr=%d, " 4096 "seq_st=%d\n", 4097 __func__, hasba, tx_ok, isaggr, seq_st); 4098 /* XXX TODO: schedule an interface reset */ 4099#ifdef ATH_DEBUG 4100 ath_printtxbuf(sc, bf_first, 4101 sc->sc_ac2q[atid->ac]->axq_qnum, 0, 0); 4102#endif 4103 } 4104 4105 /* 4106 * Walk the list of frames, figure out which ones were correctly 4107 * sent and which weren't. 4108 */ 4109 bf = bf_first; 4110 nf = bf_first->bf_state.bfs_nframes; 4111 4112 /* bf_first is going to be invalid once this list is walked */ 4113 bf_first = NULL; 4114 4115 /* 4116 * Walk the list of completed frames and determine 4117 * which need to be completed and which need to be 4118 * retransmitted. 4119 * 4120 * For completed frames, the completion functions need 4121 * to be called at the end of this function as the last 4122 * node reference may free the node. 4123 * 4124 * Finally, since the TXQ lock can't be held during the 4125 * completion callback (to avoid lock recursion), 4126 * the completion calls have to be done outside of the 4127 * lock. 4128 */ 4129 while (bf) { 4130 nframes++; 4131 ba_index = ATH_BA_INDEX(seq_st, 4132 SEQNO(bf->bf_state.bfs_seqno)); 4133 bf_next = bf->bf_next; 4134 bf->bf_next = NULL; /* Remove it from the aggr list */ 4135 4136 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4137 "%s: checking bf=%p seqno=%d; ack=%d\n", 4138 __func__, bf, SEQNO(bf->bf_state.bfs_seqno), 4139 ATH_BA_ISSET(ba, ba_index)); 4140 4141 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) { 4142 sc->sc_stats.ast_tx_aggr_ok++; 4143 ath_tx_update_baw(sc, an, atid, bf); 4144 bf->bf_state.bfs_dobaw = 0; 4145 if (! bf->bf_state.bfs_addedbaw) 4146 device_printf(sc->sc_dev, 4147 "%s: wasn't added: seqno %d\n", 4148 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4149 bf->bf_next = NULL; 4150 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 4151 } else { 4152 sc->sc_stats.ast_tx_aggr_fail++; 4153 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 4154 drops++; 4155 bf->bf_next = NULL; 4156 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 4157 } 4158 nbad++; 4159 } 4160 bf = bf_next; 4161 } 4162 4163 /* 4164 * Now that the BAW updates have been done, unlock 4165 * 4166 * txseq is grabbed before the lock is released so we 4167 * have a consistent view of what -was- in the BAW. 4168 * Anything after this point will not yet have been 4169 * TXed. 4170 */ 4171 txseq = tap->txa_start; 4172 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4173 4174 if (nframes != nf) 4175 device_printf(sc->sc_dev, 4176 "%s: num frames seen=%d; bf nframes=%d\n", 4177 __func__, nframes, nf); 4178 4179 /* 4180 * Now we know how many frames were bad, call the rate 4181 * control code. 4182 */ 4183 if (fail == 0) 4184 ath_tx_update_ratectrl(sc, ni, rc, &ts, pktlen, nframes, 4185 nbad); 4186 4187 /* 4188 * send bar if we dropped any frames 4189 */ 4190 if (drops) { 4191 /* Suspend the TX queue and get ready to send the BAR */ 4192 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4193 ath_tx_tid_bar_suspend(sc, atid); 4194 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4195 } 4196 4197 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4198 "%s: txa_start now %d\n", __func__, tap->txa_start); 4199 4200 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4201 4202 /* Prepend all frames to the beginning of the queue */ 4203 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 4204 TAILQ_REMOVE(&bf_q, bf, bf_list); 4205 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list); 4206 } 4207 4208 /* 4209 * Reschedule to grab some further frames. 4210 */ 4211 ath_tx_tid_sched(sc, atid); 4212 4213 /* 4214 * If the queue is filtered, re-schedule as required. 4215 * 4216 * This is required as there may be a subsequent TX descriptor 4217 * for this end-node that has CLRDMASK set, so it's quite possible 4218 * that a filtered frame will be followed by a non-filtered 4219 * (complete or otherwise) frame. 4220 * 4221 * XXX should we do this before we complete the frame? 4222 */ 4223 if (atid->isfiltered) 4224 ath_tx_tid_filt_comp_complete(sc, atid); 4225 4226finish_send_bar: 4227 4228 /* 4229 * Send BAR if required 4230 */ 4231 if (ath_tx_tid_bar_tx_ready(sc, atid)) 4232 ath_tx_tid_bar_tx(sc, atid); 4233 4234 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4235 4236 /* Do deferred completion */ 4237 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 4238 TAILQ_REMOVE(&bf_cq, bf, bf_list); 4239 ath_tx_default_comp(sc, bf, 0); 4240 } 4241} 4242 4243/* 4244 * Handle completion of unaggregated frames in an ADDBA 4245 * session. 4246 * 4247 * Fail is set to 1 if the entry is being freed via a call to 4248 * ath_tx_draintxq(). 4249 */ 4250static void 4251ath_tx_aggr_comp_unaggr(struct ath_softc *sc, struct ath_buf *bf, int fail) 4252{ 4253 struct ieee80211_node *ni = bf->bf_node; 4254 struct ath_node *an = ATH_NODE(ni); 4255 int tid = bf->bf_state.bfs_tid; 4256 struct ath_tid *atid = &an->an_tid[tid]; 4257 struct ath_tx_status ts; 4258 int drops = 0; 4259 4260 /* 4261 * Take a copy of this; filtering/cloning the frame may free the 4262 * bf pointer. 4263 */ 4264 ts = bf->bf_status.ds_txstat; 4265 4266 /* 4267 * Update rate control status here, before we possibly 4268 * punt to retry or cleanup. 4269 * 4270 * Do it outside of the TXQ lock. 4271 */ 4272 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 4273 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 4274 &bf->bf_status.ds_txstat, 4275 bf->bf_state.bfs_pktlen, 4276 1, (ts.ts_status == 0) ? 0 : 1); 4277 4278 /* 4279 * This is called early so atid->hwq_depth can be tracked. 4280 * This unfortunately means that it's released and regrabbed 4281 * during retry and cleanup. That's rather inefficient. 4282 */ 4283 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4284 4285 if (tid == IEEE80211_NONQOS_TID) 4286 device_printf(sc->sc_dev, "%s: TID=16!\n", __func__); 4287 4288 DPRINTF(sc, ATH_DEBUG_SW_TX, 4289 "%s: bf=%p: tid=%d, hwq_depth=%d, seqno=%d\n", 4290 __func__, bf, bf->bf_state.bfs_tid, atid->hwq_depth, 4291 SEQNO(bf->bf_state.bfs_seqno)); 4292 4293 atid->hwq_depth--; 4294 if (atid->hwq_depth < 0) 4295 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 4296 __func__, atid->hwq_depth); 4297 4298 /* 4299 * If the TID is filtered, handle completing the filter 4300 * transition before potentially kicking it to the cleanup 4301 * function. 4302 */ 4303 if (atid->isfiltered) 4304 ath_tx_tid_filt_comp_complete(sc, atid); 4305 4306 /* 4307 * If a cleanup is in progress, punt to comp_cleanup; 4308 * rather than handling it here. It's thus their 4309 * responsibility to clean up, call the completion 4310 * function in net80211, etc. 4311 */ 4312 if (atid->cleanup_inprogress) { 4313 if (atid->isfiltered) 4314 device_printf(sc->sc_dev, 4315 "%s: isfiltered=1, normal_comp?\n", 4316 __func__); 4317 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4318 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: cleanup_unaggr\n", 4319 __func__); 4320 ath_tx_comp_cleanup_unaggr(sc, bf); 4321 return; 4322 } 4323 4324 /* 4325 * XXX TODO: how does cleanup, BAR and filtered frame handling 4326 * overlap? 4327 * 4328 * If the frame is filtered OR if it's any failure but 4329 * the TID is filtered, the frame must be added to the 4330 * filtered frame list. 4331 * 4332 * However - a busy buffer can't be added to the filtered 4333 * list as it will end up being recycled without having 4334 * been made available for the hardware. 4335 */ 4336 if ((ts.ts_status & HAL_TXERR_FILT) || 4337 (ts.ts_status != 0 && atid->isfiltered)) { 4338 int freeframe; 4339 4340 if (fail != 0) 4341 device_printf(sc->sc_dev, 4342 "%s: isfiltered=1, fail=%d\n", 4343 __func__, 4344 fail); 4345 freeframe = ath_tx_tid_filt_comp_single(sc, atid, bf); 4346 if (freeframe) { 4347 /* Remove from BAW */ 4348 if (bf->bf_state.bfs_addedbaw) 4349 drops++; 4350 if (bf->bf_state.bfs_dobaw) { 4351 ath_tx_update_baw(sc, an, atid, bf); 4352 if (! bf->bf_state.bfs_addedbaw) 4353 device_printf(sc->sc_dev, 4354 "%s: wasn't added: seqno %d\n", 4355 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4356 } 4357 bf->bf_state.bfs_dobaw = 0; 4358 } 4359 4360 /* 4361 * If the frame couldn't be filtered, treat it as a drop and 4362 * prepare to send a BAR. 4363 */ 4364 if (freeframe && drops) 4365 ath_tx_tid_bar_suspend(sc, atid); 4366 4367 /* 4368 * Send BAR if required 4369 */ 4370 if (ath_tx_tid_bar_tx_ready(sc, atid)) 4371 ath_tx_tid_bar_tx(sc, atid); 4372 4373 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4374 /* 4375 * If freeframe is set, then the frame couldn't be 4376 * cloned and bf is still valid. Just complete/free it. 4377 */ 4378 if (freeframe) 4379 ath_tx_default_comp(sc, bf, fail); 4380 4381 4382 return; 4383 } 4384 /* 4385 * Don't bother with the retry check if all frames 4386 * are being failed (eg during queue deletion.) 4387 */ 4388#if 0 4389 if (fail == 0 && ts->ts_status & HAL_TXERR_XRETRY) { 4390#endif 4391 if (fail == 0 && ts.ts_status != 0) { 4392 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4393 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: retry_unaggr\n", 4394 __func__); 4395 ath_tx_aggr_retry_unaggr(sc, bf); 4396 return; 4397 } 4398 4399 /* Success? Complete */ 4400 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: TID=%d, seqno %d\n", 4401 __func__, tid, SEQNO(bf->bf_state.bfs_seqno)); 4402 if (bf->bf_state.bfs_dobaw) { 4403 ath_tx_update_baw(sc, an, atid, bf); 4404 bf->bf_state.bfs_dobaw = 0; 4405 if (! bf->bf_state.bfs_addedbaw) 4406 device_printf(sc->sc_dev, 4407 "%s: wasn't added: seqno %d\n", 4408 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4409 } 4410 4411 /* 4412 * If the queue is filtered, re-schedule as required. 4413 * 4414 * This is required as there may be a subsequent TX descriptor 4415 * for this end-node that has CLRDMASK set, so it's quite possible 4416 * that a filtered frame will be followed by a non-filtered 4417 * (complete or otherwise) frame. 4418 * 4419 * XXX should we do this before we complete the frame? 4420 */ 4421 if (atid->isfiltered) 4422 ath_tx_tid_filt_comp_complete(sc, atid); 4423 4424 /* 4425 * Send BAR if required 4426 */ 4427 if (ath_tx_tid_bar_tx_ready(sc, atid)) 4428 ath_tx_tid_bar_tx(sc, atid); 4429 4430 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4431 4432 ath_tx_default_comp(sc, bf, fail); 4433 /* bf is freed at this point */ 4434} 4435 4436void 4437ath_tx_aggr_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 4438{ 4439 if (bf->bf_state.bfs_aggr) 4440 ath_tx_aggr_comp_aggr(sc, bf, fail); 4441 else 4442 ath_tx_aggr_comp_unaggr(sc, bf, fail); 4443} 4444 4445/* 4446 * Schedule some packets from the given node/TID to the hardware. 4447 * 4448 * This is the aggregate version. 4449 */ 4450void 4451ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an, 4452 struct ath_tid *tid) 4453{ 4454 struct ath_buf *bf; 4455 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 4456 struct ieee80211_tx_ampdu *tap; 4457 ATH_AGGR_STATUS status; 4458 ath_bufhead bf_q; 4459 4460 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d\n", __func__, tid->tid); 4461 ATH_TXQ_LOCK_ASSERT(txq); 4462 4463 tap = ath_tx_get_tx_tid(an, tid->tid); 4464 4465 if (tid->tid == IEEE80211_NONQOS_TID) 4466 device_printf(sc->sc_dev, "%s: called for TID=NONQOS_TID?\n", 4467 __func__); 4468 4469 for (;;) { 4470 status = ATH_AGGR_DONE; 4471 4472 /* 4473 * If the upper layer has paused the TID, don't 4474 * queue any further packets. 4475 * 4476 * This can also occur from the completion task because 4477 * of packet loss; but as its serialised with this code, 4478 * it won't "appear" half way through queuing packets. 4479 */ 4480 if (tid->paused) 4481 break; 4482 4483 bf = TAILQ_FIRST(&tid->axq_q); 4484 if (bf == NULL) { 4485 break; 4486 } 4487 4488 /* 4489 * If the packet doesn't fall within the BAW (eg a NULL 4490 * data frame), schedule it directly; continue. 4491 */ 4492 if (! bf->bf_state.bfs_dobaw) { 4493 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4494 "%s: non-baw packet\n", 4495 __func__); 4496 ATH_TXQ_REMOVE(tid, bf, bf_list); 4497 4498 if (bf->bf_state.bfs_nframes > 1) 4499 device_printf(sc->sc_dev, 4500 "%s: aggr=%d, nframes=%d\n", 4501 __func__, 4502 bf->bf_state.bfs_aggr, 4503 bf->bf_state.bfs_nframes); 4504 4505 /* 4506 * This shouldn't happen - such frames shouldn't 4507 * ever have been queued as an aggregate in the 4508 * first place. However, make sure the fields 4509 * are correctly setup just to be totally sure. 4510 */ 4511 bf->bf_state.bfs_aggr = 0; 4512 bf->bf_state.bfs_nframes = 1; 4513 4514 ath_tx_do_ratelookup(sc, bf); 4515 ath_tx_calc_duration(sc, bf); 4516 ath_tx_calc_protection(sc, bf); 4517 ath_tx_set_rtscts(sc, bf); 4518 ath_tx_rate_fill_rcflags(sc, bf); 4519 ath_tx_setds(sc, bf); 4520 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 4521 4522 sc->sc_aggr_stats.aggr_nonbaw_pkt++; 4523 4524 /* Queue the packet; continue */ 4525 goto queuepkt; 4526 } 4527 4528 TAILQ_INIT(&bf_q); 4529 4530 /* 4531 * Do a rate control lookup on the first frame in the 4532 * list. The rate control code needs that to occur 4533 * before it can determine whether to TX. 4534 * It's inaccurate because the rate control code doesn't 4535 * really "do" aggregate lookups, so it only considers 4536 * the size of the first frame. 4537 */ 4538 ath_tx_do_ratelookup(sc, bf); 4539 bf->bf_state.bfs_rc[3].rix = 0; 4540 bf->bf_state.bfs_rc[3].tries = 0; 4541 4542 ath_tx_calc_duration(sc, bf); 4543 ath_tx_calc_protection(sc, bf); 4544 4545 ath_tx_set_rtscts(sc, bf); 4546 ath_tx_rate_fill_rcflags(sc, bf); 4547 4548 status = ath_tx_form_aggr(sc, an, tid, &bf_q); 4549 4550 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4551 "%s: ath_tx_form_aggr() status=%d\n", __func__, status); 4552 4553 /* 4554 * No frames to be picked up - out of BAW 4555 */ 4556 if (TAILQ_EMPTY(&bf_q)) 4557 break; 4558 4559 /* 4560 * This assumes that the descriptor list in the ath_bufhead 4561 * are already linked together via bf_next pointers. 4562 */ 4563 bf = TAILQ_FIRST(&bf_q); 4564 4565 if (status == ATH_AGGR_8K_LIMITED) 4566 sc->sc_aggr_stats.aggr_rts_aggr_limited++; 4567 4568 /* 4569 * If it's the only frame send as non-aggregate 4570 * assume that ath_tx_form_aggr() has checked 4571 * whether it's in the BAW and added it appropriately. 4572 */ 4573 if (bf->bf_state.bfs_nframes == 1) { 4574 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4575 "%s: single-frame aggregate\n", __func__); 4576 bf->bf_state.bfs_aggr = 0; 4577 bf->bf_state.bfs_ndelim = 0; 4578 ath_tx_setds(sc, bf); 4579 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 4580 if (status == ATH_AGGR_BAW_CLOSED) 4581 sc->sc_aggr_stats.aggr_baw_closed_single_pkt++; 4582 else 4583 sc->sc_aggr_stats.aggr_single_pkt++; 4584 } else { 4585 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4586 "%s: multi-frame aggregate: %d frames, " 4587 "length %d\n", 4588 __func__, bf->bf_state.bfs_nframes, 4589 bf->bf_state.bfs_al); 4590 bf->bf_state.bfs_aggr = 1; 4591 sc->sc_aggr_stats.aggr_pkts[bf->bf_state.bfs_nframes]++; 4592 sc->sc_aggr_stats.aggr_aggr_pkt++; 4593 4594 /* 4595 * Calculate the duration/protection as required. 4596 */ 4597 ath_tx_calc_duration(sc, bf); 4598 ath_tx_calc_protection(sc, bf); 4599 4600 /* 4601 * Update the rate and rtscts information based on the 4602 * rate decision made by the rate control code; 4603 * the first frame in the aggregate needs it. 4604 */ 4605 ath_tx_set_rtscts(sc, bf); 4606 4607 /* 4608 * Setup the relevant descriptor fields 4609 * for aggregation. The first descriptor 4610 * already points to the rest in the chain. 4611 */ 4612 ath_tx_setds_11n(sc, bf); 4613 4614 } 4615 queuepkt: 4616 //txq = bf->bf_state.bfs_txq; 4617 4618 /* Set completion handler, multi-frame aggregate or not */ 4619 bf->bf_comp = ath_tx_aggr_comp; 4620 4621 if (bf->bf_state.bfs_tid == IEEE80211_NONQOS_TID) 4622 device_printf(sc->sc_dev, "%s: TID=16?\n", __func__); 4623 4624 /* Punt to txq */ 4625 ath_tx_handoff(sc, txq, bf); 4626 4627 /* Track outstanding buffer count to hardware */ 4628 /* aggregates are "one" buffer */ 4629 tid->hwq_depth++; 4630 4631 /* 4632 * Break out if ath_tx_form_aggr() indicated 4633 * there can't be any further progress (eg BAW is full.) 4634 * Checking for an empty txq is done above. 4635 * 4636 * XXX locking on txq here? 4637 */ 4638 if (txq->axq_aggr_depth >= sc->sc_hwq_limit || 4639 status == ATH_AGGR_BAW_CLOSED) 4640 break; 4641 } 4642} 4643 4644/* 4645 * Schedule some packets from the given node/TID to the hardware. 4646 */ 4647void 4648ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an, 4649 struct ath_tid *tid) 4650{ 4651 struct ath_buf *bf; 4652 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 4653 4654 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: node %p: TID %d: called\n", 4655 __func__, an, tid->tid); 4656 4657 ATH_TXQ_LOCK_ASSERT(txq); 4658 4659 /* Check - is AMPDU pending or running? then print out something */ 4660 if (ath_tx_ampdu_pending(sc, an, tid->tid)) 4661 device_printf(sc->sc_dev, "%s: tid=%d, ampdu pending?\n", 4662 __func__, tid->tid); 4663 if (ath_tx_ampdu_running(sc, an, tid->tid)) 4664 device_printf(sc->sc_dev, "%s: tid=%d, ampdu running?\n", 4665 __func__, tid->tid); 4666 4667 for (;;) { 4668 4669 /* 4670 * If the upper layers have paused the TID, don't 4671 * queue any further packets. 4672 */ 4673 if (tid->paused) 4674 break; 4675 4676 bf = TAILQ_FIRST(&tid->axq_q); 4677 if (bf == NULL) { 4678 break; 4679 } 4680 4681 ATH_TXQ_REMOVE(tid, bf, bf_list); 4682 4683 KASSERT(txq == bf->bf_state.bfs_txq, ("txqs not equal!\n")); 4684 4685 /* Sanity check! */ 4686 if (tid->tid != bf->bf_state.bfs_tid) { 4687 device_printf(sc->sc_dev, "%s: bfs_tid %d !=" 4688 " tid %d\n", 4689 __func__, bf->bf_state.bfs_tid, tid->tid); 4690 } 4691 /* Normal completion handler */ 4692 bf->bf_comp = ath_tx_normal_comp; 4693 4694 /* Program descriptors + rate control */ 4695 ath_tx_do_ratelookup(sc, bf); 4696 ath_tx_calc_duration(sc, bf); 4697 ath_tx_calc_protection(sc, bf); 4698 ath_tx_set_rtscts(sc, bf); 4699 ath_tx_rate_fill_rcflags(sc, bf); 4700 ath_tx_setds(sc, bf); 4701 4702 /* Track outstanding buffer count to hardware */ 4703 /* aggregates are "one" buffer */ 4704 tid->hwq_depth++; 4705 4706 /* Punt to hardware or software txq */ 4707 ath_tx_handoff(sc, txq, bf); 4708 } 4709} 4710 4711/* 4712 * Schedule some packets to the given hardware queue. 4713 * 4714 * This function walks the list of TIDs (ie, ath_node TIDs 4715 * with queued traffic) and attempts to schedule traffic 4716 * from them. 4717 * 4718 * TID scheduling is implemented as a FIFO, with TIDs being 4719 * added to the end of the queue after some frames have been 4720 * scheduled. 4721 */ 4722void 4723ath_txq_sched(struct ath_softc *sc, struct ath_txq *txq) 4724{ 4725 struct ath_tid *tid, *next, *last; 4726 4727 ATH_TXQ_LOCK_ASSERT(txq); 4728 4729 /* 4730 * Don't schedule if the hardware queue is busy. 4731 * This (hopefully) gives some more time to aggregate 4732 * some packets in the aggregation queue. 4733 */ 4734 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 4735 sc->sc_aggr_stats.aggr_sched_nopkt++; 4736 return; 4737 } 4738 4739 last = TAILQ_LAST(&txq->axq_tidq, axq_t_s); 4740 4741 TAILQ_FOREACH_SAFE(tid, &txq->axq_tidq, axq_qelem, next) { 4742 /* 4743 * Suspend paused queues here; they'll be resumed 4744 * once the addba completes or times out. 4745 */ 4746 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, paused=%d\n", 4747 __func__, tid->tid, tid->paused); 4748 ath_tx_tid_unsched(sc, tid); 4749 if (tid->paused) { 4750 continue; 4751 } 4752 if (ath_tx_ampdu_running(sc, tid->an, tid->tid)) 4753 ath_tx_tid_hw_queue_aggr(sc, tid->an, tid); 4754 else 4755 ath_tx_tid_hw_queue_norm(sc, tid->an, tid); 4756 4757 /* Not empty? Re-schedule */ 4758 if (tid->axq_depth != 0) 4759 ath_tx_tid_sched(sc, tid); 4760 4761 /* Give the software queue time to aggregate more packets */ 4762 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 4763 break; 4764 } 4765 4766 /* 4767 * If this was the last entry on the original list, stop. 4768 * Otherwise nodes that have been rescheduled onto the end 4769 * of the TID FIFO list will just keep being rescheduled. 4770 */ 4771 if (tid == last) 4772 break; 4773 } 4774} 4775 4776/* 4777 * TX addba handling 4778 */ 4779 4780/* 4781 * Return net80211 TID struct pointer, or NULL for none 4782 */ 4783struct ieee80211_tx_ampdu * 4784ath_tx_get_tx_tid(struct ath_node *an, int tid) 4785{ 4786 struct ieee80211_node *ni = &an->an_node; 4787 struct ieee80211_tx_ampdu *tap; 4788 4789 if (tid == IEEE80211_NONQOS_TID) 4790 return NULL; 4791 4792 tap = &ni->ni_tx_ampdu[tid]; 4793 return tap; 4794} 4795 4796/* 4797 * Is AMPDU-TX running? 4798 */ 4799static int 4800ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, int tid) 4801{ 4802 struct ieee80211_tx_ampdu *tap; 4803 4804 if (tid == IEEE80211_NONQOS_TID) 4805 return 0; 4806 4807 tap = ath_tx_get_tx_tid(an, tid); 4808 if (tap == NULL) 4809 return 0; /* Not valid; default to not running */ 4810 4811 return !! (tap->txa_flags & IEEE80211_AGGR_RUNNING); 4812} 4813 4814/* 4815 * Is AMPDU-TX negotiation pending? 4816 */ 4817static int 4818ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid) 4819{ 4820 struct ieee80211_tx_ampdu *tap; 4821 4822 if (tid == IEEE80211_NONQOS_TID) 4823 return 0; 4824 4825 tap = ath_tx_get_tx_tid(an, tid); 4826 if (tap == NULL) 4827 return 0; /* Not valid; default to not pending */ 4828 4829 return !! (tap->txa_flags & IEEE80211_AGGR_XCHGPEND); 4830} 4831 4832/* 4833 * Is AMPDU-TX pending for the given TID? 4834 */ 4835 4836 4837/* 4838 * Method to handle sending an ADDBA request. 4839 * 4840 * We tap this so the relevant flags can be set to pause the TID 4841 * whilst waiting for the response. 4842 * 4843 * XXX there's no timeout handler we can override? 4844 */ 4845int 4846ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4847 int dialogtoken, int baparamset, int batimeout) 4848{ 4849 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4850 int tid = tap->txa_tid; 4851 struct ath_node *an = ATH_NODE(ni); 4852 struct ath_tid *atid = &an->an_tid[tid]; 4853 4854 /* 4855 * XXX danger Will Robinson! 4856 * 4857 * Although the taskqueue may be running and scheduling some more 4858 * packets, these should all be _before_ the addba sequence number. 4859 * However, net80211 will keep self-assigning sequence numbers 4860 * until addba has been negotiated. 4861 * 4862 * In the past, these packets would be "paused" (which still works 4863 * fine, as they're being scheduled to the driver in the same 4864 * serialised method which is calling the addba request routine) 4865 * and when the aggregation session begins, they'll be dequeued 4866 * as aggregate packets and added to the BAW. However, now there's 4867 * a "bf->bf_state.bfs_dobaw" flag, and this isn't set for these 4868 * packets. Thus they never get included in the BAW tracking and 4869 * this can cause the initial burst of packets after the addba 4870 * negotiation to "hang", as they quickly fall outside the BAW. 4871 * 4872 * The "eventual" solution should be to tag these packets with 4873 * dobaw. Although net80211 has given us a sequence number, 4874 * it'll be "after" the left edge of the BAW and thus it'll 4875 * fall within it. 4876 */ 4877 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4878 /* 4879 * This is a bit annoying. Until net80211 HT code inherits some 4880 * (any) locking, we may have this called in parallel BUT only 4881 * one response/timeout will be called. Grr. 4882 */ 4883 if (atid->addba_tx_pending == 0) { 4884 ath_tx_tid_pause(sc, atid); 4885 atid->addba_tx_pending = 1; 4886 } 4887 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4888 4889 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4890 "%s: called; dialogtoken=%d, baparamset=%d, batimeout=%d\n", 4891 __func__, dialogtoken, baparamset, batimeout); 4892 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4893 "%s: txa_start=%d, ni_txseqs=%d\n", 4894 __func__, tap->txa_start, ni->ni_txseqs[tid]); 4895 4896 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 4897 batimeout); 4898} 4899 4900/* 4901 * Handle an ADDBA response. 4902 * 4903 * We unpause the queue so TX'ing can resume. 4904 * 4905 * Any packets TX'ed from this point should be "aggregate" (whether 4906 * aggregate or not) so the BAW is updated. 4907 * 4908 * Note! net80211 keeps self-assigning sequence numbers until 4909 * ampdu is negotiated. This means the initially-negotiated BAW left 4910 * edge won't match the ni->ni_txseq. 4911 * 4912 * So, being very dirty, the BAW left edge is "slid" here to match 4913 * ni->ni_txseq. 4914 * 4915 * What likely SHOULD happen is that all packets subsequent to the 4916 * addba request should be tagged as aggregate and queued as non-aggregate 4917 * frames; thus updating the BAW. For now though, I'll just slide the 4918 * window. 4919 */ 4920int 4921ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4922 int status, int code, int batimeout) 4923{ 4924 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4925 int tid = tap->txa_tid; 4926 struct ath_node *an = ATH_NODE(ni); 4927 struct ath_tid *atid = &an->an_tid[tid]; 4928 int r; 4929 4930 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4931 "%s: called; status=%d, code=%d, batimeout=%d\n", __func__, 4932 status, code, batimeout); 4933 4934 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4935 "%s: txa_start=%d, ni_txseqs=%d\n", 4936 __func__, tap->txa_start, ni->ni_txseqs[tid]); 4937 4938 /* 4939 * Call this first, so the interface flags get updated 4940 * before the TID is unpaused. Otherwise a race condition 4941 * exists where the unpaused TID still doesn't yet have 4942 * IEEE80211_AGGR_RUNNING set. 4943 */ 4944 r = sc->sc_addba_response(ni, tap, status, code, batimeout); 4945 4946 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4947 atid->addba_tx_pending = 0; 4948 /* 4949 * XXX dirty! 4950 * Slide the BAW left edge to wherever net80211 left it for us. 4951 * Read above for more information. 4952 */ 4953 tap->txa_start = ni->ni_txseqs[tid]; 4954 ath_tx_tid_resume(sc, atid); 4955 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4956 return r; 4957} 4958 4959 4960/* 4961 * Stop ADDBA on a queue. 4962 * 4963 * This can be called whilst BAR TX is currently active on the queue, 4964 * so make sure this is unblocked before continuing. 4965 */ 4966void 4967ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 4968{ 4969 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4970 int tid = tap->txa_tid; 4971 struct ath_node *an = ATH_NODE(ni); 4972 struct ath_tid *atid = &an->an_tid[tid]; 4973 4974 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: called\n", __func__); 4975 4976 /* 4977 * Pause TID traffic early, so there aren't any races 4978 * Unblock the pending BAR held traffic, if it's currently paused. 4979 */ 4980 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4981 ath_tx_tid_pause(sc, atid); 4982 if (atid->bar_wait) { 4983 /* 4984 * bar_unsuspend() expects bar_tx == 1, as it should be 4985 * called from the TX completion path. This quietens 4986 * the warning. It's cleared for us anyway. 4987 */ 4988 atid->bar_tx = 1; 4989 ath_tx_tid_bar_unsuspend(sc, atid); 4990 } 4991 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4992 4993 /* There's no need to hold the TXQ lock here */ 4994 sc->sc_addba_stop(ni, tap); 4995 4996 /* 4997 * ath_tx_tid_cleanup will resume the TID if possible, otherwise 4998 * it'll set the cleanup flag, and it'll be unpaused once 4999 * things have been cleaned up. 5000 */ 5001 ath_tx_tid_cleanup(sc, an, tid); 5002} 5003 5004/* 5005 * Note: net80211 bar_timeout() doesn't call this function on BAR failure; 5006 * it simply tears down the aggregation session. Ew. 5007 * 5008 * It however will call ieee80211_ampdu_stop() which will call 5009 * ic->ic_addba_stop(). 5010 * 5011 * XXX This uses a hard-coded max BAR count value; the whole 5012 * XXX BAR TX success or failure should be better handled! 5013 */ 5014void 5015ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5016 int status) 5017{ 5018 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5019 int tid = tap->txa_tid; 5020 struct ath_node *an = ATH_NODE(ni); 5021 struct ath_tid *atid = &an->an_tid[tid]; 5022 int attempts = tap->txa_attempts; 5023 5024 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 5025 "%s: called; tap=%p, atid=%p, txa_tid=%d, atid->tid=%d, status=%d, attempts=%d\n", 5026 __func__, 5027 tap, 5028 atid, 5029 tap->txa_tid, 5030 atid->tid, 5031 status, 5032 attempts); 5033 5034 /* Note: This may update the BAW details */ 5035 sc->sc_bar_response(ni, tap, status); 5036 5037 /* Unpause the TID */ 5038 /* 5039 * XXX if this is attempt=50, the TID will be downgraded 5040 * XXX to a non-aggregate session. So we must unpause the 5041 * XXX TID here or it'll never be done. 5042 * 5043 * Also, don't call it if bar_tx/bar_wait are 0; something 5044 * has beaten us to the punch? (XXX figure out what?) 5045 */ 5046 if (status == 0 || attempts == 50) { 5047 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 5048 if (atid->bar_tx == 0 || atid->bar_wait == 0) 5049 device_printf(sc->sc_dev, 5050 "%s: huh? bar_tx=%d, bar_wait=%d\n", 5051 __func__, 5052 atid->bar_tx, atid->bar_wait); 5053 else 5054 ath_tx_tid_bar_unsuspend(sc, atid); 5055 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 5056 } 5057} 5058 5059/* 5060 * This is called whenever the pending ADDBA request times out. 5061 * Unpause and reschedule the TID. 5062 */ 5063void 5064ath_addba_response_timeout(struct ieee80211_node *ni, 5065 struct ieee80211_tx_ampdu *tap) 5066{ 5067 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5068 int tid = tap->txa_tid; 5069 struct ath_node *an = ATH_NODE(ni); 5070 struct ath_tid *atid = &an->an_tid[tid]; 5071 5072 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 5073 "%s: called; resuming\n", __func__); 5074 5075 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 5076 atid->addba_tx_pending = 0; 5077 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 5078 5079 /* Note: This updates the aggregate state to (again) pending */ 5080 sc->sc_addba_response_timeout(ni, tap); 5081 5082 /* Unpause the TID; which reschedules it */ 5083 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 5084 ath_tx_tid_resume(sc, atid); 5085 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 5086} 5087 5088static int 5089ath_legacy_dma_txsetup(struct ath_softc *sc) 5090{ 5091 5092 /* nothing new needed */ 5093 return (0); 5094} 5095 5096static int 5097ath_legacy_dma_txteardown(struct ath_softc *sc) 5098{ 5099 5100 /* nothing new needed */ 5101 return (0); 5102} 5103 5104void 5105ath_xmit_setup_legacy(struct ath_softc *sc) 5106{ 5107 /* 5108 * For now, just set the descriptor length to sizeof(ath_desc); 5109 * worry about extracting the real length out of the HAL later. 5110 */ 5111 sc->sc_tx_desclen = sizeof(struct ath_desc); 5112 sc->sc_tx_statuslen = 0; 5113 sc->sc_tx_nmaps = 1; /* only one buffer per TX desc */ 5114 5115 sc->sc_tx.xmit_setup = ath_legacy_dma_txsetup; 5116 sc->sc_tx.xmit_teardown = ath_legacy_dma_txteardown; 5117 sc->sc_tx.xmit_attach_comp_func = ath_legacy_attach_comp_func; 5118 5119 sc->sc_tx.xmit_dma_restart = ath_legacy_tx_dma_restart; 5120 sc->sc_tx.xmit_handoff = ath_legacy_xmit_handoff; 5121 5122 sc->sc_tx.xmit_drain = ath_legacy_tx_drain; 5123} 5124