if_ath_tx.c revision 233673
10Sstevel@tonic-gate/*- 20Sstevel@tonic-gate * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 30Sstevel@tonic-gate * All rights reserved. 40Sstevel@tonic-gate * 57060Srm160521 * Redistribution and use in source and binary forms, with or without 67060Srm160521 * modification, are permitted provided that the following conditions 70Sstevel@tonic-gate * are met: 80Sstevel@tonic-gate * 1. Redistributions of source code must retain the above copyright 90Sstevel@tonic-gate * notice, this list of conditions and the following disclaimer, 100Sstevel@tonic-gate * without modification. 110Sstevel@tonic-gate * 2. Redistributions in binary form must reproduce at minimum a disclaimer 120Sstevel@tonic-gate * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 130Sstevel@tonic-gate * redistribution must be conditioned upon including a substantially 140Sstevel@tonic-gate * similar Disclaimer requirement for further binary redistribution. 150Sstevel@tonic-gate * 160Sstevel@tonic-gate * NO WARRANTY 170Sstevel@tonic-gate * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 180Sstevel@tonic-gate * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 190Sstevel@tonic-gate * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 200Sstevel@tonic-gate * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 210Sstevel@tonic-gate * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 227060Srm160521 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 230Sstevel@tonic-gate * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 240Sstevel@tonic-gate * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 250Sstevel@tonic-gate * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 260Sstevel@tonic-gate * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 270Sstevel@tonic-gate * THE POSSIBILITY OF SUCH DAMAGES. 280Sstevel@tonic-gate */ 290Sstevel@tonic-gate 300Sstevel@tonic-gate#include <sys/cdefs.h> 310Sstevel@tonic-gate__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_tx.c 233673 2012-03-29 17:39:18Z adrian $"); 320Sstevel@tonic-gate 331107Ssjelinek/* 340Sstevel@tonic-gate * Driver for the Atheros Wireless LAN controller. 350Sstevel@tonic-gate * 360Sstevel@tonic-gate * This software is derived from work of Atsushi Onoe; his contribution 370Sstevel@tonic-gate * is greatly appreciated. 381107Ssjelinek */ 390Sstevel@tonic-gate 400Sstevel@tonic-gate#include "opt_inet.h" 410Sstevel@tonic-gate#include "opt_ath.h" 420Sstevel@tonic-gate#include "opt_wlan.h" 430Sstevel@tonic-gate 440Sstevel@tonic-gate#include <sys/param.h> 450Sstevel@tonic-gate#include <sys/systm.h> 460Sstevel@tonic-gate#include <sys/sysctl.h> 470Sstevel@tonic-gate#include <sys/mbuf.h> 487060Srm160521#include <sys/malloc.h> 490Sstevel@tonic-gate#include <sys/lock.h> 500Sstevel@tonic-gate#include <sys/mutex.h> 510Sstevel@tonic-gate#include <sys/kernel.h> 520Sstevel@tonic-gate#include <sys/socket.h> 530Sstevel@tonic-gate#include <sys/sockio.h> 540Sstevel@tonic-gate#include <sys/errno.h> 550Sstevel@tonic-gate#include <sys/callout.h> 560Sstevel@tonic-gate#include <sys/bus.h> 570Sstevel@tonic-gate#include <sys/endian.h> 580Sstevel@tonic-gate#include <sys/kthread.h> 590Sstevel@tonic-gate#include <sys/taskqueue.h> 600Sstevel@tonic-gate#include <sys/priv.h> 610Sstevel@tonic-gate 620Sstevel@tonic-gate#include <machine/bus.h> 630Sstevel@tonic-gate 640Sstevel@tonic-gate#include <net/if.h> 650Sstevel@tonic-gate#include <net/if_dl.h> 660Sstevel@tonic-gate#include <net/if_media.h> 670Sstevel@tonic-gate#include <net/if_types.h> 680Sstevel@tonic-gate#include <net/if_arp.h> 690Sstevel@tonic-gate#include <net/ethernet.h> 700Sstevel@tonic-gate#include <net/if_llc.h> 710Sstevel@tonic-gate 720Sstevel@tonic-gate#include <net80211/ieee80211_var.h> 730Sstevel@tonic-gate#include <net80211/ieee80211_regdomain.h> 740Sstevel@tonic-gate#ifdef IEEE80211_SUPPORT_SUPERG 750Sstevel@tonic-gate#include <net80211/ieee80211_superg.h> 760Sstevel@tonic-gate#endif 770Sstevel@tonic-gate#ifdef IEEE80211_SUPPORT_TDMA 780Sstevel@tonic-gate#include <net80211/ieee80211_tdma.h> 790Sstevel@tonic-gate#endif 800Sstevel@tonic-gate#include <net80211/ieee80211_ht.h> 810Sstevel@tonic-gate 820Sstevel@tonic-gate#include <net/bpf.h> 830Sstevel@tonic-gate 840Sstevel@tonic-gate#ifdef INET 850Sstevel@tonic-gate#include <netinet/in.h> 860Sstevel@tonic-gate#include <netinet/if_ether.h> 870Sstevel@tonic-gate#endif 880Sstevel@tonic-gate 890Sstevel@tonic-gate#include <dev/ath/if_athvar.h> 900Sstevel@tonic-gate#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 917060Srm160521#include <dev/ath/ath_hal/ah_diagcodes.h> 920Sstevel@tonic-gate 930Sstevel@tonic-gate#include <dev/ath/if_ath_debug.h> 940Sstevel@tonic-gate 950Sstevel@tonic-gate#ifdef ATH_TX99_DIAG 960Sstevel@tonic-gate#include <dev/ath/ath_tx99/ath_tx99.h> 970Sstevel@tonic-gate#endif 980Sstevel@tonic-gate 997060Srm160521#include <dev/ath/if_ath_misc.h> 1000Sstevel@tonic-gate#include <dev/ath/if_ath_tx.h> 1010Sstevel@tonic-gate#include <dev/ath/if_ath_tx_ht.h> 1027060Srm160521 1030Sstevel@tonic-gate/* 1040Sstevel@tonic-gate * How many retries to perform in software 1050Sstevel@tonic-gate */ 1060Sstevel@tonic-gate#define SWMAX_RETRIES 10 1077060Srm160521 1080Sstevel@tonic-gatestatic int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, 1090Sstevel@tonic-gate int tid); 1100Sstevel@tonic-gatestatic int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, 1110Sstevel@tonic-gate int tid); 1120Sstevel@tonic-gatestatic int ath_tx_action_frame_override_queue(struct ath_softc *sc, 1130Sstevel@tonic-gate struct ieee80211_node *ni, struct mbuf *m0, int *tid); 1140Sstevel@tonic-gatestatic int ath_tx_seqno_required(struct ath_softc *sc, 1150Sstevel@tonic-gate struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0); 1167060Srm160521 1170Sstevel@tonic-gate/* 1180Sstevel@tonic-gate * Whether to use the 11n rate scenario functions or not 1190Sstevel@tonic-gate */ 1200Sstevel@tonic-gatestatic inline int 1210Sstevel@tonic-gateath_tx_is_11n(struct ath_softc *sc) 1227060Srm160521{ 1230Sstevel@tonic-gate return (sc->sc_ah->ah_magic == 0x20065416); 1240Sstevel@tonic-gate} 1250Sstevel@tonic-gate 1260Sstevel@tonic-gate/* 1270Sstevel@tonic-gate * Obtain the current TID from the given frame. 1280Sstevel@tonic-gate * 1290Sstevel@tonic-gate * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.) 1300Sstevel@tonic-gate * This has implications for which AC/priority the packet is placed 1310Sstevel@tonic-gate * in. 1320Sstevel@tonic-gate */ 1330Sstevel@tonic-gatestatic int 1340Sstevel@tonic-gateath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0) 1350Sstevel@tonic-gate{ 1360Sstevel@tonic-gate const struct ieee80211_frame *wh; 1370Sstevel@tonic-gate int pri = M_WME_GETAC(m0); 1380Sstevel@tonic-gate 1397060Srm160521 wh = mtod(m0, const struct ieee80211_frame *); 1400Sstevel@tonic-gate if (! IEEE80211_QOS_HAS_SEQ(wh)) 1410Sstevel@tonic-gate return IEEE80211_NONQOS_TID; 1420Sstevel@tonic-gate else 1430Sstevel@tonic-gate return WME_AC_TO_TID(pri); 1440Sstevel@tonic-gate} 1450Sstevel@tonic-gate 1460Sstevel@tonic-gate/* 1470Sstevel@tonic-gate * Determine what the correct AC queue for the given frame 1487060Srm160521 * should be. 1490Sstevel@tonic-gate * 1500Sstevel@tonic-gate * This code assumes that the TIDs map consistently to 1510Sstevel@tonic-gate * the underlying hardware (or software) ath_txq. 1520Sstevel@tonic-gate * Since the sender may try to set an AC which is 1530Sstevel@tonic-gate * arbitrary, non-QoS TIDs may end up being put on 1540Sstevel@tonic-gate * completely different ACs. There's no way to put a 1550Sstevel@tonic-gate * TID into multiple ath_txq's for scheduling, so 1560Sstevel@tonic-gate * for now we override the AC/TXQ selection and set 1570Sstevel@tonic-gate * non-QOS TID frames into the BE queue. 1580Sstevel@tonic-gate * 1590Sstevel@tonic-gate * This may be completely incorrect - specifically, 1600Sstevel@tonic-gate * some management frames may end up out of order 1610Sstevel@tonic-gate * compared to the QoS traffic they're controlling. 1620Sstevel@tonic-gate * I'll look into this later. 1630Sstevel@tonic-gate */ 1640Sstevel@tonic-gatestatic int 1657060Srm160521ath_tx_getac(struct ath_softc *sc, const struct mbuf *m0) 1660Sstevel@tonic-gate{ 1677060Srm160521 const struct ieee80211_frame *wh; 1687060Srm160521 int pri = M_WME_GETAC(m0); 1697060Srm160521 wh = mtod(m0, const struct ieee80211_frame *); 1707060Srm160521 if (IEEE80211_QOS_HAS_SEQ(wh)) 1710Sstevel@tonic-gate return pri; 1720Sstevel@tonic-gate 1730Sstevel@tonic-gate return WME_AC_BE; 1740Sstevel@tonic-gate} 1750Sstevel@tonic-gate 1767060Srm160521void 1770Sstevel@tonic-gateath_txfrag_cleanup(struct ath_softc *sc, 1787060Srm160521 ath_bufhead *frags, struct ieee80211_node *ni) 1797060Srm160521{ 1807060Srm160521 struct ath_buf *bf, *next; 1817060Srm160521 1820Sstevel@tonic-gate ATH_TXBUF_LOCK_ASSERT(sc); 1830Sstevel@tonic-gate 1840Sstevel@tonic-gate TAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 1850Sstevel@tonic-gate /* NB: bf assumed clean */ 1860Sstevel@tonic-gate TAILQ_REMOVE(frags, bf, bf_list); 1870Sstevel@tonic-gate TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1880Sstevel@tonic-gate ieee80211_node_decref(ni); 1890Sstevel@tonic-gate } 1900Sstevel@tonic-gate} 1910Sstevel@tonic-gate 1920Sstevel@tonic-gate/* 1930Sstevel@tonic-gate * Setup xmit of a fragmented frame. Allocate a buffer 1940Sstevel@tonic-gate * for each frag and bump the node reference count to 1950Sstevel@tonic-gate * reflect the held reference to be setup by ath_tx_start. 1960Sstevel@tonic-gate */ 1970Sstevel@tonic-gateint 1980Sstevel@tonic-gateath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1990Sstevel@tonic-gate struct mbuf *m0, struct ieee80211_node *ni) 2000Sstevel@tonic-gate{ 2010Sstevel@tonic-gate struct mbuf *m; 2020Sstevel@tonic-gate struct ath_buf *bf; 2030Sstevel@tonic-gate 2040Sstevel@tonic-gate ATH_TXBUF_LOCK(sc); 2057060Srm160521 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 2060Sstevel@tonic-gate bf = _ath_getbuf_locked(sc); 2077060Srm160521 if (bf == NULL) { /* out of buffers, cleanup */ 2087060Srm160521 ath_txfrag_cleanup(sc, frags, ni); 2097060Srm160521 break; 2107060Srm160521 } 2117060Srm160521 ieee80211_node_incref(ni); 2120Sstevel@tonic-gate TAILQ_INSERT_TAIL(frags, bf, bf_list); 2130Sstevel@tonic-gate } 2140Sstevel@tonic-gate ATH_TXBUF_UNLOCK(sc); 2150Sstevel@tonic-gate 2160Sstevel@tonic-gate return !TAILQ_EMPTY(frags); 2170Sstevel@tonic-gate} 2180Sstevel@tonic-gate 2190Sstevel@tonic-gate/* 2200Sstevel@tonic-gate * Reclaim mbuf resources. For fragmented frames we 2217060Srm160521 * need to claim each frag chained with m_nextpkt. 2220Sstevel@tonic-gate */ 2230Sstevel@tonic-gatevoid 2240Sstevel@tonic-gateath_freetx(struct mbuf *m) 2250Sstevel@tonic-gate{ 2260Sstevel@tonic-gate struct mbuf *next; 2277060Srm160521 2287060Srm160521 do { 2297060Srm160521 next = m->m_nextpkt; 2307060Srm160521 m->m_nextpkt = NULL; 2317060Srm160521 m_freem(m); 2327060Srm160521 } while ((m = next) != NULL); 2337060Srm160521} 2347060Srm160521 2357060Srm160521static int 2367060Srm160521ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 2377060Srm160521{ 2387060Srm160521 struct mbuf *m; 2390Sstevel@tonic-gate int error; 2400Sstevel@tonic-gate 2410Sstevel@tonic-gate /* 2420Sstevel@tonic-gate * Load the DMA map so any coalescing is done. This 2430Sstevel@tonic-gate * also calculates the number of descriptors we need. 2440Sstevel@tonic-gate */ 2450Sstevel@tonic-gate error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 2460Sstevel@tonic-gate bf->bf_segs, &bf->bf_nseg, 2470Sstevel@tonic-gate BUS_DMA_NOWAIT); 2487060Srm160521 if (error == EFBIG) { 2490Sstevel@tonic-gate /* XXX packet requires too many descriptors */ 2500Sstevel@tonic-gate bf->bf_nseg = ATH_TXDESC+1; 2510Sstevel@tonic-gate } else if (error != 0) { 2520Sstevel@tonic-gate sc->sc_stats.ast_tx_busdma++; 2530Sstevel@tonic-gate ath_freetx(m0); 2540Sstevel@tonic-gate return error; 2550Sstevel@tonic-gate } 2560Sstevel@tonic-gate /* 2570Sstevel@tonic-gate * Discard null packets and check for packets that 2580Sstevel@tonic-gate * require too many TX descriptors. We try to convert 2590Sstevel@tonic-gate * the latter to a cluster. 2600Sstevel@tonic-gate */ 2617060Srm160521 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 2620Sstevel@tonic-gate sc->sc_stats.ast_tx_linear++; 2630Sstevel@tonic-gate m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC); 2640Sstevel@tonic-gate if (m == NULL) { 2650Sstevel@tonic-gate ath_freetx(m0); 2660Sstevel@tonic-gate sc->sc_stats.ast_tx_nombuf++; 2670Sstevel@tonic-gate return ENOMEM; 2680Sstevel@tonic-gate } 2690Sstevel@tonic-gate m0 = m; 2700Sstevel@tonic-gate error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 2717060Srm160521 bf->bf_segs, &bf->bf_nseg, 2720Sstevel@tonic-gate BUS_DMA_NOWAIT); 2737060Srm160521 if (error != 0) { 2747060Srm160521 sc->sc_stats.ast_tx_busdma++; 2757060Srm160521 ath_freetx(m0); 2760Sstevel@tonic-gate return error; 2770Sstevel@tonic-gate } 2780Sstevel@tonic-gate KASSERT(bf->bf_nseg <= ATH_TXDESC, 2790Sstevel@tonic-gate ("too many segments after defrag; nseg %u", bf->bf_nseg)); 2800Sstevel@tonic-gate } else if (bf->bf_nseg == 0) { /* null packet, discard */ 2810Sstevel@tonic-gate sc->sc_stats.ast_tx_nodata++; 2820Sstevel@tonic-gate ath_freetx(m0); 2830Sstevel@tonic-gate return EIO; 2840Sstevel@tonic-gate } 2850Sstevel@tonic-gate DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 2860Sstevel@tonic-gate __func__, m0, m0->m_pkthdr.len); 2870Sstevel@tonic-gate bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 2887060Srm160521 bf->bf_m = m0; 2897060Srm160521 2907060Srm160521 return 0; 2917060Srm160521} 2927060Srm160521 2937060Srm160521/* 2947060Srm160521 * Chain together segments+descriptors for a non-11n frame. 2950Sstevel@tonic-gate */ 2960Sstevel@tonic-gatestatic void 2970Sstevel@tonic-gateath_tx_chaindesclist(struct ath_softc *sc, struct ath_buf *bf) 2980Sstevel@tonic-gate{ 2990Sstevel@tonic-gate struct ath_hal *ah = sc->sc_ah; 3000Sstevel@tonic-gate struct ath_desc *ds, *ds0; 3010Sstevel@tonic-gate int i; 3020Sstevel@tonic-gate 3030Sstevel@tonic-gate /* 3047060Srm160521 * Fillin the remainder of the descriptor info. 3050Sstevel@tonic-gate */ 3060Sstevel@tonic-gate ds0 = ds = bf->bf_desc; 3070Sstevel@tonic-gate for (i = 0; i < bf->bf_nseg; i++, ds++) { 3080Sstevel@tonic-gate ds->ds_data = bf->bf_segs[i].ds_addr; 3090Sstevel@tonic-gate if (i == bf->bf_nseg - 1) 3100Sstevel@tonic-gate ds->ds_link = 0; 3110Sstevel@tonic-gate else 3120Sstevel@tonic-gate ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3130Sstevel@tonic-gate ath_hal_filltxdesc(ah, ds 3147060Srm160521 , bf->bf_segs[i].ds_len /* segment length */ 3150Sstevel@tonic-gate , i == 0 /* first segment */ 3160Sstevel@tonic-gate , i == bf->bf_nseg - 1 /* last segment */ 3170Sstevel@tonic-gate , ds0 /* first descriptor */ 3180Sstevel@tonic-gate ); 3190Sstevel@tonic-gate DPRINTF(sc, ATH_DEBUG_XMIT, 3200Sstevel@tonic-gate "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3210Sstevel@tonic-gate __func__, i, ds->ds_link, ds->ds_data, 3220Sstevel@tonic-gate ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3237060Srm160521 bf->bf_lastds = ds; 3240Sstevel@tonic-gate } 3250Sstevel@tonic-gate} 3260Sstevel@tonic-gate 3270Sstevel@tonic-gate/* 3280Sstevel@tonic-gate * Fill in the descriptor list for a aggregate subframe. 3290Sstevel@tonic-gate * 3300Sstevel@tonic-gate * The subframe is returned with the ds_link field in the last subframe 3310Sstevel@tonic-gate * pointing to 0. 3320Sstevel@tonic-gate */ 3337060Srm160521static void 3347060Srm160521ath_tx_chaindesclist_subframe(struct ath_softc *sc, struct ath_buf *bf) 3357060Srm160521{ 3367060Srm160521 struct ath_hal *ah = sc->sc_ah; 3377060Srm160521 struct ath_desc *ds, *ds0; 3380Sstevel@tonic-gate int i; 3390Sstevel@tonic-gate 3400Sstevel@tonic-gate ds0 = ds = bf->bf_desc; 3417060Srm160521 3420Sstevel@tonic-gate /* 3430Sstevel@tonic-gate * There's no need to call ath_hal_setupfirsttxdesc here; 3440Sstevel@tonic-gate * That's only going to occur for the first frame in an aggregate. 3450Sstevel@tonic-gate */ 3460Sstevel@tonic-gate for (i = 0; i < bf->bf_nseg; i++, ds++) { 3470Sstevel@tonic-gate ds->ds_data = bf->bf_segs[i].ds_addr; 3480Sstevel@tonic-gate if (i == bf->bf_nseg - 1) 3490Sstevel@tonic-gate ds->ds_link = 0; 3500Sstevel@tonic-gate else 3510Sstevel@tonic-gate ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3520Sstevel@tonic-gate 3530Sstevel@tonic-gate /* 3540Sstevel@tonic-gate * This performs the setup for an aggregate frame. 3550Sstevel@tonic-gate * This includes enabling the aggregate flags if needed. 3567060Srm160521 */ 3570Sstevel@tonic-gate ath_hal_chaintxdesc(ah, ds, 3580Sstevel@tonic-gate bf->bf_state.bfs_pktlen, 3590Sstevel@tonic-gate bf->bf_state.bfs_hdrlen, 3600Sstevel@tonic-gate HAL_PKT_TYPE_AMPDU, /* forces aggregate bits to be set */ 3610Sstevel@tonic-gate bf->bf_state.bfs_keyix, 3627060Srm160521 0, /* cipher, calculated from keyix */ 3637060Srm160521 bf->bf_state.bfs_ndelim, 3647060Srm160521 bf->bf_segs[i].ds_len, /* segment length */ 3657060Srm160521 i == 0, /* first segment */ 3660Sstevel@tonic-gate i == bf->bf_nseg - 1 /* last segment */ 3670Sstevel@tonic-gate ); 3680Sstevel@tonic-gate 3690Sstevel@tonic-gate DPRINTF(sc, ATH_DEBUG_XMIT, 3707060Srm160521 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3717060Srm160521 __func__, i, ds->ds_link, ds->ds_data, 3720Sstevel@tonic-gate ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3730Sstevel@tonic-gate bf->bf_lastds = ds; 3740Sstevel@tonic-gate } 3750Sstevel@tonic-gate} 3760Sstevel@tonic-gate 3777060Srm160521/* 3787060Srm160521 * Setup segments+descriptors for an 11n aggregate. 3797060Srm160521 * bf_first is the first buffer in the aggregate. 3807060Srm160521 * The descriptor list must already been linked together using 3817060Srm160521 * bf->bf_next. 3827060Srm160521 */ 3830Sstevel@tonic-gatestatic void 3840Sstevel@tonic-gateath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first) 3850Sstevel@tonic-gate{ 3860Sstevel@tonic-gate struct ath_buf *bf, *bf_prev = NULL; 3870Sstevel@tonic-gate 3880Sstevel@tonic-gate DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n", 3890Sstevel@tonic-gate __func__, bf_first->bf_state.bfs_nframes, 3900Sstevel@tonic-gate bf_first->bf_state.bfs_al); 3910Sstevel@tonic-gate 3920Sstevel@tonic-gate /* 3930Sstevel@tonic-gate * Setup all descriptors of all subframes. 3947060Srm160521 */ 3950Sstevel@tonic-gate bf = bf_first; 3960Sstevel@tonic-gate while (bf != NULL) { 3970Sstevel@tonic-gate DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3980Sstevel@tonic-gate "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n", 3990Sstevel@tonic-gate __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen, 4000Sstevel@tonic-gate SEQNO(bf->bf_state.bfs_seqno)); 4010Sstevel@tonic-gate 4020Sstevel@tonic-gate /* Sub-frame setup */ 4030Sstevel@tonic-gate ath_tx_chaindesclist_subframe(sc, bf); 4040Sstevel@tonic-gate 4050Sstevel@tonic-gate /* 4067060Srm160521 * Link the last descriptor of the previous frame 4077060Srm160521 * to the beginning descriptor of this frame. 4087060Srm160521 */ 4090Sstevel@tonic-gate if (bf_prev != NULL) 4100Sstevel@tonic-gate bf_prev->bf_lastds->ds_link = bf->bf_daddr; 4110Sstevel@tonic-gate 4120Sstevel@tonic-gate /* Save a copy so we can link the next descriptor in */ 4130Sstevel@tonic-gate bf_prev = bf; 4140Sstevel@tonic-gate bf = bf->bf_next; 4150Sstevel@tonic-gate } 4160Sstevel@tonic-gate 4170Sstevel@tonic-gate /* 4180Sstevel@tonic-gate * Setup first descriptor of first frame. 4190Sstevel@tonic-gate * chaintxdesc() overwrites the descriptor entries; 4200Sstevel@tonic-gate * setupfirsttxdesc() merges in things. 4210Sstevel@tonic-gate * Otherwise various fields aren't set correctly (eg flags). 4220Sstevel@tonic-gate */ 4230Sstevel@tonic-gate ath_hal_setupfirsttxdesc(sc->sc_ah, 4240Sstevel@tonic-gate bf_first->bf_desc, 4257060Srm160521 bf_first->bf_state.bfs_al, 4267060Srm160521 bf_first->bf_state.bfs_flags | HAL_TXDESC_INTREQ, 4277060Srm160521 bf_first->bf_state.bfs_txpower, 4287060Srm160521 bf_first->bf_state.bfs_txrate0, 4290Sstevel@tonic-gate bf_first->bf_state.bfs_try0, 4300Sstevel@tonic-gate bf_first->bf_state.bfs_txantenna, 4310Sstevel@tonic-gate bf_first->bf_state.bfs_ctsrate, 4320Sstevel@tonic-gate bf_first->bf_state.bfs_ctsduration); 4330Sstevel@tonic-gate 4340Sstevel@tonic-gate /* 4350Sstevel@tonic-gate * Setup the last descriptor in the list. 4360Sstevel@tonic-gate * bf_prev points to the last; bf is NULL here. 4370Sstevel@tonic-gate */ 4380Sstevel@tonic-gate ath_hal_setuplasttxdesc(sc->sc_ah, bf_prev->bf_desc, 4390Sstevel@tonic-gate bf_first->bf_desc); 4400Sstevel@tonic-gate 4410Sstevel@tonic-gate /* 4420Sstevel@tonic-gate * Set the first descriptor bf_lastds field to point to 4430Sstevel@tonic-gate * the last descriptor in the last subframe, that's where 4440Sstevel@tonic-gate * the status update will occur. 4457060Srm160521 */ 4460Sstevel@tonic-gate bf_first->bf_lastds = bf_prev->bf_lastds; 4470Sstevel@tonic-gate 4480Sstevel@tonic-gate /* 4490Sstevel@tonic-gate * And bf_last in the first descriptor points to the end of 4500Sstevel@tonic-gate * the aggregate list. 4510Sstevel@tonic-gate */ 4520Sstevel@tonic-gate bf_first->bf_last = bf_prev; 4530Sstevel@tonic-gate 4540Sstevel@tonic-gate DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__); 4550Sstevel@tonic-gate} 4560Sstevel@tonic-gate 4570Sstevel@tonic-gatestatic void 4580Sstevel@tonic-gateath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq, 4590Sstevel@tonic-gate struct ath_buf *bf) 4600Sstevel@tonic-gate{ 4617060Srm160521 ATH_TXQ_LOCK_ASSERT(txq); 4627060Srm160521 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 4637060Srm160521 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 4640Sstevel@tonic-gate if (txq->axq_link != NULL) { 4657060Srm160521 struct ath_buf *last = ATH_TXQ_LAST(txq, axq_q_s); 4667060Srm160521 struct ieee80211_frame *wh; 4677060Srm160521 4687060Srm160521 /* mark previous frame */ 4697060Srm160521 wh = mtod(last->bf_m, struct ieee80211_frame *); 4700Sstevel@tonic-gate wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 4710Sstevel@tonic-gate bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 4720Sstevel@tonic-gate BUS_DMASYNC_PREWRITE); 4730Sstevel@tonic-gate 4740Sstevel@tonic-gate /* link descriptor */ 4750Sstevel@tonic-gate *txq->axq_link = bf->bf_daddr; 4760Sstevel@tonic-gate } 4770Sstevel@tonic-gate ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4780Sstevel@tonic-gate txq->axq_link = &bf->bf_lastds->ds_link; 4790Sstevel@tonic-gate} 4800Sstevel@tonic-gate 4810Sstevel@tonic-gate/* 4820Sstevel@tonic-gate * Hand-off packet to a hardware queue. 4830Sstevel@tonic-gate */ 4840Sstevel@tonic-gatestatic void 4850Sstevel@tonic-gateath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq, 4860Sstevel@tonic-gate struct ath_buf *bf) 4870Sstevel@tonic-gate{ 4880Sstevel@tonic-gate struct ath_hal *ah = sc->sc_ah; 4890Sstevel@tonic-gate 4900Sstevel@tonic-gate /* 4910Sstevel@tonic-gate * Insert the frame on the outbound list and pass it on 4920Sstevel@tonic-gate * to the hardware. Multicast frames buffered for power 4930Sstevel@tonic-gate * save stations and transmit from the CAB queue are stored 4947060Srm160521 * on a s/w only queue and loaded on to the CAB queue in 4957060Srm160521 * the SWBA handler since frames only go out on DTIM and 4967060Srm160521 * to avoid possible races. 4977060Srm160521 */ 4980Sstevel@tonic-gate ATH_TXQ_LOCK_ASSERT(txq); 4990Sstevel@tonic-gate KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 5000Sstevel@tonic-gate ("%s: busy status 0x%x", __func__, bf->bf_flags)); 5010Sstevel@tonic-gate KASSERT(txq->axq_qnum != ATH_TXQ_SWQ, 5020Sstevel@tonic-gate ("ath_tx_handoff_hw called for mcast queue")); 5030Sstevel@tonic-gate 5040Sstevel@tonic-gate#if 0 5050Sstevel@tonic-gate /* 5060Sstevel@tonic-gate * This causes a LOR. Find out where the PCU lock is being 5070Sstevel@tonic-gate * held whilst the TXQ lock is grabbed - that shouldn't 5087060Srm160521 * be occuring. 5097060Srm160521 */ 5100Sstevel@tonic-gate ATH_PCU_LOCK(sc); 5117060Srm160521 if (sc->sc_inreset_cnt) { 5127060Srm160521 ATH_PCU_UNLOCK(sc); 5137060Srm160521 DPRINTF(sc, ATH_DEBUG_RESET, 5147060Srm160521 "%s: called with sc_in_reset != 0\n", 5150Sstevel@tonic-gate __func__); 5160Sstevel@tonic-gate DPRINTF(sc, ATH_DEBUG_XMIT, 5170Sstevel@tonic-gate "%s: queued: TXDP[%u] = %p (%p) depth %d\n", 5180Sstevel@tonic-gate __func__, txq->axq_qnum, 5190Sstevel@tonic-gate (caddr_t)bf->bf_daddr, bf->bf_desc, 5200Sstevel@tonic-gate txq->axq_depth); 5210Sstevel@tonic-gate ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 5220Sstevel@tonic-gate if (bf->bf_state.bfs_aggr) 5230Sstevel@tonic-gate txq->axq_aggr_depth++; 5240Sstevel@tonic-gate /* 5250Sstevel@tonic-gate * There's no need to update axq_link; the hardware 5267060Srm160521 * is in reset and once the reset is complete, any 5277060Srm160521 * non-empty queues will simply have DMA restarted. 5280Sstevel@tonic-gate */ 5297060Srm160521 return; 5307060Srm160521 } 5317060Srm160521 ATH_PCU_UNLOCK(sc); 5327060Srm160521#endif 5330Sstevel@tonic-gate 5340Sstevel@tonic-gate /* For now, so not to generate whitespace diffs */ 5350Sstevel@tonic-gate if (1) { 5360Sstevel@tonic-gate#ifdef IEEE80211_SUPPORT_TDMA 5370Sstevel@tonic-gate int qbusy; 5380Sstevel@tonic-gate 5390Sstevel@tonic-gate ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 5400Sstevel@tonic-gate qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 5410Sstevel@tonic-gate if (txq->axq_link == NULL) { 5420Sstevel@tonic-gate /* 5430Sstevel@tonic-gate * Be careful writing the address to TXDP. If 5440Sstevel@tonic-gate * the tx q is enabled then this write will be 5450Sstevel@tonic-gate * ignored. Normally this is not an issue but 5460Sstevel@tonic-gate * when tdma is in use and the q is beacon gated 5470Sstevel@tonic-gate * this race can occur. If the q is busy then 5487060Srm160521 * defer the work to later--either when another 5497060Srm160521 * packet comes along or when we prepare a beacon 5507060Srm160521 * frame at SWBA. 5510Sstevel@tonic-gate */ 5520Sstevel@tonic-gate if (!qbusy) { 5530Sstevel@tonic-gate ath_hal_puttxbuf(ah, txq->axq_qnum, 5540Sstevel@tonic-gate bf->bf_daddr); 5557060Srm160521 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 5567060Srm160521 DPRINTF(sc, ATH_DEBUG_XMIT, 5577060Srm160521 "%s: TXDP[%u] = %p (%p) depth %d\n", 5580Sstevel@tonic-gate __func__, txq->axq_qnum, 5590Sstevel@tonic-gate (caddr_t)bf->bf_daddr, bf->bf_desc, 5600Sstevel@tonic-gate txq->axq_depth); 5610Sstevel@tonic-gate } else { 5627060Srm160521 txq->axq_flags |= ATH_TXQ_PUTPENDING; 5637060Srm160521 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 5647060Srm160521 "%s: Q%u busy, defer enable\n", __func__, 5657060Srm160521 txq->axq_qnum); 5667060Srm160521 } 5677060Srm160521 } else { 5687060Srm160521 *txq->axq_link = bf->bf_daddr; 5697060Srm160521 DPRINTF(sc, ATH_DEBUG_XMIT, 5700Sstevel@tonic-gate "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 5710Sstevel@tonic-gate txq->axq_qnum, txq->axq_link, 5727060Srm160521 (caddr_t)bf->bf_daddr, bf->bf_desc, 5737060Srm160521 txq->axq_depth); 5747060Srm160521 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) { 5757060Srm160521 /* 5767060Srm160521 * The q was busy when we previously tried 5770Sstevel@tonic-gate * to write the address of the first buffer 5780Sstevel@tonic-gate * in the chain. Since it's not busy now 5790Sstevel@tonic-gate * handle this chore. We are certain the 5800Sstevel@tonic-gate * buffer at the front is the right one since 5810Sstevel@tonic-gate * axq_link is NULL only when the buffer list 5820Sstevel@tonic-gate * is/was empty. 5830Sstevel@tonic-gate */ 5840Sstevel@tonic-gate ath_hal_puttxbuf(ah, txq->axq_qnum, 5850Sstevel@tonic-gate TAILQ_FIRST(&txq->axq_q)->bf_daddr); 5860Sstevel@tonic-gate txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 5870Sstevel@tonic-gate DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 5880Sstevel@tonic-gate "%s: Q%u restarted\n", __func__, 5890Sstevel@tonic-gate txq->axq_qnum); 5900Sstevel@tonic-gate } 5917060Srm160521 } 5920Sstevel@tonic-gate#else 5937060Srm160521 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 5947060Srm160521 if (txq->axq_link == NULL) { 5957060Srm160521 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 5967060Srm160521 DPRINTF(sc, ATH_DEBUG_XMIT, 5977060Srm160521 "%s: TXDP[%u] = %p (%p) depth %d\n", 5980Sstevel@tonic-gate __func__, txq->axq_qnum, 5990Sstevel@tonic-gate (caddr_t)bf->bf_daddr, bf->bf_desc, 6000Sstevel@tonic-gate txq->axq_depth); 6010Sstevel@tonic-gate } else { 6020Sstevel@tonic-gate *txq->axq_link = bf->bf_daddr; 6030Sstevel@tonic-gate DPRINTF(sc, ATH_DEBUG_XMIT, 6040Sstevel@tonic-gate "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 6050Sstevel@tonic-gate txq->axq_qnum, txq->axq_link, 6060Sstevel@tonic-gate (caddr_t)bf->bf_daddr, bf->bf_desc, 6070Sstevel@tonic-gate txq->axq_depth); 6087060Srm160521 } 6090Sstevel@tonic-gate#endif /* IEEE80211_SUPPORT_TDMA */ 6100Sstevel@tonic-gate if (bf->bf_state.bfs_aggr) 6110Sstevel@tonic-gate txq->axq_aggr_depth++; 6127060Srm160521 txq->axq_link = &bf->bf_lastds->ds_link; 6130Sstevel@tonic-gate ath_hal_txstart(ah, txq->axq_qnum); 6140Sstevel@tonic-gate } 6150Sstevel@tonic-gate} 6160Sstevel@tonic-gate 6177060Srm160521/* 6187060Srm160521 * Restart TX DMA for the given TXQ. 6197060Srm160521 * 6207060Srm160521 * This must be called whether the queue is empty or not. 6217060Srm160521 */ 6227060Srm160521void 6237060Srm160521ath_txq_restart_dma(struct ath_softc *sc, struct ath_txq *txq) 6247060Srm160521{ 6257060Srm160521 struct ath_hal *ah = sc->sc_ah; 6267060Srm160521 struct ath_buf *bf, *bf_last; 6277060Srm160521 6280Sstevel@tonic-gate ATH_TXQ_LOCK_ASSERT(txq); 6297060Srm160521 6300Sstevel@tonic-gate /* This is always going to be cleared, empty or not */ 6310Sstevel@tonic-gate txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 6320Sstevel@tonic-gate 6330Sstevel@tonic-gate /* XXX make this ATH_TXQ_FIRST */ 6340Sstevel@tonic-gate bf = TAILQ_FIRST(&txq->axq_q); 6350Sstevel@tonic-gate bf_last = ATH_TXQ_LAST(txq, axq_q_s); 6360Sstevel@tonic-gate 6370Sstevel@tonic-gate if (bf == NULL) 6380Sstevel@tonic-gate return; 6390Sstevel@tonic-gate 6400Sstevel@tonic-gate ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 6411107Ssjelinek txq->axq_link = &bf_last->bf_lastds->ds_link; 6420Sstevel@tonic-gate ath_hal_txstart(ah, txq->axq_qnum); 6430Sstevel@tonic-gate} 6440Sstevel@tonic-gate 6450Sstevel@tonic-gate/* 6460Sstevel@tonic-gate * Hand off a packet to the hardware (or mcast queue.) 6470Sstevel@tonic-gate * 6480Sstevel@tonic-gate * The relevant hardware txq should be locked. 6491107Ssjelinek */ 6500Sstevel@tonic-gatestatic void 6510Sstevel@tonic-gateath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf) 6520Sstevel@tonic-gate{ 6530Sstevel@tonic-gate ATH_TXQ_LOCK_ASSERT(txq); 6540Sstevel@tonic-gate 6550Sstevel@tonic-gate if (txq->axq_qnum == ATH_TXQ_SWQ) 6560Sstevel@tonic-gate ath_tx_handoff_mcast(sc, txq, bf); 6570Sstevel@tonic-gate else 658767Ssjelinek ath_tx_handoff_hw(sc, txq, bf); 659767Ssjelinek} 660767Ssjelinek 661767Ssjelinekstatic int 6621107Ssjelinekath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni, 6631107Ssjelinek struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen, 6641107Ssjelinek int *keyix) 6651107Ssjelinek{ 6661107Ssjelinek DPRINTF(sc, ATH_DEBUG_XMIT, 6671107Ssjelinek "%s: hdrlen=%d, pktlen=%d, isfrag=%d, iswep=%d, m0=%p\n", 6681107Ssjelinek __func__, 6691107Ssjelinek *hdrlen, 670767Ssjelinek *pktlen, 6710Sstevel@tonic-gate isfrag, 6720Sstevel@tonic-gate iswep, 6730Sstevel@tonic-gate m0); 6740Sstevel@tonic-gate 6750Sstevel@tonic-gate if (iswep) { 6760Sstevel@tonic-gate const struct ieee80211_cipher *cip; 6770Sstevel@tonic-gate struct ieee80211_key *k; 6780Sstevel@tonic-gate 6790Sstevel@tonic-gate /* 6800Sstevel@tonic-gate * Construct the 802.11 header+trailer for an encrypted 6817060Srm160521 * frame. The only reason this can fail is because of an 6820Sstevel@tonic-gate * unknown or unsupported cipher/key type. 6830Sstevel@tonic-gate */ 6840Sstevel@tonic-gate k = ieee80211_crypto_encap(ni, m0); 6850Sstevel@tonic-gate if (k == NULL) { 6867060Srm160521 /* 6877060Srm160521 * This can happen when the key is yanked after the 6880Sstevel@tonic-gate * frame was queued. Just discard the frame; the 6897060Srm160521 * 802.11 layer counts failures and provides 6907060Srm160521 * debugging/diagnostics. 6910Sstevel@tonic-gate */ 6927060Srm160521 return (0); 6937060Srm160521 } 6940Sstevel@tonic-gate /* 6957060Srm160521 * Adjust the packet + header lengths for the crypto 6967060Srm160521 * additions and calculate the h/w key index. When 6970Sstevel@tonic-gate * a s/w mic is done the frame will have had any mic 6987060Srm160521 * added to it prior to entry so m0->m_pkthdr.len will 6997060Srm160521 * account for it. Otherwise we need to add it to the 7000Sstevel@tonic-gate * packet length. 7017060Srm160521 */ 7027060Srm160521 cip = k->wk_cipher; 7030Sstevel@tonic-gate (*hdrlen) += cip->ic_header; 7047060Srm160521 (*pktlen) += cip->ic_header + cip->ic_trailer; 7057060Srm160521 /* NB: frags always have any TKIP MIC done in s/w */ 7060Sstevel@tonic-gate if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 7077060Srm160521 (*pktlen) += cip->ic_miclen; 7087060Srm160521 (*keyix) = k->wk_keyix; 7090Sstevel@tonic-gate } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 7100Sstevel@tonic-gate /* 7110Sstevel@tonic-gate * Use station key cache slot, if assigned. 7120Sstevel@tonic-gate */ 7130Sstevel@tonic-gate (*keyix) = ni->ni_ucastkey.wk_keyix; 7140Sstevel@tonic-gate if ((*keyix) == IEEE80211_KEYIX_NONE) 7150Sstevel@tonic-gate (*keyix) = HAL_TXKEYIX_INVALID; 7160Sstevel@tonic-gate } else 7170Sstevel@tonic-gate (*keyix) = HAL_TXKEYIX_INVALID; 7187060Srm160521 7190Sstevel@tonic-gate return (1); 7200Sstevel@tonic-gate} 7210Sstevel@tonic-gate 7227060Srm160521static uint8_t 7237060Srm160521ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt, 7247060Srm160521 int cix, int shortPreamble) 7257060Srm160521{ 7260Sstevel@tonic-gate uint8_t ctsrate; 7270Sstevel@tonic-gate 7280Sstevel@tonic-gate /* 7290Sstevel@tonic-gate * CTS transmit rate is derived from the transmit rate 7300Sstevel@tonic-gate * by looking in the h/w rate table. We must also factor 7310Sstevel@tonic-gate * in whether or not a short preamble is to be used. 7320Sstevel@tonic-gate */ 7330Sstevel@tonic-gate /* NB: cix is set above where RTS/CTS is enabled */ 7340Sstevel@tonic-gate KASSERT(cix != 0xff, ("cix not setup")); 7350Sstevel@tonic-gate ctsrate = rt->info[cix].rateCode; 7360Sstevel@tonic-gate 7377060Srm160521 /* XXX this should only matter for legacy rates */ 7380Sstevel@tonic-gate if (shortPreamble) 7390Sstevel@tonic-gate ctsrate |= rt->info[cix].shortPreamble; 7400Sstevel@tonic-gate 7410Sstevel@tonic-gate return (ctsrate); 7427060Srm160521} 7437060Srm160521 7447060Srm160521/* 7457060Srm160521 * Calculate the RTS/CTS duration for legacy frames. 7460Sstevel@tonic-gate */ 7470Sstevel@tonic-gatestatic int 7480Sstevel@tonic-gateath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix, 7490Sstevel@tonic-gate int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt, 7500Sstevel@tonic-gate int flags) 7510Sstevel@tonic-gate{ 7520Sstevel@tonic-gate int ctsduration = 0; 7530Sstevel@tonic-gate 7540Sstevel@tonic-gate /* This mustn't be called for HT modes */ 7557060Srm160521 if (rt->info[cix].phy == IEEE80211_T_HT) { 7567060Srm160521 printf("%s: HT rate where it shouldn't be (0x%x)\n", 7577060Srm160521 __func__, rt->info[cix].rateCode); 7587060Srm160521 return (-1); 7590Sstevel@tonic-gate } 7600Sstevel@tonic-gate 7617060Srm160521 /* 7627060Srm160521 * Compute the transmit duration based on the frame 7637060Srm160521 * size and the size of an ACK frame. We call into the 7647060Srm160521 * HAL to do the computation since it depends on the 7657060Srm160521 * characteristics of the actual PHY being used. 7667060Srm160521 * 7670Sstevel@tonic-gate * NB: CTS is assumed the same size as an ACK so we can 7680Sstevel@tonic-gate * use the precalculated ACK durations. 7690Sstevel@tonic-gate */ 7700Sstevel@tonic-gate if (shortPreamble) { 7710Sstevel@tonic-gate if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 7720Sstevel@tonic-gate ctsduration += rt->info[cix].spAckDuration; 7730Sstevel@tonic-gate ctsduration += ath_hal_computetxtime(ah, 7740Sstevel@tonic-gate rt, pktlen, rix, AH_TRUE); 7750Sstevel@tonic-gate if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 7760Sstevel@tonic-gate ctsduration += rt->info[rix].spAckDuration; 7770Sstevel@tonic-gate } else { 7780Sstevel@tonic-gate if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 7797060Srm160521 ctsduration += rt->info[cix].lpAckDuration; 7800Sstevel@tonic-gate ctsduration += ath_hal_computetxtime(ah, 7810Sstevel@tonic-gate rt, pktlen, rix, AH_FALSE); 7820Sstevel@tonic-gate if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 7837060Srm160521 ctsduration += rt->info[rix].lpAckDuration; 7840Sstevel@tonic-gate } 7850Sstevel@tonic-gate 7860Sstevel@tonic-gate return (ctsduration); 7870Sstevel@tonic-gate} 7887060Srm160521 7890Sstevel@tonic-gate/* 7900Sstevel@tonic-gate * Update the given ath_buf with updated rts/cts setup and duration 7910Sstevel@tonic-gate * values. 7920Sstevel@tonic-gate * 7937060Srm160521 * To support rate lookups for each software retry, the rts/cts rate 7947060Srm160521 * and cts duration must be re-calculated. 7950Sstevel@tonic-gate * 7967060Srm160521 * This function assumes the RTS/CTS flags have been set as needed; 7977060Srm160521 * mrr has been disabled; and the rate control lookup has been done. 7980Sstevel@tonic-gate * 7997060Srm160521 * XXX TODO: MRR need only be disabled for the pre-11n NICs. 8007060Srm160521 * XXX The 11n NICs support per-rate RTS/CTS configuration. 8010Sstevel@tonic-gate */ 8020Sstevel@tonic-gatestatic void 8037060Srm160521ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf) 8047060Srm160521{ 8057060Srm160521 uint16_t ctsduration = 0; 8067060Srm160521 uint8_t ctsrate = 0; 8077060Srm160521 uint8_t rix = bf->bf_state.bfs_rc[0].rix; 8080Sstevel@tonic-gate uint8_t cix = 0; 8097060Srm160521 const HAL_RATE_TABLE *rt = sc->sc_currates; 8100Sstevel@tonic-gate 8110Sstevel@tonic-gate /* 8120Sstevel@tonic-gate * No RTS/CTS enabled? Don't bother. 8137060Srm160521 */ 8147060Srm160521 if ((bf->bf_state.bfs_flags & 8157060Srm160521 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) { 8167060Srm160521 /* XXX is this really needed? */ 8177060Srm160521 bf->bf_state.bfs_ctsrate = 0; 8187060Srm160521 bf->bf_state.bfs_ctsduration = 0; 8197060Srm160521 return; 8207060Srm160521 } 8217060Srm160521 8220Sstevel@tonic-gate /* 8237060Srm160521 * If protection is enabled, use the protection rix control 8240Sstevel@tonic-gate * rate. Otherwise use the rate0 control rate. 8250Sstevel@tonic-gate */ 8260Sstevel@tonic-gate if (bf->bf_state.bfs_doprot) 8270Sstevel@tonic-gate rix = sc->sc_protrix; 8280Sstevel@tonic-gate else 8290Sstevel@tonic-gate rix = bf->bf_state.bfs_rc[0].rix; 8300Sstevel@tonic-gate 8317060Srm160521 /* 8320Sstevel@tonic-gate * If the raw path has hard-coded ctsrate0 to something, 8330Sstevel@tonic-gate * use it. 8340Sstevel@tonic-gate */ 8350Sstevel@tonic-gate if (bf->bf_state.bfs_ctsrate0 != 0) 8360Sstevel@tonic-gate cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0); 8370Sstevel@tonic-gate else 8380Sstevel@tonic-gate /* Control rate from above */ 8390Sstevel@tonic-gate cix = rt->info[rix].controlRate; 8400Sstevel@tonic-gate 8410Sstevel@tonic-gate /* Calculate the rtscts rate for the given cix */ 8420Sstevel@tonic-gate ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix, 8430Sstevel@tonic-gate bf->bf_state.bfs_shpream); 8440Sstevel@tonic-gate 8450Sstevel@tonic-gate /* The 11n chipsets do ctsduration calculations for you */ 8460Sstevel@tonic-gate if (! ath_tx_is_11n(sc)) 8470Sstevel@tonic-gate ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix, 8480Sstevel@tonic-gate bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen, 8490Sstevel@tonic-gate rt, bf->bf_state.bfs_flags); 8500Sstevel@tonic-gate 8517060Srm160521 /* Squirrel away in ath_buf */ 8520Sstevel@tonic-gate bf->bf_state.bfs_ctsrate = ctsrate; 8537060Srm160521 bf->bf_state.bfs_ctsduration = ctsduration; 8547060Srm160521 8557060Srm160521 /* 8567060Srm160521 * Must disable multi-rate retry when using RTS/CTS. 8577060Srm160521 * XXX TODO: only for pre-11n NICs. 8587060Srm160521 */ 8597060Srm160521 bf->bf_state.bfs_ismrr = 0; 8600Sstevel@tonic-gate bf->bf_state.bfs_try0 = 8617060Srm160521 bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */ 8627060Srm160521} 8637060Srm160521 8647060Srm160521/* 8657060Srm160521 * Setup the descriptor chain for a normal or fast-frame 8667060Srm160521 * frame. 8677060Srm160521 */ 8680Sstevel@tonic-gatestatic void 8690Sstevel@tonic-gateath_tx_setds(struct ath_softc *sc, struct ath_buf *bf) 8707060Srm160521{ 8717060Srm160521 struct ath_desc *ds = bf->bf_desc; 8727060Srm160521 struct ath_hal *ah = sc->sc_ah; 8730Sstevel@tonic-gate 8740Sstevel@tonic-gate ath_hal_setuptxdesc(ah, ds 8750Sstevel@tonic-gate , bf->bf_state.bfs_pktlen /* packet length */ 8760Sstevel@tonic-gate , bf->bf_state.bfs_hdrlen /* header length */ 8770Sstevel@tonic-gate , bf->bf_state.bfs_atype /* Atheros packet type */ 8780Sstevel@tonic-gate , bf->bf_state.bfs_txpower /* txpower */ 8790Sstevel@tonic-gate , bf->bf_state.bfs_txrate0 8807060Srm160521 , bf->bf_state.bfs_try0 /* series 0 rate/tries */ 8810Sstevel@tonic-gate , bf->bf_state.bfs_keyix /* key cache index */ 8827060Srm160521 , bf->bf_state.bfs_txantenna /* antenna mode */ 8837060Srm160521 , bf->bf_state.bfs_flags /* flags */ 8847060Srm160521 , bf->bf_state.bfs_ctsrate /* rts/cts rate */ 8850Sstevel@tonic-gate , bf->bf_state.bfs_ctsduration /* rts/cts duration */ 8860Sstevel@tonic-gate ); 8877060Srm160521 8880Sstevel@tonic-gate /* 8897060Srm160521 * This will be overriden when the descriptor chain is written. 8907060Srm160521 */ 8917060Srm160521 bf->bf_lastds = ds; 8920Sstevel@tonic-gate bf->bf_last = bf; 8930Sstevel@tonic-gate 8947060Srm160521 /* XXX TODO: Setup descriptor chain */ 8950Sstevel@tonic-gate} 8967060Srm160521 8977060Srm160521/* 8987060Srm160521 * Do a rate lookup. 8990Sstevel@tonic-gate * 9000Sstevel@tonic-gate * This performs a rate lookup for the given ath_buf only if it's required. 9010Sstevel@tonic-gate * Non-data frames and raw frames don't require it. 9020Sstevel@tonic-gate * 9030Sstevel@tonic-gate * This populates the primary and MRR entries; MRR values are 9040Sstevel@tonic-gate * then disabled later on if something requires it (eg RTS/CTS on 9050Sstevel@tonic-gate * pre-11n chipsets. 9060Sstevel@tonic-gate * 9070Sstevel@tonic-gate * This needs to be done before the RTS/CTS fields are calculated 9080Sstevel@tonic-gate * as they may depend upon the rate chosen. 9090Sstevel@tonic-gate */ 9100Sstevel@tonic-gatestatic void 9110Sstevel@tonic-gateath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf) 9120Sstevel@tonic-gate{ 9137060Srm160521 uint8_t rate, rix; 9140Sstevel@tonic-gate int try0; 9150Sstevel@tonic-gate 9160Sstevel@tonic-gate if (! bf->bf_state.bfs_doratelookup) 9170Sstevel@tonic-gate return; 9180Sstevel@tonic-gate 9190Sstevel@tonic-gate /* Get rid of any previous state */ 9200Sstevel@tonic-gate bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 9210Sstevel@tonic-gate 9220Sstevel@tonic-gate ATH_NODE_LOCK(ATH_NODE(bf->bf_node)); 9237060Srm160521 ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream, 9247060Srm160521 bf->bf_state.bfs_pktlen, &rix, &try0, &rate); 9250Sstevel@tonic-gate 9267060Srm160521 /* In case MRR is disabled, make sure rc[0] is setup correctly */ 9277060Srm160521 bf->bf_state.bfs_rc[0].rix = rix; 9280Sstevel@tonic-gate bf->bf_state.bfs_rc[0].ratecode = rate; 9297060Srm160521 bf->bf_state.bfs_rc[0].tries = try0; 9307060Srm160521 9310Sstevel@tonic-gate if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY) 9327060Srm160521 ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix, 9337060Srm160521 bf->bf_state.bfs_rc); 9340Sstevel@tonic-gate ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node)); 9350Sstevel@tonic-gate 9360Sstevel@tonic-gate sc->sc_txrix = rix; /* for LED blinking */ 9370Sstevel@tonic-gate sc->sc_lastdatarix = rix; /* for fast frames */ 9380Sstevel@tonic-gate bf->bf_state.bfs_try0 = try0; 9390Sstevel@tonic-gate bf->bf_state.bfs_txrate0 = rate; 9400Sstevel@tonic-gate} 9410Sstevel@tonic-gate 9427060Srm160521/* 9437060Srm160521 * Set the rate control fields in the given descriptor based on 9447060Srm160521 * the bf_state fields and node state. 9457060Srm160521 * 9460Sstevel@tonic-gate * The bfs fields should already be set with the relevant rate 9470Sstevel@tonic-gate * control information, including whether MRR is to be enabled. 9480Sstevel@tonic-gate * 9490Sstevel@tonic-gate * Since the FreeBSD HAL currently sets up the first TX rate 9500Sstevel@tonic-gate * in ath_hal_setuptxdesc(), this will setup the MRR 9510Sstevel@tonic-gate * conditionally for the pre-11n chips, and call ath_buf_set_rate 9520Sstevel@tonic-gate * unconditionally for 11n chips. These require the 11n rate 9530Sstevel@tonic-gate * scenario to be set if MCS rates are enabled, so it's easier 9540Sstevel@tonic-gate * to just always call it. The caller can then only set rates 2, 3 9550Sstevel@tonic-gate * and 4 if multi-rate retry is needed. 9560Sstevel@tonic-gate */ 9577060Srm160521static void 9587060Srm160521ath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 9597060Srm160521 struct ath_buf *bf) 9607060Srm160521{ 9617060Srm160521 struct ath_rc_series *rc = bf->bf_state.bfs_rc; 9620Sstevel@tonic-gate 9630Sstevel@tonic-gate /* If mrr is disabled, blank tries 1, 2, 3 */ 9640Sstevel@tonic-gate if (! bf->bf_state.bfs_ismrr) 9650Sstevel@tonic-gate rc[1].tries = rc[2].tries = rc[3].tries = 0; 9660Sstevel@tonic-gate 9670Sstevel@tonic-gate /* 9680Sstevel@tonic-gate * Always call - that way a retried descriptor will 9690Sstevel@tonic-gate * have the MRR fields overwritten. 9700Sstevel@tonic-gate * 9710Sstevel@tonic-gate * XXX TODO: see if this is really needed - setting up 9720Sstevel@tonic-gate * the first descriptor should set the MRR fields to 0 9737060Srm160521 * for us anyway. 9747060Srm160521 */ 9757060Srm160521 if (ath_tx_is_11n(sc)) { 9767060Srm160521 ath_buf_set_rate(sc, ni, bf); 9770Sstevel@tonic-gate } else { 9780Sstevel@tonic-gate ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc 9790Sstevel@tonic-gate , rc[1].ratecode, rc[1].tries 9800Sstevel@tonic-gate , rc[2].ratecode, rc[2].tries 9810Sstevel@tonic-gate , rc[3].ratecode, rc[3].tries 9820Sstevel@tonic-gate ); 9830Sstevel@tonic-gate } 9840Sstevel@tonic-gate} 9850Sstevel@tonic-gate 9860Sstevel@tonic-gate/* 9870Sstevel@tonic-gate * Transmit the given frame to the hardware. 9887060Srm160521 * 9890Sstevel@tonic-gate * The frame must already be setup; rate control must already have 9907060Srm160521 * been done. 9917060Srm160521 * 9927060Srm160521 * XXX since the TXQ lock is being held here (and I dislike holding 9930Sstevel@tonic-gate * it for this long when not doing software aggregation), later on 9947060Srm160521 * break this function into "setup_normal" and "xmit_normal". The 9957060Srm160521 * lock only needs to be held for the ath_tx_handoff call. 9967060Srm160521 */ 9977060Srm160521static void 9987060Srm160521ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq, 9997060Srm160521 struct ath_buf *bf) 10007060Srm160521{ 10010Sstevel@tonic-gate 10020Sstevel@tonic-gate ATH_TXQ_LOCK_ASSERT(txq); 10030Sstevel@tonic-gate 10040Sstevel@tonic-gate /* Setup the descriptor before handoff */ 10050Sstevel@tonic-gate ath_tx_do_ratelookup(sc, bf); 10060Sstevel@tonic-gate ath_tx_rate_fill_rcflags(sc, bf); 1007 ath_tx_set_rtscts(sc, bf); 1008 ath_tx_setds(sc, bf); 1009 ath_tx_set_ratectrl(sc, bf->bf_node, bf); 1010 ath_tx_chaindesclist(sc, bf); 1011 1012 /* Hand off to hardware */ 1013 ath_tx_handoff(sc, txq, bf); 1014} 1015 1016 1017 1018static int 1019ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni, 1020 struct ath_buf *bf, struct mbuf *m0) 1021{ 1022 struct ieee80211vap *vap = ni->ni_vap; 1023 struct ath_vap *avp = ATH_VAP(vap); 1024 struct ath_hal *ah = sc->sc_ah; 1025 struct ifnet *ifp = sc->sc_ifp; 1026 struct ieee80211com *ic = ifp->if_l2com; 1027 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 1028 int error, iswep, ismcast, isfrag, ismrr; 1029 int keyix, hdrlen, pktlen, try0 = 0; 1030 u_int8_t rix = 0, txrate = 0; 1031 struct ath_desc *ds; 1032 struct ath_txq *txq; 1033 struct ieee80211_frame *wh; 1034 u_int subtype, flags; 1035 HAL_PKT_TYPE atype; 1036 const HAL_RATE_TABLE *rt; 1037 HAL_BOOL shortPreamble; 1038 struct ath_node *an; 1039 u_int pri; 1040 1041 wh = mtod(m0, struct ieee80211_frame *); 1042 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1043 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1044 isfrag = m0->m_flags & M_FRAG; 1045 hdrlen = ieee80211_anyhdrsize(wh); 1046 /* 1047 * Packet length must not include any 1048 * pad bytes; deduct them here. 1049 */ 1050 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 1051 1052 /* Handle encryption twiddling if needed */ 1053 if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen, 1054 &pktlen, &keyix)) { 1055 ath_freetx(m0); 1056 return EIO; 1057 } 1058 1059 /* packet header may have moved, reset our local pointer */ 1060 wh = mtod(m0, struct ieee80211_frame *); 1061 1062 pktlen += IEEE80211_CRC_LEN; 1063 1064 /* 1065 * Load the DMA map so any coalescing is done. This 1066 * also calculates the number of descriptors we need. 1067 */ 1068 error = ath_tx_dmasetup(sc, bf, m0); 1069 if (error != 0) 1070 return error; 1071 bf->bf_node = ni; /* NB: held reference */ 1072 m0 = bf->bf_m; /* NB: may have changed */ 1073 wh = mtod(m0, struct ieee80211_frame *); 1074 1075 /* setup descriptors */ 1076 ds = bf->bf_desc; 1077 rt = sc->sc_currates; 1078 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1079 1080 /* 1081 * NB: the 802.11 layer marks whether or not we should 1082 * use short preamble based on the current mode and 1083 * negotiated parameters. 1084 */ 1085 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1086 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 1087 shortPreamble = AH_TRUE; 1088 sc->sc_stats.ast_tx_shortpre++; 1089 } else { 1090 shortPreamble = AH_FALSE; 1091 } 1092 1093 an = ATH_NODE(ni); 1094 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1095 ismrr = 0; /* default no multi-rate retry*/ 1096 pri = M_WME_GETAC(m0); /* honor classification */ 1097 /* XXX use txparams instead of fixed values */ 1098 /* 1099 * Calculate Atheros packet type from IEEE80211 packet header, 1100 * setup for rate calculations, and select h/w transmit queue. 1101 */ 1102 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1103 case IEEE80211_FC0_TYPE_MGT: 1104 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1105 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1106 atype = HAL_PKT_TYPE_BEACON; 1107 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1108 atype = HAL_PKT_TYPE_PROBE_RESP; 1109 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1110 atype = HAL_PKT_TYPE_ATIM; 1111 else 1112 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 1113 rix = an->an_mgmtrix; 1114 txrate = rt->info[rix].rateCode; 1115 if (shortPreamble) 1116 txrate |= rt->info[rix].shortPreamble; 1117 try0 = ATH_TXMGTTRY; 1118 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1119 break; 1120 case IEEE80211_FC0_TYPE_CTL: 1121 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 1122 rix = an->an_mgmtrix; 1123 txrate = rt->info[rix].rateCode; 1124 if (shortPreamble) 1125 txrate |= rt->info[rix].shortPreamble; 1126 try0 = ATH_TXMGTTRY; 1127 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1128 break; 1129 case IEEE80211_FC0_TYPE_DATA: 1130 atype = HAL_PKT_TYPE_NORMAL; /* default */ 1131 /* 1132 * Data frames: multicast frames go out at a fixed rate, 1133 * EAPOL frames use the mgmt frame rate; otherwise consult 1134 * the rate control module for the rate to use. 1135 */ 1136 if (ismcast) { 1137 rix = an->an_mcastrix; 1138 txrate = rt->info[rix].rateCode; 1139 if (shortPreamble) 1140 txrate |= rt->info[rix].shortPreamble; 1141 try0 = 1; 1142 } else if (m0->m_flags & M_EAPOL) { 1143 /* XXX? maybe always use long preamble? */ 1144 rix = an->an_mgmtrix; 1145 txrate = rt->info[rix].rateCode; 1146 if (shortPreamble) 1147 txrate |= rt->info[rix].shortPreamble; 1148 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 1149 } else { 1150 /* 1151 * Do rate lookup on each TX, rather than using 1152 * the hard-coded TX information decided here. 1153 */ 1154 ismrr = 1; 1155 bf->bf_state.bfs_doratelookup = 1; 1156 } 1157 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 1158 flags |= HAL_TXDESC_NOACK; 1159 break; 1160 default: 1161 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 1162 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1163 /* XXX statistic */ 1164 ath_freetx(m0); 1165 return EIO; 1166 } 1167 txq = sc->sc_ac2q[pri]; 1168 1169 /* 1170 * When servicing one or more stations in power-save mode 1171 * (or) if there is some mcast data waiting on the mcast 1172 * queue (to prevent out of order delivery) multicast 1173 * frames must be buffered until after the beacon. 1174 * 1175 * XXX This likely means that if there's a station in power 1176 * save mode, we won't be doing any kind of aggregation towards 1177 * anyone. This is likely a very suboptimal way of dealing 1178 * with things. 1179 */ 1180 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) 1181 txq = &avp->av_mcastq; 1182 1183 /* 1184 * Calculate miscellaneous flags. 1185 */ 1186 if (ismcast) { 1187 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 1188 } else if (pktlen > vap->iv_rtsthreshold && 1189 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 1190 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 1191 sc->sc_stats.ast_tx_rts++; 1192 } 1193 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 1194 sc->sc_stats.ast_tx_noack++; 1195#ifdef IEEE80211_SUPPORT_TDMA 1196 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 1197 DPRINTF(sc, ATH_DEBUG_TDMA, 1198 "%s: discard frame, ACK required w/ TDMA\n", __func__); 1199 sc->sc_stats.ast_tdma_ack++; 1200 ath_freetx(m0); 1201 return EIO; 1202 } 1203#endif 1204 1205 /* 1206 * If 802.11g protection is enabled, determine whether 1207 * to use RTS/CTS or just CTS. Note that this is only 1208 * done for OFDM unicast frames. 1209 */ 1210 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1211 rt->info[rix].phy == IEEE80211_T_OFDM && 1212 (flags & HAL_TXDESC_NOACK) == 0) { 1213 bf->bf_state.bfs_doprot = 1; 1214 /* XXX fragments must use CCK rates w/ protection */ 1215 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1216 flags |= HAL_TXDESC_RTSENA; 1217 } else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1218 flags |= HAL_TXDESC_CTSENA; 1219 } 1220 /* 1221 * For frags it would be desirable to use the 1222 * highest CCK rate for RTS/CTS. But stations 1223 * farther away may detect it at a lower CCK rate 1224 * so use the configured protection rate instead 1225 * (for now). 1226 */ 1227 sc->sc_stats.ast_tx_protect++; 1228 } 1229 1230#if 0 1231 /* 1232 * If 11n protection is enabled and it's a HT frame, 1233 * enable RTS. 1234 * 1235 * XXX ic_htprotmode or ic_curhtprotmode? 1236 * XXX should it_htprotmode only matter if ic_curhtprotmode 1237 * XXX indicates it's not a HT pure environment? 1238 */ 1239 if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) && 1240 rt->info[rix].phy == IEEE80211_T_HT && 1241 (flags & HAL_TXDESC_NOACK) == 0) { 1242 cix = rt->info[sc->sc_protrix].controlRate; 1243 flags |= HAL_TXDESC_RTSENA; 1244 sc->sc_stats.ast_tx_htprotect++; 1245 } 1246#endif 1247 1248 /* 1249 * Calculate duration. This logically belongs in the 802.11 1250 * layer but it lacks sufficient information to calculate it. 1251 */ 1252 if ((flags & HAL_TXDESC_NOACK) == 0 && 1253 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 1254 u_int16_t dur; 1255 if (shortPreamble) 1256 dur = rt->info[rix].spAckDuration; 1257 else 1258 dur = rt->info[rix].lpAckDuration; 1259 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 1260 dur += dur; /* additional SIFS+ACK */ 1261 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 1262 /* 1263 * Include the size of next fragment so NAV is 1264 * updated properly. The last fragment uses only 1265 * the ACK duration 1266 */ 1267 dur += ath_hal_computetxtime(ah, rt, 1268 m0->m_nextpkt->m_pkthdr.len, 1269 rix, shortPreamble); 1270 } 1271 if (isfrag) { 1272 /* 1273 * Force hardware to use computed duration for next 1274 * fragment by disabling multi-rate retry which updates 1275 * duration based on the multi-rate duration table. 1276 */ 1277 ismrr = 0; 1278 try0 = ATH_TXMGTTRY; /* XXX? */ 1279 } 1280 *(u_int16_t *)wh->i_dur = htole16(dur); 1281 } 1282 1283 /* 1284 * Determine if a tx interrupt should be generated for 1285 * this descriptor. We take a tx interrupt to reap 1286 * descriptors when the h/w hits an EOL condition or 1287 * when the descriptor is specifically marked to generate 1288 * an interrupt. We periodically mark descriptors in this 1289 * way to insure timely replenishing of the supply needed 1290 * for sending frames. Defering interrupts reduces system 1291 * load and potentially allows more concurrent work to be 1292 * done but if done to aggressively can cause senders to 1293 * backup. 1294 * 1295 * NB: use >= to deal with sc_txintrperiod changing 1296 * dynamically through sysctl. 1297 */ 1298 if (flags & HAL_TXDESC_INTREQ) { 1299 txq->axq_intrcnt = 0; 1300 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 1301 flags |= HAL_TXDESC_INTREQ; 1302 txq->axq_intrcnt = 0; 1303 } 1304 1305 /* This point forward is actual TX bits */ 1306 1307 /* 1308 * At this point we are committed to sending the frame 1309 * and we don't need to look at m_nextpkt; clear it in 1310 * case this frame is part of frag chain. 1311 */ 1312 m0->m_nextpkt = NULL; 1313 1314 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1315 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len, 1316 sc->sc_hwmap[rix].ieeerate, -1); 1317 1318 if (ieee80211_radiotap_active_vap(vap)) { 1319 u_int64_t tsf = ath_hal_gettsf64(ah); 1320 1321 sc->sc_tx_th.wt_tsf = htole64(tsf); 1322 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1323 if (iswep) 1324 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1325 if (isfrag) 1326 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1327 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1328 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 1329 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1330 1331 ieee80211_radiotap_tx(vap, m0); 1332 } 1333 1334 /* Blank the legacy rate array */ 1335 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1336 1337 /* 1338 * ath_buf_set_rate needs at least one rate/try to setup 1339 * the rate scenario. 1340 */ 1341 bf->bf_state.bfs_rc[0].rix = rix; 1342 bf->bf_state.bfs_rc[0].tries = try0; 1343 bf->bf_state.bfs_rc[0].ratecode = txrate; 1344 1345 /* Store the decided rate index values away */ 1346 bf->bf_state.bfs_pktlen = pktlen; 1347 bf->bf_state.bfs_hdrlen = hdrlen; 1348 bf->bf_state.bfs_atype = atype; 1349 bf->bf_state.bfs_txpower = ni->ni_txpower; 1350 bf->bf_state.bfs_txrate0 = txrate; 1351 bf->bf_state.bfs_try0 = try0; 1352 bf->bf_state.bfs_keyix = keyix; 1353 bf->bf_state.bfs_txantenna = sc->sc_txantenna; 1354 bf->bf_state.bfs_flags = flags; 1355 bf->bf_txflags = flags; 1356 bf->bf_state.bfs_shpream = shortPreamble; 1357 1358 /* XXX this should be done in ath_tx_setrate() */ 1359 bf->bf_state.bfs_ctsrate0 = 0; /* ie, no hard-coded ctsrate */ 1360 bf->bf_state.bfs_ctsrate = 0; /* calculated later */ 1361 bf->bf_state.bfs_ctsduration = 0; 1362 bf->bf_state.bfs_ismrr = ismrr; 1363 1364 return 0; 1365} 1366 1367/* 1368 * Direct-dispatch the current frame to the hardware. 1369 * 1370 * This can be called by the net80211 code. 1371 * 1372 * XXX what about locking? Or, push the seqno assign into the 1373 * XXX aggregate scheduler so its serialised? 1374 */ 1375int 1376ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, 1377 struct ath_buf *bf, struct mbuf *m0) 1378{ 1379 struct ieee80211vap *vap = ni->ni_vap; 1380 struct ath_vap *avp = ATH_VAP(vap); 1381 int r = 0; 1382 u_int pri; 1383 int tid; 1384 struct ath_txq *txq; 1385 int ismcast; 1386 const struct ieee80211_frame *wh; 1387 int is_ampdu, is_ampdu_tx, is_ampdu_pending; 1388 //ieee80211_seq seqno; 1389 uint8_t type, subtype; 1390 1391 /* 1392 * Determine the target hardware queue. 1393 * 1394 * For multicast frames, the txq gets overridden to be the 1395 * software TXQ and it's done via direct-dispatch. 1396 * 1397 * For any other frame, we do a TID/QoS lookup inside the frame 1398 * to see what the TID should be. If it's a non-QoS frame, the 1399 * AC and TID are overridden. The TID/TXQ code assumes the 1400 * TID is on a predictable hardware TXQ, so we don't support 1401 * having a node TID queued to multiple hardware TXQs. 1402 * This may change in the future but would require some locking 1403 * fudgery. 1404 */ 1405 pri = ath_tx_getac(sc, m0); 1406 tid = ath_tx_gettid(sc, m0); 1407 1408 txq = sc->sc_ac2q[pri]; 1409 wh = mtod(m0, struct ieee80211_frame *); 1410 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1411 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1412 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1413 1414 /* 1415 * Enforce how deep the multicast queue can grow. 1416 * 1417 * XXX duplicated in ath_raw_xmit(). 1418 */ 1419 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1420 ATH_TXQ_LOCK(sc->sc_cabq); 1421 1422 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 1423 sc->sc_stats.ast_tx_mcastq_overflow++; 1424 r = ENOBUFS; 1425 } 1426 1427 ATH_TXQ_UNLOCK(sc->sc_cabq); 1428 1429 if (r != 0) { 1430 m_freem(m0); 1431 return r; 1432 } 1433 } 1434 1435 /* A-MPDU TX */ 1436 is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid); 1437 is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid); 1438 is_ampdu = is_ampdu_tx | is_ampdu_pending; 1439 1440 DPRINTF(sc, ATH_DEBUG_SW_TX, 1441 "%s: bf=%p, tid=%d, ac=%d, is_ampdu=%d\n", 1442 __func__, bf, tid, pri, is_ampdu); 1443 1444 /* Multicast frames go onto the software multicast queue */ 1445 if (ismcast) 1446 txq = &avp->av_mcastq; 1447 1448 /* 1449 * XXX This likely means that if there's a station in power 1450 * save mode, we won't be doing any kind of aggregation towards 1451 * anyone. This is likely a very suboptimal way of dealing 1452 * with things. 1453 */ 1454 if ((! is_ampdu) && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) 1455 txq = &avp->av_mcastq; 1456 1457 /* Do the generic frame setup */ 1458 /* XXX should just bzero the bf_state? */ 1459 bf->bf_state.bfs_dobaw = 0; 1460 bf->bf_state.bfs_seqno_assigned = 0; 1461 bf->bf_state.bfs_need_seqno = 0; 1462 bf->bf_state.bfs_seqno = -1; /* XXX debugging */ 1463 1464 /* A-MPDU TX? Manually set sequence number */ 1465 /* Don't do it whilst pending; the net80211 layer still assigns them */ 1466 /* XXX do we need locking here? */ 1467 if (is_ampdu_tx) { 1468 ATH_TXQ_LOCK(txq); 1469 /* 1470 * Always call; this function will 1471 * handle making sure that null data frames 1472 * don't get a sequence number from the current 1473 * TID and thus mess with the BAW. 1474 */ 1475 //seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0); 1476 if (ath_tx_seqno_required(sc, ni, bf, m0)) { 1477 bf->bf_state.bfs_dobaw = 1; 1478 bf->bf_state.bfs_need_seqno = 1; 1479 } 1480 ATH_TXQ_UNLOCK(txq); 1481 } else { 1482 /* No AMPDU TX, we've been assigned a sequence number. */ 1483 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1484 bf->bf_state.bfs_seqno_assigned = 1; 1485 /* XXX we should store the frag+seqno in bfs_seqno */ 1486 bf->bf_state.bfs_seqno = 1487 M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT; 1488 } 1489 } 1490 1491 /* 1492 * If needed, the sequence number has been assigned. 1493 * Squirrel it away somewhere easy to get to. 1494 */ 1495 //bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT; 1496 1497 /* Is ampdu pending? fetch the seqno and print it out */ 1498 if (is_ampdu_pending) 1499 DPRINTF(sc, ATH_DEBUG_SW_TX, 1500 "%s: tid %d: ampdu pending, seqno %d\n", 1501 __func__, tid, M_SEQNO_GET(m0)); 1502 1503 /* This also sets up the DMA map */ 1504 r = ath_tx_normal_setup(sc, ni, bf, m0); 1505 1506 if (r != 0) 1507 return r; 1508 1509 /* At this point m0 could have changed! */ 1510 m0 = bf->bf_m; 1511 1512 DPRINTF(sc, ATH_DEBUG_SW_TX, 1513 "%s: DONE: bf=%p, tid=%d, ac=%d, is_ampdu=%d, dobaw=%d, seqno=%d\n", 1514 __func__, bf, tid, pri, is_ampdu, bf->bf_state.bfs_dobaw, M_SEQNO_GET(m0)); 1515 1516#if 1 1517 /* 1518 * If it's a multicast frame, do a direct-dispatch to the 1519 * destination hardware queue. Don't bother software 1520 * queuing it. 1521 */ 1522 /* 1523 * If it's a BAR frame, do a direct dispatch to the 1524 * destination hardware queue. Don't bother software 1525 * queuing it, as the TID will now be paused. 1526 * Sending a BAR frame can occur from the net80211 txa timer 1527 * (ie, retries) or from the ath txtask (completion call.) 1528 * It queues directly to hardware because the TID is paused 1529 * at this point (and won't be unpaused until the BAR has 1530 * either been TXed successfully or max retries has been 1531 * reached.) 1532 */ 1533 if (txq == &avp->av_mcastq) { 1534 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 1535 "%s: bf=%p: mcastq: TX'ing\n", __func__, bf); 1536 ATH_TXQ_LOCK(txq); 1537 ath_tx_xmit_normal(sc, txq, bf); 1538 ATH_TXQ_UNLOCK(txq); 1539 } else if (type == IEEE80211_FC0_TYPE_CTL && 1540 subtype == IEEE80211_FC0_SUBTYPE_BAR) { 1541 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 1542 "%s: BAR: TX'ing direct\n", __func__); 1543 ATH_TXQ_LOCK(txq); 1544 ath_tx_xmit_normal(sc, txq, bf); 1545 ATH_TXQ_UNLOCK(txq); 1546 } else { 1547 /* add to software queue */ 1548 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 1549 "%s: bf=%p: swq: TX'ing\n", __func__, bf); 1550 ath_tx_swq(sc, ni, txq, bf); 1551 } 1552#else 1553 /* 1554 * For now, since there's no software queue, 1555 * direct-dispatch to the hardware. 1556 */ 1557 ATH_TXQ_LOCK(txq); 1558 ath_tx_xmit_normal(sc, txq, bf); 1559 ATH_TXQ_UNLOCK(txq); 1560#endif 1561 1562 return 0; 1563} 1564 1565static int 1566ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 1567 struct ath_buf *bf, struct mbuf *m0, 1568 const struct ieee80211_bpf_params *params) 1569{ 1570 struct ifnet *ifp = sc->sc_ifp; 1571 struct ieee80211com *ic = ifp->if_l2com; 1572 struct ath_hal *ah = sc->sc_ah; 1573 struct ieee80211vap *vap = ni->ni_vap; 1574 int error, ismcast, ismrr; 1575 int keyix, hdrlen, pktlen, try0, txantenna; 1576 u_int8_t rix, txrate; 1577 struct ieee80211_frame *wh; 1578 u_int flags; 1579 HAL_PKT_TYPE atype; 1580 const HAL_RATE_TABLE *rt; 1581 struct ath_desc *ds; 1582 u_int pri; 1583 int o_tid = -1; 1584 int do_override; 1585 1586 wh = mtod(m0, struct ieee80211_frame *); 1587 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1588 hdrlen = ieee80211_anyhdrsize(wh); 1589 /* 1590 * Packet length must not include any 1591 * pad bytes; deduct them here. 1592 */ 1593 /* XXX honor IEEE80211_BPF_DATAPAD */ 1594 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 1595 1596 1597 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n", 1598 __func__, ismcast); 1599 1600 /* Handle encryption twiddling if needed */ 1601 if (! ath_tx_tag_crypto(sc, ni, 1602 m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0, 1603 &hdrlen, &pktlen, &keyix)) { 1604 ath_freetx(m0); 1605 return EIO; 1606 } 1607 /* packet header may have moved, reset our local pointer */ 1608 wh = mtod(m0, struct ieee80211_frame *); 1609 1610 /* Do the generic frame setup */ 1611 /* XXX should just bzero the bf_state? */ 1612 bf->bf_state.bfs_dobaw = 0; 1613 1614 error = ath_tx_dmasetup(sc, bf, m0); 1615 if (error != 0) 1616 return error; 1617 m0 = bf->bf_m; /* NB: may have changed */ 1618 wh = mtod(m0, struct ieee80211_frame *); 1619 bf->bf_node = ni; /* NB: held reference */ 1620 1621 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1622 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1623 if (params->ibp_flags & IEEE80211_BPF_RTS) 1624 flags |= HAL_TXDESC_RTSENA; 1625 else if (params->ibp_flags & IEEE80211_BPF_CTS) { 1626 /* XXX assume 11g/11n protection? */ 1627 bf->bf_state.bfs_doprot = 1; 1628 flags |= HAL_TXDESC_CTSENA; 1629 } 1630 /* XXX leave ismcast to injector? */ 1631 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 1632 flags |= HAL_TXDESC_NOACK; 1633 1634 rt = sc->sc_currates; 1635 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1636 rix = ath_tx_findrix(sc, params->ibp_rate0); 1637 txrate = rt->info[rix].rateCode; 1638 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 1639 txrate |= rt->info[rix].shortPreamble; 1640 sc->sc_txrix = rix; 1641 try0 = params->ibp_try0; 1642 ismrr = (params->ibp_try1 != 0); 1643 txantenna = params->ibp_pri >> 2; 1644 if (txantenna == 0) /* XXX? */ 1645 txantenna = sc->sc_txantenna; 1646 1647 /* 1648 * Since ctsrate is fixed, store it away for later 1649 * use when the descriptor fields are being set. 1650 */ 1651 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) 1652 bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate; 1653 1654 pri = params->ibp_pri & 3; 1655 /* Override pri if the frame isn't a QoS one */ 1656 if (! IEEE80211_QOS_HAS_SEQ(wh)) 1657 pri = ath_tx_getac(sc, m0); 1658 1659 /* 1660 * NB: we mark all packets as type PSPOLL so the h/w won't 1661 * set the sequence number, duration, etc. 1662 */ 1663 atype = HAL_PKT_TYPE_PSPOLL; 1664 1665 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1666 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 1667 sc->sc_hwmap[rix].ieeerate, -1); 1668 1669 if (ieee80211_radiotap_active_vap(vap)) { 1670 u_int64_t tsf = ath_hal_gettsf64(ah); 1671 1672 sc->sc_tx_th.wt_tsf = htole64(tsf); 1673 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1674 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1675 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1676 if (m0->m_flags & M_FRAG) 1677 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1678 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1679 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 1680 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1681 1682 ieee80211_radiotap_tx(vap, m0); 1683 } 1684 1685 /* 1686 * Formulate first tx descriptor with tx controls. 1687 */ 1688 ds = bf->bf_desc; 1689 /* XXX check return value? */ 1690 1691 /* Store the decided rate index values away */ 1692 bf->bf_state.bfs_pktlen = pktlen; 1693 bf->bf_state.bfs_hdrlen = hdrlen; 1694 bf->bf_state.bfs_atype = atype; 1695 bf->bf_state.bfs_txpower = params->ibp_power; 1696 bf->bf_state.bfs_txrate0 = txrate; 1697 bf->bf_state.bfs_try0 = try0; 1698 bf->bf_state.bfs_keyix = keyix; 1699 bf->bf_state.bfs_txantenna = txantenna; 1700 bf->bf_state.bfs_flags = flags; 1701 bf->bf_txflags = flags; 1702 bf->bf_state.bfs_shpream = 1703 !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE); 1704 1705 /* XXX this should be done in ath_tx_setrate() */ 1706 bf->bf_state.bfs_ctsrate = 0; 1707 bf->bf_state.bfs_ctsduration = 0; 1708 bf->bf_state.bfs_ismrr = ismrr; 1709 1710 /* Blank the legacy rate array */ 1711 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1712 1713 bf->bf_state.bfs_rc[0].rix = 1714 ath_tx_findrix(sc, params->ibp_rate0); 1715 bf->bf_state.bfs_rc[0].tries = try0; 1716 bf->bf_state.bfs_rc[0].ratecode = txrate; 1717 1718 if (ismrr) { 1719 int rix; 1720 1721 rix = ath_tx_findrix(sc, params->ibp_rate1); 1722 bf->bf_state.bfs_rc[1].rix = rix; 1723 bf->bf_state.bfs_rc[1].tries = params->ibp_try1; 1724 1725 rix = ath_tx_findrix(sc, params->ibp_rate2); 1726 bf->bf_state.bfs_rc[2].rix = rix; 1727 bf->bf_state.bfs_rc[2].tries = params->ibp_try2; 1728 1729 rix = ath_tx_findrix(sc, params->ibp_rate3); 1730 bf->bf_state.bfs_rc[3].rix = rix; 1731 bf->bf_state.bfs_rc[3].tries = params->ibp_try3; 1732 } 1733 /* 1734 * All the required rate control decisions have been made; 1735 * fill in the rc flags. 1736 */ 1737 ath_tx_rate_fill_rcflags(sc, bf); 1738 1739 /* NB: no buffered multicast in power save support */ 1740 1741 /* XXX If it's an ADDBA, override the correct queue */ 1742 do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid); 1743 1744 /* Map ADDBA to the correct priority */ 1745 if (do_override) { 1746#if 0 1747 device_printf(sc->sc_dev, 1748 "%s: overriding tid %d pri %d -> %d\n", 1749 __func__, o_tid, pri, TID_TO_WME_AC(o_tid)); 1750#endif 1751 pri = TID_TO_WME_AC(o_tid); 1752 } 1753 1754 /* 1755 * If we're overiding the ADDBA destination, dump directly 1756 * into the hardware queue, right after any pending 1757 * frames to that node are. 1758 */ 1759 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n", 1760 __func__, do_override); 1761 1762 if (do_override) { 1763 ATH_TXQ_LOCK(sc->sc_ac2q[pri]); 1764 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf); 1765 ATH_TXQ_UNLOCK(sc->sc_ac2q[pri]); 1766 } else { 1767 /* Queue to software queue */ 1768 ath_tx_swq(sc, ni, sc->sc_ac2q[pri], bf); 1769 } 1770 1771 return 0; 1772} 1773 1774/* 1775 * Send a raw frame. 1776 * 1777 * This can be called by net80211. 1778 */ 1779int 1780ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1781 const struct ieee80211_bpf_params *params) 1782{ 1783 struct ieee80211com *ic = ni->ni_ic; 1784 struct ifnet *ifp = ic->ic_ifp; 1785 struct ath_softc *sc = ifp->if_softc; 1786 struct ath_buf *bf; 1787 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 1788 int error = 0; 1789 1790 ATH_PCU_LOCK(sc); 1791 if (sc->sc_inreset_cnt > 0) { 1792 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; bailing\n", 1793 __func__); 1794 error = EIO; 1795 ATH_PCU_UNLOCK(sc); 1796 goto bad0; 1797 } 1798 sc->sc_txstart_cnt++; 1799 ATH_PCU_UNLOCK(sc); 1800 1801 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 1802 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 1803 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ? 1804 "!running" : "invalid"); 1805 m_freem(m); 1806 error = ENETDOWN; 1807 goto bad; 1808 } 1809 1810 /* 1811 * Enforce how deep the multicast queue can grow. 1812 * 1813 * XXX duplicated in ath_tx_start(). 1814 */ 1815 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1816 ATH_TXQ_LOCK(sc->sc_cabq); 1817 1818 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 1819 sc->sc_stats.ast_tx_mcastq_overflow++; 1820 error = ENOBUFS; 1821 } 1822 1823 ATH_TXQ_UNLOCK(sc->sc_cabq); 1824 1825 if (error != 0) { 1826 m_freem(m); 1827 goto bad; 1828 } 1829 } 1830 1831 /* 1832 * Grab a TX buffer and associated resources. 1833 */ 1834 bf = ath_getbuf(sc); 1835 if (bf == NULL) { 1836 sc->sc_stats.ast_tx_nobuf++; 1837 m_freem(m); 1838 error = ENOBUFS; 1839 goto bad; 1840 } 1841 1842 if (params == NULL) { 1843 /* 1844 * Legacy path; interpret frame contents to decide 1845 * precisely how to send the frame. 1846 */ 1847 if (ath_tx_start(sc, ni, bf, m)) { 1848 error = EIO; /* XXX */ 1849 goto bad2; 1850 } 1851 } else { 1852 /* 1853 * Caller supplied explicit parameters to use in 1854 * sending the frame. 1855 */ 1856 if (ath_tx_raw_start(sc, ni, bf, m, params)) { 1857 error = EIO; /* XXX */ 1858 goto bad2; 1859 } 1860 } 1861 sc->sc_wd_timer = 5; 1862 ifp->if_opackets++; 1863 sc->sc_stats.ast_tx_raw++; 1864 1865 ATH_PCU_LOCK(sc); 1866 sc->sc_txstart_cnt--; 1867 ATH_PCU_UNLOCK(sc); 1868 1869 return 0; 1870bad2: 1871 ATH_TXBUF_LOCK(sc); 1872 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1873 ATH_TXBUF_UNLOCK(sc); 1874bad: 1875 ATH_PCU_LOCK(sc); 1876 sc->sc_txstart_cnt--; 1877 ATH_PCU_UNLOCK(sc); 1878bad0: 1879 ifp->if_oerrors++; 1880 sc->sc_stats.ast_tx_raw_fail++; 1881 ieee80211_free_node(ni); 1882 1883 return error; 1884} 1885 1886/* Some helper functions */ 1887 1888/* 1889 * ADDBA (and potentially others) need to be placed in the same 1890 * hardware queue as the TID/node it's relating to. This is so 1891 * it goes out after any pending non-aggregate frames to the 1892 * same node/TID. 1893 * 1894 * If this isn't done, the ADDBA can go out before the frames 1895 * queued in hardware. Even though these frames have a sequence 1896 * number -earlier- than the ADDBA can be transmitted (but 1897 * no frames whose sequence numbers are after the ADDBA should 1898 * be!) they'll arrive after the ADDBA - and the receiving end 1899 * will simply drop them as being out of the BAW. 1900 * 1901 * The frames can't be appended to the TID software queue - it'll 1902 * never be sent out. So these frames have to be directly 1903 * dispatched to the hardware, rather than queued in software. 1904 * So if this function returns true, the TXQ has to be 1905 * overridden and it has to be directly dispatched. 1906 * 1907 * It's a dirty hack, but someone's gotta do it. 1908 */ 1909 1910/* 1911 * XXX doesn't belong here! 1912 */ 1913static int 1914ieee80211_is_action(struct ieee80211_frame *wh) 1915{ 1916 /* Type: Management frame? */ 1917 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 1918 IEEE80211_FC0_TYPE_MGT) 1919 return 0; 1920 1921 /* Subtype: Action frame? */ 1922 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) != 1923 IEEE80211_FC0_SUBTYPE_ACTION) 1924 return 0; 1925 1926 return 1; 1927} 1928 1929#define MS(_v, _f) (((_v) & _f) >> _f##_S) 1930/* 1931 * Return an alternate TID for ADDBA request frames. 1932 * 1933 * Yes, this likely should be done in the net80211 layer. 1934 */ 1935static int 1936ath_tx_action_frame_override_queue(struct ath_softc *sc, 1937 struct ieee80211_node *ni, 1938 struct mbuf *m0, int *tid) 1939{ 1940 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 1941 struct ieee80211_action_ba_addbarequest *ia; 1942 uint8_t *frm; 1943 uint16_t baparamset; 1944 1945 /* Not action frame? Bail */ 1946 if (! ieee80211_is_action(wh)) 1947 return 0; 1948 1949 /* XXX Not needed for frames we send? */ 1950#if 0 1951 /* Correct length? */ 1952 if (! ieee80211_parse_action(ni, m)) 1953 return 0; 1954#endif 1955 1956 /* Extract out action frame */ 1957 frm = (u_int8_t *)&wh[1]; 1958 ia = (struct ieee80211_action_ba_addbarequest *) frm; 1959 1960 /* Not ADDBA? Bail */ 1961 if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA) 1962 return 0; 1963 if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST) 1964 return 0; 1965 1966 /* Extract TID, return it */ 1967 baparamset = le16toh(ia->rq_baparamset); 1968 *tid = (int) MS(baparamset, IEEE80211_BAPS_TID); 1969 1970 return 1; 1971} 1972#undef MS 1973 1974/* Per-node software queue operations */ 1975 1976/* 1977 * Add the current packet to the given BAW. 1978 * It is assumed that the current packet 1979 * 1980 * + fits inside the BAW; 1981 * + already has had a sequence number allocated. 1982 * 1983 * Since the BAW status may be modified by both the ath task and 1984 * the net80211/ifnet contexts, the TID must be locked. 1985 */ 1986void 1987ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an, 1988 struct ath_tid *tid, struct ath_buf *bf) 1989{ 1990 int index, cindex; 1991 struct ieee80211_tx_ampdu *tap; 1992 1993 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 1994 1995 if (bf->bf_state.bfs_isretried) 1996 return; 1997 1998 /* 1999 * If this occurs we're in a lot of trouble. We should try to 2000 * recover from this without the session hanging? 2001 */ 2002 if (! bf->bf_state.bfs_seqno_assigned) { 2003 device_printf(sc->sc_dev, 2004 "%s: bf=%p, seqno_assigned is 0?!\n", __func__, bf); 2005 return; 2006 } 2007 2008 tap = ath_tx_get_tx_tid(an, tid->tid); 2009 2010 if (bf->bf_state.bfs_addedbaw) 2011 device_printf(sc->sc_dev, 2012 "%s: re-added? bf=%p, tid=%d, seqno %d; window %d:%d; " 2013 "baw head=%d tail=%d\n", 2014 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2015 tap->txa_start, tap->txa_wnd, tid->baw_head, 2016 tid->baw_tail); 2017 2018 /* 2019 * Verify that the given sequence number is not outside of the 2020 * BAW. Complain loudly if that's the case. 2021 */ 2022 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2023 SEQNO(bf->bf_state.bfs_seqno))) { 2024 device_printf(sc->sc_dev, 2025 "%s: bf=%p: outside of BAW?? tid=%d, seqno %d; window %d:%d; " 2026 "baw head=%d tail=%d\n", 2027 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2028 tap->txa_start, tap->txa_wnd, tid->baw_head, 2029 tid->baw_tail); 2030 2031 } 2032 2033 /* 2034 * ni->ni_txseqs[] is the currently allocated seqno. 2035 * the txa state contains the current baw start. 2036 */ 2037 index = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno)); 2038 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2039 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2040 "%s: bf=%p, tid=%d, seqno %d; window %d:%d; index=%d cindex=%d " 2041 "baw head=%d tail=%d\n", 2042 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2043 tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head, 2044 tid->baw_tail); 2045 2046 2047#if 0 2048 assert(tid->tx_buf[cindex] == NULL); 2049#endif 2050 if (tid->tx_buf[cindex] != NULL) { 2051 device_printf(sc->sc_dev, 2052 "%s: ba packet dup (index=%d, cindex=%d, " 2053 "head=%d, tail=%d)\n", 2054 __func__, index, cindex, tid->baw_head, tid->baw_tail); 2055 device_printf(sc->sc_dev, 2056 "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n", 2057 __func__, 2058 tid->tx_buf[cindex], 2059 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno), 2060 bf, 2061 SEQNO(bf->bf_state.bfs_seqno) 2062 ); 2063 } 2064 tid->tx_buf[cindex] = bf; 2065 2066 if (index >= ((tid->baw_tail - tid->baw_head) & 2067 (ATH_TID_MAX_BUFS - 1))) { 2068 tid->baw_tail = cindex; 2069 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 2070 } 2071} 2072 2073/* 2074 * Flip the BAW buffer entry over from the existing one to the new one. 2075 * 2076 * When software retransmitting a (sub-)frame, it is entirely possible that 2077 * the frame ath_buf is marked as BUSY and can't be immediately reused. 2078 * In that instance the buffer is cloned and the new buffer is used for 2079 * retransmit. We thus need to update the ath_buf slot in the BAW buf 2080 * tracking array to maintain consistency. 2081 */ 2082static void 2083ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an, 2084 struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf) 2085{ 2086 int index, cindex; 2087 struct ieee80211_tx_ampdu *tap; 2088 int seqno = SEQNO(old_bf->bf_state.bfs_seqno); 2089 2090 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2091 2092 tap = ath_tx_get_tx_tid(an, tid->tid); 2093 index = ATH_BA_INDEX(tap->txa_start, seqno); 2094 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2095 2096 /* 2097 * Just warn for now; if it happens then we should find out 2098 * about it. It's highly likely the aggregation session will 2099 * soon hang. 2100 */ 2101 if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) { 2102 device_printf(sc->sc_dev, "%s: retransmitted buffer" 2103 " has mismatching seqno's, BA session may hang.\n", 2104 __func__); 2105 device_printf(sc->sc_dev, "%s: old seqno=%d, new_seqno=%d\n", 2106 __func__, 2107 old_bf->bf_state.bfs_seqno, 2108 new_bf->bf_state.bfs_seqno); 2109 } 2110 2111 if (tid->tx_buf[cindex] != old_bf) { 2112 device_printf(sc->sc_dev, "%s: ath_buf pointer incorrect; " 2113 " has m BA session may hang.\n", 2114 __func__); 2115 device_printf(sc->sc_dev, "%s: old bf=%p, new bf=%p\n", 2116 __func__, 2117 old_bf, new_bf); 2118 } 2119 2120 tid->tx_buf[cindex] = new_bf; 2121} 2122 2123/* 2124 * seq_start - left edge of BAW 2125 * seq_next - current/next sequence number to allocate 2126 * 2127 * Since the BAW status may be modified by both the ath task and 2128 * the net80211/ifnet contexts, the TID must be locked. 2129 */ 2130static void 2131ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an, 2132 struct ath_tid *tid, const struct ath_buf *bf) 2133{ 2134 int index, cindex; 2135 struct ieee80211_tx_ampdu *tap; 2136 int seqno = SEQNO(bf->bf_state.bfs_seqno); 2137 2138 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2139 2140 tap = ath_tx_get_tx_tid(an, tid->tid); 2141 index = ATH_BA_INDEX(tap->txa_start, seqno); 2142 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2143 2144 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2145 "%s: bf=%p: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, " 2146 "baw head=%d, tail=%d\n", 2147 __func__, bf, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index, 2148 cindex, tid->baw_head, tid->baw_tail); 2149 2150 /* 2151 * If this occurs then we have a big problem - something else 2152 * has slid tap->txa_start along without updating the BAW 2153 * tracking start/end pointers. Thus the TX BAW state is now 2154 * completely busted. 2155 * 2156 * But for now, since I haven't yet fixed TDMA and buffer cloning, 2157 * it's quite possible that a cloned buffer is making its way 2158 * here and causing it to fire off. Disable TDMA for now. 2159 */ 2160 if (tid->tx_buf[cindex] != bf) { 2161 device_printf(sc->sc_dev, 2162 "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n", 2163 __func__, 2164 bf, SEQNO(bf->bf_state.bfs_seqno), 2165 tid->tx_buf[cindex], 2166 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno)); 2167 } 2168 2169 tid->tx_buf[cindex] = NULL; 2170 2171 while (tid->baw_head != tid->baw_tail && 2172 !tid->tx_buf[tid->baw_head]) { 2173 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 2174 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 2175 } 2176 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2177 "%s: baw is now %d:%d, baw head=%d\n", 2178 __func__, tap->txa_start, tap->txa_wnd, tid->baw_head); 2179} 2180 2181/* 2182 * Mark the current node/TID as ready to TX. 2183 * 2184 * This is done to make it easy for the software scheduler to 2185 * find which nodes have data to send. 2186 * 2187 * The TXQ lock must be held. 2188 */ 2189static void 2190ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid) 2191{ 2192 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2193 2194 ATH_TXQ_LOCK_ASSERT(txq); 2195 2196 if (tid->paused) 2197 return; /* paused, can't schedule yet */ 2198 2199 if (tid->sched) 2200 return; /* already scheduled */ 2201 2202 tid->sched = 1; 2203 2204 TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem); 2205} 2206 2207/* 2208 * Mark the current node as no longer needing to be polled for 2209 * TX packets. 2210 * 2211 * The TXQ lock must be held. 2212 */ 2213static void 2214ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid) 2215{ 2216 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2217 2218 ATH_TXQ_LOCK_ASSERT(txq); 2219 2220 if (tid->sched == 0) 2221 return; 2222 2223 tid->sched = 0; 2224 TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem); 2225} 2226 2227/* 2228 * Return whether a sequence number is actually required. 2229 * 2230 * A sequence number must only be allocated at the time that a frame 2231 * is considered for addition to the BAW/aggregate and being TXed. 2232 * The sequence number must not be allocated before the frame 2233 * is added to the BAW (protected by the same lock instance) 2234 * otherwise a the multi-entrant TX path may result in a later seqno 2235 * being added to the BAW first. The subsequent addition of the 2236 * earlier seqno would then not go into the BAW as it's now outside 2237 * of said BAW. 2238 * 2239 * This routine is used by ath_tx_start() to mark whether the frame 2240 * should get a sequence number before adding it to the BAW. 2241 * 2242 * Then the actual aggregate TX routines will check whether this 2243 * flag is set and if the frame needs to go into the BAW, it'll 2244 * have a sequence number allocated for it. 2245 */ 2246static int 2247ath_tx_seqno_required(struct ath_softc *sc, struct ieee80211_node *ni, 2248 struct ath_buf *bf, struct mbuf *m0) 2249{ 2250 const struct ieee80211_frame *wh; 2251 uint8_t subtype; 2252 2253 wh = mtod(m0, const struct ieee80211_frame *); 2254 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2255 2256 /* XXX assert txq lock */ 2257 /* XXX assert ampdu is set */ 2258 2259 return ((IEEE80211_QOS_HAS_SEQ(wh) && 2260 subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL)); 2261} 2262 2263/* 2264 * Assign a sequence number manually to the given frame. 2265 * 2266 * This should only be called for A-MPDU TX frames. 2267 * 2268 * If this is called after the initial frame setup, make sure you've flushed 2269 * the DMA map or you'll risk sending stale data to the NIC. This routine 2270 * updates the actual frame contents with the relevant seqno. 2271 */ 2272int 2273ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni, 2274 struct ath_buf *bf, struct mbuf *m0) 2275{ 2276 struct ieee80211_frame *wh; 2277 int tid, pri; 2278 ieee80211_seq seqno; 2279 uint8_t subtype; 2280 2281 /* TID lookup */ 2282 wh = mtod(m0, struct ieee80211_frame *); 2283 pri = M_WME_GETAC(m0); /* honor classification */ 2284 tid = WME_AC_TO_TID(pri); 2285 DPRINTF(sc, ATH_DEBUG_SW_TX, 2286 "%s: bf=%p, pri=%d, tid=%d, qos has seq=%d\n", 2287 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2288 2289 if (! bf->bf_state.bfs_need_seqno) { 2290 device_printf(sc->sc_dev, "%s: bf=%p: need_seqno not set?!\n", 2291 __func__, bf); 2292 return -1; 2293 } 2294 /* XXX check for bfs_need_seqno? */ 2295 if (bf->bf_state.bfs_seqno_assigned) { 2296 device_printf(sc->sc_dev, 2297 "%s: bf=%p: seqno already assigned (%d)?!\n", 2298 __func__, bf, SEQNO(bf->bf_state.bfs_seqno)); 2299 return bf->bf_state.bfs_seqno >> IEEE80211_SEQ_SEQ_SHIFT; 2300 } 2301 2302 /* XXX Is it a control frame? Ignore */ 2303 2304 /* Does the packet require a sequence number? */ 2305 if (! IEEE80211_QOS_HAS_SEQ(wh)) 2306 return -1; 2307 2308 /* 2309 * Is it a QOS NULL Data frame? Give it a sequence number from 2310 * the default TID (IEEE80211_NONQOS_TID.) 2311 * 2312 * The RX path of everything I've looked at doesn't include the NULL 2313 * data frame sequence number in the aggregation state updates, so 2314 * assigning it a sequence number there will cause a BAW hole on the 2315 * RX side. 2316 */ 2317 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2318 if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) { 2319 seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID]; 2320 INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE); 2321 } else { 2322 /* Manually assign sequence number */ 2323 seqno = ni->ni_txseqs[tid]; 2324 INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE); 2325 } 2326 *(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 2327 M_SEQNO_SET(m0, seqno); 2328 bf->bf_state.bfs_seqno = seqno << IEEE80211_SEQ_SEQ_SHIFT; 2329 bf->bf_state.bfs_seqno_assigned = 1; 2330 2331 /* Return so caller can do something with it if needed */ 2332 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: -> seqno=%d\n", 2333 __func__, 2334 bf, 2335 seqno); 2336 return seqno; 2337} 2338 2339/* 2340 * Attempt to direct dispatch an aggregate frame to hardware. 2341 * If the frame is out of BAW, queue. 2342 * Otherwise, schedule it as a single frame. 2343 */ 2344static void 2345ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an, struct ath_buf *bf) 2346{ 2347 struct ieee80211_node *ni = &an->an_node; 2348 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid]; 2349 struct ath_txq *txq = bf->bf_state.bfs_txq; 2350 struct ieee80211_tx_ampdu *tap; 2351 2352 ATH_TXQ_LOCK_ASSERT(txq); 2353 2354 tap = ath_tx_get_tx_tid(an, tid->tid); 2355 2356 /* paused? queue */ 2357 if (tid->paused) { 2358 ATH_TXQ_INSERT_TAIL(tid, bf, bf_list); 2359 /* XXX don't sched - we're paused! */ 2360 return; 2361 } 2362 2363 /* 2364 * TODO: If it's _before_ the BAW left edge, complain very loudly. 2365 * This means something (else) has slid the left edge along 2366 * before we got a chance to be TXed. 2367 */ 2368 2369 /* 2370 * Is there space in this BAW for another frame? 2371 * If not, don't bother trying to schedule it; just 2372 * throw it back on the queue. 2373 * 2374 * If we allocate the sequence number before we add 2375 * it to the BAW, we risk racing with another TX 2376 * thread that gets in a frame into the BAW with 2377 * seqno greater than ours. We'd then fail the 2378 * below check and throw the frame on the tail of 2379 * the queue. The sender would then have a hole. 2380 * 2381 * XXX again, we're protecting ni->ni_txseqs[tid] 2382 * behind this hardware TXQ lock, like the rest of 2383 * the TIDs that map to it. Ugh. 2384 */ 2385 if (bf->bf_state.bfs_dobaw) { 2386 ieee80211_seq seqno; 2387 2388 /* 2389 * If the sequence number is allocated, use it. 2390 * Otherwise, use the sequence number we WOULD 2391 * allocate. 2392 */ 2393 if (bf->bf_state.bfs_seqno_assigned) 2394 seqno = SEQNO(bf->bf_state.bfs_seqno); 2395 else 2396 seqno = ni->ni_txseqs[bf->bf_state.bfs_tid]; 2397 2398 /* 2399 * Check whether either the currently allocated 2400 * sequence number _OR_ the to-be allocated 2401 * sequence number is inside the BAW. 2402 */ 2403 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, seqno)) { 2404 ATH_TXQ_INSERT_TAIL(tid, bf, bf_list); 2405 ath_tx_tid_sched(sc, tid); 2406 return; 2407 } 2408 if (! bf->bf_state.bfs_seqno_assigned) { 2409 int seqno; 2410 2411 seqno = ath_tx_tid_seqno_assign(sc, ni, bf, bf->bf_m); 2412 if (seqno < 0) { 2413 device_printf(sc->sc_dev, 2414 "%s: bf=%p, huh, seqno=-1?\n", 2415 __func__, 2416 bf); 2417 /* XXX what can we even do here? */ 2418 } 2419 /* Flush seqno update to RAM */ 2420 /* 2421 * XXX This is required because the dmasetup 2422 * XXX is done early rather than at dispatch 2423 * XXX time. Ew, we should fix this! 2424 */ 2425 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2426 BUS_DMASYNC_PREWRITE); 2427 } 2428 } 2429 2430 /* outside baw? queue */ 2431 if (bf->bf_state.bfs_dobaw && 2432 (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2433 SEQNO(bf->bf_state.bfs_seqno)))) { 2434 device_printf(sc->sc_dev, 2435 "%s: bf=%p, shouldn't be outside BAW now?!\n", 2436 __func__, 2437 bf); 2438 ATH_TXQ_INSERT_TAIL(tid, bf, bf_list); 2439 ath_tx_tid_sched(sc, tid); 2440 return; 2441 } 2442 2443 /* Direct dispatch to hardware */ 2444 ath_tx_do_ratelookup(sc, bf); 2445 ath_tx_rate_fill_rcflags(sc, bf); 2446 ath_tx_set_rtscts(sc, bf); 2447 ath_tx_setds(sc, bf); 2448 ath_tx_set_ratectrl(sc, bf->bf_node, bf); 2449 ath_tx_chaindesclist(sc, bf); 2450 2451 /* Statistics */ 2452 sc->sc_aggr_stats.aggr_low_hwq_single_pkt++; 2453 2454 /* Track per-TID hardware queue depth correctly */ 2455 tid->hwq_depth++; 2456 2457 /* Add to BAW */ 2458 if (bf->bf_state.bfs_dobaw) { 2459 ath_tx_addto_baw(sc, an, tid, bf); 2460 bf->bf_state.bfs_addedbaw = 1; 2461 } 2462 2463 /* Set completion handler, multi-frame aggregate or not */ 2464 bf->bf_comp = ath_tx_aggr_comp; 2465 2466 /* Hand off to hardware */ 2467 ath_tx_handoff(sc, txq, bf); 2468} 2469 2470/* 2471 * Attempt to send the packet. 2472 * If the queue isn't busy, direct-dispatch. 2473 * If the queue is busy enough, queue the given packet on the 2474 * relevant software queue. 2475 */ 2476void 2477ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_txq *txq, 2478 struct ath_buf *bf) 2479{ 2480 struct ath_node *an = ATH_NODE(ni); 2481 struct ieee80211_frame *wh; 2482 struct ath_tid *atid; 2483 int pri, tid; 2484 struct mbuf *m0 = bf->bf_m; 2485 2486 /* Fetch the TID - non-QoS frames get assigned to TID 16 */ 2487 wh = mtod(m0, struct ieee80211_frame *); 2488 pri = ath_tx_getac(sc, m0); 2489 tid = ath_tx_gettid(sc, m0); 2490 atid = &an->an_tid[tid]; 2491 2492 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d, seqno=%d\n", 2493 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh), SEQNO(bf->bf_state.bfs_seqno)); 2494 2495 /* Set local packet state, used to queue packets to hardware */ 2496 bf->bf_state.bfs_tid = tid; 2497 bf->bf_state.bfs_txq = txq; 2498 bf->bf_state.bfs_pri = pri; 2499 2500 /* 2501 * If the hardware queue isn't busy, queue it directly. 2502 * If the hardware queue is busy, queue it. 2503 * If the TID is paused or the traffic it outside BAW, software 2504 * queue it. 2505 */ 2506 ATH_TXQ_LOCK(txq); 2507 if (atid->paused) { 2508 /* TID is paused, queue */ 2509 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: paused\n", __func__, bf); 2510 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2511 } else if (ath_tx_ampdu_pending(sc, an, tid)) { 2512 /* AMPDU pending; queue */ 2513 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: pending\n", __func__, bf); 2514 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2515 /* XXX sched? */ 2516 } else if (ath_tx_ampdu_running(sc, an, tid)) { 2517 /* AMPDU running, attempt direct dispatch if possible */ 2518 if (txq->axq_depth < sc->sc_hwq_limit) { 2519 DPRINTF(sc, ATH_DEBUG_SW_TX, 2520 "%s: bf=%p: xmit_aggr\n", 2521 __func__, bf); 2522 ath_tx_xmit_aggr(sc, an, bf); 2523 } else { 2524 DPRINTF(sc, ATH_DEBUG_SW_TX, 2525 "%s: bf=%p: ampdu; swq'ing\n", 2526 __func__, bf); 2527 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2528 ath_tx_tid_sched(sc, atid); 2529 } 2530 } else if (txq->axq_depth < sc->sc_hwq_limit) { 2531 /* AMPDU not running, attempt direct dispatch */ 2532 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: xmit_normal\n", __func__, bf); 2533 ath_tx_xmit_normal(sc, txq, bf); 2534 } else { 2535 /* Busy; queue */ 2536 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: swq'ing\n", __func__, bf); 2537 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2538 ath_tx_tid_sched(sc, atid); 2539 } 2540 ATH_TXQ_UNLOCK(txq); 2541} 2542 2543/* 2544 * Do the basic frame setup stuff that's required before the frame 2545 * is added to a software queue. 2546 * 2547 * All frames get mostly the same treatment and it's done once. 2548 * Retransmits fiddle with things like the rate control setup, 2549 * setting the retransmit bit in the packet; doing relevant DMA/bus 2550 * syncing and relinking it (back) into the hardware TX queue. 2551 * 2552 * Note that this may cause the mbuf to be reallocated, so 2553 * m0 may not be valid. 2554 */ 2555 2556 2557/* 2558 * Configure the per-TID node state. 2559 * 2560 * This likely belongs in if_ath_node.c but I can't think of anywhere 2561 * else to put it just yet. 2562 * 2563 * This sets up the SLISTs and the mutex as appropriate. 2564 */ 2565void 2566ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an) 2567{ 2568 int i, j; 2569 struct ath_tid *atid; 2570 2571 for (i = 0; i < IEEE80211_TID_SIZE; i++) { 2572 atid = &an->an_tid[i]; 2573 TAILQ_INIT(&atid->axq_q); 2574 atid->tid = i; 2575 atid->an = an; 2576 for (j = 0; j < ATH_TID_MAX_BUFS; j++) 2577 atid->tx_buf[j] = NULL; 2578 atid->baw_head = atid->baw_tail = 0; 2579 atid->paused = 0; 2580 atid->sched = 0; 2581 atid->hwq_depth = 0; 2582 atid->cleanup_inprogress = 0; 2583 if (i == IEEE80211_NONQOS_TID) 2584 atid->ac = WME_AC_BE; 2585 else 2586 atid->ac = TID_TO_WME_AC(i); 2587 } 2588} 2589 2590/* 2591 * Pause the current TID. This stops packets from being transmitted 2592 * on it. 2593 * 2594 * Since this is also called from upper layers as well as the driver, 2595 * it will get the TID lock. 2596 */ 2597static void 2598ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid) 2599{ 2600 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 2601 tid->paused++; 2602 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n", 2603 __func__, tid->paused); 2604 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]); 2605} 2606 2607/* 2608 * Unpause the current TID, and schedule it if needed. 2609 */ 2610static void 2611ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid) 2612{ 2613 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2614 2615 tid->paused--; 2616 2617 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n", 2618 __func__, tid->paused); 2619 2620 if (tid->paused || tid->axq_depth == 0) { 2621 return; 2622 } 2623 2624 ath_tx_tid_sched(sc, tid); 2625 /* Punt some frames to the hardware if needed */ 2626 //ath_txq_sched(sc, sc->sc_ac2q[tid->ac]); 2627 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask); 2628} 2629 2630/* 2631 * Free any packets currently pending in the software TX queue. 2632 * 2633 * This will be called when a node is being deleted. 2634 * 2635 * It can also be called on an active node during an interface 2636 * reset or state transition. 2637 * 2638 * (From Linux/reference): 2639 * 2640 * TODO: For frame(s) that are in the retry state, we will reuse the 2641 * sequence number(s) without setting the retry bit. The 2642 * alternative is to give up on these and BAR the receiver's window 2643 * forward. 2644 */ 2645static void 2646ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an, 2647 struct ath_tid *tid, ath_bufhead *bf_cq) 2648{ 2649 struct ath_buf *bf; 2650 struct ieee80211_tx_ampdu *tap; 2651 struct ieee80211_node *ni = &an->an_node; 2652 int t = 0; 2653 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2654 2655 tap = ath_tx_get_tx_tid(an, tid->tid); 2656 2657 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2658 2659 /* Walk the queue, free frames */ 2660 for (;;) { 2661 bf = TAILQ_FIRST(&tid->axq_q); 2662 if (bf == NULL) { 2663 break; 2664 } 2665 2666 if (t == 0) { 2667 device_printf(sc->sc_dev, 2668 "%s: node %p: bf=%p: addbaw=%d, dobaw=%d, " 2669 "seqno_assign=%d, seqno_required=%d, seqno=%d, retry=%d\n", 2670 __func__, ni, bf, 2671 bf->bf_state.bfs_addedbaw, 2672 bf->bf_state.bfs_dobaw, 2673 bf->bf_state.bfs_need_seqno, 2674 bf->bf_state.bfs_seqno_assigned, 2675 SEQNO(bf->bf_state.bfs_seqno), 2676 bf->bf_state.bfs_retries); 2677 device_printf(sc->sc_dev, 2678 "%s: node %p: bf=%p: tid txq_depth=%d hwq_depth=%d\n", 2679 __func__, ni, bf, 2680 tid->axq_depth, 2681 tid->hwq_depth); 2682 device_printf(sc->sc_dev, 2683 "%s: node %p: bf=%p: tid %d: txq_depth=%d, " 2684 "txq_aggr_depth=%d, sched=%d, paused=%d, " 2685 "hwq_depth=%d, incomp=%d, baw_head=%d, " 2686 "baw_tail=%d txa_start=%d, ni_txseqs=%d\n", 2687 __func__, ni, bf, tid->tid, txq->axq_depth, 2688 txq->axq_aggr_depth, tid->sched, tid->paused, 2689 tid->hwq_depth, tid->incomp, tid->baw_head, 2690 tid->baw_tail, tap == NULL ? -1 : tap->txa_start, 2691 ni->ni_txseqs[tid->tid]); 2692 2693 /* XXX Dump the frame, see what it is? */ 2694 ieee80211_dump_pkt(ni->ni_ic, 2695 mtod(bf->bf_m, const uint8_t *), 2696 bf->bf_m->m_len, 0, -1); 2697 2698 //t = 1; 2699 } 2700 2701 2702 /* 2703 * If the current TID is running AMPDU, update 2704 * the BAW. 2705 */ 2706 if (ath_tx_ampdu_running(sc, an, tid->tid) && 2707 bf->bf_state.bfs_dobaw) { 2708 /* 2709 * Only remove the frame from the BAW if it's 2710 * been transmitted at least once; this means 2711 * the frame was in the BAW to begin with. 2712 */ 2713 if (bf->bf_state.bfs_retries > 0) { 2714 ath_tx_update_baw(sc, an, tid, bf); 2715 bf->bf_state.bfs_dobaw = 0; 2716 } 2717 /* 2718 * This has become a non-fatal error now 2719 */ 2720 if (! bf->bf_state.bfs_addedbaw) 2721 device_printf(sc->sc_dev, 2722 "%s: wasn't added: seqno %d\n", 2723 __func__, SEQNO(bf->bf_state.bfs_seqno)); 2724 } 2725 ATH_TXQ_REMOVE(tid, bf, bf_list); 2726 TAILQ_INSERT_TAIL(bf_cq, bf, bf_list); 2727 } 2728 2729 /* 2730 * Now that it's completed, grab the TID lock and update 2731 * the sequence number and BAW window. 2732 * Because sequence numbers have been assigned to frames 2733 * that haven't been sent yet, it's entirely possible 2734 * we'll be called with some pending frames that have not 2735 * been transmitted. 2736 * 2737 * The cleaner solution is to do the sequence number allocation 2738 * when the packet is first transmitted - and thus the "retries" 2739 * check above would be enough to update the BAW/seqno. 2740 */ 2741 2742 /* But don't do it for non-QoS TIDs */ 2743 if (tap) { 2744#if 0 2745 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 2746 "%s: node %p: TID %d: sliding BAW left edge to %d\n", 2747 __func__, an, tid->tid, tap->txa_start); 2748#endif 2749 ni->ni_txseqs[tid->tid] = tap->txa_start; 2750 tid->baw_tail = tid->baw_head; 2751 } 2752} 2753 2754/* 2755 * Flush all software queued packets for the given node. 2756 * 2757 * This occurs when a completion handler frees the last buffer 2758 * for a node, and the node is thus freed. This causes the node 2759 * to be cleaned up, which ends up calling ath_tx_node_flush. 2760 */ 2761void 2762ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an) 2763{ 2764 int tid; 2765 ath_bufhead bf_cq; 2766 struct ath_buf *bf; 2767 2768 TAILQ_INIT(&bf_cq); 2769 2770 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 2771 struct ath_tid *atid = &an->an_tid[tid]; 2772 struct ath_txq *txq = sc->sc_ac2q[atid->ac]; 2773 2774 /* Remove this tid from the list of active tids */ 2775 ATH_TXQ_LOCK(txq); 2776 ath_tx_tid_unsched(sc, atid); 2777 2778 /* Free packets */ 2779 ath_tx_tid_drain(sc, an, atid, &bf_cq); 2780 ATH_TXQ_UNLOCK(txq); 2781 } 2782 2783 /* Handle completed frames */ 2784 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 2785 TAILQ_REMOVE(&bf_cq, bf, bf_list); 2786 ath_tx_default_comp(sc, bf, 0); 2787 } 2788} 2789 2790/* 2791 * Drain all the software TXQs currently with traffic queued. 2792 */ 2793void 2794ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq) 2795{ 2796 struct ath_tid *tid; 2797 ath_bufhead bf_cq; 2798 struct ath_buf *bf; 2799 2800 TAILQ_INIT(&bf_cq); 2801 ATH_TXQ_LOCK(txq); 2802 2803 /* 2804 * Iterate over all active tids for the given txq, 2805 * flushing and unsched'ing them 2806 */ 2807 while (! TAILQ_EMPTY(&txq->axq_tidq)) { 2808 tid = TAILQ_FIRST(&txq->axq_tidq); 2809 ath_tx_tid_drain(sc, tid->an, tid, &bf_cq); 2810 ath_tx_tid_unsched(sc, tid); 2811 } 2812 2813 ATH_TXQ_UNLOCK(txq); 2814 2815 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 2816 TAILQ_REMOVE(&bf_cq, bf, bf_list); 2817 ath_tx_default_comp(sc, bf, 0); 2818 } 2819} 2820 2821/* 2822 * Handle completion of non-aggregate session frames. 2823 */ 2824void 2825ath_tx_normal_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 2826{ 2827 struct ieee80211_node *ni = bf->bf_node; 2828 struct ath_node *an = ATH_NODE(ni); 2829 int tid = bf->bf_state.bfs_tid; 2830 struct ath_tid *atid = &an->an_tid[tid]; 2831 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 2832 2833 /* The TID state is protected behind the TXQ lock */ 2834 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 2835 2836 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: fail=%d, hwq_depth now %d\n", 2837 __func__, bf, fail, atid->hwq_depth - 1); 2838 2839 atid->hwq_depth--; 2840 if (atid->hwq_depth < 0) 2841 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 2842 __func__, atid->hwq_depth); 2843 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 2844 2845 /* 2846 * punt to rate control if we're not being cleaned up 2847 * during a hw queue drain and the frame wanted an ACK. 2848 */ 2849 if (fail == 0 && ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0)) 2850 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 2851 ts, bf->bf_state.bfs_pktlen, 2852 1, (ts->ts_status == 0) ? 0 : 1); 2853 2854 ath_tx_default_comp(sc, bf, fail); 2855} 2856 2857/* 2858 * Handle cleanup of aggregate session packets that aren't 2859 * an A-MPDU. 2860 * 2861 * There's no need to update the BAW here - the session is being 2862 * torn down. 2863 */ 2864static void 2865ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf) 2866{ 2867 struct ieee80211_node *ni = bf->bf_node; 2868 struct ath_node *an = ATH_NODE(ni); 2869 int tid = bf->bf_state.bfs_tid; 2870 struct ath_tid *atid = &an->an_tid[tid]; 2871 2872 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: TID %d: incomp=%d\n", 2873 __func__, tid, atid->incomp); 2874 2875 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 2876 atid->incomp--; 2877 if (atid->incomp == 0) { 2878 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 2879 "%s: TID %d: cleaned up! resume!\n", 2880 __func__, tid); 2881 atid->cleanup_inprogress = 0; 2882 ath_tx_tid_resume(sc, atid); 2883 } 2884 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 2885 2886 ath_tx_default_comp(sc, bf, 0); 2887} 2888 2889/* 2890 * Performs transmit side cleanup when TID changes from aggregated to 2891 * unaggregated. 2892 * 2893 * - Discard all retry frames from the s/w queue. 2894 * - Fix the tx completion function for all buffers in s/w queue. 2895 * - Count the number of unacked frames, and let transmit completion 2896 * handle it later. 2897 * 2898 * The caller is responsible for pausing the TID. 2899 */ 2900static void 2901ath_tx_cleanup(struct ath_softc *sc, struct ath_node *an, int tid) 2902{ 2903 struct ath_tid *atid = &an->an_tid[tid]; 2904 struct ieee80211_tx_ampdu *tap; 2905 struct ath_buf *bf, *bf_next; 2906 ath_bufhead bf_cq; 2907 2908 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 2909 "%s: TID %d: called\n", __func__, tid); 2910 2911 TAILQ_INIT(&bf_cq); 2912 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 2913 2914 /* 2915 * Update the frames in the software TX queue: 2916 * 2917 * + Discard retry frames in the queue 2918 * + Fix the completion function to be non-aggregate 2919 */ 2920 bf = TAILQ_FIRST(&atid->axq_q); 2921 while (bf) { 2922 if (bf->bf_state.bfs_isretried) { 2923 bf_next = TAILQ_NEXT(bf, bf_list); 2924 TAILQ_REMOVE(&atid->axq_q, bf, bf_list); 2925 atid->axq_depth--; 2926 if (bf->bf_state.bfs_dobaw) { 2927 ath_tx_update_baw(sc, an, atid, bf); 2928 if (! bf->bf_state.bfs_addedbaw) 2929 device_printf(sc->sc_dev, 2930 "%s: wasn't added: seqno %d\n", 2931 __func__, 2932 SEQNO(bf->bf_state.bfs_seqno)); 2933 } 2934 bf->bf_state.bfs_dobaw = 0; 2935 /* 2936 * Call the default completion handler with "fail" just 2937 * so upper levels are suitably notified about this. 2938 */ 2939 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 2940 bf = bf_next; 2941 continue; 2942 } 2943 /* Give these the default completion handler */ 2944 bf->bf_comp = ath_tx_normal_comp; 2945 bf = TAILQ_NEXT(bf, bf_list); 2946 } 2947 2948 /* The caller is required to pause the TID */ 2949#if 0 2950 /* Pause the TID */ 2951 ath_tx_tid_pause(sc, atid); 2952#endif 2953 2954 /* 2955 * Calculate what hardware-queued frames exist based 2956 * on the current BAW size. Ie, what frames have been 2957 * added to the TX hardware queue for this TID but 2958 * not yet ACKed. 2959 */ 2960 tap = ath_tx_get_tx_tid(an, tid); 2961 /* Need the lock - fiddling with BAW */ 2962 while (atid->baw_head != atid->baw_tail) { 2963 if (atid->tx_buf[atid->baw_head]) { 2964 atid->incomp++; 2965 atid->cleanup_inprogress = 1; 2966 atid->tx_buf[atid->baw_head] = NULL; 2967 } 2968 INCR(atid->baw_head, ATH_TID_MAX_BUFS); 2969 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 2970 } 2971 2972 /* 2973 * If cleanup is required, defer TID scheduling 2974 * until all the HW queued packets have been 2975 * sent. 2976 */ 2977 if (! atid->cleanup_inprogress) 2978 ath_tx_tid_resume(sc, atid); 2979 2980 if (atid->cleanup_inprogress) 2981 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 2982 "%s: TID %d: cleanup needed: %d packets\n", 2983 __func__, tid, atid->incomp); 2984 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 2985 2986 /* Handle completing frames and fail them */ 2987 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 2988 TAILQ_REMOVE(&bf_cq, bf, bf_list); 2989 ath_tx_default_comp(sc, bf, 1); 2990 } 2991} 2992 2993static void 2994ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) 2995{ 2996 struct ieee80211_frame *wh; 2997 2998 wh = mtod(bf->bf_m, struct ieee80211_frame *); 2999 /* Only update/resync if needed */ 3000 if (bf->bf_state.bfs_isretried == 0) { 3001 wh->i_fc[1] |= IEEE80211_FC1_RETRY; 3002 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3003 BUS_DMASYNC_PREWRITE); 3004 } 3005 sc->sc_stats.ast_tx_swretries++; 3006 bf->bf_state.bfs_isretried = 1; 3007 bf->bf_state.bfs_retries ++; 3008} 3009 3010static struct ath_buf * 3011ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an, 3012 struct ath_tid *tid, struct ath_buf *bf) 3013{ 3014 struct ath_buf *nbf; 3015 int error; 3016 3017 nbf = ath_buf_clone(sc, bf); 3018 3019#if 0 3020 device_printf(sc->sc_dev, "%s: ATH_BUF_BUSY; cloning\n", 3021 __func__); 3022#endif 3023 3024 if (nbf == NULL) { 3025 /* Failed to clone */ 3026 device_printf(sc->sc_dev, 3027 "%s: failed to clone a busy buffer\n", 3028 __func__); 3029 return NULL; 3030 } 3031 3032 /* Setup the dma for the new buffer */ 3033 error = ath_tx_dmasetup(sc, nbf, nbf->bf_m); 3034 if (error != 0) { 3035 device_printf(sc->sc_dev, 3036 "%s: failed to setup dma for clone\n", 3037 __func__); 3038 /* 3039 * Put this at the head of the list, not tail; 3040 * that way it doesn't interfere with the 3041 * busy buffer logic (which uses the tail of 3042 * the list.) 3043 */ 3044 ATH_TXBUF_LOCK(sc); 3045 TAILQ_INSERT_HEAD(&sc->sc_txbuf, nbf, bf_list); 3046 ATH_TXBUF_UNLOCK(sc); 3047 return NULL; 3048 } 3049 3050 /* Update BAW if required, before we free the original buf */ 3051 if (bf->bf_state.bfs_dobaw) 3052 ath_tx_switch_baw_buf(sc, an, tid, bf, nbf); 3053 3054 /* Free current buffer; return the older buffer */ 3055 bf->bf_m = NULL; 3056 bf->bf_node = NULL; 3057 ath_freebuf(sc, bf); 3058 return nbf; 3059} 3060 3061/* 3062 * Handle retrying an unaggregate frame in an aggregate 3063 * session. 3064 * 3065 * If too many retries occur, pause the TID, wait for 3066 * any further retransmits (as there's no reason why 3067 * non-aggregate frames in an aggregate session are 3068 * transmitted in-order; they just have to be in-BAW) 3069 * and then queue a BAR. 3070 */ 3071static void 3072ath_tx_aggr_retry_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3073{ 3074 struct ieee80211_node *ni = bf->bf_node; 3075 struct ath_node *an = ATH_NODE(ni); 3076 int tid = bf->bf_state.bfs_tid; 3077 struct ath_tid *atid = &an->an_tid[tid]; 3078 struct ieee80211_tx_ampdu *tap; 3079 int txseq; 3080 3081 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3082 3083 tap = ath_tx_get_tx_tid(an, tid); 3084 3085 /* 3086 * If the buffer is marked as busy, we can't directly 3087 * reuse it. Instead, try to clone the buffer. 3088 * If the clone is successful, recycle the old buffer. 3089 * If the clone is unsuccessful, set bfs_retries to max 3090 * to force the next bit of code to free the buffer 3091 * for us. 3092 */ 3093 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3094 (bf->bf_flags & ATH_BUF_BUSY)) { 3095 struct ath_buf *nbf; 3096 nbf = ath_tx_retry_clone(sc, an, atid, bf); 3097 if (nbf) 3098 /* bf has been freed at this point */ 3099 bf = nbf; 3100 else 3101 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3102 } 3103 3104 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3105 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3106 "%s: exceeded retries; seqno %d\n", 3107 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3108 sc->sc_stats.ast_tx_swretrymax++; 3109 3110 /* Update BAW anyway */ 3111 if (bf->bf_state.bfs_dobaw) { 3112 ath_tx_update_baw(sc, an, atid, bf); 3113 if (! bf->bf_state.bfs_addedbaw) 3114 device_printf(sc->sc_dev, 3115 "%s: wasn't added: seqno %d\n", 3116 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3117 } 3118 bf->bf_state.bfs_dobaw = 0; 3119 3120 /* Send BAR frame */ 3121 /* 3122 * This'll end up going into net80211 and back out 3123 * again, via ic->ic_raw_xmit(). 3124 */ 3125 txseq = tap->txa_start; 3126 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3127 3128 device_printf(sc->sc_dev, 3129 "%s: TID %d: send BAR; seq %d\n", __func__, tid, txseq); 3130 3131 /* XXX TODO: send BAR */ 3132 3133 /* Free buffer, bf is free after this call */ 3134 ath_tx_default_comp(sc, bf, 0); 3135 return; 3136 } 3137 3138 /* 3139 * This increments the retry counter as well as 3140 * sets the retry flag in the ath_buf and packet 3141 * body. 3142 */ 3143 ath_tx_set_retry(sc, bf); 3144 3145 /* 3146 * Insert this at the head of the queue, so it's 3147 * retried before any current/subsequent frames. 3148 */ 3149 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list); 3150 ath_tx_tid_sched(sc, atid); 3151 3152 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3153} 3154 3155/* 3156 * Common code for aggregate excessive retry/subframe retry. 3157 * If retrying, queues buffers to bf_q. If not, frees the 3158 * buffers. 3159 * 3160 * XXX should unify this with ath_tx_aggr_retry_unaggr() 3161 */ 3162static int 3163ath_tx_retry_subframe(struct ath_softc *sc, struct ath_buf *bf, 3164 ath_bufhead *bf_q) 3165{ 3166 struct ieee80211_node *ni = bf->bf_node; 3167 struct ath_node *an = ATH_NODE(ni); 3168 int tid = bf->bf_state.bfs_tid; 3169 struct ath_tid *atid = &an->an_tid[tid]; 3170 3171 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[atid->ac]); 3172 3173 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 3174 ath_hal_set11nburstduration(sc->sc_ah, bf->bf_desc, 0); 3175 /* ath_hal_set11n_virtualmorefrag(sc->sc_ah, bf->bf_desc, 0); */ 3176 3177 /* 3178 * If the buffer is marked as busy, we can't directly 3179 * reuse it. Instead, try to clone the buffer. 3180 * If the clone is successful, recycle the old buffer. 3181 * If the clone is unsuccessful, set bfs_retries to max 3182 * to force the next bit of code to free the buffer 3183 * for us. 3184 */ 3185 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3186 (bf->bf_flags & ATH_BUF_BUSY)) { 3187 struct ath_buf *nbf; 3188 nbf = ath_tx_retry_clone(sc, an, atid, bf); 3189 if (nbf) 3190 /* bf has been freed at this point */ 3191 bf = nbf; 3192 else 3193 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3194 } 3195 3196 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3197 sc->sc_stats.ast_tx_swretrymax++; 3198 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3199 "%s: max retries: seqno %d\n", 3200 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3201 ath_tx_update_baw(sc, an, atid, bf); 3202 if (! bf->bf_state.bfs_addedbaw) 3203 device_printf(sc->sc_dev, 3204 "%s: wasn't added: seqno %d\n", 3205 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3206 bf->bf_state.bfs_dobaw = 0; 3207 return 1; 3208 } 3209 3210 ath_tx_set_retry(sc, bf); 3211 bf->bf_next = NULL; /* Just to make sure */ 3212 3213 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 3214 return 0; 3215} 3216 3217/* 3218 * error pkt completion for an aggregate destination 3219 */ 3220static void 3221ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first, 3222 struct ath_tid *tid) 3223{ 3224 struct ieee80211_node *ni = bf_first->bf_node; 3225 struct ath_node *an = ATH_NODE(ni); 3226 struct ath_buf *bf_next, *bf; 3227 ath_bufhead bf_q; 3228 int drops = 0; 3229 struct ieee80211_tx_ampdu *tap; 3230 ath_bufhead bf_cq; 3231 3232 TAILQ_INIT(&bf_q); 3233 TAILQ_INIT(&bf_cq); 3234 3235 /* 3236 * Update rate control - all frames have failed. 3237 * 3238 * XXX use the length in the first frame in the series; 3239 * XXX just so things are consistent for now. 3240 */ 3241 ath_tx_update_ratectrl(sc, ni, bf_first->bf_state.bfs_rc, 3242 &bf_first->bf_status.ds_txstat, 3243 bf_first->bf_state.bfs_pktlen, 3244 bf_first->bf_state.bfs_nframes, bf_first->bf_state.bfs_nframes); 3245 3246 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 3247 tap = ath_tx_get_tx_tid(an, tid->tid); 3248 sc->sc_stats.ast_tx_aggr_failall++; 3249 3250 /* Retry all subframes */ 3251 bf = bf_first; 3252 while (bf) { 3253 bf_next = bf->bf_next; 3254 bf->bf_next = NULL; /* Remove it from the aggr list */ 3255 sc->sc_stats.ast_tx_aggr_fail++; 3256 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 3257 drops++; 3258 bf->bf_next = NULL; 3259 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3260 } 3261 bf = bf_next; 3262 } 3263 3264 /* Prepend all frames to the beginning of the queue */ 3265 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 3266 TAILQ_REMOVE(&bf_q, bf, bf_list); 3267 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 3268 } 3269 3270 ath_tx_tid_sched(sc, tid); 3271 3272 /* 3273 * send bar if we dropped any frames 3274 * 3275 * Keep the txq lock held for now, as we need to ensure 3276 * that ni_txseqs[] is consistent (as it's being updated 3277 * in the ifnet TX context or raw TX context.) 3278 */ 3279 if (drops) { 3280 int txseq = tap->txa_start; 3281 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]); 3282 device_printf(sc->sc_dev, 3283 "%s: TID %d: send BAR; seq %d\n", 3284 __func__, tid->tid, txseq); 3285 3286 /* XXX TODO: send BAR */ 3287 } else { 3288 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]); 3289 } 3290 3291 /* Complete frames which errored out */ 3292 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3293 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3294 ath_tx_default_comp(sc, bf, 0); 3295 } 3296} 3297 3298/* 3299 * Handle clean-up of packets from an aggregate list. 3300 * 3301 * There's no need to update the BAW here - the session is being 3302 * torn down. 3303 */ 3304static void 3305ath_tx_comp_cleanup_aggr(struct ath_softc *sc, struct ath_buf *bf_first) 3306{ 3307 struct ath_buf *bf, *bf_next; 3308 struct ieee80211_node *ni = bf_first->bf_node; 3309 struct ath_node *an = ATH_NODE(ni); 3310 int tid = bf_first->bf_state.bfs_tid; 3311 struct ath_tid *atid = &an->an_tid[tid]; 3312 3313 bf = bf_first; 3314 3315 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3316 3317 /* update incomp */ 3318 while (bf) { 3319 atid->incomp--; 3320 bf = bf->bf_next; 3321 } 3322 3323 if (atid->incomp == 0) { 3324 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3325 "%s: TID %d: cleaned up! resume!\n", 3326 __func__, tid); 3327 atid->cleanup_inprogress = 0; 3328 ath_tx_tid_resume(sc, atid); 3329 } 3330 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3331 3332 /* Handle frame completion */ 3333 while (bf) { 3334 bf_next = bf->bf_next; 3335 ath_tx_default_comp(sc, bf, 1); 3336 bf = bf_next; 3337 } 3338} 3339 3340/* 3341 * Handle completion of an set of aggregate frames. 3342 * 3343 * XXX for now, simply complete each sub-frame. 3344 * 3345 * Note: the completion handler is the last descriptor in the aggregate, 3346 * not the last descriptor in the first frame. 3347 */ 3348static void 3349ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first, 3350 int fail) 3351{ 3352 //struct ath_desc *ds = bf->bf_lastds; 3353 struct ieee80211_node *ni = bf_first->bf_node; 3354 struct ath_node *an = ATH_NODE(ni); 3355 int tid = bf_first->bf_state.bfs_tid; 3356 struct ath_tid *atid = &an->an_tid[tid]; 3357 struct ath_tx_status ts; 3358 struct ieee80211_tx_ampdu *tap; 3359 ath_bufhead bf_q; 3360 ath_bufhead bf_cq; 3361 int seq_st, tx_ok; 3362 int hasba, isaggr; 3363 uint32_t ba[2]; 3364 struct ath_buf *bf, *bf_next; 3365 int ba_index; 3366 int drops = 0; 3367 int nframes = 0, nbad = 0, nf; 3368 int pktlen; 3369 /* XXX there's too much on the stack? */ 3370 struct ath_rc_series rc[4]; 3371 int txseq; 3372 3373 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: called; hwq_depth=%d\n", 3374 __func__, atid->hwq_depth); 3375 3376 /* The TID state is kept behind the TXQ lock */ 3377 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3378 3379 atid->hwq_depth--; 3380 if (atid->hwq_depth < 0) 3381 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3382 __func__, atid->hwq_depth); 3383 3384 /* 3385 * Punt cleanup to the relevant function, not our problem now 3386 */ 3387 if (atid->cleanup_inprogress) { 3388 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3389 ath_tx_comp_cleanup_aggr(sc, bf_first); 3390 return; 3391 } 3392 3393 /* 3394 * Take a copy; this may be needed -after- bf_first 3395 * has been completed and freed. 3396 */ 3397 ts = bf_first->bf_status.ds_txstat; 3398 /* 3399 * XXX for now, use the first frame in the aggregate for 3400 * XXX rate control completion; it's at least consistent. 3401 */ 3402 pktlen = bf_first->bf_state.bfs_pktlen; 3403 3404 /* 3405 * handle errors first 3406 */ 3407 if (ts.ts_status & HAL_TXERR_XRETRY) { 3408 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3409 ath_tx_comp_aggr_error(sc, bf_first, atid); 3410 return; 3411 } 3412 3413 TAILQ_INIT(&bf_q); 3414 TAILQ_INIT(&bf_cq); 3415 tap = ath_tx_get_tx_tid(an, tid); 3416 3417 /* 3418 * extract starting sequence and block-ack bitmap 3419 */ 3420 /* XXX endian-ness of seq_st, ba? */ 3421 seq_st = ts.ts_seqnum; 3422 hasba = !! (ts.ts_flags & HAL_TX_BA); 3423 tx_ok = (ts.ts_status == 0); 3424 isaggr = bf_first->bf_state.bfs_aggr; 3425 ba[0] = ts.ts_ba_low; 3426 ba[1] = ts.ts_ba_high; 3427 3428 /* 3429 * Copy the TX completion status and the rate control 3430 * series from the first descriptor, as it may be freed 3431 * before the rate control code can get its grubby fingers 3432 * into things. 3433 */ 3434 memcpy(rc, bf_first->bf_state.bfs_rc, sizeof(rc)); 3435 3436 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3437 "%s: txa_start=%d, tx_ok=%d, status=%.8x, flags=%.8x, " 3438 "isaggr=%d, seq_st=%d, hasba=%d, ba=%.8x, %.8x\n", 3439 __func__, tap->txa_start, tx_ok, ts.ts_status, ts.ts_flags, 3440 isaggr, seq_st, hasba, ba[0], ba[1]); 3441 3442 /* Occasionally, the MAC sends a tx status for the wrong TID. */ 3443 if (tid != ts.ts_tid) { 3444 device_printf(sc->sc_dev, "%s: tid %d != hw tid %d\n", 3445 __func__, tid, ts.ts_tid); 3446 tx_ok = 0; 3447 } 3448 3449 /* AR5416 BA bug; this requires an interface reset */ 3450 if (isaggr && tx_ok && (! hasba)) { 3451 device_printf(sc->sc_dev, 3452 "%s: AR5416 bug: hasba=%d; txok=%d, isaggr=%d, " 3453 "seq_st=%d\n", 3454 __func__, hasba, tx_ok, isaggr, seq_st); 3455 /* XXX TODO: schedule an interface reset */ 3456 } 3457 3458 /* 3459 * Walk the list of frames, figure out which ones were correctly 3460 * sent and which weren't. 3461 */ 3462 bf = bf_first; 3463 nf = bf_first->bf_state.bfs_nframes; 3464 3465 /* bf_first is going to be invalid once this list is walked */ 3466 bf_first = NULL; 3467 3468 /* 3469 * Walk the list of completed frames and determine 3470 * which need to be completed and which need to be 3471 * retransmitted. 3472 * 3473 * For completed frames, the completion functions need 3474 * to be called at the end of this function as the last 3475 * node reference may free the node. 3476 * 3477 * Finally, since the TXQ lock can't be held during the 3478 * completion callback (to avoid lock recursion), 3479 * the completion calls have to be done outside of the 3480 * lock. 3481 */ 3482 while (bf) { 3483 nframes++; 3484 ba_index = ATH_BA_INDEX(seq_st, 3485 SEQNO(bf->bf_state.bfs_seqno)); 3486 bf_next = bf->bf_next; 3487 bf->bf_next = NULL; /* Remove it from the aggr list */ 3488 3489 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3490 "%s: checking bf=%p seqno=%d; ack=%d\n", 3491 __func__, bf, SEQNO(bf->bf_state.bfs_seqno), 3492 ATH_BA_ISSET(ba, ba_index)); 3493 3494 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) { 3495 sc->sc_stats.ast_tx_aggr_ok++; 3496 ath_tx_update_baw(sc, an, atid, bf); 3497 bf->bf_state.bfs_dobaw = 0; 3498 if (! bf->bf_state.bfs_addedbaw) 3499 device_printf(sc->sc_dev, 3500 "%s: wasn't added: seqno %d\n", 3501 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3502 bf->bf_next = NULL; 3503 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3504 } else { 3505 sc->sc_stats.ast_tx_aggr_fail++; 3506 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 3507 drops++; 3508 bf->bf_next = NULL; 3509 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3510 } 3511 nbad++; 3512 } 3513 bf = bf_next; 3514 } 3515 3516 /* 3517 * Now that the BAW updates have been done, unlock 3518 * 3519 * txseq is grabbed before the lock is released so we 3520 * have a consistent view of what -was- in the BAW. 3521 * Anything after this point will not yet have been 3522 * TXed. 3523 */ 3524 txseq = tap->txa_start; 3525 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3526 3527 if (nframes != nf) 3528 device_printf(sc->sc_dev, 3529 "%s: num frames seen=%d; bf nframes=%d\n", 3530 __func__, nframes, nf); 3531 3532 /* 3533 * Now we know how many frames were bad, call the rate 3534 * control code. 3535 */ 3536 if (fail == 0) 3537 ath_tx_update_ratectrl(sc, ni, rc, &ts, pktlen, nframes, 3538 nbad); 3539 3540 /* 3541 * send bar if we dropped any frames 3542 */ 3543 if (drops) { 3544 device_printf(sc->sc_dev, 3545 "%s: TID %d: send BAR; seq %d\n", __func__, tid, txseq); 3546 /* XXX TODO: send BAR */ 3547 } 3548 3549 /* Prepend all frames to the beginning of the queue */ 3550 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3551 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 3552 TAILQ_REMOVE(&bf_q, bf, bf_list); 3553 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list); 3554 } 3555 ath_tx_tid_sched(sc, atid); 3556 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3557 3558 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3559 "%s: txa_start now %d\n", __func__, tap->txa_start); 3560 3561 /* Do deferred completion */ 3562 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3563 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3564 ath_tx_default_comp(sc, bf, 0); 3565 } 3566} 3567 3568/* 3569 * Handle completion of unaggregated frames in an ADDBA 3570 * session. 3571 * 3572 * Fail is set to 1 if the entry is being freed via a call to 3573 * ath_tx_draintxq(). 3574 */ 3575static void 3576ath_tx_aggr_comp_unaggr(struct ath_softc *sc, struct ath_buf *bf, int fail) 3577{ 3578 struct ieee80211_node *ni = bf->bf_node; 3579 struct ath_node *an = ATH_NODE(ni); 3580 int tid = bf->bf_state.bfs_tid; 3581 struct ath_tid *atid = &an->an_tid[tid]; 3582 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3583 3584 /* 3585 * Update rate control status here, before we possibly 3586 * punt to retry or cleanup. 3587 * 3588 * Do it outside of the TXQ lock. 3589 */ 3590 if (fail == 0 && ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0)) 3591 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 3592 &bf->bf_status.ds_txstat, 3593 bf->bf_state.bfs_pktlen, 3594 1, (ts->ts_status == 0) ? 0 : 1); 3595 3596 /* 3597 * This is called early so atid->hwq_depth can be tracked. 3598 * This unfortunately means that it's released and regrabbed 3599 * during retry and cleanup. That's rather inefficient. 3600 */ 3601 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3602 3603 if (tid == IEEE80211_NONQOS_TID) 3604 device_printf(sc->sc_dev, "%s: TID=16!\n", __func__); 3605 3606 DPRINTF(sc, ATH_DEBUG_SW_TX, 3607 "%s: bf=%p: tid=%d, hwq_depth=%d, seqno=%d\n", 3608 __func__, bf, bf->bf_state.bfs_tid, atid->hwq_depth, 3609 SEQNO(bf->bf_state.bfs_seqno)); 3610 3611 atid->hwq_depth--; 3612 if (atid->hwq_depth < 0) 3613 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3614 __func__, atid->hwq_depth); 3615 3616 /* 3617 * If a cleanup is in progress, punt to comp_cleanup; 3618 * rather than handling it here. It's thus their 3619 * responsibility to clean up, call the completion 3620 * function in net80211, etc. 3621 */ 3622 if (atid->cleanup_inprogress) { 3623 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3624 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: cleanup_unaggr\n", 3625 __func__); 3626 ath_tx_comp_cleanup_unaggr(sc, bf); 3627 return; 3628 } 3629 3630 /* 3631 * Don't bother with the retry check if all frames 3632 * are being failed (eg during queue deletion.) 3633 */ 3634 if (fail == 0 && ts->ts_status & HAL_TXERR_XRETRY) { 3635 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3636 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: retry_unaggr\n", 3637 __func__); 3638 ath_tx_aggr_retry_unaggr(sc, bf); 3639 return; 3640 } 3641 3642 /* Success? Complete */ 3643 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: TID=%d, seqno %d\n", 3644 __func__, tid, SEQNO(bf->bf_state.bfs_seqno)); 3645 if (bf->bf_state.bfs_dobaw) { 3646 ath_tx_update_baw(sc, an, atid, bf); 3647 bf->bf_state.bfs_dobaw = 0; 3648 if (! bf->bf_state.bfs_addedbaw) 3649 device_printf(sc->sc_dev, 3650 "%s: wasn't added: seqno %d\n", 3651 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3652 } 3653 3654 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3655 3656 ath_tx_default_comp(sc, bf, fail); 3657 /* bf is freed at this point */ 3658} 3659 3660void 3661ath_tx_aggr_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3662{ 3663 if (bf->bf_state.bfs_aggr) 3664 ath_tx_aggr_comp_aggr(sc, bf, fail); 3665 else 3666 ath_tx_aggr_comp_unaggr(sc, bf, fail); 3667} 3668 3669/* 3670 * Schedule some packets from the given node/TID to the hardware. 3671 * 3672 * This is the aggregate version. 3673 */ 3674void 3675ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an, 3676 struct ath_tid *tid) 3677{ 3678 struct ath_buf *bf; 3679 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 3680 struct ieee80211_tx_ampdu *tap; 3681 struct ieee80211_node *ni = &an->an_node; 3682 ATH_AGGR_STATUS status; 3683 ath_bufhead bf_q; 3684 3685 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d\n", __func__, tid->tid); 3686 ATH_TXQ_LOCK_ASSERT(txq); 3687 3688 tap = ath_tx_get_tx_tid(an, tid->tid); 3689 3690 if (tid->tid == IEEE80211_NONQOS_TID) 3691 device_printf(sc->sc_dev, "%s: called for TID=NONQOS_TID?\n", 3692 __func__); 3693 3694 for (;;) { 3695 status = ATH_AGGR_DONE; 3696 3697 /* 3698 * If the upper layer has paused the TID, don't 3699 * queue any further packets. 3700 * 3701 * This can also occur from the completion task because 3702 * of packet loss; but as its serialised with this code, 3703 * it won't "appear" half way through queuing packets. 3704 */ 3705 if (tid->paused) 3706 break; 3707 3708 bf = TAILQ_FIRST(&tid->axq_q); 3709 if (bf == NULL) { 3710 break; 3711 } 3712 3713 /* 3714 * If the packet doesn't fall within the BAW (eg a NULL 3715 * data frame), schedule it directly; continue. 3716 */ 3717 if (! bf->bf_state.bfs_dobaw) { 3718 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3719 "%s: non-baw packet\n", 3720 __func__); 3721 ATH_TXQ_REMOVE(tid, bf, bf_list); 3722 bf->bf_state.bfs_aggr = 0; 3723 ath_tx_do_ratelookup(sc, bf); 3724 ath_tx_rate_fill_rcflags(sc, bf); 3725 ath_tx_set_rtscts(sc, bf); 3726 ath_tx_setds(sc, bf); 3727 ath_tx_chaindesclist(sc, bf); 3728 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 3729 ath_tx_set_ratectrl(sc, ni, bf); 3730 3731 sc->sc_aggr_stats.aggr_nonbaw_pkt++; 3732 3733 /* Queue the packet; continue */ 3734 goto queuepkt; 3735 } 3736 3737 TAILQ_INIT(&bf_q); 3738 3739 /* 3740 * Do a rate control lookup on the first frame in the 3741 * list. The rate control code needs that to occur 3742 * before it can determine whether to TX. 3743 * It's inaccurate because the rate control code doesn't 3744 * really "do" aggregate lookups, so it only considers 3745 * the size of the first frame. 3746 */ 3747 ath_tx_do_ratelookup(sc, bf); 3748 bf->bf_state.bfs_rc[3].rix = 0; 3749 bf->bf_state.bfs_rc[3].tries = 0; 3750 ath_tx_rate_fill_rcflags(sc, bf); 3751 3752 status = ath_tx_form_aggr(sc, an, tid, &bf_q); 3753 3754 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3755 "%s: ath_tx_form_aggr() status=%d\n", __func__, status); 3756 3757 /* 3758 * No frames to be picked up - out of BAW 3759 */ 3760 if (TAILQ_EMPTY(&bf_q)) 3761 break; 3762 3763 /* 3764 * This assumes that the descriptor list in the ath_bufhead 3765 * are already linked together via bf_next pointers. 3766 */ 3767 bf = TAILQ_FIRST(&bf_q); 3768 3769 /* 3770 * If it's the only frame send as non-aggregate 3771 * assume that ath_tx_form_aggr() has checked 3772 * whether it's in the BAW and added it appropriately. 3773 */ 3774 if (bf->bf_state.bfs_nframes == 1) { 3775 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3776 "%s: single-frame aggregate\n", __func__); 3777 bf->bf_state.bfs_aggr = 0; 3778 ath_tx_set_rtscts(sc, bf); 3779 ath_tx_setds(sc, bf); 3780 ath_tx_chaindesclist(sc, bf); 3781 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 3782 ath_tx_set_ratectrl(sc, ni, bf); 3783 if (status == ATH_AGGR_BAW_CLOSED) 3784 sc->sc_aggr_stats.aggr_baw_closed_single_pkt++; 3785 else 3786 sc->sc_aggr_stats.aggr_single_pkt++; 3787 } else { 3788 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3789 "%s: multi-frame aggregate: %d frames, " 3790 "length %d\n", 3791 __func__, bf->bf_state.bfs_nframes, 3792 bf->bf_state.bfs_al); 3793 bf->bf_state.bfs_aggr = 1; 3794 sc->sc_aggr_stats.aggr_pkts[bf->bf_state.bfs_nframes]++; 3795 sc->sc_aggr_stats.aggr_aggr_pkt++; 3796 3797 /* 3798 * Update the rate and rtscts information based on the 3799 * rate decision made by the rate control code; 3800 * the first frame in the aggregate needs it. 3801 */ 3802 ath_tx_set_rtscts(sc, bf); 3803 3804 /* 3805 * Setup the relevant descriptor fields 3806 * for aggregation. The first descriptor 3807 * already points to the rest in the chain. 3808 */ 3809 ath_tx_setds_11n(sc, bf); 3810 3811 /* 3812 * setup first desc with rate and aggr info 3813 */ 3814 ath_tx_set_ratectrl(sc, ni, bf); 3815 } 3816 queuepkt: 3817 //txq = bf->bf_state.bfs_txq; 3818 3819 /* Set completion handler, multi-frame aggregate or not */ 3820 bf->bf_comp = ath_tx_aggr_comp; 3821 3822 if (bf->bf_state.bfs_tid == IEEE80211_NONQOS_TID) 3823 device_printf(sc->sc_dev, "%s: TID=16?\n", __func__); 3824 3825 /* Punt to txq */ 3826 ath_tx_handoff(sc, txq, bf); 3827 3828 /* Track outstanding buffer count to hardware */ 3829 /* aggregates are "one" buffer */ 3830 tid->hwq_depth++; 3831 3832 /* 3833 * Break out if ath_tx_form_aggr() indicated 3834 * there can't be any further progress (eg BAW is full.) 3835 * Checking for an empty txq is done above. 3836 * 3837 * XXX locking on txq here? 3838 */ 3839 if (txq->axq_aggr_depth >= sc->sc_hwq_limit || 3840 status == ATH_AGGR_BAW_CLOSED) 3841 break; 3842 } 3843} 3844 3845/* 3846 * Schedule some packets from the given node/TID to the hardware. 3847 */ 3848void 3849ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an, 3850 struct ath_tid *tid) 3851{ 3852 struct ath_buf *bf; 3853 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 3854 struct ieee80211_node *ni = &an->an_node; 3855 3856 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: node %p: TID %d: called\n", 3857 __func__, an, tid->tid); 3858 3859 ATH_TXQ_LOCK_ASSERT(txq); 3860 3861 /* Check - is AMPDU pending or running? then print out something */ 3862 if (ath_tx_ampdu_pending(sc, an, tid->tid)) 3863 device_printf(sc->sc_dev, "%s: tid=%d, ampdu pending?\n", 3864 __func__, tid->tid); 3865 if (ath_tx_ampdu_running(sc, an, tid->tid)) 3866 device_printf(sc->sc_dev, "%s: tid=%d, ampdu running?\n", 3867 __func__, tid->tid); 3868 3869 for (;;) { 3870 3871 /* 3872 * If the upper layers have paused the TID, don't 3873 * queue any further packets. 3874 */ 3875 if (tid->paused) 3876 break; 3877 3878 bf = TAILQ_FIRST(&tid->axq_q); 3879 if (bf == NULL) { 3880 break; 3881 } 3882 3883 ATH_TXQ_REMOVE(tid, bf, bf_list); 3884 3885 KASSERT(txq == bf->bf_state.bfs_txq, ("txqs not equal!\n")); 3886 3887 /* Sanity check! */ 3888 if (tid->tid != bf->bf_state.bfs_tid) { 3889 device_printf(sc->sc_dev, "%s: bfs_tid %d !=" 3890 " tid %d\n", 3891 __func__, bf->bf_state.bfs_tid, tid->tid); 3892 } 3893 /* Normal completion handler */ 3894 bf->bf_comp = ath_tx_normal_comp; 3895 3896 /* Program descriptors + rate control */ 3897 ath_tx_do_ratelookup(sc, bf); 3898 ath_tx_rate_fill_rcflags(sc, bf); 3899 ath_tx_set_rtscts(sc, bf); 3900 ath_tx_setds(sc, bf); 3901 ath_tx_chaindesclist(sc, bf); 3902 ath_tx_set_ratectrl(sc, ni, bf); 3903 3904 /* Track outstanding buffer count to hardware */ 3905 /* aggregates are "one" buffer */ 3906 tid->hwq_depth++; 3907 3908 /* Punt to hardware or software txq */ 3909 ath_tx_handoff(sc, txq, bf); 3910 } 3911} 3912 3913/* 3914 * Schedule some packets to the given hardware queue. 3915 * 3916 * This function walks the list of TIDs (ie, ath_node TIDs 3917 * with queued traffic) and attempts to schedule traffic 3918 * from them. 3919 * 3920 * TID scheduling is implemented as a FIFO, with TIDs being 3921 * added to the end of the queue after some frames have been 3922 * scheduled. 3923 */ 3924void 3925ath_txq_sched(struct ath_softc *sc, struct ath_txq *txq) 3926{ 3927 struct ath_tid *tid, *next, *last; 3928 3929 ATH_TXQ_LOCK_ASSERT(txq); 3930 3931 /* 3932 * Don't schedule if the hardware queue is busy. 3933 * This (hopefully) gives some more time to aggregate 3934 * some packets in the aggregation queue. 3935 */ 3936 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 3937 sc->sc_aggr_stats.aggr_sched_nopkt++; 3938 return; 3939 } 3940 3941 last = TAILQ_LAST(&txq->axq_tidq, axq_t_s); 3942 3943 TAILQ_FOREACH_SAFE(tid, &txq->axq_tidq, axq_qelem, next) { 3944 /* 3945 * Suspend paused queues here; they'll be resumed 3946 * once the addba completes or times out. 3947 */ 3948 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, paused=%d\n", 3949 __func__, tid->tid, tid->paused); 3950 ath_tx_tid_unsched(sc, tid); 3951 if (tid->paused) { 3952 continue; 3953 } 3954 if (ath_tx_ampdu_running(sc, tid->an, tid->tid)) 3955 ath_tx_tid_hw_queue_aggr(sc, tid->an, tid); 3956 else 3957 ath_tx_tid_hw_queue_norm(sc, tid->an, tid); 3958 3959 /* Not empty? Re-schedule */ 3960 if (tid->axq_depth != 0) 3961 ath_tx_tid_sched(sc, tid); 3962 3963 /* Give the software queue time to aggregate more packets */ 3964 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 3965 break; 3966 } 3967 3968 /* 3969 * If this was the last entry on the original list, stop. 3970 * Otherwise nodes that have been rescheduled onto the end 3971 * of the TID FIFO list will just keep being rescheduled. 3972 */ 3973 if (tid == last) 3974 break; 3975 } 3976} 3977 3978/* 3979 * TX addba handling 3980 */ 3981 3982/* 3983 * Return net80211 TID struct pointer, or NULL for none 3984 */ 3985struct ieee80211_tx_ampdu * 3986ath_tx_get_tx_tid(struct ath_node *an, int tid) 3987{ 3988 struct ieee80211_node *ni = &an->an_node; 3989 struct ieee80211_tx_ampdu *tap; 3990 int ac; 3991 3992 if (tid == IEEE80211_NONQOS_TID) 3993 return NULL; 3994 3995 ac = TID_TO_WME_AC(tid); 3996 3997 tap = &ni->ni_tx_ampdu[ac]; 3998 return tap; 3999} 4000 4001/* 4002 * Is AMPDU-TX running? 4003 */ 4004static int 4005ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, int tid) 4006{ 4007 struct ieee80211_tx_ampdu *tap; 4008 4009 if (tid == IEEE80211_NONQOS_TID) 4010 return 0; 4011 4012 tap = ath_tx_get_tx_tid(an, tid); 4013 if (tap == NULL) 4014 return 0; /* Not valid; default to not running */ 4015 4016 return !! (tap->txa_flags & IEEE80211_AGGR_RUNNING); 4017} 4018 4019/* 4020 * Is AMPDU-TX negotiation pending? 4021 */ 4022static int 4023ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid) 4024{ 4025 struct ieee80211_tx_ampdu *tap; 4026 4027 if (tid == IEEE80211_NONQOS_TID) 4028 return 0; 4029 4030 tap = ath_tx_get_tx_tid(an, tid); 4031 if (tap == NULL) 4032 return 0; /* Not valid; default to not pending */ 4033 4034 return !! (tap->txa_flags & IEEE80211_AGGR_XCHGPEND); 4035} 4036 4037/* 4038 * Is AMPDU-TX pending for the given TID? 4039 */ 4040 4041 4042/* 4043 * Method to handle sending an ADDBA request. 4044 * 4045 * We tap this so the relevant flags can be set to pause the TID 4046 * whilst waiting for the response. 4047 * 4048 * XXX there's no timeout handler we can override? 4049 */ 4050int 4051ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4052 int dialogtoken, int baparamset, int batimeout) 4053{ 4054 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4055 int tid = WME_AC_TO_TID(tap->txa_ac); 4056 struct ath_node *an = ATH_NODE(ni); 4057 struct ath_tid *atid = &an->an_tid[tid]; 4058 4059 /* 4060 * XXX danger Will Robinson! 4061 * 4062 * Although the taskqueue may be running and scheduling some more 4063 * packets, these should all be _before_ the addba sequence number. 4064 * However, net80211 will keep self-assigning sequence numbers 4065 * until addba has been negotiated. 4066 * 4067 * In the past, these packets would be "paused" (which still works 4068 * fine, as they're being scheduled to the driver in the same 4069 * serialised method which is calling the addba request routine) 4070 * and when the aggregation session begins, they'll be dequeued 4071 * as aggregate packets and added to the BAW. However, now there's 4072 * a "bf->bf_state.bfs_dobaw" flag, and this isn't set for these 4073 * packets. Thus they never get included in the BAW tracking and 4074 * this can cause the initial burst of packets after the addba 4075 * negotiation to "hang", as they quickly fall outside the BAW. 4076 * 4077 * The "eventual" solution should be to tag these packets with 4078 * dobaw. Although net80211 has given us a sequence number, 4079 * it'll be "after" the left edge of the BAW and thus it'll 4080 * fall within it. 4081 */ 4082 ath_tx_tid_pause(sc, atid); 4083 4084 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4085 "%s: called; dialogtoken=%d, baparamset=%d, batimeout=%d\n", 4086 __func__, dialogtoken, baparamset, batimeout); 4087 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4088 "%s: txa_start=%d, ni_txseqs=%d\n", 4089 __func__, tap->txa_start, ni->ni_txseqs[tid]); 4090 4091 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 4092 batimeout); 4093} 4094 4095/* 4096 * Handle an ADDBA response. 4097 * 4098 * We unpause the queue so TX'ing can resume. 4099 * 4100 * Any packets TX'ed from this point should be "aggregate" (whether 4101 * aggregate or not) so the BAW is updated. 4102 * 4103 * Note! net80211 keeps self-assigning sequence numbers until 4104 * ampdu is negotiated. This means the initially-negotiated BAW left 4105 * edge won't match the ni->ni_txseq. 4106 * 4107 * So, being very dirty, the BAW left edge is "slid" here to match 4108 * ni->ni_txseq. 4109 * 4110 * What likely SHOULD happen is that all packets subsequent to the 4111 * addba request should be tagged as aggregate and queued as non-aggregate 4112 * frames; thus updating the BAW. For now though, I'll just slide the 4113 * window. 4114 */ 4115int 4116ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4117 int status, int code, int batimeout) 4118{ 4119 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4120 int tid = WME_AC_TO_TID(tap->txa_ac); 4121 struct ath_node *an = ATH_NODE(ni); 4122 struct ath_tid *atid = &an->an_tid[tid]; 4123 int r; 4124 4125 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4126 "%s: called; status=%d, code=%d, batimeout=%d\n", __func__, 4127 status, code, batimeout); 4128 4129 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4130 "%s: txa_start=%d, ni_txseqs=%d\n", 4131 __func__, tap->txa_start, ni->ni_txseqs[tid]); 4132 4133 /* 4134 * Call this first, so the interface flags get updated 4135 * before the TID is unpaused. Otherwise a race condition 4136 * exists where the unpaused TID still doesn't yet have 4137 * IEEE80211_AGGR_RUNNING set. 4138 */ 4139 r = sc->sc_addba_response(ni, tap, status, code, batimeout); 4140 4141 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4142 /* 4143 * XXX dirty! 4144 * Slide the BAW left edge to wherever net80211 left it for us. 4145 * Read above for more information. 4146 */ 4147 tap->txa_start = ni->ni_txseqs[tid]; 4148 ath_tx_tid_resume(sc, atid); 4149 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4150 return r; 4151} 4152 4153 4154/* 4155 * Stop ADDBA on a queue. 4156 */ 4157void 4158ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 4159{ 4160 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4161 int tid = WME_AC_TO_TID(tap->txa_ac); 4162 struct ath_node *an = ATH_NODE(ni); 4163 struct ath_tid *atid = &an->an_tid[tid]; 4164 4165 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: called\n", __func__); 4166 4167 /* Pause TID traffic early, so there aren't any races */ 4168 ath_tx_tid_pause(sc, atid); 4169 4170 /* There's no need to hold the TXQ lock here */ 4171 sc->sc_addba_stop(ni, tap); 4172 4173 /* 4174 * ath_tx_cleanup will resume the TID if possible, otherwise 4175 * it'll set the cleanup flag, and it'll be unpaused once 4176 * things have been cleaned up. 4177 */ 4178 ath_tx_cleanup(sc, an, tid); 4179} 4180 4181/* 4182 * Note: net80211 bar_timeout() doesn't call this function on BAR failure; 4183 * it simply tears down the aggregation session. Ew. 4184 * 4185 * It however will call ieee80211_ampdu_stop() which will call 4186 * ic->ic_addba_stop(). 4187 * 4188 * XXX This uses a hard-coded max BAR count value; the whole 4189 * XXX BAR TX success or failure should be better handled! 4190 */ 4191void 4192ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4193 int status) 4194{ 4195 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4196 int tid = WME_AC_TO_TID(tap->txa_ac); 4197 struct ath_node *an = ATH_NODE(ni); 4198 struct ath_tid *atid = &an->an_tid[tid]; 4199 int attempts = tap->txa_attempts; 4200 4201 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4202 "%s: called; status=%d\n", __func__, status); 4203 4204 /* Note: This may update the BAW details */ 4205 sc->sc_bar_response(ni, tap, status); 4206 4207 /* Unpause the TID */ 4208 /* 4209 * XXX if this is attempt=50, the TID will be downgraded 4210 * XXX to a non-aggregate session. So we must unpause the 4211 * XXX TID here or it'll never be done. 4212 */ 4213 if (status == 0 || attempts == 50) { 4214 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4215 ath_tx_tid_resume(sc, atid); 4216 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4217 } 4218} 4219 4220/* 4221 * This is called whenever the pending ADDBA request times out. 4222 * Unpause and reschedule the TID. 4223 */ 4224void 4225ath_addba_response_timeout(struct ieee80211_node *ni, 4226 struct ieee80211_tx_ampdu *tap) 4227{ 4228 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4229 int tid = WME_AC_TO_TID(tap->txa_ac); 4230 struct ath_node *an = ATH_NODE(ni); 4231 struct ath_tid *atid = &an->an_tid[tid]; 4232 4233 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4234 "%s: called; resuming\n", __func__); 4235 4236 /* Note: This updates the aggregate state to (again) pending */ 4237 sc->sc_addba_response_timeout(ni, tap); 4238 4239 /* Unpause the TID; which reschedules it */ 4240 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4241 ath_tx_tid_resume(sc, atid); 4242 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4243} 4244