if_ath_rx.c revision 242782
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_rx.c 242782 2012-11-08 18:11:31Z adrian $"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42/* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49#include "opt_ah.h" 50#include "opt_wlan.h" 51 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysctl.h> 55#include <sys/mbuf.h> 56#include <sys/malloc.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/kernel.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/errno.h> 63#include <sys/callout.h> 64#include <sys/bus.h> 65#include <sys/endian.h> 66#include <sys/kthread.h> 67#include <sys/taskqueue.h> 68#include <sys/priv.h> 69#include <sys/module.h> 70#include <sys/ktr.h> 71#include <sys/smp.h> /* for mp_ncpus */ 72 73#include <machine/bus.h> 74 75#include <net/if.h> 76#include <net/if_dl.h> 77#include <net/if_media.h> 78#include <net/if_types.h> 79#include <net/if_arp.h> 80#include <net/ethernet.h> 81#include <net/if_llc.h> 82 83#include <net80211/ieee80211_var.h> 84#include <net80211/ieee80211_regdomain.h> 85#ifdef IEEE80211_SUPPORT_SUPERG 86#include <net80211/ieee80211_superg.h> 87#endif 88#ifdef IEEE80211_SUPPORT_TDMA 89#include <net80211/ieee80211_tdma.h> 90#endif 91 92#include <net/bpf.h> 93 94#ifdef INET 95#include <netinet/in.h> 96#include <netinet/if_ether.h> 97#endif 98 99#include <dev/ath/if_athvar.h> 100#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101#include <dev/ath/ath_hal/ah_diagcodes.h> 102 103#include <dev/ath/if_ath_debug.h> 104#include <dev/ath/if_ath_misc.h> 105#include <dev/ath/if_ath_tsf.h> 106#include <dev/ath/if_ath_tx.h> 107#include <dev/ath/if_ath_sysctl.h> 108#include <dev/ath/if_ath_led.h> 109#include <dev/ath/if_ath_keycache.h> 110#include <dev/ath/if_ath_rx.h> 111#include <dev/ath/if_ath_beacon.h> 112#include <dev/ath/if_athdfs.h> 113 114#ifdef ATH_TX99_DIAG 115#include <dev/ath/ath_tx99/ath_tx99.h> 116#endif 117 118#ifdef ATH_DEBUG_ALQ 119#include <dev/ath/if_ath_alq.h> 120#endif 121 122/* 123 * Calculate the receive filter according to the 124 * operating mode and state: 125 * 126 * o always accept unicast, broadcast, and multicast traffic 127 * o accept PHY error frames when hardware doesn't have MIB support 128 * to count and we need them for ANI (sta mode only until recently) 129 * and we are not scanning (ANI is disabled) 130 * NB: older hal's add rx filter bits out of sight and we need to 131 * blindly preserve them 132 * o probe request frames are accepted only when operating in 133 * hostap, adhoc, mesh, or monitor modes 134 * o enable promiscuous mode 135 * - when in monitor mode 136 * - if interface marked PROMISC (assumes bridge setting is filtered) 137 * o accept beacons: 138 * - when operating in station mode for collecting rssi data when 139 * the station is otherwise quiet, or 140 * - when operating in adhoc mode so the 802.11 layer creates 141 * node table entries for peers, 142 * - when scanning 143 * - when doing s/w beacon miss (e.g. for ap+sta) 144 * - when operating in ap mode in 11g to detect overlapping bss that 145 * require protection 146 * - when operating in mesh mode to detect neighbors 147 * o accept control frames: 148 * - when in monitor mode 149 * XXX HT protection for 11n 150 */ 151u_int32_t 152ath_calcrxfilter(struct ath_softc *sc) 153{ 154 struct ifnet *ifp = sc->sc_ifp; 155 struct ieee80211com *ic = ifp->if_l2com; 156 u_int32_t rfilt; 157 158 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 159 if (!sc->sc_needmib && !sc->sc_scanning) 160 rfilt |= HAL_RX_FILTER_PHYERR; 161 if (ic->ic_opmode != IEEE80211_M_STA) 162 rfilt |= HAL_RX_FILTER_PROBEREQ; 163 /* XXX ic->ic_monvaps != 0? */ 164 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 165 rfilt |= HAL_RX_FILTER_PROM; 166 if (ic->ic_opmode == IEEE80211_M_STA || 167 ic->ic_opmode == IEEE80211_M_IBSS || 168 sc->sc_swbmiss || sc->sc_scanning) 169 rfilt |= HAL_RX_FILTER_BEACON; 170 /* 171 * NB: We don't recalculate the rx filter when 172 * ic_protmode changes; otherwise we could do 173 * this only when ic_protmode != NONE. 174 */ 175 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 176 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 177 rfilt |= HAL_RX_FILTER_BEACON; 178 179 /* 180 * Enable hardware PS-POLL RX only for hostap mode; 181 * STA mode sends PS-POLL frames but never 182 * receives them. 183 */ 184 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 185 0, NULL) == HAL_OK && 186 ic->ic_opmode == IEEE80211_M_HOSTAP) 187 rfilt |= HAL_RX_FILTER_PSPOLL; 188 189 if (sc->sc_nmeshvaps) { 190 rfilt |= HAL_RX_FILTER_BEACON; 191 if (sc->sc_hasbmatch) 192 rfilt |= HAL_RX_FILTER_BSSID; 193 else 194 rfilt |= HAL_RX_FILTER_PROM; 195 } 196 if (ic->ic_opmode == IEEE80211_M_MONITOR) 197 rfilt |= HAL_RX_FILTER_CONTROL; 198 199 /* 200 * Enable RX of compressed BAR frames only when doing 201 * 802.11n. Required for A-MPDU. 202 */ 203 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 204 rfilt |= HAL_RX_FILTER_COMPBAR; 205 206 /* 207 * Enable radar PHY errors if requested by the 208 * DFS module. 209 */ 210 if (sc->sc_dodfs) 211 rfilt |= HAL_RX_FILTER_PHYRADAR; 212 213 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 214 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 215 return rfilt; 216} 217 218static int 219ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 220{ 221 struct ath_hal *ah = sc->sc_ah; 222 int error; 223 struct mbuf *m; 224 struct ath_desc *ds; 225 226 m = bf->bf_m; 227 if (m == NULL) { 228 /* 229 * NB: by assigning a page to the rx dma buffer we 230 * implicitly satisfy the Atheros requirement that 231 * this buffer be cache-line-aligned and sized to be 232 * multiple of the cache line size. Not doing this 233 * causes weird stuff to happen (for the 5210 at least). 234 */ 235 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 236 if (m == NULL) { 237 DPRINTF(sc, ATH_DEBUG_ANY, 238 "%s: no mbuf/cluster\n", __func__); 239 sc->sc_stats.ast_rx_nombuf++; 240 return ENOMEM; 241 } 242 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 243 244 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 245 bf->bf_dmamap, m, 246 bf->bf_segs, &bf->bf_nseg, 247 BUS_DMA_NOWAIT); 248 if (error != 0) { 249 DPRINTF(sc, ATH_DEBUG_ANY, 250 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 251 __func__, error); 252 sc->sc_stats.ast_rx_busdma++; 253 m_freem(m); 254 return error; 255 } 256 KASSERT(bf->bf_nseg == 1, 257 ("multi-segment packet; nseg %u", bf->bf_nseg)); 258 bf->bf_m = m; 259 } 260 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 261 262 /* 263 * Setup descriptors. For receive we always terminate 264 * the descriptor list with a self-linked entry so we'll 265 * not get overrun under high load (as can happen with a 266 * 5212 when ANI processing enables PHY error frames). 267 * 268 * To insure the last descriptor is self-linked we create 269 * each descriptor as self-linked and add it to the end. As 270 * each additional descriptor is added the previous self-linked 271 * entry is ``fixed'' naturally. This should be safe even 272 * if DMA is happening. When processing RX interrupts we 273 * never remove/process the last, self-linked, entry on the 274 * descriptor list. This insures the hardware always has 275 * someplace to write a new frame. 276 */ 277 /* 278 * 11N: we can no longer afford to self link the last descriptor. 279 * MAC acknowledges BA status as long as it copies frames to host 280 * buffer (or rx fifo). This can incorrectly acknowledge packets 281 * to a sender if last desc is self-linked. 282 */ 283 ds = bf->bf_desc; 284 if (sc->sc_rxslink) 285 ds->ds_link = bf->bf_daddr; /* link to self */ 286 else 287 ds->ds_link = 0; /* terminate the list */ 288 ds->ds_data = bf->bf_segs[0].ds_addr; 289 ath_hal_setuprxdesc(ah, ds 290 , m->m_len /* buffer size */ 291 , 0 292 ); 293 294 if (sc->sc_rxlink != NULL) 295 *sc->sc_rxlink = bf->bf_daddr; 296 sc->sc_rxlink = &ds->ds_link; 297 return 0; 298} 299 300/* 301 * Intercept management frames to collect beacon rssi data 302 * and to do ibss merges. 303 */ 304void 305ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 306 int subtype, int rssi, int nf) 307{ 308 struct ieee80211vap *vap = ni->ni_vap; 309 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 310 311 /* 312 * Call up first so subsequent work can use information 313 * potentially stored in the node (e.g. for ibss merge). 314 */ 315 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 316 switch (subtype) { 317 case IEEE80211_FC0_SUBTYPE_BEACON: 318 /* update rssi statistics for use by the hal */ 319 /* XXX unlocked check against vap->iv_bss? */ 320 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 321 if (sc->sc_syncbeacon && 322 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 323 /* 324 * Resync beacon timers using the tsf of the beacon 325 * frame we just received. 326 */ 327 ath_beacon_config(sc, vap); 328 } 329 /* fall thru... */ 330 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 331 if (vap->iv_opmode == IEEE80211_M_IBSS && 332 vap->iv_state == IEEE80211_S_RUN) { 333 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 334 uint64_t tsf = ath_extend_tsf(sc, rstamp, 335 ath_hal_gettsf64(sc->sc_ah)); 336 /* 337 * Handle ibss merge as needed; check the tsf on the 338 * frame before attempting the merge. The 802.11 spec 339 * says the station should change it's bssid to match 340 * the oldest station with the same ssid, where oldest 341 * is determined by the tsf. Note that hardware 342 * reconfiguration happens through callback to 343 * ath_newstate as the state machine will go from 344 * RUN -> RUN when this happens. 345 */ 346 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 347 DPRINTF(sc, ATH_DEBUG_STATE, 348 "ibss merge, rstamp %u tsf %ju " 349 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 350 (uintmax_t)ni->ni_tstamp.tsf); 351 (void) ieee80211_ibss_merge(ni); 352 } 353 } 354 break; 355 } 356} 357 358#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 359static void 360ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m, 361 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 362{ 363 struct ath_softc *sc = ifp->if_softc; 364 365 /* Fill in the extension bitmap */ 366 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 367 368 /* Fill in the vendor header */ 369 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 370 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 371 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 372 373 /* XXX what should this be? */ 374 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 375 sc->sc_rx_th.wr_vh.vh_skip_len = 376 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 377 378 /* General version info */ 379 sc->sc_rx_th.wr_v.vh_version = 1; 380 381 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 382 383 /* rssi */ 384 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 385 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 386 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 387 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 388 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 389 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 390 391 /* evm */ 392 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 393 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 394 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 395 /* XXX TODO: extend this to include 3-stream EVM */ 396 397 /* phyerr info */ 398 if (rs->rs_status & HAL_RXERR_PHY) 399 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 400 else 401 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 402 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 403 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 404} 405#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 406 407static void 408ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 409 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 410{ 411#define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 412#define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 413#define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 414#define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 415 struct ath_softc *sc = ifp->if_softc; 416 const HAL_RATE_TABLE *rt; 417 uint8_t rix; 418 419 rt = sc->sc_currates; 420 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 421 rix = rt->rateCodeToIndex[rs->rs_rate]; 422 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 423 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 424#ifdef AH_SUPPORT_AR5416 425 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 426 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 427 struct ieee80211com *ic = ifp->if_l2com; 428 429 if ((rs->rs_flags & HAL_RX_2040) == 0) 430 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 431 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 432 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 433 else 434 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 435 if ((rs->rs_flags & HAL_RX_GI) == 0) 436 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 437 } 438#endif 439 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 440 if (rs->rs_status & HAL_RXERR_CRC) 441 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 442 /* XXX propagate other error flags from descriptor */ 443 sc->sc_rx_th.wr_antnoise = nf; 444 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 445 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 446#undef CHAN_HT 447#undef CHAN_HT20 448#undef CHAN_HT40U 449#undef CHAN_HT40D 450} 451 452static void 453ath_handle_micerror(struct ieee80211com *ic, 454 struct ieee80211_frame *wh, int keyix) 455{ 456 struct ieee80211_node *ni; 457 458 /* XXX recheck MIC to deal w/ chips that lie */ 459 /* XXX discard MIC errors on !data frames */ 460 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 461 if (ni != NULL) { 462 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 463 ieee80211_free_node(ni); 464 } 465} 466 467int 468ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 469 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf) 470{ 471 struct ath_hal *ah = sc->sc_ah; 472 struct mbuf *m = bf->bf_m; 473 uint64_t rstamp; 474 int len, type; 475 struct ifnet *ifp = sc->sc_ifp; 476 struct ieee80211com *ic = ifp->if_l2com; 477 struct ieee80211_node *ni; 478 int is_good = 0; 479 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 480 481 /* 482 * Calculate the correct 64 bit TSF given 483 * the TSF64 register value and rs_tstamp. 484 */ 485 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 486 487 /* These aren't specifically errors */ 488#ifdef AH_SUPPORT_AR5416 489 if (rs->rs_flags & HAL_RX_GI) 490 sc->sc_stats.ast_rx_halfgi++; 491 if (rs->rs_flags & HAL_RX_2040) 492 sc->sc_stats.ast_rx_2040++; 493 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 494 sc->sc_stats.ast_rx_pre_crc_err++; 495 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 496 sc->sc_stats.ast_rx_post_crc_err++; 497 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 498 sc->sc_stats.ast_rx_decrypt_busy_err++; 499 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 500 sc->sc_stats.ast_rx_hi_rx_chain++; 501#endif /* AH_SUPPORT_AR5416 */ 502 503 if (rs->rs_status != 0) { 504 if (rs->rs_status & HAL_RXERR_CRC) 505 sc->sc_stats.ast_rx_crcerr++; 506 if (rs->rs_status & HAL_RXERR_FIFO) 507 sc->sc_stats.ast_rx_fifoerr++; 508 if (rs->rs_status & HAL_RXERR_PHY) { 509 sc->sc_stats.ast_rx_phyerr++; 510 /* Process DFS radar events */ 511 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 512 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 513 /* Since we're touching the frame data, sync it */ 514 bus_dmamap_sync(sc->sc_dmat, 515 bf->bf_dmamap, 516 BUS_DMASYNC_POSTREAD); 517 /* Now pass it to the radar processing code */ 518 ath_dfs_process_phy_err(sc, m, rstamp, rs); 519 } 520 521 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 522 if (rs->rs_phyerr < 64) 523 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 524 goto rx_error; /* NB: don't count in ierrors */ 525 } 526 if (rs->rs_status & HAL_RXERR_DECRYPT) { 527 /* 528 * Decrypt error. If the error occurred 529 * because there was no hardware key, then 530 * let the frame through so the upper layers 531 * can process it. This is necessary for 5210 532 * parts which have no way to setup a ``clear'' 533 * key cache entry. 534 * 535 * XXX do key cache faulting 536 */ 537 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 538 goto rx_accept; 539 sc->sc_stats.ast_rx_badcrypt++; 540 } 541 /* 542 * Similar as above - if the failure was a keymiss 543 * just punt it up to the upper layers for now. 544 */ 545 if (rs->rs_status & HAL_RXERR_KEYMISS) { 546 sc->sc_stats.ast_rx_keymiss++; 547 goto rx_accept; 548 } 549 if (rs->rs_status & HAL_RXERR_MIC) { 550 sc->sc_stats.ast_rx_badmic++; 551 /* 552 * Do minimal work required to hand off 553 * the 802.11 header for notification. 554 */ 555 /* XXX frag's and qos frames */ 556 len = rs->rs_datalen; 557 if (len >= sizeof (struct ieee80211_frame)) { 558 bus_dmamap_sync(sc->sc_dmat, 559 bf->bf_dmamap, 560 BUS_DMASYNC_POSTREAD); 561 ath_handle_micerror(ic, 562 mtod(m, struct ieee80211_frame *), 563 sc->sc_splitmic ? 564 rs->rs_keyix-32 : rs->rs_keyix); 565 } 566 } 567 ifp->if_ierrors++; 568rx_error: 569 /* 570 * Cleanup any pending partial frame. 571 */ 572 if (re->m_rxpending != NULL) { 573 m_freem(re->m_rxpending); 574 re->m_rxpending = NULL; 575 } 576 /* 577 * When a tap is present pass error frames 578 * that have been requested. By default we 579 * pass decrypt+mic errors but others may be 580 * interesting (e.g. crc). 581 */ 582 if (ieee80211_radiotap_active(ic) && 583 (rs->rs_status & sc->sc_monpass)) { 584 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 585 BUS_DMASYNC_POSTREAD); 586 /* NB: bpf needs the mbuf length setup */ 587 len = rs->rs_datalen; 588 m->m_pkthdr.len = m->m_len = len; 589 bf->bf_m = NULL; 590 ath_rx_tap(ifp, m, rs, rstamp, nf); 591#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 592 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 593#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 594 ieee80211_radiotap_rx_all(ic, m); 595 m_freem(m); 596 } 597 /* XXX pass MIC errors up for s/w reclaculation */ 598 goto rx_next; 599 } 600rx_accept: 601 /* 602 * Sync and unmap the frame. At this point we're 603 * committed to passing the mbuf somewhere so clear 604 * bf_m; this means a new mbuf must be allocated 605 * when the rx descriptor is setup again to receive 606 * another frame. 607 */ 608 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 609 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 610 bf->bf_m = NULL; 611 612 len = rs->rs_datalen; 613 m->m_len = len; 614 615 if (rs->rs_more) { 616 /* 617 * Frame spans multiple descriptors; save 618 * it for the next completed descriptor, it 619 * will be used to construct a jumbogram. 620 */ 621 if (re->m_rxpending != NULL) { 622 /* NB: max frame size is currently 2 clusters */ 623 sc->sc_stats.ast_rx_toobig++; 624 m_freem(re->m_rxpending); 625 } 626 m->m_pkthdr.rcvif = ifp; 627 m->m_pkthdr.len = len; 628 re->m_rxpending = m; 629 goto rx_next; 630 } else if (re->m_rxpending != NULL) { 631 /* 632 * This is the second part of a jumbogram, 633 * chain it to the first mbuf, adjust the 634 * frame length, and clear the rxpending state. 635 */ 636 re->m_rxpending->m_next = m; 637 re->m_rxpending->m_pkthdr.len += len; 638 m = re->m_rxpending; 639 re->m_rxpending = NULL; 640 } else { 641 /* 642 * Normal single-descriptor receive; setup 643 * the rcvif and packet length. 644 */ 645 m->m_pkthdr.rcvif = ifp; 646 m->m_pkthdr.len = len; 647 } 648 649 /* 650 * Validate rs->rs_antenna. 651 * 652 * Some users w/ AR9285 NICs have reported crashes 653 * here because rs_antenna field is bogusly large. 654 * Let's enforce the maximum antenna limit of 8 655 * (and it shouldn't be hard coded, but that's a 656 * separate problem) and if there's an issue, print 657 * out an error and adjust rs_antenna to something 658 * sensible. 659 * 660 * This code should be removed once the actual 661 * root cause of the issue has been identified. 662 * For example, it may be that the rs_antenna 663 * field is only valid for the lsat frame of 664 * an aggregate and it just happens that it is 665 * "mostly" right. (This is a general statement - 666 * the majority of the statistics are only valid 667 * for the last frame in an aggregate. 668 */ 669 if (rs->rs_antenna > 7) { 670 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 671 __func__, rs->rs_antenna); 672#ifdef ATH_DEBUG 673 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 674#endif /* ATH_DEBUG */ 675 rs->rs_antenna = 0; /* XXX better than nothing */ 676 } 677 678 ifp->if_ipackets++; 679 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 680 681 /* 682 * Populate the rx status block. When there are bpf 683 * listeners we do the additional work to provide 684 * complete status. Otherwise we fill in only the 685 * material required by ieee80211_input. Note that 686 * noise setting is filled in above. 687 */ 688 if (ieee80211_radiotap_active(ic)) { 689 ath_rx_tap(ifp, m, rs, rstamp, nf); 690#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 691 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 692#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 693 } 694 695 /* 696 * From this point on we assume the frame is at least 697 * as large as ieee80211_frame_min; verify that. 698 */ 699 if (len < IEEE80211_MIN_LEN) { 700 if (!ieee80211_radiotap_active(ic)) { 701 DPRINTF(sc, ATH_DEBUG_RECV, 702 "%s: short packet %d\n", __func__, len); 703 sc->sc_stats.ast_rx_tooshort++; 704 } else { 705 /* NB: in particular this captures ack's */ 706 ieee80211_radiotap_rx_all(ic, m); 707 } 708 m_freem(m); 709 goto rx_next; 710 } 711 712 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 713 const HAL_RATE_TABLE *rt = sc->sc_currates; 714 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 715 716 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 717 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 718 } 719 720 m_adj(m, -IEEE80211_CRC_LEN); 721 722 /* 723 * Locate the node for sender, track state, and then 724 * pass the (referenced) node up to the 802.11 layer 725 * for its use. 726 */ 727 ni = ieee80211_find_rxnode_withkey(ic, 728 mtod(m, const struct ieee80211_frame_min *), 729 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 730 IEEE80211_KEYIX_NONE : rs->rs_keyix); 731 sc->sc_lastrs = rs; 732 733#ifdef AH_SUPPORT_AR5416 734 if (rs->rs_isaggr) 735 sc->sc_stats.ast_rx_agg++; 736#endif /* AH_SUPPORT_AR5416 */ 737 738 if (ni != NULL) { 739 /* 740 * Only punt packets for ampdu reorder processing for 741 * 11n nodes; net80211 enforces that M_AMPDU is only 742 * set for 11n nodes. 743 */ 744 if (ni->ni_flags & IEEE80211_NODE_HT) 745 m->m_flags |= M_AMPDU; 746 747 /* 748 * Sending station is known, dispatch directly. 749 */ 750 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 751 ieee80211_free_node(ni); 752 /* 753 * Arrange to update the last rx timestamp only for 754 * frames from our ap when operating in station mode. 755 * This assumes the rx key is always setup when 756 * associated. 757 */ 758 if (ic->ic_opmode == IEEE80211_M_STA && 759 rs->rs_keyix != HAL_RXKEYIX_INVALID) 760 is_good = 1; 761 } else { 762 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 763 } 764 /* 765 * Track rx rssi and do any rx antenna management. 766 */ 767 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 768 if (sc->sc_diversity) { 769 /* 770 * When using fast diversity, change the default rx 771 * antenna if diversity chooses the other antenna 3 772 * times in a row. 773 */ 774 if (sc->sc_defant != rs->rs_antenna) { 775 if (++sc->sc_rxotherant >= 3) 776 ath_setdefantenna(sc, rs->rs_antenna); 777 } else 778 sc->sc_rxotherant = 0; 779 } 780 781 /* Newer school diversity - kite specific for now */ 782 /* XXX perhaps migrate the normal diversity code to this? */ 783 if ((ah)->ah_rxAntCombDiversity) 784 (*(ah)->ah_rxAntCombDiversity)(ah, rs, ticks, hz); 785 786 if (sc->sc_softled) { 787 /* 788 * Blink for any data frame. Otherwise do a 789 * heartbeat-style blink when idle. The latter 790 * is mainly for station mode where we depend on 791 * periodic beacon frames to trigger the poll event. 792 */ 793 if (type == IEEE80211_FC0_TYPE_DATA) { 794 const HAL_RATE_TABLE *rt = sc->sc_currates; 795 ath_led_event(sc, 796 rt->rateCodeToIndex[rs->rs_rate]); 797 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 798 ath_led_event(sc, 0); 799 } 800rx_next: 801 return (is_good); 802} 803 804#define ATH_RX_MAX 128 805 806static void 807ath_rx_proc(struct ath_softc *sc, int resched) 808{ 809#define PA2DESC(_sc, _pa) \ 810 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 811 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 812 struct ath_buf *bf; 813 struct ifnet *ifp = sc->sc_ifp; 814 struct ath_hal *ah = sc->sc_ah; 815#ifdef IEEE80211_SUPPORT_SUPERG 816 struct ieee80211com *ic = ifp->if_l2com; 817#endif 818 struct ath_desc *ds; 819 struct ath_rx_status *rs; 820 struct mbuf *m; 821 int ngood; 822 HAL_STATUS status; 823 int16_t nf; 824 u_int64_t tsf; 825 int npkts = 0; 826 827 /* XXX we must not hold the ATH_LOCK here */ 828 ATH_UNLOCK_ASSERT(sc); 829 ATH_PCU_UNLOCK_ASSERT(sc); 830 831 ATH_PCU_LOCK(sc); 832 sc->sc_rxproc_cnt++; 833 ATH_PCU_UNLOCK(sc); 834 835 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 836 ngood = 0; 837 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 838 sc->sc_stats.ast_rx_noise = nf; 839 tsf = ath_hal_gettsf64(ah); 840 do { 841 /* 842 * Don't process too many packets at a time; give the 843 * TX thread time to also run - otherwise the TX 844 * latency can jump by quite a bit, causing throughput 845 * degredation. 846 */ 847 if (npkts >= ATH_RX_MAX) 848 break; 849 850 bf = TAILQ_FIRST(&sc->sc_rxbuf); 851 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 852 if_printf(ifp, "%s: no buffer!\n", __func__); 853 break; 854 } else if (bf == NULL) { 855 /* 856 * End of List: 857 * this can happen for non-self-linked RX chains 858 */ 859 sc->sc_stats.ast_rx_hitqueueend++; 860 break; 861 } 862 m = bf->bf_m; 863 if (m == NULL) { /* NB: shouldn't happen */ 864 /* 865 * If mbuf allocation failed previously there 866 * will be no mbuf; try again to re-populate it. 867 */ 868 /* XXX make debug msg */ 869 if_printf(ifp, "%s: no mbuf!\n", __func__); 870 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 871 goto rx_proc_next; 872 } 873 ds = bf->bf_desc; 874 if (ds->ds_link == bf->bf_daddr) { 875 /* NB: never process the self-linked entry at the end */ 876 sc->sc_stats.ast_rx_hitqueueend++; 877 break; 878 } 879 /* XXX sync descriptor memory */ 880 /* 881 * Must provide the virtual address of the current 882 * descriptor, the physical address, and the virtual 883 * address of the next descriptor in the h/w chain. 884 * This allows the HAL to look ahead to see if the 885 * hardware is done with a descriptor by checking the 886 * done bit in the following descriptor and the address 887 * of the current descriptor the DMA engine is working 888 * on. All this is necessary because of our use of 889 * a self-linked list to avoid rx overruns. 890 */ 891 rs = &bf->bf_status.ds_rxstat; 892 status = ath_hal_rxprocdesc(ah, ds, 893 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 894#ifdef ATH_DEBUG 895 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 896 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 897#endif 898 if (status == HAL_EINPROGRESS) 899 break; 900 901 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 902 npkts++; 903 904 /* 905 * Process a single frame. 906 */ 907 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf)) 908 ngood++; 909rx_proc_next: 910 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 911 } while (ath_rxbuf_init(sc, bf) == 0); 912 913 /* rx signal state monitoring */ 914 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 915 if (ngood) 916 sc->sc_lastrx = tsf; 917 918 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 919 /* Queue DFS tasklet if needed */ 920 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 921 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 922 923 /* 924 * Now that all the RX frames were handled that 925 * need to be handled, kick the PCU if there's 926 * been an RXEOL condition. 927 */ 928 ATH_PCU_LOCK(sc); 929 if (resched && sc->sc_kickpcu) { 930 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 931 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 932 __func__, npkts); 933 934 /* XXX rxslink? */ 935 /* 936 * XXX can we hold the PCU lock here? 937 * Are there any net80211 buffer calls involved? 938 */ 939 bf = TAILQ_FIRST(&sc->sc_rxbuf); 940 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 941 ath_hal_rxena(ah); /* enable recv descriptors */ 942 ath_mode_init(sc); /* set filters, etc. */ 943 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 944 945 ath_hal_intrset(ah, sc->sc_imask); 946 sc->sc_kickpcu = 0; 947 } 948 ATH_PCU_UNLOCK(sc); 949 950 /* XXX check this inside of IF_LOCK? */ 951 if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 952#ifdef IEEE80211_SUPPORT_SUPERG 953 ieee80211_ff_age_all(ic, 100); 954#endif 955 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 956 ath_tx_kick(sc); 957 } 958#undef PA2DESC 959 960 /* 961 * If we hit the maximum number of frames in this round, 962 * reschedule for another immediate pass. This gives 963 * the TX and TX completion routines time to run, which 964 * will reduce latency. 965 */ 966 if (npkts >= ATH_RX_MAX) 967 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 968 969 ATH_PCU_LOCK(sc); 970 sc->sc_rxproc_cnt--; 971 ATH_PCU_UNLOCK(sc); 972} 973 974#undef ATH_RX_MAX 975 976/* 977 * Only run the RX proc if it's not already running. 978 * Since this may get run as part of the reset/flush path, 979 * the task can't clash with an existing, running tasklet. 980 */ 981static void 982ath_legacy_rx_tasklet(void *arg, int npending) 983{ 984 struct ath_softc *sc = arg; 985 986 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 987 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 988 ATH_PCU_LOCK(sc); 989 if (sc->sc_inreset_cnt > 0) { 990 device_printf(sc->sc_dev, 991 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 992 ATH_PCU_UNLOCK(sc); 993 return; 994 } 995 ATH_PCU_UNLOCK(sc); 996 997 ath_rx_proc(sc, 1); 998} 999 1000static void 1001ath_legacy_flushrecv(struct ath_softc *sc) 1002{ 1003 1004 ath_rx_proc(sc, 0); 1005} 1006 1007/* 1008 * Disable the receive h/w in preparation for a reset. 1009 */ 1010static void 1011ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1012{ 1013#define PA2DESC(_sc, _pa) \ 1014 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1015 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1016 struct ath_hal *ah = sc->sc_ah; 1017 1018 ath_hal_stoppcurecv(ah); /* disable PCU */ 1019 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1020 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1021 /* 1022 * TODO: see if this particular DELAY() is required; it may be 1023 * masking some missing FIFO flush or DMA sync. 1024 */ 1025#if 0 1026 if (dodelay) 1027#endif 1028 DELAY(3000); /* 3ms is long enough for 1 frame */ 1029#ifdef ATH_DEBUG 1030 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1031 struct ath_buf *bf; 1032 u_int ix; 1033 1034 device_printf(sc->sc_dev, 1035 "%s: rx queue %p, link %p\n", 1036 __func__, 1037 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1038 sc->sc_rxlink); 1039 ix = 0; 1040 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1041 struct ath_desc *ds = bf->bf_desc; 1042 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1043 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1044 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1045 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1046 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1047 ix++; 1048 } 1049 } 1050#endif 1051 /* 1052 * Free both high/low RX pending, just in case. 1053 */ 1054 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1055 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1056 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1057 } 1058 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1059 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1060 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1061 } 1062 sc->sc_rxlink = NULL; /* just in case */ 1063#undef PA2DESC 1064} 1065 1066/* 1067 * Enable the receive h/w following a reset. 1068 */ 1069static int 1070ath_legacy_startrecv(struct ath_softc *sc) 1071{ 1072 struct ath_hal *ah = sc->sc_ah; 1073 struct ath_buf *bf; 1074 1075 sc->sc_rxlink = NULL; 1076 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1077 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1078 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1079 int error = ath_rxbuf_init(sc, bf); 1080 if (error != 0) { 1081 DPRINTF(sc, ATH_DEBUG_RECV, 1082 "%s: ath_rxbuf_init failed %d\n", 1083 __func__, error); 1084 return error; 1085 } 1086 } 1087 1088 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1089 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1090 ath_hal_rxena(ah); /* enable recv descriptors */ 1091 ath_mode_init(sc); /* set filters, etc. */ 1092 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1093 return 0; 1094} 1095 1096static int 1097ath_legacy_dma_rxsetup(struct ath_softc *sc) 1098{ 1099 int error; 1100 1101 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1102 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1103 if (error != 0) 1104 return (error); 1105 1106 return (0); 1107} 1108 1109static int 1110ath_legacy_dma_rxteardown(struct ath_softc *sc) 1111{ 1112 1113 if (sc->sc_rxdma.dd_desc_len != 0) 1114 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1115 return (0); 1116} 1117 1118void 1119ath_recv_setup_legacy(struct ath_softc *sc) 1120{ 1121 1122 /* Sensible legacy defaults */ 1123 sc->sc_rx_statuslen = 0; 1124 1125 sc->sc_rx.recv_start = ath_legacy_startrecv; 1126 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1127 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1128 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1129 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1130 1131 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1132 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1133} 1134