1138569Ssam/*- 2138569Ssam * Copyright (c) 2004 INRIA 3139530Ssam * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 4138569Ssam * All rights reserved. 5138569Ssam * 6138569Ssam * Redistribution and use in source and binary forms, with or without 7138569Ssam * modification, are permitted provided that the following conditions 8138569Ssam * are met: 9138569Ssam * 1. Redistributions of source code must retain the above copyright 10138569Ssam * notice, this list of conditions and the following disclaimer, 11138569Ssam without modification. 12138569Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13138569Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14138569Ssam * redistribution must be conditioned upon including a substantially 15138569Ssam * similar Disclaimer requirement for further binary redistribution. 16138569Ssam * 3. Neither the names of the above-listed copyright holders nor the names 17138569Ssam * of any contributors may be used to endorse or promote products derived 18138569Ssam * from this software without specific prior written permission. 19138569Ssam * 20138569Ssam * Alternatively, this software may be distributed under the terms of the 21138569Ssam * GNU General Public License ("GPL") version 2 as published by the Free 22138569Ssam * Software Foundation. 23138569Ssam * 24138569Ssam * NO WARRANTY 25138569Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26138569Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27138569Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 28138569Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 29138569Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 30138569Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31138569Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32138569Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 33138569Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34138569Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35138569Ssam * THE POSSIBILITY OF SUCH DAMAGES. 36138569Ssam * 37138569Ssam * $FreeBSD$ 38138569Ssam */ 39138569Ssam 40138569Ssam#ifndef _DEV_ATH_RATE_AMRR_H 41138569Ssam#define _DEV_ATH_RATE_AMRR_H 42138569Ssam 43138569Ssam/* per-device state */ 44138569Ssamstruct amrr_softc { 45138569Ssam struct ath_ratectrl arc; /* base state */ 46138569Ssam}; 47138569Ssam 48138569Ssam/* per-node state */ 49138569Ssamstruct amrr_node { 50178354Ssam int amn_rix; /* current rate index */ 51178354Ssam int amn_ticks; /* time of last update */ 52178354Ssam int amn_interval; /* update interval (ticks) */ 53138569Ssam /* AMRR statistics for this node */ 54138569Ssam u_int amn_tx_try0_cnt; 55138569Ssam u_int amn_tx_try1_cnt; 56138569Ssam u_int amn_tx_try2_cnt; 57138569Ssam u_int amn_tx_try3_cnt; 58138569Ssam u_int amn_tx_failure_cnt; 59138569Ssam /* AMRR algorithm state for this node */ 60138569Ssam u_int amn_success_threshold; 61138569Ssam u_int amn_success; 62138569Ssam u_int amn_recovery; 63138569Ssam /* rate index et al. */ 64138569Ssam u_int8_t amn_tx_rix0; /* series 0 rate index */ 65138569Ssam u_int8_t amn_tx_rate0; /* series 0 h/w rate */ 66138569Ssam u_int8_t amn_tx_rate1; /* series 1 h/w rate */ 67138569Ssam u_int8_t amn_tx_rate2; /* series 2 h/w rate */ 68138569Ssam u_int8_t amn_tx_rate3; /* series 3 h/w rate */ 69138569Ssam u_int8_t amn_tx_rate0sp; /* series 0 short preamble h/w rate */ 70138569Ssam u_int8_t amn_tx_rate1sp; /* series 1 short preamble h/w rate */ 71138569Ssam u_int8_t amn_tx_rate2sp; /* series 2 short preamble h/w rate */ 72138569Ssam u_int8_t amn_tx_rate3sp; /* series 3 short preamble h/w rate */ 73138569Ssam u_int8_t amn_tx_try0; /* series 0 try count */ 74138569Ssam u_int amn_tx_try1; /* series 1 try count */ 75138569Ssam u_int amn_tx_try2; /* series 2 try count */ 76138569Ssam u_int amn_tx_try3; /* series 3 try count */ 77138569Ssam}; 78138569Ssam#define ATH_NODE_AMRR(an) ((struct amrr_node *)&an[1]) 79138569Ssam#endif /* _DEV_ATH_RATE_AMRR_H */ 80