ar5416_attach.c revision 243840
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 243840 2012-12-03 23:45:06Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar5416/ar5416.ini" 32 33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 34 HAL_BOOL power_off); 35static void ar5416DisablePCIE(struct ath_hal *ah); 36static void ar5416WriteIni(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38static void ar5416SpurMitigate(struct ath_hal *ah, 39 const struct ieee80211_channel *chan); 40 41static void 42ar5416AniSetup(struct ath_hal *ah) 43{ 44 static const struct ar5212AniParams aniparams = { 45 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 46 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 47 .coarseHigh = { -14, -14, -14, -14, -12 }, 48 .coarseLow = { -64, -64, -64, -64, -70 }, 49 .firpwr = { -78, -78, -78, -78, -80 }, 50 .maxSpurImmunityLevel = 7, 51 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 52 .maxFirstepLevel = 2, /* levels 0..2 */ 53 .firstep = { 0, 4, 8 }, 54 .ofdmTrigHigh = 500, 55 .ofdmTrigLow = 200, 56 .cckTrigHigh = 200, 57 .cckTrigLow = 100, 58 .rssiThrHigh = 40, 59 .rssiThrLow = 7, 60 .period = 100, 61 }; 62 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 63 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 64 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 65} 66 67/* 68 * AR5416 doesn't do OLC or temperature compensation. 69 */ 70static void 71ar5416olcInit(struct ath_hal *ah) 72{ 73} 74 75static void 76ar5416olcTempCompensation(struct ath_hal *ah) 77{ 78} 79 80/* 81 * Attach for an AR5416 part. 82 */ 83void 84ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 85 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 86{ 87 struct ath_hal_5212 *ahp; 88 struct ath_hal *ah; 89 90 ahp = &ahp5416->ah_5212; 91 ar5212InitState(ahp, devid, sc, st, sh, status); 92 ah = &ahp->ah_priv.h; 93 94 /* override 5212 methods for our needs */ 95 ah->ah_magic = AR5416_MAGIC; 96 ah->ah_getRateTable = ar5416GetRateTable; 97 ah->ah_detach = ar5416Detach; 98 99 /* Reset functions */ 100 ah->ah_reset = ar5416Reset; 101 ah->ah_phyDisable = ar5416PhyDisable; 102 ah->ah_disable = ar5416Disable; 103 ah->ah_configPCIE = ar5416ConfigPCIE; 104 ah->ah_disablePCIE = ar5416DisablePCIE; 105 ah->ah_perCalibration = ar5416PerCalibration; 106 ah->ah_perCalibrationN = ar5416PerCalibrationN, 107 ah->ah_resetCalValid = ar5416ResetCalValid, 108 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 109 ah->ah_setTxPower = ar5416SetTransmitPower; 110 ah->ah_setBoardValues = ar5416SetBoardValues; 111 112 /* Transmit functions */ 113 ah->ah_stopTxDma = ar5416StopTxDma; 114 ah->ah_setupTxDesc = ar5416SetupTxDesc; 115 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 116 ah->ah_fillTxDesc = ar5416FillTxDesc; 117 ah->ah_procTxDesc = ar5416ProcTxDesc; 118 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 119 ah->ah_setupTxQueue = ar5416SetupTxQueue; 120 ah->ah_resetTxQueue = ar5416ResetTxQueue; 121 122 /* Receive Functions */ 123 ah->ah_getRxFilter = ar5416GetRxFilter; 124 ah->ah_setRxFilter = ar5416SetRxFilter; 125 ah->ah_stopDmaReceive = ar5416StopDmaReceive; 126 ah->ah_startPcuReceive = ar5416StartPcuReceive; 127 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 128 ah->ah_setupRxDesc = ar5416SetupRxDesc; 129 ah->ah_procRxDesc = ar5416ProcRxDesc; 130 ah->ah_rxMonitor = ar5416RxMonitor; 131 ah->ah_aniPoll = ar5416AniPoll; 132 ah->ah_procMibEvent = ar5416ProcessMibIntr; 133 134 /* Misc Functions */ 135 ah->ah_getCapability = ar5416GetCapability; 136 ah->ah_setCapability = ar5416SetCapability; 137 ah->ah_getDiagState = ar5416GetDiagState; 138 ah->ah_setLedState = ar5416SetLedState; 139 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 140 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 141 ah->ah_gpioGet = ar5416GpioGet; 142 ah->ah_gpioSet = ar5416GpioSet; 143 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 144 ah->ah_getTsf64 = ar5416GetTsf64; 145 ah->ah_setTsf64 = ar5416SetTsf64; 146 ah->ah_resetTsf = ar5416ResetTsf; 147 ah->ah_getRfGain = ar5416GetRfgain; 148 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 149 ah->ah_setDecompMask = ar5416SetDecompMask; 150 ah->ah_setCoverageClass = ar5416SetCoverageClass; 151 ah->ah_setQuiet = ar5416SetQuiet; 152 ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts; 153 154 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 155 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 156 157 /* DFS Functions */ 158 ah->ah_enableDfs = ar5416EnableDfs; 159 ah->ah_getDfsThresh = ar5416GetDfsThresh; 160 ah->ah_getDfsDefaultThresh = ar5416GetDfsDefaultThresh; 161 ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 162 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 163 164 /* Power Management Functions */ 165 ah->ah_setPowerMode = ar5416SetPowerMode; 166 167 /* Beacon Management Functions */ 168 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 169 ah->ah_beaconInit = ar5416BeaconInit; 170 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 171 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 172 ah->ah_getNextTBTT = ar5416GetNextTBTT; 173 174 /* 802.11n Functions */ 175 ah->ah_chainTxDesc = ar5416ChainTxDesc; 176 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 177 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 178 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 179 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 180 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 181 ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 182 ah->ah_clr11nAggr = ar5416Clr11nAggr; 183 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 184 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 185 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 186 ah->ah_get11nRxClear = ar5416Get11nRxClear; 187 ah->ah_set11nRxClear = ar5416Set11nRxClear; 188 189 /* Interrupt functions */ 190 ah->ah_isInterruptPending = ar5416IsInterruptPending; 191 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 192 ah->ah_setInterrupts = ar5416SetInterrupts; 193 194 /* Bluetooth Coexistence functions */ 195 ah->ah_btCoexSetInfo = ar5416SetBTCoexInfo; 196 ah->ah_btCoexSetConfig = ar5416BTCoexConfig; 197 ah->ah_btCoexSetQcuThresh = ar5416BTCoexSetQcuThresh; 198 ah->ah_btCoexSetWeights = ar5416BTCoexSetWeights; 199 ah->ah_btCoexSetBmissThresh = ar5416BTCoexSetupBmissThresh; 200 ah->ah_btcoexSetParameter = ar5416BTCoexSetParameter; 201 ah->ah_btCoexDisable = ar5416BTCoexDisable; 202 ah->ah_btCoexEnable = ar5416BTCoexEnable; 203 204 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 205 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 206#ifdef AH_SUPPORT_WRITE_EEPROM 207 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 208#endif 209 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 210 211 /* Internal ops */ 212 AH5416(ah)->ah_writeIni = ar5416WriteIni; 213 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 214 215 /* Internal baseband ops */ 216 AH5416(ah)->ah_initPLL = ar5416InitPLL; 217 218 /* Internal calibration ops */ 219 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 220 221 /* Internal TX power control related operations */ 222 AH5416(ah)->ah_olcInit = ar5416olcInit; 223 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 224 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 225 226 /* 227 * Start by setting all Owl devices to 2x2 228 */ 229 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 230 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 231 232 /* Enable all ANI functions to begin with */ 233 AH5416(ah)->ah_ani_function = 0xffffffff; 234 235 /* Set overridable ANI methods */ 236 AH5212(ah)->ah_aniControl = ar5416AniControl; 237} 238 239uint32_t 240ar5416GetRadioRev(struct ath_hal *ah) 241{ 242 uint32_t val; 243 int i; 244 245 /* Read Radio Chip Rev Extract */ 246 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 247 for (i = 0; i < 8; i++) 248 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 249 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 250 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 251 return ath_hal_reverseBits(val, 8); 252} 253 254/* 255 * Attach for an AR5416 part. 256 */ 257static struct ath_hal * 258ar5416Attach(uint16_t devid, HAL_SOFTC sc, 259 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 260 HAL_STATUS *status) 261{ 262 struct ath_hal_5416 *ahp5416; 263 struct ath_hal_5212 *ahp; 264 struct ath_hal *ah; 265 uint32_t val; 266 HAL_STATUS ecode; 267 HAL_BOOL rfStatus; 268 269 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 270 __func__, sc, (void*) st, (void*) sh); 271 272 /* NB: memory is returned zero'd */ 273 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 274 /* extra space for Owl 2.1/2.2 WAR */ 275 sizeof(ar5416Addac) 276 ); 277 if (ahp5416 == AH_NULL) { 278 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 279 "%s: cannot allocate memory for state block\n", __func__); 280 *status = HAL_ENOMEM; 281 return AH_NULL; 282 } 283 ar5416InitState(ahp5416, devid, sc, st, sh, status); 284 ahp = &ahp5416->ah_5212; 285 ah = &ahp->ah_priv.h; 286 287 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 288 /* reset chip */ 289 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 290 ecode = HAL_EIO; 291 goto bad; 292 } 293 294 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 295 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 296 ecode = HAL_EIO; 297 goto bad; 298 } 299 /* Read Revisions from Chips before taking out of reset */ 300 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 301 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 302 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 303 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 304 305 /* setup common ini data; rf backends handle remainder */ 306 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 307 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 308 309 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 310 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 311 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 312 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 313 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 314 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 315 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 316 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 317 318 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 319 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 320 struct ini { 321 uint32_t *data; /* NB: !const */ 322 int rows, cols; 323 }; 324 /* override CLKDRV value */ 325 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 326 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 327 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 328 } 329 330 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 331 ar5416AttachPCIE(ah); 332 333 ecode = ath_hal_v14EepromAttach(ah); 334 if (ecode != HAL_OK) 335 goto bad; 336 337 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 338 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 339 __func__); 340 ecode = HAL_EIO; 341 goto bad; 342 } 343 344 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 345 346 if (!ar5212ChipTest(ah)) { 347 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 348 __func__); 349 ecode = HAL_ESELFTEST; 350 goto bad; 351 } 352 353 /* 354 * Set correct Baseband to analog shift 355 * setting to access analog chips. 356 */ 357 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 358 359 /* Read Radio Chip Rev Extract */ 360 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 361 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 362 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 363 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 364 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 365 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 366 break; 367 default: 368 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 369 /* 370 * When RF_Silen is used the analog chip is reset. 371 * So when the system boots with radio switch off 372 * the RF chip rev reads back as zero and we need 373 * to use the mac+phy revs to set the radio rev. 374 */ 375 AH_PRIVATE(ah)->ah_analog5GhzRev = 376 AR_RAD5133_SREV_MAJOR; 377 break; 378 } 379 /* NB: silently accept anything in release code per Atheros */ 380#ifdef AH_DEBUG 381 HALDEBUG(ah, HAL_DEBUG_ANY, 382 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 383 "this driver\n", __func__, 384 AH_PRIVATE(ah)->ah_analog5GhzRev); 385 ecode = HAL_ENOTSUPP; 386 goto bad; 387#endif 388 } 389 390 /* 391 * Got everything we need now to setup the capabilities. 392 */ 393 if (!ar5416FillCapabilityInfo(ah)) { 394 ecode = HAL_EEREAD; 395 goto bad; 396 } 397 398 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 399 if (ecode != HAL_OK) { 400 HALDEBUG(ah, HAL_DEBUG_ANY, 401 "%s: error getting mac address from EEPROM\n", __func__); 402 goto bad; 403 } 404 /* XXX How about the serial number ? */ 405 /* Read Reg Domain */ 406 AH_PRIVATE(ah)->ah_currentRD = 407 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 408 AH_PRIVATE(ah)->ah_currentRDext = 409 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 410 411 /* 412 * ah_miscMode is populated by ar5416FillCapabilityInfo() 413 * starting from griffin. Set here to make sure that 414 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 415 * placed into hardware. 416 */ 417 if (ahp->ah_miscMode != 0) 418 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 419 420 rfStatus = ar2133RfAttach(ah, &ecode); 421 if (!rfStatus) { 422 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 423 __func__, ecode); 424 goto bad; 425 } 426 427 ar5416AniSetup(ah); /* Anti Noise Immunity */ 428 429 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 430 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 431 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 432 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 433 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 434 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 435 436 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 437 438 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 439 440 return ah; 441bad: 442 if (ahp) 443 ar5416Detach((struct ath_hal *) ahp); 444 if (status) 445 *status = ecode; 446 return AH_NULL; 447} 448 449void 450ar5416Detach(struct ath_hal *ah) 451{ 452 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 453 454 HALASSERT(ah != AH_NULL); 455 HALASSERT(ah->ah_magic == AR5416_MAGIC); 456 457 /* Make sure that chip is awake before writing to it */ 458 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 459 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 460 "%s: failed to wake up chip\n", 461 __func__); 462 463 ar5416AniDetach(ah); 464 ar5212RfDetach(ah); 465 ah->ah_disable(ah); 466 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 467 ath_hal_eepromDetach(ah); 468 ath_hal_free(ah); 469} 470 471void 472ar5416AttachPCIE(struct ath_hal *ah) 473{ 474 if (AH_PRIVATE(ah)->ah_ispcie) 475 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 476 else 477 ath_hal_disablePCIE(ah); 478} 479 480static void 481ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 482{ 483 484 /* This is only applicable for AR5418 (AR5416 PCIe) */ 485 if (! AH_PRIVATE(ah)->ah_ispcie) 486 return; 487 488 if (! restore) { 489 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 490 OS_DELAY(1000); 491 } 492 493 if (power_off) { /* Power-off */ 494 /* clear bit 19 to disable L1 */ 495 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 496 } else { /* Power-on */ 497 /* Set default WAR values for Owl */ 498 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 499 500 /* set bit 19 to allow forcing of pcie core into L1 state */ 501 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 502 } 503} 504 505/* 506 * Disable PCIe PHY if PCIe isn't used. 507 */ 508static void 509ar5416DisablePCIE(struct ath_hal *ah) 510{ 511 512 /* PCIe? Don't */ 513 if (AH_PRIVATE(ah)->ah_ispcie) 514 return; 515 516 /* .. Only applicable for AR5416v2 or later */ 517 if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah))) 518 return; 519 520 OS_REG_WRITE_BUFFER_ENABLE(ah); 521 522 /* 523 * Disable the PCIe PHY. 524 */ 525 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 526 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 527 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 528 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 529 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 530 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 531 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 532 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 533 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 534 535 /* Load the new settings */ 536 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 537 538 OS_REG_WRITE_BUFFER_FLUSH(ah); 539 OS_REG_WRITE_BUFFER_DISABLE(ah); 540} 541 542static void 543ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 544{ 545 u_int modesIndex, freqIndex; 546 int regWrites = 0; 547 548 /* Setup the indices for the next set of register array writes */ 549 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 550 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 551 freqIndex = 2; 552 if (IEEE80211_IS_CHAN_HT40(chan)) 553 modesIndex = 3; 554 else if (IEEE80211_IS_CHAN_108G(chan)) 555 modesIndex = 5; 556 else 557 modesIndex = 4; 558 } else { 559 freqIndex = 1; 560 if (IEEE80211_IS_CHAN_HT40(chan) || 561 IEEE80211_IS_CHAN_TURBO(chan)) 562 modesIndex = 2; 563 else 564 modesIndex = 1; 565 } 566 567 /* Set correct Baseband to analog shift setting to access analog chips. */ 568 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 569 570 /* 571 * Write addac shifts 572 */ 573 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 574 575 /* NB: only required for Sowl */ 576 if (AR_SREV_SOWL(ah)) 577 ar5416EepromSetAddac(ah, chan); 578 579 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 580 regWrites); 581 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 582 583 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 584 modesIndex, regWrites); 585 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 586 1, regWrites); 587 588 /* XXX updated regWrites? */ 589 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 590} 591 592/* 593 * Convert to baseband spur frequency given input channel frequency 594 * and compute register settings below. 595 */ 596 597static void 598ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 599{ 600 uint16_t freq = ath_hal_gethwchannel(ah, chan); 601 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 602 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 603 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 604 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 605 static const int inc[4] = { 0, 100, 0, 0 }; 606 607 int bb_spur = AR_NO_SPUR; 608 int bin, cur_bin; 609 int spur_freq_sd; 610 int spur_delta_phase; 611 int denominator; 612 int upper, lower, cur_vit_mask; 613 int tmp, new; 614 int i; 615 616 int8_t mask_m[123]; 617 int8_t mask_p[123]; 618 int8_t mask_amt; 619 int tmp_mask; 620 int cur_bb_spur; 621 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 622 623 OS_MEMZERO(mask_m, sizeof(mask_m)); 624 OS_MEMZERO(mask_p, sizeof(mask_p)); 625 626 /* 627 * Need to verify range +/- 9.5 for static ht20, otherwise spur 628 * is out-of-band and can be ignored. 629 */ 630 /* XXX ath9k changes */ 631 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 632 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 633 if (AR_NO_SPUR == cur_bb_spur) 634 break; 635 cur_bb_spur = cur_bb_spur - (freq * 10); 636 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 637 bb_spur = cur_bb_spur; 638 break; 639 } 640 } 641 if (AR_NO_SPUR == bb_spur) 642 return; 643 644 bin = bb_spur * 32; 645 646 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 647 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 648 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 649 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 650 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 651 652 OS_REG_WRITE_BUFFER_ENABLE(ah); 653 654 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 655 656 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 657 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 658 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 659 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 660 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 661 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 662 /* 663 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 664 * config, no offset for HT20. 665 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 666 * /80 for dyn2040. 667 */ 668 spur_delta_phase = ((bb_spur * 524288) / 100) & 669 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 670 /* 671 * in 11A mode the denominator of spur_freq_sd should be 40 and 672 * it should be 44 in 11G 673 */ 674 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 675 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 676 677 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 678 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 679 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 680 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 681 682 683 /* 684 * ============================================ 685 * pilot mask 1 [31:0] = +6..-26, no 0 bin 686 * pilot mask 2 [19:0] = +26..+7 687 * 688 * channel mask 1 [31:0] = +6..-26, no 0 bin 689 * channel mask 2 [19:0] = +26..+7 690 */ 691 //cur_bin = -26; 692 cur_bin = -6000; 693 upper = bin + 100; 694 lower = bin - 100; 695 696 for (i = 0; i < 4; i++) { 697 int pilot_mask = 0; 698 int chan_mask = 0; 699 int bp = 0; 700 for (bp = 0; bp < 30; bp++) { 701 if ((cur_bin > lower) && (cur_bin < upper)) { 702 pilot_mask = pilot_mask | 0x1 << bp; 703 chan_mask = chan_mask | 0x1 << bp; 704 } 705 cur_bin += 100; 706 } 707 cur_bin += inc[i]; 708 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 709 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 710 } 711 712 /* ================================================= 713 * viterbi mask 1 based on channel magnitude 714 * four levels 0-3 715 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 716 * [1 2 2 1] for -9.6 or [1 2 1] for +16 717 * - enable_mask_ppm, all bins move with freq 718 * 719 * - mask_select, 8 bits for rates (reg 67,0x990c) 720 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 721 * choose which mask to use mask or mask2 722 */ 723 724 /* 725 * viterbi mask 2 2nd set for per data rate puncturing 726 * four levels 0-3 727 * - mask_select, 8 bits for rates (reg 67) 728 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 729 * [1 2 2 1] for -9.6 or [1 2 1] for +16 730 */ 731 cur_vit_mask = 6100; 732 upper = bin + 120; 733 lower = bin - 120; 734 735 for (i = 0; i < 123; i++) { 736 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 737 if ((abs(cur_vit_mask - bin)) < 75) { 738 mask_amt = 1; 739 } else { 740 mask_amt = 0; 741 } 742 if (cur_vit_mask < 0) { 743 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 744 } else { 745 mask_p[cur_vit_mask / 100] = mask_amt; 746 } 747 } 748 cur_vit_mask -= 100; 749 } 750 751 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 752 | (mask_m[48] << 26) | (mask_m[49] << 24) 753 | (mask_m[50] << 22) | (mask_m[51] << 20) 754 | (mask_m[52] << 18) | (mask_m[53] << 16) 755 | (mask_m[54] << 14) | (mask_m[55] << 12) 756 | (mask_m[56] << 10) | (mask_m[57] << 8) 757 | (mask_m[58] << 6) | (mask_m[59] << 4) 758 | (mask_m[60] << 2) | (mask_m[61] << 0); 759 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 760 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 761 762 tmp_mask = (mask_m[31] << 28) 763 | (mask_m[32] << 26) | (mask_m[33] << 24) 764 | (mask_m[34] << 22) | (mask_m[35] << 20) 765 | (mask_m[36] << 18) | (mask_m[37] << 16) 766 | (mask_m[48] << 14) | (mask_m[39] << 12) 767 | (mask_m[40] << 10) | (mask_m[41] << 8) 768 | (mask_m[42] << 6) | (mask_m[43] << 4) 769 | (mask_m[44] << 2) | (mask_m[45] << 0); 770 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 771 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 772 773 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 774 | (mask_m[18] << 26) | (mask_m[18] << 24) 775 | (mask_m[20] << 22) | (mask_m[20] << 20) 776 | (mask_m[22] << 18) | (mask_m[22] << 16) 777 | (mask_m[24] << 14) | (mask_m[24] << 12) 778 | (mask_m[25] << 10) | (mask_m[26] << 8) 779 | (mask_m[27] << 6) | (mask_m[28] << 4) 780 | (mask_m[29] << 2) | (mask_m[30] << 0); 781 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 782 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 783 784 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 785 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 786 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 787 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 788 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 789 | (mask_m[10] << 10) | (mask_m[11] << 8) 790 | (mask_m[12] << 6) | (mask_m[13] << 4) 791 | (mask_m[14] << 2) | (mask_m[15] << 0); 792 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 793 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 794 795 tmp_mask = (mask_p[15] << 28) 796 | (mask_p[14] << 26) | (mask_p[13] << 24) 797 | (mask_p[12] << 22) | (mask_p[11] << 20) 798 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 799 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 800 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 801 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 802 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 803 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 804 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 805 806 tmp_mask = (mask_p[30] << 28) 807 | (mask_p[29] << 26) | (mask_p[28] << 24) 808 | (mask_p[27] << 22) | (mask_p[26] << 20) 809 | (mask_p[25] << 18) | (mask_p[24] << 16) 810 | (mask_p[23] << 14) | (mask_p[22] << 12) 811 | (mask_p[21] << 10) | (mask_p[20] << 8) 812 | (mask_p[19] << 6) | (mask_p[18] << 4) 813 | (mask_p[17] << 2) | (mask_p[16] << 0); 814 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 815 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 816 817 tmp_mask = (mask_p[45] << 28) 818 | (mask_p[44] << 26) | (mask_p[43] << 24) 819 | (mask_p[42] << 22) | (mask_p[41] << 20) 820 | (mask_p[40] << 18) | (mask_p[39] << 16) 821 | (mask_p[38] << 14) | (mask_p[37] << 12) 822 | (mask_p[36] << 10) | (mask_p[35] << 8) 823 | (mask_p[34] << 6) | (mask_p[33] << 4) 824 | (mask_p[32] << 2) | (mask_p[31] << 0); 825 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 826 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 827 828 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 829 | (mask_p[59] << 26) | (mask_p[58] << 24) 830 | (mask_p[57] << 22) | (mask_p[56] << 20) 831 | (mask_p[55] << 18) | (mask_p[54] << 16) 832 | (mask_p[53] << 14) | (mask_p[52] << 12) 833 | (mask_p[51] << 10) | (mask_p[50] << 8) 834 | (mask_p[49] << 6) | (mask_p[48] << 4) 835 | (mask_p[47] << 2) | (mask_p[46] << 0); 836 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 837 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 838 839 OS_REG_WRITE_BUFFER_FLUSH(ah); 840 OS_REG_WRITE_BUFFER_DISABLE(ah); 841} 842 843/* 844 * Fill all software cached or static hardware state information. 845 * Return failure if capabilities are to come from EEPROM and 846 * cannot be read. 847 */ 848HAL_BOOL 849ar5416FillCapabilityInfo(struct ath_hal *ah) 850{ 851 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 852 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 853 uint16_t val; 854 855 /* Construct wireless mode from EEPROM */ 856 pCap->halWirelessModes = 0; 857 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 858 pCap->halWirelessModes |= HAL_MODE_11A 859 | HAL_MODE_11NA_HT20 860 | HAL_MODE_11NA_HT40PLUS 861 | HAL_MODE_11NA_HT40MINUS 862 ; 863 } 864 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 865 pCap->halWirelessModes |= HAL_MODE_11G 866 | HAL_MODE_11NG_HT20 867 | HAL_MODE_11NG_HT40PLUS 868 | HAL_MODE_11NG_HT40MINUS 869 ; 870 pCap->halWirelessModes |= HAL_MODE_11A 871 | HAL_MODE_11NA_HT20 872 | HAL_MODE_11NA_HT40PLUS 873 | HAL_MODE_11NA_HT40MINUS 874 ; 875 } 876 877 pCap->halLow2GhzChan = 2312; 878 pCap->halHigh2GhzChan = 2732; 879 880 pCap->halLow5GhzChan = 4915; 881 pCap->halHigh5GhzChan = 6100; 882 883 pCap->halCipherCkipSupport = AH_FALSE; 884 pCap->halCipherTkipSupport = AH_TRUE; 885 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 886 887 pCap->halMicCkipSupport = AH_FALSE; 888 pCap->halMicTkipSupport = AH_TRUE; 889 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 890 /* 891 * Starting with Griffin TX+RX mic keys can be combined 892 * in one key cache slot. 893 */ 894 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 895 pCap->halChanSpreadSupport = AH_TRUE; 896 pCap->halSleepAfterBeaconBroken = AH_TRUE; 897 898 pCap->halCompressSupport = AH_FALSE; 899 pCap->halBurstSupport = AH_TRUE; 900 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 901 pCap->halChapTuningSupport = AH_TRUE; 902 pCap->halTurboPrimeSupport = AH_TRUE; 903 904 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 905 906 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 907 pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 908 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 909 pCap->halVEOLSupport = AH_TRUE; 910 pCap->halBssIdMaskSupport = AH_TRUE; 911 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 912 pCap->halTsfAddSupport = AH_TRUE; 913 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 914 915 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 916 pCap->halTotalQueues = val; 917 else 918 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 919 920 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 921 pCap->halKeyCacheSize = val; 922 else 923 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 924 925 /* XXX Which chips? */ 926 pCap->halChanHalfRate = AH_TRUE; 927 pCap->halChanQuarterRate = AH_TRUE; 928 929 pCap->halTstampPrecision = 32; 930 pCap->halHwPhyCounterSupport = AH_TRUE; 931 pCap->halIntrMask = HAL_INT_COMMON 932 | HAL_INT_RX 933 | HAL_INT_TX 934 | HAL_INT_FATAL 935 | HAL_INT_BNR 936 | HAL_INT_BMISC 937 | HAL_INT_DTIMSYNC 938 | HAL_INT_TSFOOR 939 | HAL_INT_CST 940 | HAL_INT_GTT 941 ; 942 943 pCap->halFastCCSupport = AH_TRUE; 944 pCap->halNumGpioPins = 14; 945 pCap->halWowSupport = AH_FALSE; 946 pCap->halWowMatchPatternExact = AH_FALSE; 947 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 948 pCap->halAutoSleepSupport = AH_FALSE; 949 pCap->hal4kbSplitTransSupport = AH_TRUE; 950 /* Disable this so Block-ACK works correctly */ 951 pCap->halHasRxSelfLinkedTail = AH_FALSE; 952#if 0 /* XXX not yet */ 953 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 954 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 955#endif 956 pCap->halHTSupport = AH_TRUE; 957 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 958 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 959 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 960 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 961 pCap->halTxStreams = 2; 962 pCap->halRxStreams = 2; 963 964 /* 965 * If the TX or RX chainmask has less than 2 chains active, 966 * mark it as a 1-stream device for the relevant stream. 967 */ 968 if (owl_get_ntxchains(pCap->halTxChainMask) == 1) 969 pCap->halTxStreams = 1; 970 /* XXX Eww */ 971 if (owl_get_ntxchains(pCap->halRxChainMask) == 1) 972 pCap->halRxStreams = 1; 973 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 974 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 975 pCap->halForcePpmSupport = AH_TRUE; 976 pCap->halEnhancedPmSupport = AH_TRUE; 977 pCap->halBssidMatchSupport = AH_TRUE; 978 pCap->halGTTSupport = AH_TRUE; 979 pCap->halCSTSupport = AH_TRUE; 980 pCap->halEnhancedDfsSupport = AH_FALSE; 981 /* Hardware supports 32 bit TSF values in the RX descriptor */ 982 pCap->halHasLongRxDescTsf = AH_TRUE; 983 /* 984 * BB Read WAR: this is only for AR5008/AR9001 NICs 985 * It is also set individually in the AR91xx attach functions. 986 */ 987 if (AR_SREV_OWL(ah)) 988 pCap->halHasBBReadWar = AH_TRUE; 989 990 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 991 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 992 /* NB: enabled by default */ 993 ahpriv->ah_rfkillEnabled = AH_TRUE; 994 pCap->halRfSilentSupport = AH_TRUE; 995 } 996 997 /* 998 * The MAC will mark frames as RXed if there's a descriptor 999 * to write them to. So if it hits a self-linked final descriptor, 1000 * it'll keep ACKing frames even though they're being silently 1001 * dropped. Thus, this particular feature of the driver can't 1002 * be used for 802.11n devices. 1003 */ 1004 ahpriv->ah_rxornIsFatal = AH_FALSE; 1005 1006 /* 1007 * If it's a PCI NIC, ask the HAL OS layer to serialise 1008 * register access, or SMP machines may cause the hardware 1009 * to hang. This is applicable to AR5416 and AR9220; I'm not 1010 * sure about AR9160 or AR9227. 1011 */ 1012 if (! AH_PRIVATE(ah)->ah_ispcie) 1013 pCap->halSerialiseRegWar = 1; 1014 1015 return AH_TRUE; 1016} 1017 1018static const char* 1019ar5416Probe(uint16_t vendorid, uint16_t devid) 1020{ 1021 if (vendorid == ATHEROS_VENDOR_ID) { 1022 if (devid == AR5416_DEVID_PCI) 1023 return "Atheros 5416"; 1024 if (devid == AR5416_DEVID_PCIE) 1025 return "Atheros 5418"; 1026 } 1027 return AH_NULL; 1028} 1029AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 1030