ar5416_attach.c revision 243424
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17188970Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 243424 2012-11-23 05:32:24Z adrian $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25189747Ssam#include "ah_eeprom_v14.h" 26189747Ssam 27185377Ssam#include "ar5416/ar5416.h" 28185377Ssam#include "ar5416/ar5416reg.h" 29185377Ssam#include "ar5416/ar5416phy.h" 30185377Ssam 31185377Ssam#include "ar5416/ar5416.ini" 32185377Ssam 33235972Sadrianstatic void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 34235972Sadrian HAL_BOOL power_off); 35235957Sadrianstatic void ar5416DisablePCIE(struct ath_hal *ah); 36189747Ssamstatic void ar5416WriteIni(struct ath_hal *ah, 37189747Ssam const struct ieee80211_channel *chan); 38189747Ssamstatic void ar5416SpurMitigate(struct ath_hal *ah, 39189747Ssam const struct ieee80211_channel *chan); 40188979Ssam 41185377Ssamstatic void 42185377Ssamar5416AniSetup(struct ath_hal *ah) 43185377Ssam{ 44185377Ssam static const struct ar5212AniParams aniparams = { 45185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 46185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 47185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 48185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 49185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 50242408Sadrian .maxSpurImmunityLevel = 7, 51242408Sadrian .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 52185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 53185377Ssam .firstep = { 0, 4, 8 }, 54185377Ssam .ofdmTrigHigh = 500, 55185377Ssam .ofdmTrigLow = 200, 56185377Ssam .cckTrigHigh = 200, 57185377Ssam .cckTrigLow = 100, 58185377Ssam .rssiThrHigh = 40, 59185377Ssam .rssiThrLow = 7, 60185377Ssam .period = 100, 61185377Ssam }; 62219979Sadrian /* NB: disable ANI noise immmunity for reliable RIFS rx */ 63222276Sadrian AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 64242411Sadrian ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 65185377Ssam} 66185377Ssam 67185377Ssam/* 68219393Sadrian * AR5416 doesn't do OLC or temperature compensation. 69219393Sadrian */ 70219393Sadrianstatic void 71219393Sadrianar5416olcInit(struct ath_hal *ah) 72219393Sadrian{ 73219393Sadrian} 74219393Sadrian 75219393Sadrianstatic void 76219393Sadrianar5416olcTempCompensation(struct ath_hal *ah) 77219393Sadrian{ 78219393Sadrian} 79219393Sadrian 80219393Sadrian/* 81185377Ssam * Attach for an AR5416 part. 82185377Ssam */ 83185377Ssamvoid 84185377Ssamar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 85185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 86185377Ssam{ 87185377Ssam struct ath_hal_5212 *ahp; 88185377Ssam struct ath_hal *ah; 89185377Ssam 90185377Ssam ahp = &ahp5416->ah_5212; 91185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 92185377Ssam ah = &ahp->ah_priv.h; 93185377Ssam 94185377Ssam /* override 5212 methods for our needs */ 95185377Ssam ah->ah_magic = AR5416_MAGIC; 96185377Ssam ah->ah_getRateTable = ar5416GetRateTable; 97185377Ssam ah->ah_detach = ar5416Detach; 98185377Ssam 99185377Ssam /* Reset functions */ 100185377Ssam ah->ah_reset = ar5416Reset; 101185377Ssam ah->ah_phyDisable = ar5416PhyDisable; 102185377Ssam ah->ah_disable = ar5416Disable; 103188979Ssam ah->ah_configPCIE = ar5416ConfigPCIE; 104235957Sadrian ah->ah_disablePCIE = ar5416DisablePCIE; 105185377Ssam ah->ah_perCalibration = ar5416PerCalibration; 106185380Ssam ah->ah_perCalibrationN = ar5416PerCalibrationN, 107185380Ssam ah->ah_resetCalValid = ar5416ResetCalValid, 108185377Ssam ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 109203930Srpaulo ah->ah_setTxPower = ar5416SetTransmitPower; 110203930Srpaulo ah->ah_setBoardValues = ar5416SetBoardValues; 111185377Ssam 112185377Ssam /* Transmit functions */ 113185377Ssam ah->ah_stopTxDma = ar5416StopTxDma; 114185377Ssam ah->ah_setupTxDesc = ar5416SetupTxDesc; 115185377Ssam ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 116185377Ssam ah->ah_fillTxDesc = ar5416FillTxDesc; 117185377Ssam ah->ah_procTxDesc = ar5416ProcTxDesc; 118217621Sadrian ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 119219792Sadrian ah->ah_setupTxQueue = ar5416SetupTxQueue; 120219792Sadrian ah->ah_resetTxQueue = ar5416ResetTxQueue; 121185377Ssam 122185377Ssam /* Receive Functions */ 123224512Sadrian ah->ah_getRxFilter = ar5416GetRxFilter; 124224512Sadrian ah->ah_setRxFilter = ar5416SetRxFilter; 125234747Sadrian ah->ah_stopDmaReceive = ar5416StopDmaReceive; 126185377Ssam ah->ah_startPcuReceive = ar5416StartPcuReceive; 127185377Ssam ah->ah_stopPcuReceive = ar5416StopPcuReceive; 128185377Ssam ah->ah_setupRxDesc = ar5416SetupRxDesc; 129185377Ssam ah->ah_procRxDesc = ar5416ProcRxDesc; 130217687Sadrian ah->ah_rxMonitor = ar5416RxMonitor; 131217687Sadrian ah->ah_aniPoll = ar5416AniPoll; 132217687Sadrian ah->ah_procMibEvent = ar5416ProcessMibIntr; 133185377Ssam 134185377Ssam /* Misc Functions */ 135217686Sadrian ah->ah_getCapability = ar5416GetCapability; 136231368Sadrian ah->ah_setCapability = ar5416SetCapability; 137185377Ssam ah->ah_getDiagState = ar5416GetDiagState; 138185377Ssam ah->ah_setLedState = ar5416SetLedState; 139185377Ssam ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 140185377Ssam ah->ah_gpioCfgInput = ar5416GpioCfgInput; 141185377Ssam ah->ah_gpioGet = ar5416GpioGet; 142185377Ssam ah->ah_gpioSet = ar5416GpioSet; 143185377Ssam ah->ah_gpioSetIntr = ar5416GpioSetIntr; 144225444Sadrian ah->ah_getTsf64 = ar5416GetTsf64; 145243424Sadrian ah->ah_setTsf64 = ar5416SetTsf64; 146185377Ssam ah->ah_resetTsf = ar5416ResetTsf; 147185377Ssam ah->ah_getRfGain = ar5416GetRfgain; 148185377Ssam ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 149185377Ssam ah->ah_setDecompMask = ar5416SetDecompMask; 150185377Ssam ah->ah_setCoverageClass = ar5416SetCoverageClass; 151222644Sadrian ah->ah_setQuiet = ar5416SetQuiet; 152234873Sadrian ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts; 153185377Ssam 154185377Ssam ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 155185377Ssam ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 156185377Ssam 157222584Sadrian /* DFS Functions */ 158222584Sadrian ah->ah_enableDfs = ar5416EnableDfs; 159222584Sadrian ah->ah_getDfsThresh = ar5416GetDfsThresh; 160239638Sadrian ah->ah_getDfsDefaultThresh = ar5416GetDfsDefaultThresh; 161222815Sadrian ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 162224709Sadrian ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 163222584Sadrian 164185377Ssam /* Power Management Functions */ 165185377Ssam ah->ah_setPowerMode = ar5416SetPowerMode; 166185377Ssam 167185377Ssam /* Beacon Management Functions */ 168185377Ssam ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 169185377Ssam ah->ah_beaconInit = ar5416BeaconInit; 170185377Ssam ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 171185377Ssam ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 172225444Sadrian ah->ah_getNextTBTT = ar5416GetNextTBTT; 173185377Ssam 174218066Sadrian /* 802.11n Functions */ 175185377Ssam ah->ah_chainTxDesc = ar5416ChainTxDesc; 176185377Ssam ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 177185377Ssam ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 178185377Ssam ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 179226767Sadrian ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 180185377Ssam ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 181226767Sadrian ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 182185377Ssam ah->ah_clr11nAggr = ar5416Clr11nAggr; 183185377Ssam ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 184185377Ssam ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 185185377Ssam ah->ah_set11nMac2040 = ar5416Set11nMac2040; 186185377Ssam ah->ah_get11nRxClear = ar5416Get11nRxClear; 187185377Ssam ah->ah_set11nRxClear = ar5416Set11nRxClear; 188185377Ssam 189185377Ssam /* Interrupt functions */ 190185377Ssam ah->ah_isInterruptPending = ar5416IsInterruptPending; 191185377Ssam ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 192185377Ssam ah->ah_setInterrupts = ar5416SetInterrupts; 193185377Ssam 194185377Ssam ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 195185377Ssam ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 196185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 197185377Ssam ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 198185377Ssam#endif 199185377Ssam ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 200185377Ssam 201219393Sadrian /* Internal ops */ 202189747Ssam AH5416(ah)->ah_writeIni = ar5416WriteIni; 203189747Ssam AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 204219393Sadrian 205220990Sadrian /* Internal baseband ops */ 206220990Sadrian AH5416(ah)->ah_initPLL = ar5416InitPLL; 207220990Sadrian 208219480Sadrian /* Internal calibration ops */ 209219480Sadrian AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 210219480Sadrian 211219393Sadrian /* Internal TX power control related operations */ 212219393Sadrian AH5416(ah)->ah_olcInit = ar5416olcInit; 213219393Sadrian AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 214219393Sadrian AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 215219393Sadrian 216185377Ssam /* 217185377Ssam * Start by setting all Owl devices to 2x2 218185377Ssam */ 219185377Ssam AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 220185377Ssam AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 221218763Sadrian 222218763Sadrian /* Enable all ANI functions to begin with */ 223222276Sadrian AH5416(ah)->ah_ani_function = 0xffffffff; 224222265Sadrian 225222265Sadrian /* Set overridable ANI methods */ 226222265Sadrian AH5212(ah)->ah_aniControl = ar5416AniControl; 227185377Ssam} 228185377Ssam 229188971Ssamuint32_t 230188971Ssamar5416GetRadioRev(struct ath_hal *ah) 231188971Ssam{ 232188971Ssam uint32_t val; 233188971Ssam int i; 234188971Ssam 235188971Ssam /* Read Radio Chip Rev Extract */ 236188971Ssam OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 237188971Ssam for (i = 0; i < 8; i++) 238188971Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 239188971Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 240188971Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 241188971Ssam return ath_hal_reverseBits(val, 8); 242188971Ssam} 243188971Ssam 244185377Ssam/* 245185377Ssam * Attach for an AR5416 part. 246185377Ssam */ 247188972Ssamstatic struct ath_hal * 248185377Ssamar5416Attach(uint16_t devid, HAL_SOFTC sc, 249217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 250217624Sadrian HAL_STATUS *status) 251185377Ssam{ 252185377Ssam struct ath_hal_5416 *ahp5416; 253185377Ssam struct ath_hal_5212 *ahp; 254185377Ssam struct ath_hal *ah; 255185377Ssam uint32_t val; 256185377Ssam HAL_STATUS ecode; 257185377Ssam HAL_BOOL rfStatus; 258185377Ssam 259225883Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 260185377Ssam __func__, sc, (void*) st, (void*) sh); 261185377Ssam 262185377Ssam /* NB: memory is returned zero'd */ 263185377Ssam ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 264185377Ssam /* extra space for Owl 2.1/2.2 WAR */ 265185377Ssam sizeof(ar5416Addac) 266185377Ssam ); 267185377Ssam if (ahp5416 == AH_NULL) { 268225883Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 269185377Ssam "%s: cannot allocate memory for state block\n", __func__); 270185377Ssam *status = HAL_ENOMEM; 271185377Ssam return AH_NULL; 272185377Ssam } 273185377Ssam ar5416InitState(ahp5416, devid, sc, st, sh, status); 274185377Ssam ahp = &ahp5416->ah_5212; 275185377Ssam ah = &ahp->ah_priv.h; 276185377Ssam 277185377Ssam if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 278185377Ssam /* reset chip */ 279185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 280185377Ssam ecode = HAL_EIO; 281185377Ssam goto bad; 282185377Ssam } 283185377Ssam 284185377Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 285185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 286185377Ssam ecode = HAL_EIO; 287185377Ssam goto bad; 288185377Ssam } 289185377Ssam /* Read Revisions from Chips before taking out of reset */ 290185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 291185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 292185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 293188979Ssam AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 294185377Ssam 295185377Ssam /* setup common ini data; rf backends handle remainder */ 296185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 297185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 298185377Ssam 299185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 300185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 301185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 302185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 303185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 304185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 305185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 306185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 307185377Ssam 308219840Sadrian if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 309219839Sadrian ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 310185377Ssam struct ini { 311185377Ssam uint32_t *data; /* NB: !const */ 312185377Ssam int rows, cols; 313185377Ssam }; 314185377Ssam /* override CLKDRV value */ 315185377Ssam OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 316185377Ssam AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 317185377Ssam HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 318185377Ssam } 319185377Ssam 320188979Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 321188979Ssam ar5416AttachPCIE(ah); 322188979Ssam 323188973Ssam ecode = ath_hal_v14EepromAttach(ah); 324188973Ssam if (ecode != HAL_OK) 325188973Ssam goto bad; 326188973Ssam 327185377Ssam if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 328185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 329185377Ssam __func__); 330185377Ssam ecode = HAL_EIO; 331185377Ssam goto bad; 332185377Ssam } 333185377Ssam 334185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 335185377Ssam 336185377Ssam if (!ar5212ChipTest(ah)) { 337185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 338185377Ssam __func__); 339185377Ssam ecode = HAL_ESELFTEST; 340185377Ssam goto bad; 341185377Ssam } 342185377Ssam 343185377Ssam /* 344185377Ssam * Set correct Baseband to analog shift 345185377Ssam * setting to access analog chips. 346185377Ssam */ 347185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 348185377Ssam 349185377Ssam /* Read Radio Chip Rev Extract */ 350228515Sadrian AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 351185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 352185377Ssam case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 353185377Ssam case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 354185377Ssam case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 355185377Ssam case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 356185377Ssam break; 357185377Ssam default: 358185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 359185377Ssam /* 360185377Ssam * When RF_Silen is used the analog chip is reset. 361185377Ssam * So when the system boots with radio switch off 362185377Ssam * the RF chip rev reads back as zero and we need 363185377Ssam * to use the mac+phy revs to set the radio rev. 364185377Ssam */ 365185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 366185377Ssam AR_RAD5133_SREV_MAJOR; 367185377Ssam break; 368185377Ssam } 369185377Ssam /* NB: silently accept anything in release code per Atheros */ 370185377Ssam#ifdef AH_DEBUG 371185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 372185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 373185377Ssam "this driver\n", __func__, 374185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 375185377Ssam ecode = HAL_ENOTSUPP; 376185377Ssam goto bad; 377185377Ssam#endif 378185377Ssam } 379185377Ssam 380185377Ssam /* 381185377Ssam * Got everything we need now to setup the capabilities. 382185377Ssam */ 383185377Ssam if (!ar5416FillCapabilityInfo(ah)) { 384185377Ssam ecode = HAL_EEREAD; 385185377Ssam goto bad; 386185377Ssam } 387185377Ssam 388185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 389185377Ssam if (ecode != HAL_OK) { 390185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 391185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 392185377Ssam goto bad; 393185377Ssam } 394185377Ssam /* XXX How about the serial number ? */ 395185377Ssam /* Read Reg Domain */ 396185377Ssam AH_PRIVATE(ah)->ah_currentRD = 397185377Ssam ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 398221596Sadrian AH_PRIVATE(ah)->ah_currentRDext = 399221596Sadrian ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 400185377Ssam 401185377Ssam /* 402185377Ssam * ah_miscMode is populated by ar5416FillCapabilityInfo() 403185377Ssam * starting from griffin. Set here to make sure that 404185377Ssam * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 405185380Ssam * placed into hardware. 406185377Ssam */ 407185377Ssam if (ahp->ah_miscMode != 0) 408219771Sadrian OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 409185377Ssam 410185377Ssam rfStatus = ar2133RfAttach(ah, &ecode); 411185377Ssam if (!rfStatus) { 412185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 413185377Ssam __func__, ecode); 414185377Ssam goto bad; 415185377Ssam } 416185377Ssam 417185377Ssam ar5416AniSetup(ah); /* Anti Noise Immunity */ 418218068Sadrian 419218068Sadrian AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 420218068Sadrian AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 421218068Sadrian AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 422218068Sadrian AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 423218068Sadrian AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 424218068Sadrian AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 425218068Sadrian 426203882Srpaulo ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 427185377Ssam 428185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 429185377Ssam 430185377Ssam return ah; 431185377Ssambad: 432185377Ssam if (ahp) 433185377Ssam ar5416Detach((struct ath_hal *) ahp); 434185377Ssam if (status) 435185377Ssam *status = ecode; 436185377Ssam return AH_NULL; 437185377Ssam} 438185377Ssam 439185377Ssamvoid 440185377Ssamar5416Detach(struct ath_hal *ah) 441185377Ssam{ 442185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 443185377Ssam 444185377Ssam HALASSERT(ah != AH_NULL); 445185377Ssam HALASSERT(ah->ah_magic == AR5416_MAGIC); 446185377Ssam 447221777Sadrian /* Make sure that chip is awake before writing to it */ 448221777Sadrian if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 449221777Sadrian HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 450221777Sadrian "%s: failed to wake up chip\n", 451221777Sadrian __func__); 452221777Sadrian 453185380Ssam ar5416AniDetach(ah); 454185377Ssam ar5212RfDetach(ah); 455185377Ssam ah->ah_disable(ah); 456185377Ssam ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 457185377Ssam ath_hal_eepromDetach(ah); 458185377Ssam ath_hal_free(ah); 459185377Ssam} 460185377Ssam 461188979Ssamvoid 462188979Ssamar5416AttachPCIE(struct ath_hal *ah) 463188979Ssam{ 464188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) 465235972Sadrian ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 466188979Ssam else 467188979Ssam ath_hal_disablePCIE(ah); 468188979Ssam} 469188979Ssam 470188979Ssamstatic void 471235972Sadrianar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 472188979Ssam{ 473236017Sadrian 474236017Sadrian /* This is only applicable for AR5418 (AR5416 PCIe) */ 475236017Sadrian if (! AH_PRIVATE(ah)->ah_ispcie) 476236017Sadrian return; 477236017Sadrian 478236017Sadrian if (! restore) { 479188979Ssam ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 480188979Ssam OS_DELAY(1000); 481236017Sadrian } 482236017Sadrian 483236017Sadrian if (power_off) { /* Power-off */ 484236017Sadrian /* clear bit 19 to disable L1 */ 485236017Sadrian OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 486236017Sadrian } else { /* Power-on */ 487236017Sadrian /* Set default WAR values for Owl */ 488236017Sadrian OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 489236017Sadrian 490236017Sadrian /* set bit 19 to allow forcing of pcie core into L1 state */ 491188979Ssam OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 492188979Ssam } 493188979Ssam} 494188979Ssam 495236017Sadrian/* 496236017Sadrian * Disable PCIe PHY if PCIe isn't used. 497236017Sadrian */ 498189747Ssamstatic void 499235957Sadrianar5416DisablePCIE(struct ath_hal *ah) 500235957Sadrian{ 501236017Sadrian 502236017Sadrian /* PCIe? Don't */ 503236017Sadrian if (AH_PRIVATE(ah)->ah_ispcie) 504236017Sadrian return; 505236017Sadrian 506236017Sadrian /* .. Only applicable for AR5416v2 or later */ 507236017Sadrian if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah))) 508236017Sadrian return; 509236017Sadrian 510236017Sadrian OS_REG_WRITE_BUFFER_ENABLE(ah); 511236017Sadrian 512236017Sadrian /* 513236017Sadrian * Disable the PCIe PHY. 514236017Sadrian */ 515236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 516236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 517236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 518236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 519236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 520236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 521236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 522236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 523236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 524236017Sadrian 525236017Sadrian /* Load the new settings */ 526236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 527236017Sadrian 528236017Sadrian OS_REG_WRITE_BUFFER_FLUSH(ah); 529236017Sadrian OS_REG_WRITE_BUFFER_DISABLE(ah); 530235957Sadrian} 531235957Sadrian 532235957Sadrianstatic void 533189747Ssamar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 534189747Ssam{ 535189747Ssam u_int modesIndex, freqIndex; 536189747Ssam int regWrites = 0; 537189747Ssam 538189747Ssam /* Setup the indices for the next set of register array writes */ 539189747Ssam /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 540189747Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 541189747Ssam freqIndex = 2; 542189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 543189747Ssam modesIndex = 3; 544189747Ssam else if (IEEE80211_IS_CHAN_108G(chan)) 545189747Ssam modesIndex = 5; 546189747Ssam else 547189747Ssam modesIndex = 4; 548189747Ssam } else { 549189747Ssam freqIndex = 1; 550189747Ssam if (IEEE80211_IS_CHAN_HT40(chan) || 551189747Ssam IEEE80211_IS_CHAN_TURBO(chan)) 552189747Ssam modesIndex = 2; 553189747Ssam else 554189747Ssam modesIndex = 1; 555189747Ssam } 556189747Ssam 557189747Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 558189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 559189747Ssam 560189747Ssam /* 561189747Ssam * Write addac shifts 562189747Ssam */ 563189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 564219863Sadrian 565189747Ssam /* NB: only required for Sowl */ 566219863Sadrian if (AR_SREV_SOWL(ah)) 567219863Sadrian ar5416EepromSetAddac(ah, chan); 568219863Sadrian 569189747Ssam regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 570189747Ssam regWrites); 571189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 572189747Ssam 573189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 574189747Ssam modesIndex, regWrites); 575189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 576189747Ssam 1, regWrites); 577189747Ssam 578189747Ssam /* XXX updated regWrites? */ 579189747Ssam AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 580189747Ssam} 581189747Ssam 582185377Ssam/* 583189747Ssam * Convert to baseband spur frequency given input channel frequency 584189747Ssam * and compute register settings below. 585189747Ssam */ 586189747Ssam 587189747Ssamstatic void 588189747Ssamar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 589189747Ssam{ 590189747Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 591189747Ssam static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 592189747Ssam AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 593189747Ssam static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 594189747Ssam AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 595189747Ssam static const int inc[4] = { 0, 100, 0, 0 }; 596189747Ssam 597189747Ssam int bb_spur = AR_NO_SPUR; 598189747Ssam int bin, cur_bin; 599189747Ssam int spur_freq_sd; 600189747Ssam int spur_delta_phase; 601189747Ssam int denominator; 602189747Ssam int upper, lower, cur_vit_mask; 603189747Ssam int tmp, new; 604189747Ssam int i; 605189747Ssam 606189747Ssam int8_t mask_m[123]; 607189747Ssam int8_t mask_p[123]; 608189747Ssam int8_t mask_amt; 609189747Ssam int tmp_mask; 610189747Ssam int cur_bb_spur; 611189747Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 612189747Ssam 613189747Ssam OS_MEMZERO(mask_m, sizeof(mask_m)); 614189747Ssam OS_MEMZERO(mask_p, sizeof(mask_p)); 615189747Ssam 616189747Ssam /* 617189747Ssam * Need to verify range +/- 9.5 for static ht20, otherwise spur 618189747Ssam * is out-of-band and can be ignored. 619189747Ssam */ 620189747Ssam /* XXX ath9k changes */ 621189747Ssam for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 622189747Ssam cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 623189747Ssam if (AR_NO_SPUR == cur_bb_spur) 624189747Ssam break; 625189747Ssam cur_bb_spur = cur_bb_spur - (freq * 10); 626189747Ssam if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 627189747Ssam bb_spur = cur_bb_spur; 628189747Ssam break; 629189747Ssam } 630189747Ssam } 631189747Ssam if (AR_NO_SPUR == bb_spur) 632189747Ssam return; 633189747Ssam 634189747Ssam bin = bb_spur * 32; 635189747Ssam 636189747Ssam tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 637189747Ssam new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 638189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 639189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 640189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 641189747Ssam 642234664Sadrian OS_REG_WRITE_BUFFER_ENABLE(ah); 643234664Sadrian 644189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 645189747Ssam 646189747Ssam new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 647189747Ssam AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 648189747Ssam AR_PHY_SPUR_REG_MASK_RATE_SELECT | 649189747Ssam AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 650189747Ssam SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 651189747Ssam OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 652189747Ssam /* 653189747Ssam * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 654189747Ssam * config, no offset for HT20. 655189747Ssam * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 656189747Ssam * /80 for dyn2040. 657189747Ssam */ 658189747Ssam spur_delta_phase = ((bb_spur * 524288) / 100) & 659189747Ssam AR_PHY_TIMING11_SPUR_DELTA_PHASE; 660189747Ssam /* 661189747Ssam * in 11A mode the denominator of spur_freq_sd should be 40 and 662189747Ssam * it should be 44 in 11G 663189747Ssam */ 664189747Ssam denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 665189747Ssam spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 666189747Ssam 667189747Ssam new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 668189747Ssam SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 669189747Ssam SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 670189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 671189747Ssam 672189747Ssam 673189747Ssam /* 674189747Ssam * ============================================ 675189747Ssam * pilot mask 1 [31:0] = +6..-26, no 0 bin 676189747Ssam * pilot mask 2 [19:0] = +26..+7 677189747Ssam * 678189747Ssam * channel mask 1 [31:0] = +6..-26, no 0 bin 679189747Ssam * channel mask 2 [19:0] = +26..+7 680189747Ssam */ 681189747Ssam //cur_bin = -26; 682189747Ssam cur_bin = -6000; 683189747Ssam upper = bin + 100; 684189747Ssam lower = bin - 100; 685189747Ssam 686189747Ssam for (i = 0; i < 4; i++) { 687189747Ssam int pilot_mask = 0; 688189747Ssam int chan_mask = 0; 689189747Ssam int bp = 0; 690189747Ssam for (bp = 0; bp < 30; bp++) { 691189747Ssam if ((cur_bin > lower) && (cur_bin < upper)) { 692189747Ssam pilot_mask = pilot_mask | 0x1 << bp; 693189747Ssam chan_mask = chan_mask | 0x1 << bp; 694189747Ssam } 695189747Ssam cur_bin += 100; 696189747Ssam } 697189747Ssam cur_bin += inc[i]; 698189747Ssam OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 699189747Ssam OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 700189747Ssam } 701189747Ssam 702189747Ssam /* ================================================= 703189747Ssam * viterbi mask 1 based on channel magnitude 704189747Ssam * four levels 0-3 705189747Ssam * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 706189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 707189747Ssam * - enable_mask_ppm, all bins move with freq 708189747Ssam * 709189747Ssam * - mask_select, 8 bits for rates (reg 67,0x990c) 710189747Ssam * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 711189747Ssam * choose which mask to use mask or mask2 712189747Ssam */ 713189747Ssam 714189747Ssam /* 715189747Ssam * viterbi mask 2 2nd set for per data rate puncturing 716189747Ssam * four levels 0-3 717189747Ssam * - mask_select, 8 bits for rates (reg 67) 718189747Ssam * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 719189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 720189747Ssam */ 721189747Ssam cur_vit_mask = 6100; 722189747Ssam upper = bin + 120; 723189747Ssam lower = bin - 120; 724189747Ssam 725189747Ssam for (i = 0; i < 123; i++) { 726189747Ssam if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 727189747Ssam if ((abs(cur_vit_mask - bin)) < 75) { 728189747Ssam mask_amt = 1; 729189747Ssam } else { 730189747Ssam mask_amt = 0; 731189747Ssam } 732189747Ssam if (cur_vit_mask < 0) { 733189747Ssam mask_m[abs(cur_vit_mask / 100)] = mask_amt; 734189747Ssam } else { 735189747Ssam mask_p[cur_vit_mask / 100] = mask_amt; 736189747Ssam } 737189747Ssam } 738189747Ssam cur_vit_mask -= 100; 739189747Ssam } 740189747Ssam 741189747Ssam tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 742189747Ssam | (mask_m[48] << 26) | (mask_m[49] << 24) 743189747Ssam | (mask_m[50] << 22) | (mask_m[51] << 20) 744189747Ssam | (mask_m[52] << 18) | (mask_m[53] << 16) 745189747Ssam | (mask_m[54] << 14) | (mask_m[55] << 12) 746189747Ssam | (mask_m[56] << 10) | (mask_m[57] << 8) 747189747Ssam | (mask_m[58] << 6) | (mask_m[59] << 4) 748189747Ssam | (mask_m[60] << 2) | (mask_m[61] << 0); 749189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 750189747Ssam OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 751189747Ssam 752189747Ssam tmp_mask = (mask_m[31] << 28) 753189747Ssam | (mask_m[32] << 26) | (mask_m[33] << 24) 754189747Ssam | (mask_m[34] << 22) | (mask_m[35] << 20) 755189747Ssam | (mask_m[36] << 18) | (mask_m[37] << 16) 756189747Ssam | (mask_m[48] << 14) | (mask_m[39] << 12) 757189747Ssam | (mask_m[40] << 10) | (mask_m[41] << 8) 758189747Ssam | (mask_m[42] << 6) | (mask_m[43] << 4) 759189747Ssam | (mask_m[44] << 2) | (mask_m[45] << 0); 760189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 761189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 762189747Ssam 763189747Ssam tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 764189747Ssam | (mask_m[18] << 26) | (mask_m[18] << 24) 765189747Ssam | (mask_m[20] << 22) | (mask_m[20] << 20) 766189747Ssam | (mask_m[22] << 18) | (mask_m[22] << 16) 767189747Ssam | (mask_m[24] << 14) | (mask_m[24] << 12) 768189747Ssam | (mask_m[25] << 10) | (mask_m[26] << 8) 769189747Ssam | (mask_m[27] << 6) | (mask_m[28] << 4) 770189747Ssam | (mask_m[29] << 2) | (mask_m[30] << 0); 771189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 772189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 773189747Ssam 774189747Ssam tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 775189747Ssam | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 776189747Ssam | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 777189747Ssam | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 778189747Ssam | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 779189747Ssam | (mask_m[10] << 10) | (mask_m[11] << 8) 780189747Ssam | (mask_m[12] << 6) | (mask_m[13] << 4) 781189747Ssam | (mask_m[14] << 2) | (mask_m[15] << 0); 782189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 783189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 784189747Ssam 785189747Ssam tmp_mask = (mask_p[15] << 28) 786189747Ssam | (mask_p[14] << 26) | (mask_p[13] << 24) 787189747Ssam | (mask_p[12] << 22) | (mask_p[11] << 20) 788189747Ssam | (mask_p[10] << 18) | (mask_p[ 9] << 16) 789189747Ssam | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 790189747Ssam | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 791189747Ssam | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 792189747Ssam | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 793189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 794189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 795189747Ssam 796189747Ssam tmp_mask = (mask_p[30] << 28) 797189747Ssam | (mask_p[29] << 26) | (mask_p[28] << 24) 798189747Ssam | (mask_p[27] << 22) | (mask_p[26] << 20) 799189747Ssam | (mask_p[25] << 18) | (mask_p[24] << 16) 800189747Ssam | (mask_p[23] << 14) | (mask_p[22] << 12) 801189747Ssam | (mask_p[21] << 10) | (mask_p[20] << 8) 802189747Ssam | (mask_p[19] << 6) | (mask_p[18] << 4) 803189747Ssam | (mask_p[17] << 2) | (mask_p[16] << 0); 804189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 805189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 806189747Ssam 807189747Ssam tmp_mask = (mask_p[45] << 28) 808189747Ssam | (mask_p[44] << 26) | (mask_p[43] << 24) 809189747Ssam | (mask_p[42] << 22) | (mask_p[41] << 20) 810189747Ssam | (mask_p[40] << 18) | (mask_p[39] << 16) 811189747Ssam | (mask_p[38] << 14) | (mask_p[37] << 12) 812189747Ssam | (mask_p[36] << 10) | (mask_p[35] << 8) 813189747Ssam | (mask_p[34] << 6) | (mask_p[33] << 4) 814189747Ssam | (mask_p[32] << 2) | (mask_p[31] << 0); 815189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 816189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 817189747Ssam 818189747Ssam tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 819189747Ssam | (mask_p[59] << 26) | (mask_p[58] << 24) 820189747Ssam | (mask_p[57] << 22) | (mask_p[56] << 20) 821189747Ssam | (mask_p[55] << 18) | (mask_p[54] << 16) 822189747Ssam | (mask_p[53] << 14) | (mask_p[52] << 12) 823189747Ssam | (mask_p[51] << 10) | (mask_p[50] << 8) 824189747Ssam | (mask_p[49] << 6) | (mask_p[48] << 4) 825189747Ssam | (mask_p[47] << 2) | (mask_p[46] << 0); 826189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 827189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 828234664Sadrian 829234664Sadrian OS_REG_WRITE_BUFFER_FLUSH(ah); 830234664Sadrian OS_REG_WRITE_BUFFER_DISABLE(ah); 831189747Ssam} 832189747Ssam 833189747Ssam/* 834185377Ssam * Fill all software cached or static hardware state information. 835185377Ssam * Return failure if capabilities are to come from EEPROM and 836185377Ssam * cannot be read. 837185377Ssam */ 838185377SsamHAL_BOOL 839185377Ssamar5416FillCapabilityInfo(struct ath_hal *ah) 840185377Ssam{ 841185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 842185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 843185377Ssam uint16_t val; 844185377Ssam 845185377Ssam /* Construct wireless mode from EEPROM */ 846185377Ssam pCap->halWirelessModes = 0; 847185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 848185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 849185377Ssam | HAL_MODE_11NA_HT20 850185377Ssam | HAL_MODE_11NA_HT40PLUS 851185377Ssam | HAL_MODE_11NA_HT40MINUS 852185377Ssam ; 853185377Ssam } 854185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 855185377Ssam pCap->halWirelessModes |= HAL_MODE_11G 856185377Ssam | HAL_MODE_11NG_HT20 857185377Ssam | HAL_MODE_11NG_HT40PLUS 858185377Ssam | HAL_MODE_11NG_HT40MINUS 859185377Ssam ; 860185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 861185377Ssam | HAL_MODE_11NA_HT20 862185377Ssam | HAL_MODE_11NA_HT40PLUS 863185377Ssam | HAL_MODE_11NA_HT40MINUS 864185377Ssam ; 865185377Ssam } 866185377Ssam 867185377Ssam pCap->halLow2GhzChan = 2312; 868185377Ssam pCap->halHigh2GhzChan = 2732; 869185377Ssam 870185377Ssam pCap->halLow5GhzChan = 4915; 871185377Ssam pCap->halHigh5GhzChan = 6100; 872185377Ssam 873185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 874185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 875185377Ssam pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 876185377Ssam 877185377Ssam pCap->halMicCkipSupport = AH_FALSE; 878185377Ssam pCap->halMicTkipSupport = AH_TRUE; 879185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 880185377Ssam /* 881185377Ssam * Starting with Griffin TX+RX mic keys can be combined 882185377Ssam * in one key cache slot. 883185377Ssam */ 884185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 885185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 886185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 887185377Ssam 888185377Ssam pCap->halCompressSupport = AH_FALSE; 889185377Ssam pCap->halBurstSupport = AH_TRUE; 890185377Ssam pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 891185377Ssam pCap->halChapTuningSupport = AH_TRUE; 892185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 893185377Ssam 894185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 895185377Ssam 896185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 897238858Sadrian pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 898239643Sadrian pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 899185377Ssam pCap->halVEOLSupport = AH_TRUE; 900185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 901222020Sadrian pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 902185377Ssam pCap->halTsfAddSupport = AH_TRUE; 903221603Sadrian pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 904185377Ssam 905185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 906185377Ssam pCap->halTotalQueues = val; 907185377Ssam else 908185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 909185377Ssam 910185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 911185377Ssam pCap->halKeyCacheSize = val; 912185377Ssam else 913185377Ssam pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 914185377Ssam 915240448Sadrian /* XXX Which chips? */ 916240448Sadrian pCap->halChanHalfRate = AH_TRUE; 917240448Sadrian pCap->halChanQuarterRate = AH_TRUE; 918185377Ssam 919185377Ssam pCap->halTstampPrecision = 32; 920185377Ssam pCap->halHwPhyCounterSupport = AH_TRUE; 921192396Ssam pCap->halIntrMask = HAL_INT_COMMON 922192396Ssam | HAL_INT_RX 923192396Ssam | HAL_INT_TX 924192396Ssam | HAL_INT_FATAL 925192396Ssam | HAL_INT_BNR 926192396Ssam | HAL_INT_BMISC 927192396Ssam | HAL_INT_DTIMSYNC 928192396Ssam | HAL_INT_TSFOOR 929192396Ssam | HAL_INT_CST 930192396Ssam | HAL_INT_GTT 931192396Ssam ; 932185377Ssam 933185377Ssam pCap->halFastCCSupport = AH_TRUE; 934228893Sadrian pCap->halNumGpioPins = 14; 935185377Ssam pCap->halWowSupport = AH_FALSE; 936185377Ssam pCap->halWowMatchPatternExact = AH_FALSE; 937185377Ssam pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 938185377Ssam pCap->halAutoSleepSupport = AH_FALSE; 939218441Sadrian pCap->hal4kbSplitTransSupport = AH_TRUE; 940220324Sadrian /* Disable this so Block-ACK works correctly */ 941220324Sadrian pCap->halHasRxSelfLinkedTail = AH_FALSE; 942185377Ssam#if 0 /* XXX not yet */ 943185377Ssam pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 944185377Ssam pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 945185377Ssam#endif 946185377Ssam pCap->halHTSupport = AH_TRUE; 947185377Ssam pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 948185377Ssam /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 949185377Ssam pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 950218150Sadrian /* AR5416 may have 3 antennas but is a 2x2 stream device */ 951218150Sadrian pCap->halTxStreams = 2; 952218150Sadrian pCap->halRxStreams = 2; 953231368Sadrian 954230847Sadrian /* 955230847Sadrian * If the TX or RX chainmask has less than 2 chains active, 956230847Sadrian * mark it as a 1-stream device for the relevant stream. 957230847Sadrian */ 958230847Sadrian if (owl_get_ntxchains(pCap->halTxChainMask) == 1) 959230847Sadrian pCap->halTxStreams = 1; 960230847Sadrian /* XXX Eww */ 961230847Sadrian if (owl_get_ntxchains(pCap->halRxChainMask) == 1) 962230847Sadrian pCap->halRxStreams = 1; 963185377Ssam pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 964221603Sadrian pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 965185377Ssam pCap->halForcePpmSupport = AH_TRUE; 966185377Ssam pCap->halEnhancedPmSupport = AH_TRUE; 967195114Ssam pCap->halBssidMatchSupport = AH_TRUE; 968221603Sadrian pCap->halGTTSupport = AH_TRUE; 969221603Sadrian pCap->halCSTSupport = AH_TRUE; 970222584Sadrian pCap->halEnhancedDfsSupport = AH_FALSE; 971225444Sadrian /* Hardware supports 32 bit TSF values in the RX descriptor */ 972225444Sadrian pCap->halHasLongRxDescTsf = AH_TRUE; 973226488Sadrian /* 974226488Sadrian * BB Read WAR: this is only for AR5008/AR9001 NICs 975226488Sadrian * It is also set individually in the AR91xx attach functions. 976226488Sadrian */ 977226488Sadrian if (AR_SREV_OWL(ah)) 978226488Sadrian pCap->halHasBBReadWar = AH_TRUE; 979185377Ssam 980185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 981185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 982185377Ssam /* NB: enabled by default */ 983185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 984185377Ssam pCap->halRfSilentSupport = AH_TRUE; 985185377Ssam } 986185377Ssam 987227410Sadrian /* 988227410Sadrian * The MAC will mark frames as RXed if there's a descriptor 989227410Sadrian * to write them to. So if it hits a self-linked final descriptor, 990227410Sadrian * it'll keep ACKing frames even though they're being silently 991227410Sadrian * dropped. Thus, this particular feature of the driver can't 992227410Sadrian * be used for 802.11n devices. 993227410Sadrian */ 994185377Ssam ahpriv->ah_rxornIsFatal = AH_FALSE; 995185377Ssam 996227410Sadrian /* 997227410Sadrian * If it's a PCI NIC, ask the HAL OS layer to serialise 998227410Sadrian * register access, or SMP machines may cause the hardware 999227410Sadrian * to hang. This is applicable to AR5416 and AR9220; I'm not 1000227410Sadrian * sure about AR9160 or AR9227. 1001227410Sadrian */ 1002227410Sadrian if (! AH_PRIVATE(ah)->ah_ispcie) 1003227410Sadrian pCap->halSerialiseRegWar = 1; 1004227410Sadrian 1005185377Ssam return AH_TRUE; 1006185377Ssam} 1007185406Ssam 1008185406Ssamstatic const char* 1009185406Ssamar5416Probe(uint16_t vendorid, uint16_t devid) 1010185406Ssam{ 1011227372Sadrian if (vendorid == ATHEROS_VENDOR_ID) { 1012227372Sadrian if (devid == AR5416_DEVID_PCI) 1013227372Sadrian return "Atheros 5416"; 1014227372Sadrian if (devid == AR5416_DEVID_PCIE) 1015227372Sadrian return "Atheros 5418"; 1016227372Sadrian } 1017185406Ssam return AH_NULL; 1018185406Ssam} 1019185418SsamAH_CHIP(AR5416, ar5416Probe, ar5416Attach); 1020