ar5416_attach.c revision 224709
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17188970Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 224709 2011-08-08 13:15:39Z adrian $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25189747Ssam#include "ah_eeprom_v14.h" 26189747Ssam 27185377Ssam#include "ar5416/ar5416.h" 28185377Ssam#include "ar5416/ar5416reg.h" 29185377Ssam#include "ar5416/ar5416phy.h" 30185377Ssam 31185377Ssam#include "ar5416/ar5416.ini" 32185377Ssam 33188979Ssamstatic void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34189747Ssamstatic void ar5416WriteIni(struct ath_hal *ah, 35189747Ssam const struct ieee80211_channel *chan); 36189747Ssamstatic void ar5416SpurMitigate(struct ath_hal *ah, 37189747Ssam const struct ieee80211_channel *chan); 38188979Ssam 39185377Ssamstatic void 40185377Ssamar5416AniSetup(struct ath_hal *ah) 41185377Ssam{ 42185377Ssam static const struct ar5212AniParams aniparams = { 43185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 46185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 47185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 48185377Ssam .maxSpurImmunityLevel = 2, 49185377Ssam .cycPwrThr1 = { 2, 4, 6 }, 50185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 51185377Ssam .firstep = { 0, 4, 8 }, 52185377Ssam .ofdmTrigHigh = 500, 53185377Ssam .ofdmTrigLow = 200, 54185377Ssam .cckTrigHigh = 200, 55185377Ssam .cckTrigLow = 100, 56185377Ssam .rssiThrHigh = 40, 57185377Ssam .rssiThrLow = 7, 58185377Ssam .period = 100, 59185377Ssam }; 60219979Sadrian /* NB: disable ANI noise immmunity for reliable RIFS rx */ 61222276Sadrian AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 62219979Sadrian ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 63185377Ssam} 64185377Ssam 65185377Ssam/* 66219393Sadrian * AR5416 doesn't do OLC or temperature compensation. 67219393Sadrian */ 68219393Sadrianstatic void 69219393Sadrianar5416olcInit(struct ath_hal *ah) 70219393Sadrian{ 71219393Sadrian} 72219393Sadrian 73219393Sadrianstatic void 74219393Sadrianar5416olcTempCompensation(struct ath_hal *ah) 75219393Sadrian{ 76219393Sadrian} 77219393Sadrian 78219393Sadrian/* 79185377Ssam * Attach for an AR5416 part. 80185377Ssam */ 81185377Ssamvoid 82185377Ssamar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 83185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 84185377Ssam{ 85185377Ssam struct ath_hal_5212 *ahp; 86185377Ssam struct ath_hal *ah; 87185377Ssam 88185377Ssam ahp = &ahp5416->ah_5212; 89185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 90185377Ssam ah = &ahp->ah_priv.h; 91185377Ssam 92185377Ssam /* override 5212 methods for our needs */ 93185377Ssam ah->ah_magic = AR5416_MAGIC; 94185377Ssam ah->ah_getRateTable = ar5416GetRateTable; 95185377Ssam ah->ah_detach = ar5416Detach; 96185377Ssam 97185377Ssam /* Reset functions */ 98185377Ssam ah->ah_reset = ar5416Reset; 99185377Ssam ah->ah_phyDisable = ar5416PhyDisable; 100185377Ssam ah->ah_disable = ar5416Disable; 101188979Ssam ah->ah_configPCIE = ar5416ConfigPCIE; 102185377Ssam ah->ah_perCalibration = ar5416PerCalibration; 103185380Ssam ah->ah_perCalibrationN = ar5416PerCalibrationN, 104185380Ssam ah->ah_resetCalValid = ar5416ResetCalValid, 105185377Ssam ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 106203930Srpaulo ah->ah_setTxPower = ar5416SetTransmitPower; 107203930Srpaulo ah->ah_setBoardValues = ar5416SetBoardValues; 108185377Ssam 109185377Ssam /* Transmit functions */ 110185377Ssam ah->ah_stopTxDma = ar5416StopTxDma; 111185377Ssam ah->ah_setupTxDesc = ar5416SetupTxDesc; 112185377Ssam ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 113185377Ssam ah->ah_fillTxDesc = ar5416FillTxDesc; 114185377Ssam ah->ah_procTxDesc = ar5416ProcTxDesc; 115217621Sadrian ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 116219792Sadrian ah->ah_setupTxQueue = ar5416SetupTxQueue; 117219792Sadrian ah->ah_resetTxQueue = ar5416ResetTxQueue; 118185377Ssam 119185377Ssam /* Receive Functions */ 120224512Sadrian ah->ah_getRxFilter = ar5416GetRxFilter; 121224512Sadrian ah->ah_setRxFilter = ar5416SetRxFilter; 122185377Ssam ah->ah_startPcuReceive = ar5416StartPcuReceive; 123185377Ssam ah->ah_stopPcuReceive = ar5416StopPcuReceive; 124185377Ssam ah->ah_setupRxDesc = ar5416SetupRxDesc; 125185377Ssam ah->ah_procRxDesc = ar5416ProcRxDesc; 126217687Sadrian ah->ah_rxMonitor = ar5416RxMonitor; 127217687Sadrian ah->ah_aniPoll = ar5416AniPoll; 128217687Sadrian ah->ah_procMibEvent = ar5416ProcessMibIntr; 129185377Ssam 130185377Ssam /* Misc Functions */ 131217686Sadrian ah->ah_getCapability = ar5416GetCapability; 132185377Ssam ah->ah_getDiagState = ar5416GetDiagState; 133185377Ssam ah->ah_setLedState = ar5416SetLedState; 134185377Ssam ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 135185377Ssam ah->ah_gpioCfgInput = ar5416GpioCfgInput; 136185377Ssam ah->ah_gpioGet = ar5416GpioGet; 137185377Ssam ah->ah_gpioSet = ar5416GpioSet; 138185377Ssam ah->ah_gpioSetIntr = ar5416GpioSetIntr; 139185377Ssam ah->ah_resetTsf = ar5416ResetTsf; 140185377Ssam ah->ah_getRfGain = ar5416GetRfgain; 141185377Ssam ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 142185377Ssam ah->ah_setDecompMask = ar5416SetDecompMask; 143185377Ssam ah->ah_setCoverageClass = ar5416SetCoverageClass; 144222644Sadrian ah->ah_setQuiet = ar5416SetQuiet; 145185377Ssam 146185377Ssam ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 147185377Ssam ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 148185377Ssam 149222584Sadrian /* DFS Functions */ 150222584Sadrian ah->ah_enableDfs = ar5416EnableDfs; 151222584Sadrian ah->ah_getDfsThresh = ar5416GetDfsThresh; 152222815Sadrian ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 153224709Sadrian ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 154222584Sadrian 155185377Ssam /* Power Management Functions */ 156185377Ssam ah->ah_setPowerMode = ar5416SetPowerMode; 157185377Ssam 158185377Ssam /* Beacon Management Functions */ 159185377Ssam ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 160185377Ssam ah->ah_beaconInit = ar5416BeaconInit; 161185377Ssam ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 162185377Ssam ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 163185377Ssam 164218066Sadrian /* 802.11n Functions */ 165185377Ssam ah->ah_chainTxDesc = ar5416ChainTxDesc; 166185377Ssam ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 167185377Ssam ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 168185377Ssam ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 169185377Ssam ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 170185377Ssam ah->ah_clr11nAggr = ar5416Clr11nAggr; 171185377Ssam ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 172185377Ssam ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 173185377Ssam ah->ah_set11nMac2040 = ar5416Set11nMac2040; 174185377Ssam ah->ah_get11nRxClear = ar5416Get11nRxClear; 175185377Ssam ah->ah_set11nRxClear = ar5416Set11nRxClear; 176185377Ssam 177185377Ssam /* Interrupt functions */ 178185377Ssam ah->ah_isInterruptPending = ar5416IsInterruptPending; 179185377Ssam ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 180185377Ssam ah->ah_setInterrupts = ar5416SetInterrupts; 181185377Ssam 182185377Ssam ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 183185377Ssam ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 184185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 185185377Ssam ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 186185377Ssam#endif 187185377Ssam ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 188185377Ssam 189219393Sadrian /* Internal ops */ 190189747Ssam AH5416(ah)->ah_writeIni = ar5416WriteIni; 191189747Ssam AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 192219393Sadrian 193220990Sadrian /* Internal baseband ops */ 194220990Sadrian AH5416(ah)->ah_initPLL = ar5416InitPLL; 195220990Sadrian 196219480Sadrian /* Internal calibration ops */ 197219480Sadrian AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 198219480Sadrian 199219393Sadrian /* Internal TX power control related operations */ 200219393Sadrian AH5416(ah)->ah_olcInit = ar5416olcInit; 201219393Sadrian AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 202219393Sadrian AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 203219393Sadrian 204185377Ssam /* 205185377Ssam * Start by setting all Owl devices to 2x2 206185377Ssam */ 207185377Ssam AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 208185377Ssam AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 209218763Sadrian 210218763Sadrian /* Enable all ANI functions to begin with */ 211222276Sadrian AH5416(ah)->ah_ani_function = 0xffffffff; 212222265Sadrian 213222265Sadrian /* Set overridable ANI methods */ 214222265Sadrian AH5212(ah)->ah_aniControl = ar5416AniControl; 215185377Ssam} 216185377Ssam 217188971Ssamuint32_t 218188971Ssamar5416GetRadioRev(struct ath_hal *ah) 219188971Ssam{ 220188971Ssam uint32_t val; 221188971Ssam int i; 222188971Ssam 223188971Ssam /* Read Radio Chip Rev Extract */ 224188971Ssam OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 225188971Ssam for (i = 0; i < 8; i++) 226188971Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 227188971Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 228188971Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 229188971Ssam return ath_hal_reverseBits(val, 8); 230188971Ssam} 231188971Ssam 232185377Ssam/* 233185377Ssam * Attach for an AR5416 part. 234185377Ssam */ 235188972Ssamstatic struct ath_hal * 236185377Ssamar5416Attach(uint16_t devid, HAL_SOFTC sc, 237217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 238217624Sadrian HAL_STATUS *status) 239185377Ssam{ 240185377Ssam struct ath_hal_5416 *ahp5416; 241185377Ssam struct ath_hal_5212 *ahp; 242185377Ssam struct ath_hal *ah; 243185377Ssam uint32_t val; 244185377Ssam HAL_STATUS ecode; 245185377Ssam HAL_BOOL rfStatus; 246185377Ssam 247223466Sadrian HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 248185377Ssam __func__, sc, (void*) st, (void*) sh); 249185377Ssam 250185377Ssam /* NB: memory is returned zero'd */ 251185377Ssam ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 252185377Ssam /* extra space for Owl 2.1/2.2 WAR */ 253185377Ssam sizeof(ar5416Addac) 254185377Ssam ); 255185377Ssam if (ahp5416 == AH_NULL) { 256223466Sadrian HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY, 257185377Ssam "%s: cannot allocate memory for state block\n", __func__); 258185377Ssam *status = HAL_ENOMEM; 259185377Ssam return AH_NULL; 260185377Ssam } 261185377Ssam ar5416InitState(ahp5416, devid, sc, st, sh, status); 262185377Ssam ahp = &ahp5416->ah_5212; 263185377Ssam ah = &ahp->ah_priv.h; 264185377Ssam 265185377Ssam if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 266185377Ssam /* reset chip */ 267185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 268185377Ssam ecode = HAL_EIO; 269185377Ssam goto bad; 270185377Ssam } 271185377Ssam 272185377Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 273185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 274185377Ssam ecode = HAL_EIO; 275185377Ssam goto bad; 276185377Ssam } 277185377Ssam /* Read Revisions from Chips before taking out of reset */ 278185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 279185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 280185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 281188979Ssam AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 282185377Ssam 283185377Ssam /* setup common ini data; rf backends handle remainder */ 284185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 285185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 286185377Ssam 287185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 288185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 289185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 290185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 291185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 292185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 293185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 294185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 295185377Ssam 296219840Sadrian if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 297219839Sadrian ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 298185377Ssam struct ini { 299185377Ssam uint32_t *data; /* NB: !const */ 300185377Ssam int rows, cols; 301185377Ssam }; 302185377Ssam /* override CLKDRV value */ 303185377Ssam OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 304185377Ssam AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 305185377Ssam HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 306185377Ssam } 307185377Ssam 308188979Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 309188979Ssam ar5416AttachPCIE(ah); 310188979Ssam 311188973Ssam ecode = ath_hal_v14EepromAttach(ah); 312188973Ssam if (ecode != HAL_OK) 313188973Ssam goto bad; 314188973Ssam 315185377Ssam if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 316185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 317185377Ssam __func__); 318185377Ssam ecode = HAL_EIO; 319185377Ssam goto bad; 320185377Ssam } 321185377Ssam 322185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 323185377Ssam 324185377Ssam if (!ar5212ChipTest(ah)) { 325185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 326185377Ssam __func__); 327185377Ssam ecode = HAL_ESELFTEST; 328185377Ssam goto bad; 329185377Ssam } 330185377Ssam 331185377Ssam /* 332185377Ssam * Set correct Baseband to analog shift 333185377Ssam * setting to access analog chips. 334185377Ssam */ 335185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 336185377Ssam 337185377Ssam /* Read Radio Chip Rev Extract */ 338185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 339185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 340185377Ssam case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 341185377Ssam case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 342185377Ssam case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 343185377Ssam case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 344185377Ssam break; 345185377Ssam default: 346185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 347185377Ssam /* 348185377Ssam * When RF_Silen is used the analog chip is reset. 349185377Ssam * So when the system boots with radio switch off 350185377Ssam * the RF chip rev reads back as zero and we need 351185377Ssam * to use the mac+phy revs to set the radio rev. 352185377Ssam */ 353185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 354185377Ssam AR_RAD5133_SREV_MAJOR; 355185377Ssam break; 356185377Ssam } 357185377Ssam /* NB: silently accept anything in release code per Atheros */ 358185377Ssam#ifdef AH_DEBUG 359185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 360185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 361185377Ssam "this driver\n", __func__, 362185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 363185377Ssam ecode = HAL_ENOTSUPP; 364185377Ssam goto bad; 365185377Ssam#endif 366185377Ssam } 367185377Ssam 368185377Ssam /* 369185377Ssam * Got everything we need now to setup the capabilities. 370185377Ssam */ 371185377Ssam if (!ar5416FillCapabilityInfo(ah)) { 372185377Ssam ecode = HAL_EEREAD; 373185377Ssam goto bad; 374185377Ssam } 375185377Ssam 376185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 377185377Ssam if (ecode != HAL_OK) { 378185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 379185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 380185377Ssam goto bad; 381185377Ssam } 382185377Ssam /* XXX How about the serial number ? */ 383185377Ssam /* Read Reg Domain */ 384185377Ssam AH_PRIVATE(ah)->ah_currentRD = 385185377Ssam ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 386221596Sadrian AH_PRIVATE(ah)->ah_currentRDext = 387221596Sadrian ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 388185377Ssam 389185377Ssam /* 390185377Ssam * ah_miscMode is populated by ar5416FillCapabilityInfo() 391185377Ssam * starting from griffin. Set here to make sure that 392185377Ssam * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 393185380Ssam * placed into hardware. 394185377Ssam */ 395185377Ssam if (ahp->ah_miscMode != 0) 396219771Sadrian OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 397185377Ssam 398185377Ssam rfStatus = ar2133RfAttach(ah, &ecode); 399185377Ssam if (!rfStatus) { 400185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 401185377Ssam __func__, ecode); 402185377Ssam goto bad; 403185377Ssam } 404185377Ssam 405185377Ssam ar5416AniSetup(ah); /* Anti Noise Immunity */ 406218068Sadrian 407218068Sadrian AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 408218068Sadrian AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 409218068Sadrian AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 410218068Sadrian AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 411218068Sadrian AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 412218068Sadrian AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 413218068Sadrian 414203882Srpaulo ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 415185377Ssam 416185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 417185377Ssam 418185377Ssam return ah; 419185377Ssambad: 420185377Ssam if (ahp) 421185377Ssam ar5416Detach((struct ath_hal *) ahp); 422185377Ssam if (status) 423185377Ssam *status = ecode; 424185377Ssam return AH_NULL; 425185377Ssam} 426185377Ssam 427185377Ssamvoid 428185377Ssamar5416Detach(struct ath_hal *ah) 429185377Ssam{ 430185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 431185377Ssam 432185377Ssam HALASSERT(ah != AH_NULL); 433185377Ssam HALASSERT(ah->ah_magic == AR5416_MAGIC); 434185377Ssam 435221777Sadrian /* Make sure that chip is awake before writing to it */ 436221777Sadrian if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 437221777Sadrian HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 438221777Sadrian "%s: failed to wake up chip\n", 439221777Sadrian __func__); 440221777Sadrian 441185380Ssam ar5416AniDetach(ah); 442185377Ssam ar5212RfDetach(ah); 443185377Ssam ah->ah_disable(ah); 444185377Ssam ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 445185377Ssam ath_hal_eepromDetach(ah); 446185377Ssam ath_hal_free(ah); 447185377Ssam} 448185377Ssam 449188979Ssamvoid 450188979Ssamar5416AttachPCIE(struct ath_hal *ah) 451188979Ssam{ 452188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) 453188979Ssam ath_hal_configPCIE(ah, AH_FALSE); 454188979Ssam else 455188979Ssam ath_hal_disablePCIE(ah); 456188979Ssam} 457188979Ssam 458188979Ssamstatic void 459188979Ssamar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 460188979Ssam{ 461188979Ssam if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 462188979Ssam ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 463188979Ssam OS_DELAY(1000); 464188979Ssam OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 465188979Ssam OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 466188979Ssam } 467188979Ssam} 468188979Ssam 469189747Ssamstatic void 470189747Ssamar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 471189747Ssam{ 472189747Ssam u_int modesIndex, freqIndex; 473189747Ssam int regWrites = 0; 474189747Ssam 475189747Ssam /* Setup the indices for the next set of register array writes */ 476189747Ssam /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 477189747Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 478189747Ssam freqIndex = 2; 479189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 480189747Ssam modesIndex = 3; 481189747Ssam else if (IEEE80211_IS_CHAN_108G(chan)) 482189747Ssam modesIndex = 5; 483189747Ssam else 484189747Ssam modesIndex = 4; 485189747Ssam } else { 486189747Ssam freqIndex = 1; 487189747Ssam if (IEEE80211_IS_CHAN_HT40(chan) || 488189747Ssam IEEE80211_IS_CHAN_TURBO(chan)) 489189747Ssam modesIndex = 2; 490189747Ssam else 491189747Ssam modesIndex = 1; 492189747Ssam } 493189747Ssam 494189747Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 495189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 496189747Ssam 497189747Ssam /* 498189747Ssam * Write addac shifts 499189747Ssam */ 500189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 501219863Sadrian 502189747Ssam /* NB: only required for Sowl */ 503219863Sadrian if (AR_SREV_SOWL(ah)) 504219863Sadrian ar5416EepromSetAddac(ah, chan); 505219863Sadrian 506189747Ssam regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 507189747Ssam regWrites); 508189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 509189747Ssam 510189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 511189747Ssam modesIndex, regWrites); 512189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 513189747Ssam 1, regWrites); 514189747Ssam 515189747Ssam /* XXX updated regWrites? */ 516189747Ssam AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 517189747Ssam} 518189747Ssam 519185377Ssam/* 520189747Ssam * Convert to baseband spur frequency given input channel frequency 521189747Ssam * and compute register settings below. 522189747Ssam */ 523189747Ssam 524189747Ssamstatic void 525189747Ssamar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 526189747Ssam{ 527189747Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 528189747Ssam static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 529189747Ssam AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 530189747Ssam static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 531189747Ssam AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 532189747Ssam static const int inc[4] = { 0, 100, 0, 0 }; 533189747Ssam 534189747Ssam int bb_spur = AR_NO_SPUR; 535189747Ssam int bin, cur_bin; 536189747Ssam int spur_freq_sd; 537189747Ssam int spur_delta_phase; 538189747Ssam int denominator; 539189747Ssam int upper, lower, cur_vit_mask; 540189747Ssam int tmp, new; 541189747Ssam int i; 542189747Ssam 543189747Ssam int8_t mask_m[123]; 544189747Ssam int8_t mask_p[123]; 545189747Ssam int8_t mask_amt; 546189747Ssam int tmp_mask; 547189747Ssam int cur_bb_spur; 548189747Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 549189747Ssam 550189747Ssam OS_MEMZERO(mask_m, sizeof(mask_m)); 551189747Ssam OS_MEMZERO(mask_p, sizeof(mask_p)); 552189747Ssam 553189747Ssam /* 554189747Ssam * Need to verify range +/- 9.5 for static ht20, otherwise spur 555189747Ssam * is out-of-band and can be ignored. 556189747Ssam */ 557189747Ssam /* XXX ath9k changes */ 558189747Ssam for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 559189747Ssam cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 560189747Ssam if (AR_NO_SPUR == cur_bb_spur) 561189747Ssam break; 562189747Ssam cur_bb_spur = cur_bb_spur - (freq * 10); 563189747Ssam if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 564189747Ssam bb_spur = cur_bb_spur; 565189747Ssam break; 566189747Ssam } 567189747Ssam } 568189747Ssam if (AR_NO_SPUR == bb_spur) 569189747Ssam return; 570189747Ssam 571189747Ssam bin = bb_spur * 32; 572189747Ssam 573189747Ssam tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 574189747Ssam new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 575189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 576189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 577189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 578189747Ssam 579189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 580189747Ssam 581189747Ssam new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 582189747Ssam AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 583189747Ssam AR_PHY_SPUR_REG_MASK_RATE_SELECT | 584189747Ssam AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 585189747Ssam SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 586189747Ssam OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 587189747Ssam /* 588189747Ssam * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 589189747Ssam * config, no offset for HT20. 590189747Ssam * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 591189747Ssam * /80 for dyn2040. 592189747Ssam */ 593189747Ssam spur_delta_phase = ((bb_spur * 524288) / 100) & 594189747Ssam AR_PHY_TIMING11_SPUR_DELTA_PHASE; 595189747Ssam /* 596189747Ssam * in 11A mode the denominator of spur_freq_sd should be 40 and 597189747Ssam * it should be 44 in 11G 598189747Ssam */ 599189747Ssam denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 600189747Ssam spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 601189747Ssam 602189747Ssam new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 603189747Ssam SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 604189747Ssam SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 605189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 606189747Ssam 607189747Ssam 608189747Ssam /* 609189747Ssam * ============================================ 610189747Ssam * pilot mask 1 [31:0] = +6..-26, no 0 bin 611189747Ssam * pilot mask 2 [19:0] = +26..+7 612189747Ssam * 613189747Ssam * channel mask 1 [31:0] = +6..-26, no 0 bin 614189747Ssam * channel mask 2 [19:0] = +26..+7 615189747Ssam */ 616189747Ssam //cur_bin = -26; 617189747Ssam cur_bin = -6000; 618189747Ssam upper = bin + 100; 619189747Ssam lower = bin - 100; 620189747Ssam 621189747Ssam for (i = 0; i < 4; i++) { 622189747Ssam int pilot_mask = 0; 623189747Ssam int chan_mask = 0; 624189747Ssam int bp = 0; 625189747Ssam for (bp = 0; bp < 30; bp++) { 626189747Ssam if ((cur_bin > lower) && (cur_bin < upper)) { 627189747Ssam pilot_mask = pilot_mask | 0x1 << bp; 628189747Ssam chan_mask = chan_mask | 0x1 << bp; 629189747Ssam } 630189747Ssam cur_bin += 100; 631189747Ssam } 632189747Ssam cur_bin += inc[i]; 633189747Ssam OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 634189747Ssam OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 635189747Ssam } 636189747Ssam 637189747Ssam /* ================================================= 638189747Ssam * viterbi mask 1 based on channel magnitude 639189747Ssam * four levels 0-3 640189747Ssam * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 641189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 642189747Ssam * - enable_mask_ppm, all bins move with freq 643189747Ssam * 644189747Ssam * - mask_select, 8 bits for rates (reg 67,0x990c) 645189747Ssam * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 646189747Ssam * choose which mask to use mask or mask2 647189747Ssam */ 648189747Ssam 649189747Ssam /* 650189747Ssam * viterbi mask 2 2nd set for per data rate puncturing 651189747Ssam * four levels 0-3 652189747Ssam * - mask_select, 8 bits for rates (reg 67) 653189747Ssam * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 654189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 655189747Ssam */ 656189747Ssam cur_vit_mask = 6100; 657189747Ssam upper = bin + 120; 658189747Ssam lower = bin - 120; 659189747Ssam 660189747Ssam for (i = 0; i < 123; i++) { 661189747Ssam if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 662189747Ssam if ((abs(cur_vit_mask - bin)) < 75) { 663189747Ssam mask_amt = 1; 664189747Ssam } else { 665189747Ssam mask_amt = 0; 666189747Ssam } 667189747Ssam if (cur_vit_mask < 0) { 668189747Ssam mask_m[abs(cur_vit_mask / 100)] = mask_amt; 669189747Ssam } else { 670189747Ssam mask_p[cur_vit_mask / 100] = mask_amt; 671189747Ssam } 672189747Ssam } 673189747Ssam cur_vit_mask -= 100; 674189747Ssam } 675189747Ssam 676189747Ssam tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 677189747Ssam | (mask_m[48] << 26) | (mask_m[49] << 24) 678189747Ssam | (mask_m[50] << 22) | (mask_m[51] << 20) 679189747Ssam | (mask_m[52] << 18) | (mask_m[53] << 16) 680189747Ssam | (mask_m[54] << 14) | (mask_m[55] << 12) 681189747Ssam | (mask_m[56] << 10) | (mask_m[57] << 8) 682189747Ssam | (mask_m[58] << 6) | (mask_m[59] << 4) 683189747Ssam | (mask_m[60] << 2) | (mask_m[61] << 0); 684189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 685189747Ssam OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 686189747Ssam 687189747Ssam tmp_mask = (mask_m[31] << 28) 688189747Ssam | (mask_m[32] << 26) | (mask_m[33] << 24) 689189747Ssam | (mask_m[34] << 22) | (mask_m[35] << 20) 690189747Ssam | (mask_m[36] << 18) | (mask_m[37] << 16) 691189747Ssam | (mask_m[48] << 14) | (mask_m[39] << 12) 692189747Ssam | (mask_m[40] << 10) | (mask_m[41] << 8) 693189747Ssam | (mask_m[42] << 6) | (mask_m[43] << 4) 694189747Ssam | (mask_m[44] << 2) | (mask_m[45] << 0); 695189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 696189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 697189747Ssam 698189747Ssam tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 699189747Ssam | (mask_m[18] << 26) | (mask_m[18] << 24) 700189747Ssam | (mask_m[20] << 22) | (mask_m[20] << 20) 701189747Ssam | (mask_m[22] << 18) | (mask_m[22] << 16) 702189747Ssam | (mask_m[24] << 14) | (mask_m[24] << 12) 703189747Ssam | (mask_m[25] << 10) | (mask_m[26] << 8) 704189747Ssam | (mask_m[27] << 6) | (mask_m[28] << 4) 705189747Ssam | (mask_m[29] << 2) | (mask_m[30] << 0); 706189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 707189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 708189747Ssam 709189747Ssam tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 710189747Ssam | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 711189747Ssam | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 712189747Ssam | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 713189747Ssam | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 714189747Ssam | (mask_m[10] << 10) | (mask_m[11] << 8) 715189747Ssam | (mask_m[12] << 6) | (mask_m[13] << 4) 716189747Ssam | (mask_m[14] << 2) | (mask_m[15] << 0); 717189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 718189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 719189747Ssam 720189747Ssam tmp_mask = (mask_p[15] << 28) 721189747Ssam | (mask_p[14] << 26) | (mask_p[13] << 24) 722189747Ssam | (mask_p[12] << 22) | (mask_p[11] << 20) 723189747Ssam | (mask_p[10] << 18) | (mask_p[ 9] << 16) 724189747Ssam | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 725189747Ssam | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 726189747Ssam | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 727189747Ssam | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 728189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 729189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 730189747Ssam 731189747Ssam tmp_mask = (mask_p[30] << 28) 732189747Ssam | (mask_p[29] << 26) | (mask_p[28] << 24) 733189747Ssam | (mask_p[27] << 22) | (mask_p[26] << 20) 734189747Ssam | (mask_p[25] << 18) | (mask_p[24] << 16) 735189747Ssam | (mask_p[23] << 14) | (mask_p[22] << 12) 736189747Ssam | (mask_p[21] << 10) | (mask_p[20] << 8) 737189747Ssam | (mask_p[19] << 6) | (mask_p[18] << 4) 738189747Ssam | (mask_p[17] << 2) | (mask_p[16] << 0); 739189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 740189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 741189747Ssam 742189747Ssam tmp_mask = (mask_p[45] << 28) 743189747Ssam | (mask_p[44] << 26) | (mask_p[43] << 24) 744189747Ssam | (mask_p[42] << 22) | (mask_p[41] << 20) 745189747Ssam | (mask_p[40] << 18) | (mask_p[39] << 16) 746189747Ssam | (mask_p[38] << 14) | (mask_p[37] << 12) 747189747Ssam | (mask_p[36] << 10) | (mask_p[35] << 8) 748189747Ssam | (mask_p[34] << 6) | (mask_p[33] << 4) 749189747Ssam | (mask_p[32] << 2) | (mask_p[31] << 0); 750189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 751189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 752189747Ssam 753189747Ssam tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 754189747Ssam | (mask_p[59] << 26) | (mask_p[58] << 24) 755189747Ssam | (mask_p[57] << 22) | (mask_p[56] << 20) 756189747Ssam | (mask_p[55] << 18) | (mask_p[54] << 16) 757189747Ssam | (mask_p[53] << 14) | (mask_p[52] << 12) 758189747Ssam | (mask_p[51] << 10) | (mask_p[50] << 8) 759189747Ssam | (mask_p[49] << 6) | (mask_p[48] << 4) 760189747Ssam | (mask_p[47] << 2) | (mask_p[46] << 0); 761189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 762189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 763189747Ssam} 764189747Ssam 765189747Ssam/* 766185377Ssam * Fill all software cached or static hardware state information. 767185377Ssam * Return failure if capabilities are to come from EEPROM and 768185377Ssam * cannot be read. 769185377Ssam */ 770185377SsamHAL_BOOL 771185377Ssamar5416FillCapabilityInfo(struct ath_hal *ah) 772185377Ssam{ 773185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 774185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 775185377Ssam uint16_t val; 776185377Ssam 777185377Ssam /* Construct wireless mode from EEPROM */ 778185377Ssam pCap->halWirelessModes = 0; 779185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 780185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 781185377Ssam | HAL_MODE_11NA_HT20 782185377Ssam | HAL_MODE_11NA_HT40PLUS 783185377Ssam | HAL_MODE_11NA_HT40MINUS 784185377Ssam ; 785185377Ssam } 786185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 787185377Ssam pCap->halWirelessModes |= HAL_MODE_11G 788185377Ssam | HAL_MODE_11NG_HT20 789185377Ssam | HAL_MODE_11NG_HT40PLUS 790185377Ssam | HAL_MODE_11NG_HT40MINUS 791185377Ssam ; 792185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 793185377Ssam | HAL_MODE_11NA_HT20 794185377Ssam | HAL_MODE_11NA_HT40PLUS 795185377Ssam | HAL_MODE_11NA_HT40MINUS 796185377Ssam ; 797185377Ssam } 798185377Ssam 799185377Ssam pCap->halLow2GhzChan = 2312; 800185377Ssam pCap->halHigh2GhzChan = 2732; 801185377Ssam 802185377Ssam pCap->halLow5GhzChan = 4915; 803185377Ssam pCap->halHigh5GhzChan = 6100; 804185377Ssam 805185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 806185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 807185377Ssam pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 808185377Ssam 809185377Ssam pCap->halMicCkipSupport = AH_FALSE; 810185377Ssam pCap->halMicTkipSupport = AH_TRUE; 811185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 812185377Ssam /* 813185377Ssam * Starting with Griffin TX+RX mic keys can be combined 814185377Ssam * in one key cache slot. 815185377Ssam */ 816185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 817185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 818185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 819185377Ssam 820185377Ssam pCap->halCompressSupport = AH_FALSE; 821185377Ssam pCap->halBurstSupport = AH_TRUE; 822185377Ssam pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 823185377Ssam pCap->halChapTuningSupport = AH_TRUE; 824185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 825185377Ssam 826185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 827185377Ssam 828185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 829185377Ssam pCap->halVEOLSupport = AH_TRUE; 830185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 831222020Sadrian pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 832185377Ssam pCap->halTsfAddSupport = AH_TRUE; 833221603Sadrian pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 834185377Ssam 835185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 836185377Ssam pCap->halTotalQueues = val; 837185377Ssam else 838185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 839185377Ssam 840185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 841185377Ssam pCap->halKeyCacheSize = val; 842185377Ssam else 843185377Ssam pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 844185377Ssam 845185377Ssam /* XXX not needed */ 846185377Ssam pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 847185377Ssam pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 848185377Ssam 849185377Ssam pCap->halTstampPrecision = 32; 850185377Ssam pCap->halHwPhyCounterSupport = AH_TRUE; 851192396Ssam pCap->halIntrMask = HAL_INT_COMMON 852192396Ssam | HAL_INT_RX 853192396Ssam | HAL_INT_TX 854192396Ssam | HAL_INT_FATAL 855192396Ssam | HAL_INT_BNR 856192396Ssam | HAL_INT_BMISC 857192396Ssam | HAL_INT_DTIMSYNC 858192396Ssam | HAL_INT_TSFOOR 859192396Ssam | HAL_INT_CST 860192396Ssam | HAL_INT_GTT 861192396Ssam ; 862185377Ssam 863185377Ssam pCap->halFastCCSupport = AH_TRUE; 864185377Ssam pCap->halNumGpioPins = 6; 865185377Ssam pCap->halWowSupport = AH_FALSE; 866185377Ssam pCap->halWowMatchPatternExact = AH_FALSE; 867185377Ssam pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 868185377Ssam pCap->halAutoSleepSupport = AH_FALSE; 869218441Sadrian pCap->hal4kbSplitTransSupport = AH_TRUE; 870220324Sadrian /* Disable this so Block-ACK works correctly */ 871220324Sadrian pCap->halHasRxSelfLinkedTail = AH_FALSE; 872185377Ssam#if 0 /* XXX not yet */ 873185377Ssam pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 874185377Ssam pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 875185377Ssam#endif 876185377Ssam pCap->halHTSupport = AH_TRUE; 877185377Ssam pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 878185377Ssam /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 879185377Ssam pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 880218150Sadrian /* AR5416 may have 3 antennas but is a 2x2 stream device */ 881218150Sadrian pCap->halTxStreams = 2; 882218150Sadrian pCap->halRxStreams = 2; 883185377Ssam pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 884221603Sadrian pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 885185377Ssam pCap->halForcePpmSupport = AH_TRUE; 886185377Ssam pCap->halEnhancedPmSupport = AH_TRUE; 887195114Ssam pCap->halBssidMatchSupport = AH_TRUE; 888221603Sadrian pCap->halGTTSupport = AH_TRUE; 889221603Sadrian pCap->halCSTSupport = AH_TRUE; 890222584Sadrian pCap->halEnhancedDfsSupport = AH_FALSE; 891185377Ssam 892185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 893185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 894185377Ssam /* NB: enabled by default */ 895185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 896185377Ssam pCap->halRfSilentSupport = AH_TRUE; 897185377Ssam } 898185377Ssam 899185377Ssam ahpriv->ah_rxornIsFatal = AH_FALSE; 900185377Ssam 901185377Ssam return AH_TRUE; 902185377Ssam} 903185406Ssam 904185406Ssamstatic const char* 905185406Ssamar5416Probe(uint16_t vendorid, uint16_t devid) 906185406Ssam{ 907185406Ssam if (vendorid == ATHEROS_VENDOR_ID && 908185406Ssam (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 909185406Ssam return "Atheros 5416"; 910185406Ssam return AH_NULL; 911185406Ssam} 912185418SsamAH_CHIP(AR5416, ar5416Probe, ar5416Attach); 913