ar5416_attach.c revision 222020
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17188970Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 222020 2011-05-17 11:52:53Z adrian $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25189747Ssam#include "ah_eeprom_v14.h" 26189747Ssam 27185377Ssam#include "ar5416/ar5416.h" 28185377Ssam#include "ar5416/ar5416reg.h" 29185377Ssam#include "ar5416/ar5416phy.h" 30185377Ssam 31185377Ssam#include "ar5416/ar5416.ini" 32185377Ssam 33188979Ssamstatic void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34189747Ssamstatic void ar5416WriteIni(struct ath_hal *ah, 35189747Ssam const struct ieee80211_channel *chan); 36189747Ssamstatic void ar5416SpurMitigate(struct ath_hal *ah, 37189747Ssam const struct ieee80211_channel *chan); 38188979Ssam 39185377Ssamstatic void 40185377Ssamar5416AniSetup(struct ath_hal *ah) 41185377Ssam{ 42185377Ssam static const struct ar5212AniParams aniparams = { 43185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 46185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 47185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 48185377Ssam .maxSpurImmunityLevel = 2, 49185377Ssam .cycPwrThr1 = { 2, 4, 6 }, 50185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 51185377Ssam .firstep = { 0, 4, 8 }, 52185377Ssam .ofdmTrigHigh = 500, 53185377Ssam .ofdmTrigLow = 200, 54185377Ssam .cckTrigHigh = 200, 55185377Ssam .cckTrigLow = 100, 56185377Ssam .rssiThrHigh = 40, 57185377Ssam .rssiThrLow = 7, 58185377Ssam .period = 100, 59185377Ssam }; 60219979Sadrian /* NB: disable ANI noise immmunity for reliable RIFS rx */ 61219979Sadrian AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL; 62219979Sadrian ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 63185377Ssam} 64185377Ssam 65185377Ssam/* 66219393Sadrian * AR5416 doesn't do OLC or temperature compensation. 67219393Sadrian */ 68219393Sadrianstatic void 69219393Sadrianar5416olcInit(struct ath_hal *ah) 70219393Sadrian{ 71219393Sadrian} 72219393Sadrian 73219393Sadrianstatic void 74219393Sadrianar5416olcTempCompensation(struct ath_hal *ah) 75219393Sadrian{ 76219393Sadrian} 77219393Sadrian 78219393Sadrian/* 79185377Ssam * Attach for an AR5416 part. 80185377Ssam */ 81185377Ssamvoid 82185377Ssamar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 83185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 84185377Ssam{ 85185377Ssam struct ath_hal_5212 *ahp; 86185377Ssam struct ath_hal *ah; 87185377Ssam 88185377Ssam ahp = &ahp5416->ah_5212; 89185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 90185377Ssam ah = &ahp->ah_priv.h; 91185377Ssam 92185377Ssam /* override 5212 methods for our needs */ 93185377Ssam ah->ah_magic = AR5416_MAGIC; 94185377Ssam ah->ah_getRateTable = ar5416GetRateTable; 95185377Ssam ah->ah_detach = ar5416Detach; 96185377Ssam 97185377Ssam /* Reset functions */ 98185377Ssam ah->ah_reset = ar5416Reset; 99185377Ssam ah->ah_phyDisable = ar5416PhyDisable; 100185377Ssam ah->ah_disable = ar5416Disable; 101188979Ssam ah->ah_configPCIE = ar5416ConfigPCIE; 102185377Ssam ah->ah_perCalibration = ar5416PerCalibration; 103185380Ssam ah->ah_perCalibrationN = ar5416PerCalibrationN, 104185380Ssam ah->ah_resetCalValid = ar5416ResetCalValid, 105185377Ssam ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 106203930Srpaulo ah->ah_setTxPower = ar5416SetTransmitPower; 107203930Srpaulo ah->ah_setBoardValues = ar5416SetBoardValues; 108185377Ssam 109185377Ssam /* Transmit functions */ 110185377Ssam ah->ah_stopTxDma = ar5416StopTxDma; 111185377Ssam ah->ah_setupTxDesc = ar5416SetupTxDesc; 112185377Ssam ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 113185377Ssam ah->ah_fillTxDesc = ar5416FillTxDesc; 114185377Ssam ah->ah_procTxDesc = ar5416ProcTxDesc; 115217621Sadrian ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 116219792Sadrian ah->ah_setupTxQueue = ar5416SetupTxQueue; 117219792Sadrian ah->ah_resetTxQueue = ar5416ResetTxQueue; 118185377Ssam 119185377Ssam /* Receive Functions */ 120185377Ssam ah->ah_startPcuReceive = ar5416StartPcuReceive; 121185377Ssam ah->ah_stopPcuReceive = ar5416StopPcuReceive; 122185377Ssam ah->ah_setupRxDesc = ar5416SetupRxDesc; 123185377Ssam ah->ah_procRxDesc = ar5416ProcRxDesc; 124217687Sadrian ah->ah_rxMonitor = ar5416RxMonitor; 125217687Sadrian ah->ah_aniPoll = ar5416AniPoll; 126217687Sadrian ah->ah_procMibEvent = ar5416ProcessMibIntr; 127185377Ssam 128185377Ssam /* Misc Functions */ 129217686Sadrian ah->ah_getCapability = ar5416GetCapability; 130185377Ssam ah->ah_getDiagState = ar5416GetDiagState; 131185377Ssam ah->ah_setLedState = ar5416SetLedState; 132185377Ssam ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 133185377Ssam ah->ah_gpioCfgInput = ar5416GpioCfgInput; 134185377Ssam ah->ah_gpioGet = ar5416GpioGet; 135185377Ssam ah->ah_gpioSet = ar5416GpioSet; 136185377Ssam ah->ah_gpioSetIntr = ar5416GpioSetIntr; 137185377Ssam ah->ah_resetTsf = ar5416ResetTsf; 138185377Ssam ah->ah_getRfGain = ar5416GetRfgain; 139185377Ssam ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 140185377Ssam ah->ah_setDecompMask = ar5416SetDecompMask; 141185377Ssam ah->ah_setCoverageClass = ar5416SetCoverageClass; 142185377Ssam 143185377Ssam ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 144185377Ssam ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 145185377Ssam 146185377Ssam /* Power Management Functions */ 147185377Ssam ah->ah_setPowerMode = ar5416SetPowerMode; 148185377Ssam 149185377Ssam /* Beacon Management Functions */ 150185377Ssam ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 151185377Ssam ah->ah_beaconInit = ar5416BeaconInit; 152185377Ssam ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 153185377Ssam ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 154185377Ssam 155218066Sadrian /* 802.11n Functions */ 156185377Ssam ah->ah_chainTxDesc = ar5416ChainTxDesc; 157185377Ssam ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 158185377Ssam ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 159185377Ssam ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 160185377Ssam ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 161185377Ssam ah->ah_clr11nAggr = ar5416Clr11nAggr; 162185377Ssam ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 163185377Ssam ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 164185377Ssam ah->ah_set11nMac2040 = ar5416Set11nMac2040; 165185377Ssam ah->ah_get11nRxClear = ar5416Get11nRxClear; 166185377Ssam ah->ah_set11nRxClear = ar5416Set11nRxClear; 167185377Ssam 168185377Ssam /* Interrupt functions */ 169185377Ssam ah->ah_isInterruptPending = ar5416IsInterruptPending; 170185377Ssam ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 171185377Ssam ah->ah_setInterrupts = ar5416SetInterrupts; 172185377Ssam 173185377Ssam ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 174185377Ssam ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 175185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 176185377Ssam ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 177185377Ssam#endif 178185377Ssam ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 179185377Ssam 180219393Sadrian /* Internal ops */ 181189747Ssam AH5416(ah)->ah_writeIni = ar5416WriteIni; 182189747Ssam AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 183219393Sadrian 184220990Sadrian /* Internal baseband ops */ 185220990Sadrian AH5416(ah)->ah_initPLL = ar5416InitPLL; 186220990Sadrian 187219480Sadrian /* Internal calibration ops */ 188219480Sadrian AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 189219480Sadrian 190219393Sadrian /* Internal TX power control related operations */ 191219393Sadrian AH5416(ah)->ah_olcInit = ar5416olcInit; 192219393Sadrian AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 193219393Sadrian AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 194219393Sadrian 195185377Ssam /* 196185377Ssam * Start by setting all Owl devices to 2x2 197185377Ssam */ 198185377Ssam AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 199185377Ssam AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 200218763Sadrian 201218763Sadrian /* Enable all ANI functions to begin with */ 202218763Sadrian AH5416(ah)->ah_ani_function = HAL_ANI_ALL; 203185377Ssam} 204185377Ssam 205188971Ssamuint32_t 206188971Ssamar5416GetRadioRev(struct ath_hal *ah) 207188971Ssam{ 208188971Ssam uint32_t val; 209188971Ssam int i; 210188971Ssam 211188971Ssam /* Read Radio Chip Rev Extract */ 212188971Ssam OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 213188971Ssam for (i = 0; i < 8; i++) 214188971Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 215188971Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 216188971Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 217188971Ssam return ath_hal_reverseBits(val, 8); 218188971Ssam} 219188971Ssam 220185377Ssam/* 221185377Ssam * Attach for an AR5416 part. 222185377Ssam */ 223188972Ssamstatic struct ath_hal * 224185377Ssamar5416Attach(uint16_t devid, HAL_SOFTC sc, 225217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 226217624Sadrian HAL_STATUS *status) 227185377Ssam{ 228185377Ssam struct ath_hal_5416 *ahp5416; 229185377Ssam struct ath_hal_5212 *ahp; 230185377Ssam struct ath_hal *ah; 231185377Ssam uint32_t val; 232185377Ssam HAL_STATUS ecode; 233185377Ssam HAL_BOOL rfStatus; 234185377Ssam 235185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 236185377Ssam __func__, sc, (void*) st, (void*) sh); 237185377Ssam 238185377Ssam /* NB: memory is returned zero'd */ 239185377Ssam ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 240185377Ssam /* extra space for Owl 2.1/2.2 WAR */ 241185377Ssam sizeof(ar5416Addac) 242185377Ssam ); 243185377Ssam if (ahp5416 == AH_NULL) { 244185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 245185377Ssam "%s: cannot allocate memory for state block\n", __func__); 246185377Ssam *status = HAL_ENOMEM; 247185377Ssam return AH_NULL; 248185377Ssam } 249185377Ssam ar5416InitState(ahp5416, devid, sc, st, sh, status); 250185377Ssam ahp = &ahp5416->ah_5212; 251185377Ssam ah = &ahp->ah_priv.h; 252185377Ssam 253185377Ssam if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 254185377Ssam /* reset chip */ 255185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 256185377Ssam ecode = HAL_EIO; 257185377Ssam goto bad; 258185377Ssam } 259185377Ssam 260185377Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 261185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 262185377Ssam ecode = HAL_EIO; 263185377Ssam goto bad; 264185377Ssam } 265185377Ssam /* Read Revisions from Chips before taking out of reset */ 266185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 267185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 268185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 269188979Ssam AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 270185377Ssam 271185377Ssam /* setup common ini data; rf backends handle remainder */ 272185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 273185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 274185377Ssam 275185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 276185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 277185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 278185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 279185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 280185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 281185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 282185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 283185377Ssam 284219840Sadrian if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 285219839Sadrian ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 286185377Ssam struct ini { 287185377Ssam uint32_t *data; /* NB: !const */ 288185377Ssam int rows, cols; 289185377Ssam }; 290185377Ssam /* override CLKDRV value */ 291185377Ssam OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 292185377Ssam AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 293185377Ssam HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 294185377Ssam } 295185377Ssam 296188979Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 297188979Ssam ar5416AttachPCIE(ah); 298188979Ssam 299188973Ssam ecode = ath_hal_v14EepromAttach(ah); 300188973Ssam if (ecode != HAL_OK) 301188973Ssam goto bad; 302188973Ssam 303185377Ssam if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 304185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 305185377Ssam __func__); 306185377Ssam ecode = HAL_EIO; 307185377Ssam goto bad; 308185377Ssam } 309185377Ssam 310185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 311185377Ssam 312185377Ssam if (!ar5212ChipTest(ah)) { 313185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 314185377Ssam __func__); 315185377Ssam ecode = HAL_ESELFTEST; 316185377Ssam goto bad; 317185377Ssam } 318185377Ssam 319185377Ssam /* 320185377Ssam * Set correct Baseband to analog shift 321185377Ssam * setting to access analog chips. 322185377Ssam */ 323185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 324185377Ssam 325185377Ssam /* Read Radio Chip Rev Extract */ 326185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 327185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 328185377Ssam case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 329185377Ssam case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 330185377Ssam case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 331185377Ssam case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 332185377Ssam break; 333185377Ssam default: 334185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 335185377Ssam /* 336185377Ssam * When RF_Silen is used the analog chip is reset. 337185377Ssam * So when the system boots with radio switch off 338185377Ssam * the RF chip rev reads back as zero and we need 339185377Ssam * to use the mac+phy revs to set the radio rev. 340185377Ssam */ 341185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 342185377Ssam AR_RAD5133_SREV_MAJOR; 343185377Ssam break; 344185377Ssam } 345185377Ssam /* NB: silently accept anything in release code per Atheros */ 346185377Ssam#ifdef AH_DEBUG 347185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 348185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 349185377Ssam "this driver\n", __func__, 350185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 351185377Ssam ecode = HAL_ENOTSUPP; 352185377Ssam goto bad; 353185377Ssam#endif 354185377Ssam } 355185377Ssam 356185377Ssam /* 357185377Ssam * Got everything we need now to setup the capabilities. 358185377Ssam */ 359185377Ssam if (!ar5416FillCapabilityInfo(ah)) { 360185377Ssam ecode = HAL_EEREAD; 361185377Ssam goto bad; 362185377Ssam } 363185377Ssam 364185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 365185377Ssam if (ecode != HAL_OK) { 366185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 367185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 368185377Ssam goto bad; 369185377Ssam } 370185377Ssam /* XXX How about the serial number ? */ 371185377Ssam /* Read Reg Domain */ 372185377Ssam AH_PRIVATE(ah)->ah_currentRD = 373185377Ssam ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 374221596Sadrian AH_PRIVATE(ah)->ah_currentRDext = 375221596Sadrian ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 376185377Ssam 377185377Ssam /* 378185377Ssam * ah_miscMode is populated by ar5416FillCapabilityInfo() 379185377Ssam * starting from griffin. Set here to make sure that 380185377Ssam * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 381185380Ssam * placed into hardware. 382185377Ssam */ 383185377Ssam if (ahp->ah_miscMode != 0) 384219771Sadrian OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 385185377Ssam 386185377Ssam rfStatus = ar2133RfAttach(ah, &ecode); 387185377Ssam if (!rfStatus) { 388185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 389185377Ssam __func__, ecode); 390185377Ssam goto bad; 391185377Ssam } 392185377Ssam 393185377Ssam ar5416AniSetup(ah); /* Anti Noise Immunity */ 394218068Sadrian 395218068Sadrian AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 396218068Sadrian AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 397218068Sadrian AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 398218068Sadrian AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 399218068Sadrian AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 400218068Sadrian AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 401218068Sadrian 402203882Srpaulo ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 403185377Ssam 404185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 405185377Ssam 406185377Ssam return ah; 407185377Ssambad: 408185377Ssam if (ahp) 409185377Ssam ar5416Detach((struct ath_hal *) ahp); 410185377Ssam if (status) 411185377Ssam *status = ecode; 412185377Ssam return AH_NULL; 413185377Ssam} 414185377Ssam 415185377Ssamvoid 416185377Ssamar5416Detach(struct ath_hal *ah) 417185377Ssam{ 418185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 419185377Ssam 420185377Ssam HALASSERT(ah != AH_NULL); 421185377Ssam HALASSERT(ah->ah_magic == AR5416_MAGIC); 422185377Ssam 423221777Sadrian /* Make sure that chip is awake before writing to it */ 424221777Sadrian if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 425221777Sadrian HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 426221777Sadrian "%s: failed to wake up chip\n", 427221777Sadrian __func__); 428221777Sadrian 429185380Ssam ar5416AniDetach(ah); 430185377Ssam ar5212RfDetach(ah); 431185377Ssam ah->ah_disable(ah); 432185377Ssam ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 433185377Ssam ath_hal_eepromDetach(ah); 434185377Ssam ath_hal_free(ah); 435185377Ssam} 436185377Ssam 437188979Ssamvoid 438188979Ssamar5416AttachPCIE(struct ath_hal *ah) 439188979Ssam{ 440188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) 441188979Ssam ath_hal_configPCIE(ah, AH_FALSE); 442188979Ssam else 443188979Ssam ath_hal_disablePCIE(ah); 444188979Ssam} 445188979Ssam 446188979Ssamstatic void 447188979Ssamar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 448188979Ssam{ 449188979Ssam if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 450188979Ssam ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 451188979Ssam OS_DELAY(1000); 452188979Ssam OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 453188979Ssam OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 454188979Ssam } 455188979Ssam} 456188979Ssam 457189747Ssamstatic void 458189747Ssamar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 459189747Ssam{ 460189747Ssam u_int modesIndex, freqIndex; 461189747Ssam int regWrites = 0; 462189747Ssam 463189747Ssam /* Setup the indices for the next set of register array writes */ 464189747Ssam /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 465189747Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 466189747Ssam freqIndex = 2; 467189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 468189747Ssam modesIndex = 3; 469189747Ssam else if (IEEE80211_IS_CHAN_108G(chan)) 470189747Ssam modesIndex = 5; 471189747Ssam else 472189747Ssam modesIndex = 4; 473189747Ssam } else { 474189747Ssam freqIndex = 1; 475189747Ssam if (IEEE80211_IS_CHAN_HT40(chan) || 476189747Ssam IEEE80211_IS_CHAN_TURBO(chan)) 477189747Ssam modesIndex = 2; 478189747Ssam else 479189747Ssam modesIndex = 1; 480189747Ssam } 481189747Ssam 482189747Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 483189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 484189747Ssam 485189747Ssam /* 486189747Ssam * Write addac shifts 487189747Ssam */ 488189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 489219863Sadrian 490189747Ssam /* NB: only required for Sowl */ 491219863Sadrian if (AR_SREV_SOWL(ah)) 492219863Sadrian ar5416EepromSetAddac(ah, chan); 493219863Sadrian 494189747Ssam regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 495189747Ssam regWrites); 496189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 497189747Ssam 498189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 499189747Ssam modesIndex, regWrites); 500189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 501189747Ssam 1, regWrites); 502189747Ssam 503189747Ssam /* XXX updated regWrites? */ 504189747Ssam AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 505189747Ssam} 506189747Ssam 507185377Ssam/* 508189747Ssam * Convert to baseband spur frequency given input channel frequency 509189747Ssam * and compute register settings below. 510189747Ssam */ 511189747Ssam 512189747Ssamstatic void 513189747Ssamar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 514189747Ssam{ 515189747Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 516189747Ssam static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 517189747Ssam AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 518189747Ssam static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 519189747Ssam AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 520189747Ssam static const int inc[4] = { 0, 100, 0, 0 }; 521189747Ssam 522189747Ssam int bb_spur = AR_NO_SPUR; 523189747Ssam int bin, cur_bin; 524189747Ssam int spur_freq_sd; 525189747Ssam int spur_delta_phase; 526189747Ssam int denominator; 527189747Ssam int upper, lower, cur_vit_mask; 528189747Ssam int tmp, new; 529189747Ssam int i; 530189747Ssam 531189747Ssam int8_t mask_m[123]; 532189747Ssam int8_t mask_p[123]; 533189747Ssam int8_t mask_amt; 534189747Ssam int tmp_mask; 535189747Ssam int cur_bb_spur; 536189747Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 537189747Ssam 538189747Ssam OS_MEMZERO(mask_m, sizeof(mask_m)); 539189747Ssam OS_MEMZERO(mask_p, sizeof(mask_p)); 540189747Ssam 541189747Ssam /* 542189747Ssam * Need to verify range +/- 9.5 for static ht20, otherwise spur 543189747Ssam * is out-of-band and can be ignored. 544189747Ssam */ 545189747Ssam /* XXX ath9k changes */ 546189747Ssam for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 547189747Ssam cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 548189747Ssam if (AR_NO_SPUR == cur_bb_spur) 549189747Ssam break; 550189747Ssam cur_bb_spur = cur_bb_spur - (freq * 10); 551189747Ssam if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 552189747Ssam bb_spur = cur_bb_spur; 553189747Ssam break; 554189747Ssam } 555189747Ssam } 556189747Ssam if (AR_NO_SPUR == bb_spur) 557189747Ssam return; 558189747Ssam 559189747Ssam bin = bb_spur * 32; 560189747Ssam 561189747Ssam tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 562189747Ssam new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 563189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 564189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 565189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 566189747Ssam 567189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 568189747Ssam 569189747Ssam new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 570189747Ssam AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 571189747Ssam AR_PHY_SPUR_REG_MASK_RATE_SELECT | 572189747Ssam AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 573189747Ssam SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 574189747Ssam OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 575189747Ssam /* 576189747Ssam * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 577189747Ssam * config, no offset for HT20. 578189747Ssam * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 579189747Ssam * /80 for dyn2040. 580189747Ssam */ 581189747Ssam spur_delta_phase = ((bb_spur * 524288) / 100) & 582189747Ssam AR_PHY_TIMING11_SPUR_DELTA_PHASE; 583189747Ssam /* 584189747Ssam * in 11A mode the denominator of spur_freq_sd should be 40 and 585189747Ssam * it should be 44 in 11G 586189747Ssam */ 587189747Ssam denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 588189747Ssam spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 589189747Ssam 590189747Ssam new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 591189747Ssam SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 592189747Ssam SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 593189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 594189747Ssam 595189747Ssam 596189747Ssam /* 597189747Ssam * ============================================ 598189747Ssam * pilot mask 1 [31:0] = +6..-26, no 0 bin 599189747Ssam * pilot mask 2 [19:0] = +26..+7 600189747Ssam * 601189747Ssam * channel mask 1 [31:0] = +6..-26, no 0 bin 602189747Ssam * channel mask 2 [19:0] = +26..+7 603189747Ssam */ 604189747Ssam //cur_bin = -26; 605189747Ssam cur_bin = -6000; 606189747Ssam upper = bin + 100; 607189747Ssam lower = bin - 100; 608189747Ssam 609189747Ssam for (i = 0; i < 4; i++) { 610189747Ssam int pilot_mask = 0; 611189747Ssam int chan_mask = 0; 612189747Ssam int bp = 0; 613189747Ssam for (bp = 0; bp < 30; bp++) { 614189747Ssam if ((cur_bin > lower) && (cur_bin < upper)) { 615189747Ssam pilot_mask = pilot_mask | 0x1 << bp; 616189747Ssam chan_mask = chan_mask | 0x1 << bp; 617189747Ssam } 618189747Ssam cur_bin += 100; 619189747Ssam } 620189747Ssam cur_bin += inc[i]; 621189747Ssam OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 622189747Ssam OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 623189747Ssam } 624189747Ssam 625189747Ssam /* ================================================= 626189747Ssam * viterbi mask 1 based on channel magnitude 627189747Ssam * four levels 0-3 628189747Ssam * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 629189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 630189747Ssam * - enable_mask_ppm, all bins move with freq 631189747Ssam * 632189747Ssam * - mask_select, 8 bits for rates (reg 67,0x990c) 633189747Ssam * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 634189747Ssam * choose which mask to use mask or mask2 635189747Ssam */ 636189747Ssam 637189747Ssam /* 638189747Ssam * viterbi mask 2 2nd set for per data rate puncturing 639189747Ssam * four levels 0-3 640189747Ssam * - mask_select, 8 bits for rates (reg 67) 641189747Ssam * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 642189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 643189747Ssam */ 644189747Ssam cur_vit_mask = 6100; 645189747Ssam upper = bin + 120; 646189747Ssam lower = bin - 120; 647189747Ssam 648189747Ssam for (i = 0; i < 123; i++) { 649189747Ssam if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 650189747Ssam if ((abs(cur_vit_mask - bin)) < 75) { 651189747Ssam mask_amt = 1; 652189747Ssam } else { 653189747Ssam mask_amt = 0; 654189747Ssam } 655189747Ssam if (cur_vit_mask < 0) { 656189747Ssam mask_m[abs(cur_vit_mask / 100)] = mask_amt; 657189747Ssam } else { 658189747Ssam mask_p[cur_vit_mask / 100] = mask_amt; 659189747Ssam } 660189747Ssam } 661189747Ssam cur_vit_mask -= 100; 662189747Ssam } 663189747Ssam 664189747Ssam tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 665189747Ssam | (mask_m[48] << 26) | (mask_m[49] << 24) 666189747Ssam | (mask_m[50] << 22) | (mask_m[51] << 20) 667189747Ssam | (mask_m[52] << 18) | (mask_m[53] << 16) 668189747Ssam | (mask_m[54] << 14) | (mask_m[55] << 12) 669189747Ssam | (mask_m[56] << 10) | (mask_m[57] << 8) 670189747Ssam | (mask_m[58] << 6) | (mask_m[59] << 4) 671189747Ssam | (mask_m[60] << 2) | (mask_m[61] << 0); 672189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 673189747Ssam OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 674189747Ssam 675189747Ssam tmp_mask = (mask_m[31] << 28) 676189747Ssam | (mask_m[32] << 26) | (mask_m[33] << 24) 677189747Ssam | (mask_m[34] << 22) | (mask_m[35] << 20) 678189747Ssam | (mask_m[36] << 18) | (mask_m[37] << 16) 679189747Ssam | (mask_m[48] << 14) | (mask_m[39] << 12) 680189747Ssam | (mask_m[40] << 10) | (mask_m[41] << 8) 681189747Ssam | (mask_m[42] << 6) | (mask_m[43] << 4) 682189747Ssam | (mask_m[44] << 2) | (mask_m[45] << 0); 683189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 684189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 685189747Ssam 686189747Ssam tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 687189747Ssam | (mask_m[18] << 26) | (mask_m[18] << 24) 688189747Ssam | (mask_m[20] << 22) | (mask_m[20] << 20) 689189747Ssam | (mask_m[22] << 18) | (mask_m[22] << 16) 690189747Ssam | (mask_m[24] << 14) | (mask_m[24] << 12) 691189747Ssam | (mask_m[25] << 10) | (mask_m[26] << 8) 692189747Ssam | (mask_m[27] << 6) | (mask_m[28] << 4) 693189747Ssam | (mask_m[29] << 2) | (mask_m[30] << 0); 694189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 695189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 696189747Ssam 697189747Ssam tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 698189747Ssam | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 699189747Ssam | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 700189747Ssam | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 701189747Ssam | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 702189747Ssam | (mask_m[10] << 10) | (mask_m[11] << 8) 703189747Ssam | (mask_m[12] << 6) | (mask_m[13] << 4) 704189747Ssam | (mask_m[14] << 2) | (mask_m[15] << 0); 705189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 706189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 707189747Ssam 708189747Ssam tmp_mask = (mask_p[15] << 28) 709189747Ssam | (mask_p[14] << 26) | (mask_p[13] << 24) 710189747Ssam | (mask_p[12] << 22) | (mask_p[11] << 20) 711189747Ssam | (mask_p[10] << 18) | (mask_p[ 9] << 16) 712189747Ssam | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 713189747Ssam | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 714189747Ssam | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 715189747Ssam | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 716189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 717189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 718189747Ssam 719189747Ssam tmp_mask = (mask_p[30] << 28) 720189747Ssam | (mask_p[29] << 26) | (mask_p[28] << 24) 721189747Ssam | (mask_p[27] << 22) | (mask_p[26] << 20) 722189747Ssam | (mask_p[25] << 18) | (mask_p[24] << 16) 723189747Ssam | (mask_p[23] << 14) | (mask_p[22] << 12) 724189747Ssam | (mask_p[21] << 10) | (mask_p[20] << 8) 725189747Ssam | (mask_p[19] << 6) | (mask_p[18] << 4) 726189747Ssam | (mask_p[17] << 2) | (mask_p[16] << 0); 727189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 728189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 729189747Ssam 730189747Ssam tmp_mask = (mask_p[45] << 28) 731189747Ssam | (mask_p[44] << 26) | (mask_p[43] << 24) 732189747Ssam | (mask_p[42] << 22) | (mask_p[41] << 20) 733189747Ssam | (mask_p[40] << 18) | (mask_p[39] << 16) 734189747Ssam | (mask_p[38] << 14) | (mask_p[37] << 12) 735189747Ssam | (mask_p[36] << 10) | (mask_p[35] << 8) 736189747Ssam | (mask_p[34] << 6) | (mask_p[33] << 4) 737189747Ssam | (mask_p[32] << 2) | (mask_p[31] << 0); 738189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 739189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 740189747Ssam 741189747Ssam tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 742189747Ssam | (mask_p[59] << 26) | (mask_p[58] << 24) 743189747Ssam | (mask_p[57] << 22) | (mask_p[56] << 20) 744189747Ssam | (mask_p[55] << 18) | (mask_p[54] << 16) 745189747Ssam | (mask_p[53] << 14) | (mask_p[52] << 12) 746189747Ssam | (mask_p[51] << 10) | (mask_p[50] << 8) 747189747Ssam | (mask_p[49] << 6) | (mask_p[48] << 4) 748189747Ssam | (mask_p[47] << 2) | (mask_p[46] << 0); 749189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 750189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 751189747Ssam} 752189747Ssam 753189747Ssam/* 754185377Ssam * Fill all software cached or static hardware state information. 755185377Ssam * Return failure if capabilities are to come from EEPROM and 756185377Ssam * cannot be read. 757185377Ssam */ 758185377SsamHAL_BOOL 759185377Ssamar5416FillCapabilityInfo(struct ath_hal *ah) 760185377Ssam{ 761185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 762185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 763185377Ssam uint16_t val; 764185377Ssam 765185377Ssam /* Construct wireless mode from EEPROM */ 766185377Ssam pCap->halWirelessModes = 0; 767185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 768185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 769185377Ssam | HAL_MODE_11NA_HT20 770185377Ssam | HAL_MODE_11NA_HT40PLUS 771185377Ssam | HAL_MODE_11NA_HT40MINUS 772185377Ssam ; 773185377Ssam } 774185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 775185377Ssam pCap->halWirelessModes |= HAL_MODE_11G 776185377Ssam | HAL_MODE_11NG_HT20 777185377Ssam | HAL_MODE_11NG_HT40PLUS 778185377Ssam | HAL_MODE_11NG_HT40MINUS 779185377Ssam ; 780185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 781185377Ssam | HAL_MODE_11NA_HT20 782185377Ssam | HAL_MODE_11NA_HT40PLUS 783185377Ssam | HAL_MODE_11NA_HT40MINUS 784185377Ssam ; 785185377Ssam } 786185377Ssam 787185377Ssam pCap->halLow2GhzChan = 2312; 788185377Ssam pCap->halHigh2GhzChan = 2732; 789185377Ssam 790185377Ssam pCap->halLow5GhzChan = 4915; 791185377Ssam pCap->halHigh5GhzChan = 6100; 792185377Ssam 793185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 794185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 795185377Ssam pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 796185377Ssam 797185377Ssam pCap->halMicCkipSupport = AH_FALSE; 798185377Ssam pCap->halMicTkipSupport = AH_TRUE; 799185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 800185377Ssam /* 801185377Ssam * Starting with Griffin TX+RX mic keys can be combined 802185377Ssam * in one key cache slot. 803185377Ssam */ 804185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 805185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 806185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 807185377Ssam 808185377Ssam pCap->halCompressSupport = AH_FALSE; 809185377Ssam pCap->halBurstSupport = AH_TRUE; 810185377Ssam pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 811185377Ssam pCap->halChapTuningSupport = AH_TRUE; 812185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 813185377Ssam 814185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 815185377Ssam 816185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 817185377Ssam pCap->halVEOLSupport = AH_TRUE; 818185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 819222020Sadrian pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 820185377Ssam pCap->halTsfAddSupport = AH_TRUE; 821221603Sadrian pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 822185377Ssam 823185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 824185377Ssam pCap->halTotalQueues = val; 825185377Ssam else 826185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 827185377Ssam 828185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 829185377Ssam pCap->halKeyCacheSize = val; 830185377Ssam else 831185377Ssam pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 832185377Ssam 833185377Ssam /* XXX not needed */ 834185377Ssam pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 835185377Ssam pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 836185377Ssam 837185377Ssam pCap->halTstampPrecision = 32; 838185377Ssam pCap->halHwPhyCounterSupport = AH_TRUE; 839192396Ssam pCap->halIntrMask = HAL_INT_COMMON 840192396Ssam | HAL_INT_RX 841192396Ssam | HAL_INT_TX 842192396Ssam | HAL_INT_FATAL 843192396Ssam | HAL_INT_BNR 844192396Ssam | HAL_INT_BMISC 845192396Ssam | HAL_INT_DTIMSYNC 846192396Ssam | HAL_INT_TSFOOR 847192396Ssam | HAL_INT_CST 848192396Ssam | HAL_INT_GTT 849192396Ssam ; 850185377Ssam 851185377Ssam pCap->halFastCCSupport = AH_TRUE; 852185377Ssam pCap->halNumGpioPins = 6; 853185377Ssam pCap->halWowSupport = AH_FALSE; 854185377Ssam pCap->halWowMatchPatternExact = AH_FALSE; 855185377Ssam pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 856185377Ssam pCap->halAutoSleepSupport = AH_FALSE; 857218441Sadrian pCap->hal4kbSplitTransSupport = AH_TRUE; 858220324Sadrian /* Disable this so Block-ACK works correctly */ 859220324Sadrian pCap->halHasRxSelfLinkedTail = AH_FALSE; 860185377Ssam#if 0 /* XXX not yet */ 861185377Ssam pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 862185377Ssam pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 863185377Ssam#endif 864185377Ssam pCap->halHTSupport = AH_TRUE; 865185377Ssam pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 866185377Ssam /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 867185377Ssam pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 868218150Sadrian /* AR5416 may have 3 antennas but is a 2x2 stream device */ 869218150Sadrian pCap->halTxStreams = 2; 870218150Sadrian pCap->halRxStreams = 2; 871185377Ssam pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 872221603Sadrian pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 873185377Ssam pCap->halForcePpmSupport = AH_TRUE; 874185377Ssam pCap->halEnhancedPmSupport = AH_TRUE; 875195114Ssam pCap->halBssidMatchSupport = AH_TRUE; 876221603Sadrian pCap->halGTTSupport = AH_TRUE; 877221603Sadrian pCap->halCSTSupport = AH_TRUE; 878185377Ssam 879185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 880185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 881185377Ssam /* NB: enabled by default */ 882185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 883185377Ssam pCap->halRfSilentSupport = AH_TRUE; 884185377Ssam } 885185377Ssam 886185377Ssam ahpriv->ah_rxornIsFatal = AH_FALSE; 887185377Ssam 888185377Ssam return AH_TRUE; 889185377Ssam} 890185406Ssam 891185406Ssamstatic const char* 892185406Ssamar5416Probe(uint16_t vendorid, uint16_t devid) 893185406Ssam{ 894185406Ssam if (vendorid == ATHEROS_VENDOR_ID && 895185406Ssam (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 896185406Ssam return "Atheros 5416"; 897185406Ssam return AH_NULL; 898185406Ssam} 899185418SsamAH_CHIP(AR5416, ar5416Probe, ar5416Attach); 900