ar5416_attach.c revision 219480
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17188970Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 219480 2011-03-11 11:35:36Z adrian $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25189747Ssam#include "ah_eeprom_v14.h" 26189747Ssam 27185377Ssam#include "ar5416/ar5416.h" 28185377Ssam#include "ar5416/ar5416reg.h" 29185377Ssam#include "ar5416/ar5416phy.h" 30185377Ssam 31185377Ssam#include "ar5416/ar5416.ini" 32185377Ssam 33188979Ssamstatic void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34189747Ssamstatic void ar5416WriteIni(struct ath_hal *ah, 35189747Ssam const struct ieee80211_channel *chan); 36189747Ssamstatic void ar5416SpurMitigate(struct ath_hal *ah, 37189747Ssam const struct ieee80211_channel *chan); 38188979Ssam 39185377Ssamstatic void 40185377Ssamar5416AniSetup(struct ath_hal *ah) 41185377Ssam{ 42185377Ssam static const struct ar5212AniParams aniparams = { 43185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 46185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 47185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 48185377Ssam .maxSpurImmunityLevel = 2, 49185377Ssam .cycPwrThr1 = { 2, 4, 6 }, 50185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 51185377Ssam .firstep = { 0, 4, 8 }, 52185377Ssam .ofdmTrigHigh = 500, 53185377Ssam .ofdmTrigLow = 200, 54185377Ssam .cckTrigHigh = 200, 55185377Ssam .cckTrigLow = 100, 56185377Ssam .rssiThrHigh = 40, 57185377Ssam .rssiThrLow = 7, 58185377Ssam .period = 100, 59185377Ssam }; 60185377Ssam /* NB: ANI is not enabled yet */ 61218762Sadrian ar5416AniAttach(ah, &aniparams, &aniparams, AH_FALSE); 62185377Ssam} 63185377Ssam 64185377Ssam/* 65219393Sadrian * AR5416 doesn't do OLC or temperature compensation. 66219393Sadrian */ 67219393Sadrianstatic void 68219393Sadrianar5416olcInit(struct ath_hal *ah) 69219393Sadrian{ 70219393Sadrian} 71219393Sadrian 72219393Sadrianstatic void 73219393Sadrianar5416olcTempCompensation(struct ath_hal *ah) 74219393Sadrian{ 75219393Sadrian} 76219393Sadrian 77219393Sadrian/* 78185377Ssam * Attach for an AR5416 part. 79185377Ssam */ 80185377Ssamvoid 81185377Ssamar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 82185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 83185377Ssam{ 84185377Ssam struct ath_hal_5212 *ahp; 85185377Ssam struct ath_hal *ah; 86185377Ssam 87185377Ssam ahp = &ahp5416->ah_5212; 88185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 89185377Ssam ah = &ahp->ah_priv.h; 90185377Ssam 91185377Ssam /* override 5212 methods for our needs */ 92185377Ssam ah->ah_magic = AR5416_MAGIC; 93185377Ssam ah->ah_getRateTable = ar5416GetRateTable; 94185377Ssam ah->ah_detach = ar5416Detach; 95185377Ssam 96185377Ssam /* Reset functions */ 97185377Ssam ah->ah_reset = ar5416Reset; 98185377Ssam ah->ah_phyDisable = ar5416PhyDisable; 99185377Ssam ah->ah_disable = ar5416Disable; 100188979Ssam ah->ah_configPCIE = ar5416ConfigPCIE; 101185377Ssam ah->ah_perCalibration = ar5416PerCalibration; 102185380Ssam ah->ah_perCalibrationN = ar5416PerCalibrationN, 103185380Ssam ah->ah_resetCalValid = ar5416ResetCalValid, 104185377Ssam ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 105203930Srpaulo ah->ah_setTxPower = ar5416SetTransmitPower; 106203930Srpaulo ah->ah_setBoardValues = ar5416SetBoardValues; 107185377Ssam 108185377Ssam /* Transmit functions */ 109185377Ssam ah->ah_stopTxDma = ar5416StopTxDma; 110185377Ssam ah->ah_setupTxDesc = ar5416SetupTxDesc; 111185377Ssam ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 112185377Ssam ah->ah_fillTxDesc = ar5416FillTxDesc; 113185377Ssam ah->ah_procTxDesc = ar5416ProcTxDesc; 114217621Sadrian ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 115185377Ssam 116185377Ssam /* Receive Functions */ 117185377Ssam ah->ah_startPcuReceive = ar5416StartPcuReceive; 118185377Ssam ah->ah_stopPcuReceive = ar5416StopPcuReceive; 119185377Ssam ah->ah_setupRxDesc = ar5416SetupRxDesc; 120185377Ssam ah->ah_procRxDesc = ar5416ProcRxDesc; 121217687Sadrian ah->ah_rxMonitor = ar5416RxMonitor; 122217687Sadrian ah->ah_aniPoll = ar5416AniPoll; 123217687Sadrian ah->ah_procMibEvent = ar5416ProcessMibIntr; 124185377Ssam 125185377Ssam /* Misc Functions */ 126217686Sadrian ah->ah_getCapability = ar5416GetCapability; 127185377Ssam ah->ah_getDiagState = ar5416GetDiagState; 128185377Ssam ah->ah_setLedState = ar5416SetLedState; 129185377Ssam ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 130185377Ssam ah->ah_gpioCfgInput = ar5416GpioCfgInput; 131185377Ssam ah->ah_gpioGet = ar5416GpioGet; 132185377Ssam ah->ah_gpioSet = ar5416GpioSet; 133185377Ssam ah->ah_gpioSetIntr = ar5416GpioSetIntr; 134185377Ssam ah->ah_resetTsf = ar5416ResetTsf; 135185377Ssam ah->ah_getRfGain = ar5416GetRfgain; 136185377Ssam ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 137185377Ssam ah->ah_setDecompMask = ar5416SetDecompMask; 138185377Ssam ah->ah_setCoverageClass = ar5416SetCoverageClass; 139185377Ssam 140185377Ssam ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 141185377Ssam ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 142185377Ssam 143185377Ssam /* Power Management Functions */ 144185377Ssam ah->ah_setPowerMode = ar5416SetPowerMode; 145185377Ssam 146185377Ssam /* Beacon Management Functions */ 147185377Ssam ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 148185377Ssam ah->ah_beaconInit = ar5416BeaconInit; 149185377Ssam ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 150185377Ssam ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 151185377Ssam 152218066Sadrian /* 802.11n Functions */ 153185377Ssam ah->ah_chainTxDesc = ar5416ChainTxDesc; 154185377Ssam ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 155185377Ssam ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 156185377Ssam ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 157185377Ssam ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 158185377Ssam ah->ah_clr11nAggr = ar5416Clr11nAggr; 159185377Ssam ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 160185377Ssam ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 161185377Ssam ah->ah_set11nMac2040 = ar5416Set11nMac2040; 162185377Ssam ah->ah_get11nRxClear = ar5416Get11nRxClear; 163185377Ssam ah->ah_set11nRxClear = ar5416Set11nRxClear; 164185377Ssam 165185377Ssam /* Interrupt functions */ 166185377Ssam ah->ah_isInterruptPending = ar5416IsInterruptPending; 167185377Ssam ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 168185377Ssam ah->ah_setInterrupts = ar5416SetInterrupts; 169185377Ssam 170185377Ssam ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 171185377Ssam ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 172185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 173185377Ssam ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 174185377Ssam#endif 175185377Ssam ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 176185377Ssam 177219393Sadrian /* Internal ops */ 178189747Ssam AH5416(ah)->ah_writeIni = ar5416WriteIni; 179189747Ssam AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 180219393Sadrian 181219480Sadrian /* Internal calibration ops */ 182219480Sadrian AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 183219480Sadrian 184219393Sadrian /* Internal TX power control related operations */ 185219393Sadrian AH5416(ah)->ah_olcInit = ar5416olcInit; 186219393Sadrian AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 187219393Sadrian AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 188219393Sadrian 189185377Ssam /* 190185377Ssam * Start by setting all Owl devices to 2x2 191185377Ssam */ 192185377Ssam AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 193185377Ssam AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 194218763Sadrian 195218763Sadrian /* Enable all ANI functions to begin with */ 196218763Sadrian AH5416(ah)->ah_ani_function = HAL_ANI_ALL; 197185377Ssam} 198185377Ssam 199188971Ssamuint32_t 200188971Ssamar5416GetRadioRev(struct ath_hal *ah) 201188971Ssam{ 202188971Ssam uint32_t val; 203188971Ssam int i; 204188971Ssam 205188971Ssam /* Read Radio Chip Rev Extract */ 206188971Ssam OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 207188971Ssam for (i = 0; i < 8; i++) 208188971Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 209188971Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 210188971Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 211188971Ssam return ath_hal_reverseBits(val, 8); 212188971Ssam} 213188971Ssam 214185377Ssam/* 215185377Ssam * Attach for an AR5416 part. 216185377Ssam */ 217188972Ssamstatic struct ath_hal * 218185377Ssamar5416Attach(uint16_t devid, HAL_SOFTC sc, 219217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 220217624Sadrian HAL_STATUS *status) 221185377Ssam{ 222185377Ssam struct ath_hal_5416 *ahp5416; 223185377Ssam struct ath_hal_5212 *ahp; 224185377Ssam struct ath_hal *ah; 225185377Ssam uint32_t val; 226185377Ssam HAL_STATUS ecode; 227185377Ssam HAL_BOOL rfStatus; 228185377Ssam 229185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 230185377Ssam __func__, sc, (void*) st, (void*) sh); 231185377Ssam 232185377Ssam /* NB: memory is returned zero'd */ 233185377Ssam ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 234185377Ssam /* extra space for Owl 2.1/2.2 WAR */ 235185377Ssam sizeof(ar5416Addac) 236185377Ssam ); 237185377Ssam if (ahp5416 == AH_NULL) { 238185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 239185377Ssam "%s: cannot allocate memory for state block\n", __func__); 240185377Ssam *status = HAL_ENOMEM; 241185377Ssam return AH_NULL; 242185377Ssam } 243185377Ssam ar5416InitState(ahp5416, devid, sc, st, sh, status); 244185377Ssam ahp = &ahp5416->ah_5212; 245185377Ssam ah = &ahp->ah_priv.h; 246185377Ssam 247185377Ssam if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 248185377Ssam /* reset chip */ 249185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 250185377Ssam ecode = HAL_EIO; 251185377Ssam goto bad; 252185377Ssam } 253185377Ssam 254185377Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 255185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 256185377Ssam ecode = HAL_EIO; 257185377Ssam goto bad; 258185377Ssam } 259185377Ssam /* Read Revisions from Chips before taking out of reset */ 260185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 261185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 262185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 263188979Ssam AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 264185377Ssam 265185377Ssam /* setup common ini data; rf backends handle remainder */ 266185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 267185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 268185377Ssam 269185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 270185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 271185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 272185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 273185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 274185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 275185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 276185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 277185377Ssam 278185377Ssam if (!IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 279185377Ssam struct ini { 280185377Ssam uint32_t *data; /* NB: !const */ 281185377Ssam int rows, cols; 282185377Ssam }; 283185377Ssam /* override CLKDRV value */ 284185377Ssam OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 285185377Ssam AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 286185377Ssam HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 287185377Ssam } 288185377Ssam 289188979Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 290188979Ssam ar5416AttachPCIE(ah); 291188979Ssam 292188973Ssam ecode = ath_hal_v14EepromAttach(ah); 293188973Ssam if (ecode != HAL_OK) 294188973Ssam goto bad; 295188973Ssam 296185377Ssam if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 297185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 298185377Ssam __func__); 299185377Ssam ecode = HAL_EIO; 300185377Ssam goto bad; 301185377Ssam } 302185377Ssam 303185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 304185377Ssam 305185377Ssam if (!ar5212ChipTest(ah)) { 306185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 307185377Ssam __func__); 308185377Ssam ecode = HAL_ESELFTEST; 309185377Ssam goto bad; 310185377Ssam } 311185377Ssam 312185377Ssam /* 313185377Ssam * Set correct Baseband to analog shift 314185377Ssam * setting to access analog chips. 315185377Ssam */ 316185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 317185377Ssam 318185377Ssam /* Read Radio Chip Rev Extract */ 319185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 320185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 321185377Ssam case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 322185377Ssam case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 323185377Ssam case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 324185377Ssam case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 325185377Ssam break; 326185377Ssam default: 327185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 328185377Ssam /* 329185377Ssam * When RF_Silen is used the analog chip is reset. 330185377Ssam * So when the system boots with radio switch off 331185377Ssam * the RF chip rev reads back as zero and we need 332185377Ssam * to use the mac+phy revs to set the radio rev. 333185377Ssam */ 334185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 335185377Ssam AR_RAD5133_SREV_MAJOR; 336185377Ssam break; 337185377Ssam } 338185377Ssam /* NB: silently accept anything in release code per Atheros */ 339185377Ssam#ifdef AH_DEBUG 340185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 341185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 342185377Ssam "this driver\n", __func__, 343185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 344185377Ssam ecode = HAL_ENOTSUPP; 345185377Ssam goto bad; 346185377Ssam#endif 347185377Ssam } 348185377Ssam 349185377Ssam /* 350185377Ssam * Got everything we need now to setup the capabilities. 351185377Ssam */ 352185377Ssam if (!ar5416FillCapabilityInfo(ah)) { 353185377Ssam ecode = HAL_EEREAD; 354185377Ssam goto bad; 355185377Ssam } 356185377Ssam 357185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 358185377Ssam if (ecode != HAL_OK) { 359185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 360185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 361185377Ssam goto bad; 362185377Ssam } 363185377Ssam /* XXX How about the serial number ? */ 364185377Ssam /* Read Reg Domain */ 365185377Ssam AH_PRIVATE(ah)->ah_currentRD = 366185377Ssam ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 367185377Ssam 368185377Ssam /* 369185377Ssam * ah_miscMode is populated by ar5416FillCapabilityInfo() 370185377Ssam * starting from griffin. Set here to make sure that 371185377Ssam * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 372185380Ssam * placed into hardware. 373185377Ssam */ 374185377Ssam if (ahp->ah_miscMode != 0) 375185377Ssam OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 376185377Ssam 377185377Ssam rfStatus = ar2133RfAttach(ah, &ecode); 378185377Ssam if (!rfStatus) { 379185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 380185377Ssam __func__, ecode); 381185377Ssam goto bad; 382185377Ssam } 383185377Ssam 384185377Ssam ar5416AniSetup(ah); /* Anti Noise Immunity */ 385218068Sadrian 386218068Sadrian AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 387218068Sadrian AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 388218068Sadrian AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 389218068Sadrian AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 390218068Sadrian AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 391218068Sadrian AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 392218068Sadrian 393203882Srpaulo ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 394185377Ssam 395185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 396185377Ssam 397185377Ssam return ah; 398185377Ssambad: 399185377Ssam if (ahp) 400185377Ssam ar5416Detach((struct ath_hal *) ahp); 401185377Ssam if (status) 402185377Ssam *status = ecode; 403185377Ssam return AH_NULL; 404185377Ssam} 405185377Ssam 406185377Ssamvoid 407185377Ssamar5416Detach(struct ath_hal *ah) 408185377Ssam{ 409185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 410185377Ssam 411185377Ssam HALASSERT(ah != AH_NULL); 412185377Ssam HALASSERT(ah->ah_magic == AR5416_MAGIC); 413185377Ssam 414185380Ssam ar5416AniDetach(ah); 415185377Ssam ar5212RfDetach(ah); 416185377Ssam ah->ah_disable(ah); 417185377Ssam ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 418185377Ssam ath_hal_eepromDetach(ah); 419185377Ssam ath_hal_free(ah); 420185377Ssam} 421185377Ssam 422188979Ssamvoid 423188979Ssamar5416AttachPCIE(struct ath_hal *ah) 424188979Ssam{ 425188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) 426188979Ssam ath_hal_configPCIE(ah, AH_FALSE); 427188979Ssam else 428188979Ssam ath_hal_disablePCIE(ah); 429188979Ssam} 430188979Ssam 431188979Ssamstatic void 432188979Ssamar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 433188979Ssam{ 434188979Ssam if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 435188979Ssam ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 436188979Ssam OS_DELAY(1000); 437188979Ssam OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 438188979Ssam OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 439188979Ssam } 440188979Ssam} 441188979Ssam 442189747Ssamstatic void 443189747Ssamar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 444189747Ssam{ 445189747Ssam u_int modesIndex, freqIndex; 446189747Ssam int regWrites = 0; 447189747Ssam 448189747Ssam /* Setup the indices for the next set of register array writes */ 449189747Ssam /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 450189747Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 451189747Ssam freqIndex = 2; 452189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 453189747Ssam modesIndex = 3; 454189747Ssam else if (IEEE80211_IS_CHAN_108G(chan)) 455189747Ssam modesIndex = 5; 456189747Ssam else 457189747Ssam modesIndex = 4; 458189747Ssam } else { 459189747Ssam freqIndex = 1; 460189747Ssam if (IEEE80211_IS_CHAN_HT40(chan) || 461189747Ssam IEEE80211_IS_CHAN_TURBO(chan)) 462189747Ssam modesIndex = 2; 463189747Ssam else 464189747Ssam modesIndex = 1; 465189747Ssam } 466189747Ssam 467189747Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 468189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 469189747Ssam 470189747Ssam /* 471189747Ssam * Write addac shifts 472189747Ssam */ 473189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 474189747Ssam#if 0 475189747Ssam /* NB: only required for Sowl */ 476189747Ssam ar5416EepromSetAddac(ah, chan); 477189747Ssam#endif 478189747Ssam regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 479189747Ssam regWrites); 480189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 481189747Ssam 482189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 483189747Ssam modesIndex, regWrites); 484189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 485189747Ssam 1, regWrites); 486189747Ssam 487189747Ssam /* XXX updated regWrites? */ 488189747Ssam AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 489189747Ssam} 490189747Ssam 491185377Ssam/* 492189747Ssam * Convert to baseband spur frequency given input channel frequency 493189747Ssam * and compute register settings below. 494189747Ssam */ 495189747Ssam 496189747Ssamstatic void 497189747Ssamar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 498189747Ssam{ 499189747Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 500189747Ssam static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 501189747Ssam AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 502189747Ssam static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 503189747Ssam AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 504189747Ssam static const int inc[4] = { 0, 100, 0, 0 }; 505189747Ssam 506189747Ssam int bb_spur = AR_NO_SPUR; 507189747Ssam int bin, cur_bin; 508189747Ssam int spur_freq_sd; 509189747Ssam int spur_delta_phase; 510189747Ssam int denominator; 511189747Ssam int upper, lower, cur_vit_mask; 512189747Ssam int tmp, new; 513189747Ssam int i; 514189747Ssam 515189747Ssam int8_t mask_m[123]; 516189747Ssam int8_t mask_p[123]; 517189747Ssam int8_t mask_amt; 518189747Ssam int tmp_mask; 519189747Ssam int cur_bb_spur; 520189747Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 521189747Ssam 522189747Ssam OS_MEMZERO(mask_m, sizeof(mask_m)); 523189747Ssam OS_MEMZERO(mask_p, sizeof(mask_p)); 524189747Ssam 525189747Ssam /* 526189747Ssam * Need to verify range +/- 9.5 for static ht20, otherwise spur 527189747Ssam * is out-of-band and can be ignored. 528189747Ssam */ 529189747Ssam /* XXX ath9k changes */ 530189747Ssam for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 531189747Ssam cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 532189747Ssam if (AR_NO_SPUR == cur_bb_spur) 533189747Ssam break; 534189747Ssam cur_bb_spur = cur_bb_spur - (freq * 10); 535189747Ssam if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 536189747Ssam bb_spur = cur_bb_spur; 537189747Ssam break; 538189747Ssam } 539189747Ssam } 540189747Ssam if (AR_NO_SPUR == bb_spur) 541189747Ssam return; 542189747Ssam 543189747Ssam bin = bb_spur * 32; 544189747Ssam 545189747Ssam tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 546189747Ssam new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 547189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 548189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 549189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 550189747Ssam 551189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 552189747Ssam 553189747Ssam new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 554189747Ssam AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 555189747Ssam AR_PHY_SPUR_REG_MASK_RATE_SELECT | 556189747Ssam AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 557189747Ssam SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 558189747Ssam OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 559189747Ssam /* 560189747Ssam * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 561189747Ssam * config, no offset for HT20. 562189747Ssam * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 563189747Ssam * /80 for dyn2040. 564189747Ssam */ 565189747Ssam spur_delta_phase = ((bb_spur * 524288) / 100) & 566189747Ssam AR_PHY_TIMING11_SPUR_DELTA_PHASE; 567189747Ssam /* 568189747Ssam * in 11A mode the denominator of spur_freq_sd should be 40 and 569189747Ssam * it should be 44 in 11G 570189747Ssam */ 571189747Ssam denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 572189747Ssam spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 573189747Ssam 574189747Ssam new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 575189747Ssam SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 576189747Ssam SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 577189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 578189747Ssam 579189747Ssam 580189747Ssam /* 581189747Ssam * ============================================ 582189747Ssam * pilot mask 1 [31:0] = +6..-26, no 0 bin 583189747Ssam * pilot mask 2 [19:0] = +26..+7 584189747Ssam * 585189747Ssam * channel mask 1 [31:0] = +6..-26, no 0 bin 586189747Ssam * channel mask 2 [19:0] = +26..+7 587189747Ssam */ 588189747Ssam //cur_bin = -26; 589189747Ssam cur_bin = -6000; 590189747Ssam upper = bin + 100; 591189747Ssam lower = bin - 100; 592189747Ssam 593189747Ssam for (i = 0; i < 4; i++) { 594189747Ssam int pilot_mask = 0; 595189747Ssam int chan_mask = 0; 596189747Ssam int bp = 0; 597189747Ssam for (bp = 0; bp < 30; bp++) { 598189747Ssam if ((cur_bin > lower) && (cur_bin < upper)) { 599189747Ssam pilot_mask = pilot_mask | 0x1 << bp; 600189747Ssam chan_mask = chan_mask | 0x1 << bp; 601189747Ssam } 602189747Ssam cur_bin += 100; 603189747Ssam } 604189747Ssam cur_bin += inc[i]; 605189747Ssam OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 606189747Ssam OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 607189747Ssam } 608189747Ssam 609189747Ssam /* ================================================= 610189747Ssam * viterbi mask 1 based on channel magnitude 611189747Ssam * four levels 0-3 612189747Ssam * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 613189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 614189747Ssam * - enable_mask_ppm, all bins move with freq 615189747Ssam * 616189747Ssam * - mask_select, 8 bits for rates (reg 67,0x990c) 617189747Ssam * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 618189747Ssam * choose which mask to use mask or mask2 619189747Ssam */ 620189747Ssam 621189747Ssam /* 622189747Ssam * viterbi mask 2 2nd set for per data rate puncturing 623189747Ssam * four levels 0-3 624189747Ssam * - mask_select, 8 bits for rates (reg 67) 625189747Ssam * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 626189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 627189747Ssam */ 628189747Ssam cur_vit_mask = 6100; 629189747Ssam upper = bin + 120; 630189747Ssam lower = bin - 120; 631189747Ssam 632189747Ssam for (i = 0; i < 123; i++) { 633189747Ssam if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 634189747Ssam if ((abs(cur_vit_mask - bin)) < 75) { 635189747Ssam mask_amt = 1; 636189747Ssam } else { 637189747Ssam mask_amt = 0; 638189747Ssam } 639189747Ssam if (cur_vit_mask < 0) { 640189747Ssam mask_m[abs(cur_vit_mask / 100)] = mask_amt; 641189747Ssam } else { 642189747Ssam mask_p[cur_vit_mask / 100] = mask_amt; 643189747Ssam } 644189747Ssam } 645189747Ssam cur_vit_mask -= 100; 646189747Ssam } 647189747Ssam 648189747Ssam tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 649189747Ssam | (mask_m[48] << 26) | (mask_m[49] << 24) 650189747Ssam | (mask_m[50] << 22) | (mask_m[51] << 20) 651189747Ssam | (mask_m[52] << 18) | (mask_m[53] << 16) 652189747Ssam | (mask_m[54] << 14) | (mask_m[55] << 12) 653189747Ssam | (mask_m[56] << 10) | (mask_m[57] << 8) 654189747Ssam | (mask_m[58] << 6) | (mask_m[59] << 4) 655189747Ssam | (mask_m[60] << 2) | (mask_m[61] << 0); 656189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 657189747Ssam OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 658189747Ssam 659189747Ssam tmp_mask = (mask_m[31] << 28) 660189747Ssam | (mask_m[32] << 26) | (mask_m[33] << 24) 661189747Ssam | (mask_m[34] << 22) | (mask_m[35] << 20) 662189747Ssam | (mask_m[36] << 18) | (mask_m[37] << 16) 663189747Ssam | (mask_m[48] << 14) | (mask_m[39] << 12) 664189747Ssam | (mask_m[40] << 10) | (mask_m[41] << 8) 665189747Ssam | (mask_m[42] << 6) | (mask_m[43] << 4) 666189747Ssam | (mask_m[44] << 2) | (mask_m[45] << 0); 667189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 668189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 669189747Ssam 670189747Ssam tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 671189747Ssam | (mask_m[18] << 26) | (mask_m[18] << 24) 672189747Ssam | (mask_m[20] << 22) | (mask_m[20] << 20) 673189747Ssam | (mask_m[22] << 18) | (mask_m[22] << 16) 674189747Ssam | (mask_m[24] << 14) | (mask_m[24] << 12) 675189747Ssam | (mask_m[25] << 10) | (mask_m[26] << 8) 676189747Ssam | (mask_m[27] << 6) | (mask_m[28] << 4) 677189747Ssam | (mask_m[29] << 2) | (mask_m[30] << 0); 678189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 679189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 680189747Ssam 681189747Ssam tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 682189747Ssam | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 683189747Ssam | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 684189747Ssam | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 685189747Ssam | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 686189747Ssam | (mask_m[10] << 10) | (mask_m[11] << 8) 687189747Ssam | (mask_m[12] << 6) | (mask_m[13] << 4) 688189747Ssam | (mask_m[14] << 2) | (mask_m[15] << 0); 689189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 690189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 691189747Ssam 692189747Ssam tmp_mask = (mask_p[15] << 28) 693189747Ssam | (mask_p[14] << 26) | (mask_p[13] << 24) 694189747Ssam | (mask_p[12] << 22) | (mask_p[11] << 20) 695189747Ssam | (mask_p[10] << 18) | (mask_p[ 9] << 16) 696189747Ssam | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 697189747Ssam | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 698189747Ssam | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 699189747Ssam | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 700189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 701189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 702189747Ssam 703189747Ssam tmp_mask = (mask_p[30] << 28) 704189747Ssam | (mask_p[29] << 26) | (mask_p[28] << 24) 705189747Ssam | (mask_p[27] << 22) | (mask_p[26] << 20) 706189747Ssam | (mask_p[25] << 18) | (mask_p[24] << 16) 707189747Ssam | (mask_p[23] << 14) | (mask_p[22] << 12) 708189747Ssam | (mask_p[21] << 10) | (mask_p[20] << 8) 709189747Ssam | (mask_p[19] << 6) | (mask_p[18] << 4) 710189747Ssam | (mask_p[17] << 2) | (mask_p[16] << 0); 711189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 712189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 713189747Ssam 714189747Ssam tmp_mask = (mask_p[45] << 28) 715189747Ssam | (mask_p[44] << 26) | (mask_p[43] << 24) 716189747Ssam | (mask_p[42] << 22) | (mask_p[41] << 20) 717189747Ssam | (mask_p[40] << 18) | (mask_p[39] << 16) 718189747Ssam | (mask_p[38] << 14) | (mask_p[37] << 12) 719189747Ssam | (mask_p[36] << 10) | (mask_p[35] << 8) 720189747Ssam | (mask_p[34] << 6) | (mask_p[33] << 4) 721189747Ssam | (mask_p[32] << 2) | (mask_p[31] << 0); 722189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 723189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 724189747Ssam 725189747Ssam tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 726189747Ssam | (mask_p[59] << 26) | (mask_p[58] << 24) 727189747Ssam | (mask_p[57] << 22) | (mask_p[56] << 20) 728189747Ssam | (mask_p[55] << 18) | (mask_p[54] << 16) 729189747Ssam | (mask_p[53] << 14) | (mask_p[52] << 12) 730189747Ssam | (mask_p[51] << 10) | (mask_p[50] << 8) 731189747Ssam | (mask_p[49] << 6) | (mask_p[48] << 4) 732189747Ssam | (mask_p[47] << 2) | (mask_p[46] << 0); 733189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 734189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 735189747Ssam} 736189747Ssam 737189747Ssam/* 738185377Ssam * Fill all software cached or static hardware state information. 739185377Ssam * Return failure if capabilities are to come from EEPROM and 740185377Ssam * cannot be read. 741185377Ssam */ 742185377SsamHAL_BOOL 743185377Ssamar5416FillCapabilityInfo(struct ath_hal *ah) 744185377Ssam{ 745185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 746185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 747185377Ssam uint16_t val; 748185377Ssam 749185377Ssam /* Construct wireless mode from EEPROM */ 750185377Ssam pCap->halWirelessModes = 0; 751185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 752185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 753185377Ssam | HAL_MODE_11NA_HT20 754185377Ssam | HAL_MODE_11NA_HT40PLUS 755185377Ssam | HAL_MODE_11NA_HT40MINUS 756185377Ssam ; 757185377Ssam } 758185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 759185377Ssam pCap->halWirelessModes |= HAL_MODE_11G 760185377Ssam | HAL_MODE_11NG_HT20 761185377Ssam | HAL_MODE_11NG_HT40PLUS 762185377Ssam | HAL_MODE_11NG_HT40MINUS 763185377Ssam ; 764185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 765185377Ssam | HAL_MODE_11NA_HT20 766185377Ssam | HAL_MODE_11NA_HT40PLUS 767185377Ssam | HAL_MODE_11NA_HT40MINUS 768185377Ssam ; 769185377Ssam } 770185377Ssam 771185377Ssam pCap->halLow2GhzChan = 2312; 772185377Ssam pCap->halHigh2GhzChan = 2732; 773185377Ssam 774185377Ssam pCap->halLow5GhzChan = 4915; 775185377Ssam pCap->halHigh5GhzChan = 6100; 776185377Ssam 777185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 778185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 779185377Ssam pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 780185377Ssam 781185377Ssam pCap->halMicCkipSupport = AH_FALSE; 782185377Ssam pCap->halMicTkipSupport = AH_TRUE; 783185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 784185377Ssam /* 785185377Ssam * Starting with Griffin TX+RX mic keys can be combined 786185377Ssam * in one key cache slot. 787185377Ssam */ 788185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 789185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 790185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 791185377Ssam 792185377Ssam pCap->halCompressSupport = AH_FALSE; 793185377Ssam pCap->halBurstSupport = AH_TRUE; 794185377Ssam pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 795185377Ssam pCap->halChapTuningSupport = AH_TRUE; 796185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 797185377Ssam 798185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 799185377Ssam 800185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 801185377Ssam pCap->halVEOLSupport = AH_TRUE; 802185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 803185377Ssam pCap->halMcastKeySrchSupport = AH_FALSE; 804185377Ssam pCap->halTsfAddSupport = AH_TRUE; 805185377Ssam 806185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 807185377Ssam pCap->halTotalQueues = val; 808185377Ssam else 809185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 810185377Ssam 811185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 812185377Ssam pCap->halKeyCacheSize = val; 813185377Ssam else 814185377Ssam pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 815185377Ssam 816185377Ssam /* XXX not needed */ 817185377Ssam pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 818185377Ssam pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 819185377Ssam 820185377Ssam pCap->halTstampPrecision = 32; 821185377Ssam pCap->halHwPhyCounterSupport = AH_TRUE; 822192396Ssam pCap->halIntrMask = HAL_INT_COMMON 823192396Ssam | HAL_INT_RX 824192396Ssam | HAL_INT_TX 825192396Ssam | HAL_INT_FATAL 826192396Ssam | HAL_INT_BNR 827192396Ssam | HAL_INT_BMISC 828192396Ssam | HAL_INT_DTIMSYNC 829192396Ssam | HAL_INT_TSFOOR 830192396Ssam | HAL_INT_CST 831192396Ssam | HAL_INT_GTT 832192396Ssam ; 833185377Ssam 834185377Ssam pCap->halFastCCSupport = AH_TRUE; 835185377Ssam pCap->halNumGpioPins = 6; 836185377Ssam pCap->halWowSupport = AH_FALSE; 837185377Ssam pCap->halWowMatchPatternExact = AH_FALSE; 838185377Ssam pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 839185377Ssam pCap->halAutoSleepSupport = AH_FALSE; 840218441Sadrian pCap->hal4kbSplitTransSupport = AH_TRUE; 841185377Ssam#if 0 /* XXX not yet */ 842185377Ssam pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 843185377Ssam pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 844185377Ssam#endif 845185377Ssam pCap->halHTSupport = AH_TRUE; 846185377Ssam pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 847185377Ssam /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 848185377Ssam pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 849218150Sadrian /* AR5416 may have 3 antennas but is a 2x2 stream device */ 850218150Sadrian pCap->halTxStreams = 2; 851218150Sadrian pCap->halRxStreams = 2; 852185377Ssam pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 853185377Ssam pCap->halMbssidAggrSupport = AH_TRUE; 854185377Ssam pCap->halForcePpmSupport = AH_TRUE; 855185377Ssam pCap->halEnhancedPmSupport = AH_TRUE; 856195114Ssam pCap->halBssidMatchSupport = AH_TRUE; 857185377Ssam 858185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 859185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 860185377Ssam /* NB: enabled by default */ 861185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 862185377Ssam pCap->halRfSilentSupport = AH_TRUE; 863185377Ssam } 864185377Ssam 865185377Ssam ahpriv->ah_rxornIsFatal = AH_FALSE; 866185377Ssam 867185377Ssam return AH_TRUE; 868185377Ssam} 869185406Ssam 870185406Ssamstatic const char* 871185406Ssamar5416Probe(uint16_t vendorid, uint16_t devid) 872185406Ssam{ 873185406Ssam if (vendorid == ATHEROS_VENDOR_ID && 874185406Ssam (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 875185406Ssam return "Atheros 5416"; 876185406Ssam return AH_NULL; 877185406Ssam} 878185418SsamAH_CHIP(AR5416, ar5416Probe, ar5416Attach); 879