ar5416_attach.c revision 219393
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 219393 2011-03-08 06:59:59Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar5416/ar5416.ini" 32 33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34static void ar5416WriteIni(struct ath_hal *ah, 35 const struct ieee80211_channel *chan); 36static void ar5416SpurMitigate(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 39static void 40ar5416AniSetup(struct ath_hal *ah) 41{ 42 static const struct ar5212AniParams aniparams = { 43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45 .coarseHigh = { -14, -14, -14, -14, -12 }, 46 .coarseLow = { -64, -64, -64, -64, -70 }, 47 .firpwr = { -78, -78, -78, -78, -80 }, 48 .maxSpurImmunityLevel = 2, 49 .cycPwrThr1 = { 2, 4, 6 }, 50 .maxFirstepLevel = 2, /* levels 0..2 */ 51 .firstep = { 0, 4, 8 }, 52 .ofdmTrigHigh = 500, 53 .ofdmTrigLow = 200, 54 .cckTrigHigh = 200, 55 .cckTrigLow = 100, 56 .rssiThrHigh = 40, 57 .rssiThrLow = 7, 58 .period = 100, 59 }; 60 /* NB: ANI is not enabled yet */ 61 ar5416AniAttach(ah, &aniparams, &aniparams, AH_FALSE); 62} 63 64/* 65 * AR5416 doesn't do OLC or temperature compensation. 66 */ 67static void 68ar5416olcInit(struct ath_hal *ah) 69{ 70} 71 72static void 73ar5416olcTempCompensation(struct ath_hal *ah) 74{ 75} 76 77/* 78 * Attach for an AR5416 part. 79 */ 80void 81ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 82 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 83{ 84 struct ath_hal_5212 *ahp; 85 struct ath_hal *ah; 86 87 ahp = &ahp5416->ah_5212; 88 ar5212InitState(ahp, devid, sc, st, sh, status); 89 ah = &ahp->ah_priv.h; 90 91 /* override 5212 methods for our needs */ 92 ah->ah_magic = AR5416_MAGIC; 93 ah->ah_getRateTable = ar5416GetRateTable; 94 ah->ah_detach = ar5416Detach; 95 96 /* Reset functions */ 97 ah->ah_reset = ar5416Reset; 98 ah->ah_phyDisable = ar5416PhyDisable; 99 ah->ah_disable = ar5416Disable; 100 ah->ah_configPCIE = ar5416ConfigPCIE; 101 ah->ah_perCalibration = ar5416PerCalibration; 102 ah->ah_perCalibrationN = ar5416PerCalibrationN, 103 ah->ah_resetCalValid = ar5416ResetCalValid, 104 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 105 ah->ah_setTxPower = ar5416SetTransmitPower; 106 ah->ah_setBoardValues = ar5416SetBoardValues; 107 108 /* Transmit functions */ 109 ah->ah_stopTxDma = ar5416StopTxDma; 110 ah->ah_setupTxDesc = ar5416SetupTxDesc; 111 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 112 ah->ah_fillTxDesc = ar5416FillTxDesc; 113 ah->ah_procTxDesc = ar5416ProcTxDesc; 114 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 115 116 /* Receive Functions */ 117 ah->ah_startPcuReceive = ar5416StartPcuReceive; 118 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 119 ah->ah_setupRxDesc = ar5416SetupRxDesc; 120 ah->ah_procRxDesc = ar5416ProcRxDesc; 121 ah->ah_rxMonitor = ar5416RxMonitor; 122 ah->ah_aniPoll = ar5416AniPoll; 123 ah->ah_procMibEvent = ar5416ProcessMibIntr; 124 125 /* Misc Functions */ 126 ah->ah_getCapability = ar5416GetCapability; 127 ah->ah_getDiagState = ar5416GetDiagState; 128 ah->ah_setLedState = ar5416SetLedState; 129 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 130 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 131 ah->ah_gpioGet = ar5416GpioGet; 132 ah->ah_gpioSet = ar5416GpioSet; 133 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 134 ah->ah_resetTsf = ar5416ResetTsf; 135 ah->ah_getRfGain = ar5416GetRfgain; 136 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 137 ah->ah_setDecompMask = ar5416SetDecompMask; 138 ah->ah_setCoverageClass = ar5416SetCoverageClass; 139 140 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 141 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 142 143 /* Power Management Functions */ 144 ah->ah_setPowerMode = ar5416SetPowerMode; 145 146 /* Beacon Management Functions */ 147 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 148 ah->ah_beaconInit = ar5416BeaconInit; 149 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 150 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 151 152 /* 802.11n Functions */ 153 ah->ah_chainTxDesc = ar5416ChainTxDesc; 154 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 155 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 156 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 157 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 158 ah->ah_clr11nAggr = ar5416Clr11nAggr; 159 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 160 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 161 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 162 ah->ah_get11nRxClear = ar5416Get11nRxClear; 163 ah->ah_set11nRxClear = ar5416Set11nRxClear; 164 165 /* Interrupt functions */ 166 ah->ah_isInterruptPending = ar5416IsInterruptPending; 167 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 168 ah->ah_setInterrupts = ar5416SetInterrupts; 169 170 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 171 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 172#ifdef AH_SUPPORT_WRITE_EEPROM 173 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 174#endif 175 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 176 177 /* Internal ops */ 178 AH5416(ah)->ah_writeIni = ar5416WriteIni; 179 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 180 181 /* Internal TX power control related operations */ 182 AH5416(ah)->ah_olcInit = ar5416olcInit; 183 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 184 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 185 186 /* 187 * Start by setting all Owl devices to 2x2 188 */ 189 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 190 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 191 192 /* Enable all ANI functions to begin with */ 193 AH5416(ah)->ah_ani_function = HAL_ANI_ALL; 194} 195 196uint32_t 197ar5416GetRadioRev(struct ath_hal *ah) 198{ 199 uint32_t val; 200 int i; 201 202 /* Read Radio Chip Rev Extract */ 203 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 204 for (i = 0; i < 8; i++) 205 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 206 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 207 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 208 return ath_hal_reverseBits(val, 8); 209} 210 211/* 212 * Attach for an AR5416 part. 213 */ 214static struct ath_hal * 215ar5416Attach(uint16_t devid, HAL_SOFTC sc, 216 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 217 HAL_STATUS *status) 218{ 219 struct ath_hal_5416 *ahp5416; 220 struct ath_hal_5212 *ahp; 221 struct ath_hal *ah; 222 uint32_t val; 223 HAL_STATUS ecode; 224 HAL_BOOL rfStatus; 225 226 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 227 __func__, sc, (void*) st, (void*) sh); 228 229 /* NB: memory is returned zero'd */ 230 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 231 /* extra space for Owl 2.1/2.2 WAR */ 232 sizeof(ar5416Addac) 233 ); 234 if (ahp5416 == AH_NULL) { 235 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 236 "%s: cannot allocate memory for state block\n", __func__); 237 *status = HAL_ENOMEM; 238 return AH_NULL; 239 } 240 ar5416InitState(ahp5416, devid, sc, st, sh, status); 241 ahp = &ahp5416->ah_5212; 242 ah = &ahp->ah_priv.h; 243 244 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 245 /* reset chip */ 246 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 247 ecode = HAL_EIO; 248 goto bad; 249 } 250 251 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 252 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 253 ecode = HAL_EIO; 254 goto bad; 255 } 256 /* Read Revisions from Chips before taking out of reset */ 257 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 258 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 259 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 260 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 261 262 /* setup common ini data; rf backends handle remainder */ 263 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 264 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 265 266 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 267 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 268 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 269 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 270 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 271 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 272 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 273 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 274 275 if (!IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 276 struct ini { 277 uint32_t *data; /* NB: !const */ 278 int rows, cols; 279 }; 280 /* override CLKDRV value */ 281 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 282 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 283 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 284 } 285 286 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 287 ar5416AttachPCIE(ah); 288 289 ecode = ath_hal_v14EepromAttach(ah); 290 if (ecode != HAL_OK) 291 goto bad; 292 293 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 294 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 295 __func__); 296 ecode = HAL_EIO; 297 goto bad; 298 } 299 300 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 301 302 if (!ar5212ChipTest(ah)) { 303 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 304 __func__); 305 ecode = HAL_ESELFTEST; 306 goto bad; 307 } 308 309 /* 310 * Set correct Baseband to analog shift 311 * setting to access analog chips. 312 */ 313 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 314 315 /* Read Radio Chip Rev Extract */ 316 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 317 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 318 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 319 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 320 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 321 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 322 break; 323 default: 324 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 325 /* 326 * When RF_Silen is used the analog chip is reset. 327 * So when the system boots with radio switch off 328 * the RF chip rev reads back as zero and we need 329 * to use the mac+phy revs to set the radio rev. 330 */ 331 AH_PRIVATE(ah)->ah_analog5GhzRev = 332 AR_RAD5133_SREV_MAJOR; 333 break; 334 } 335 /* NB: silently accept anything in release code per Atheros */ 336#ifdef AH_DEBUG 337 HALDEBUG(ah, HAL_DEBUG_ANY, 338 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 339 "this driver\n", __func__, 340 AH_PRIVATE(ah)->ah_analog5GhzRev); 341 ecode = HAL_ENOTSUPP; 342 goto bad; 343#endif 344 } 345 346 /* 347 * Got everything we need now to setup the capabilities. 348 */ 349 if (!ar5416FillCapabilityInfo(ah)) { 350 ecode = HAL_EEREAD; 351 goto bad; 352 } 353 354 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 355 if (ecode != HAL_OK) { 356 HALDEBUG(ah, HAL_DEBUG_ANY, 357 "%s: error getting mac address from EEPROM\n", __func__); 358 goto bad; 359 } 360 /* XXX How about the serial number ? */ 361 /* Read Reg Domain */ 362 AH_PRIVATE(ah)->ah_currentRD = 363 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 364 365 /* 366 * ah_miscMode is populated by ar5416FillCapabilityInfo() 367 * starting from griffin. Set here to make sure that 368 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 369 * placed into hardware. 370 */ 371 if (ahp->ah_miscMode != 0) 372 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 373 374 rfStatus = ar2133RfAttach(ah, &ecode); 375 if (!rfStatus) { 376 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 377 __func__, ecode); 378 goto bad; 379 } 380 381 ar5416AniSetup(ah); /* Anti Noise Immunity */ 382 383 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 384 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 385 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 386 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 387 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 388 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 389 390 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 391 392 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 393 394 return ah; 395bad: 396 if (ahp) 397 ar5416Detach((struct ath_hal *) ahp); 398 if (status) 399 *status = ecode; 400 return AH_NULL; 401} 402 403void 404ar5416Detach(struct ath_hal *ah) 405{ 406 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 407 408 HALASSERT(ah != AH_NULL); 409 HALASSERT(ah->ah_magic == AR5416_MAGIC); 410 411 ar5416AniDetach(ah); 412 ar5212RfDetach(ah); 413 ah->ah_disable(ah); 414 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 415 ath_hal_eepromDetach(ah); 416 ath_hal_free(ah); 417} 418 419void 420ar5416AttachPCIE(struct ath_hal *ah) 421{ 422 if (AH_PRIVATE(ah)->ah_ispcie) 423 ath_hal_configPCIE(ah, AH_FALSE); 424 else 425 ath_hal_disablePCIE(ah); 426} 427 428static void 429ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 430{ 431 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 432 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 433 OS_DELAY(1000); 434 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 435 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 436 } 437} 438 439static void 440ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 441{ 442 u_int modesIndex, freqIndex; 443 int regWrites = 0; 444 445 /* Setup the indices for the next set of register array writes */ 446 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 447 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 448 freqIndex = 2; 449 if (IEEE80211_IS_CHAN_HT40(chan)) 450 modesIndex = 3; 451 else if (IEEE80211_IS_CHAN_108G(chan)) 452 modesIndex = 5; 453 else 454 modesIndex = 4; 455 } else { 456 freqIndex = 1; 457 if (IEEE80211_IS_CHAN_HT40(chan) || 458 IEEE80211_IS_CHAN_TURBO(chan)) 459 modesIndex = 2; 460 else 461 modesIndex = 1; 462 } 463 464 /* Set correct Baseband to analog shift setting to access analog chips. */ 465 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 466 467 /* 468 * Write addac shifts 469 */ 470 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 471#if 0 472 /* NB: only required for Sowl */ 473 ar5416EepromSetAddac(ah, chan); 474#endif 475 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 476 regWrites); 477 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 478 479 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 480 modesIndex, regWrites); 481 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 482 1, regWrites); 483 484 /* XXX updated regWrites? */ 485 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 486} 487 488/* 489 * Convert to baseband spur frequency given input channel frequency 490 * and compute register settings below. 491 */ 492 493static void 494ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 495{ 496 uint16_t freq = ath_hal_gethwchannel(ah, chan); 497 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 498 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 499 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 500 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 501 static const int inc[4] = { 0, 100, 0, 0 }; 502 503 int bb_spur = AR_NO_SPUR; 504 int bin, cur_bin; 505 int spur_freq_sd; 506 int spur_delta_phase; 507 int denominator; 508 int upper, lower, cur_vit_mask; 509 int tmp, new; 510 int i; 511 512 int8_t mask_m[123]; 513 int8_t mask_p[123]; 514 int8_t mask_amt; 515 int tmp_mask; 516 int cur_bb_spur; 517 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 518 519 OS_MEMZERO(mask_m, sizeof(mask_m)); 520 OS_MEMZERO(mask_p, sizeof(mask_p)); 521 522 /* 523 * Need to verify range +/- 9.5 for static ht20, otherwise spur 524 * is out-of-band and can be ignored. 525 */ 526 /* XXX ath9k changes */ 527 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 528 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 529 if (AR_NO_SPUR == cur_bb_spur) 530 break; 531 cur_bb_spur = cur_bb_spur - (freq * 10); 532 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 533 bb_spur = cur_bb_spur; 534 break; 535 } 536 } 537 if (AR_NO_SPUR == bb_spur) 538 return; 539 540 bin = bb_spur * 32; 541 542 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 543 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 544 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 545 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 546 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 547 548 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 549 550 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 551 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 552 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 553 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 554 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 555 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 556 /* 557 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 558 * config, no offset for HT20. 559 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 560 * /80 for dyn2040. 561 */ 562 spur_delta_phase = ((bb_spur * 524288) / 100) & 563 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 564 /* 565 * in 11A mode the denominator of spur_freq_sd should be 40 and 566 * it should be 44 in 11G 567 */ 568 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 569 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 570 571 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 572 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 573 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 574 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 575 576 577 /* 578 * ============================================ 579 * pilot mask 1 [31:0] = +6..-26, no 0 bin 580 * pilot mask 2 [19:0] = +26..+7 581 * 582 * channel mask 1 [31:0] = +6..-26, no 0 bin 583 * channel mask 2 [19:0] = +26..+7 584 */ 585 //cur_bin = -26; 586 cur_bin = -6000; 587 upper = bin + 100; 588 lower = bin - 100; 589 590 for (i = 0; i < 4; i++) { 591 int pilot_mask = 0; 592 int chan_mask = 0; 593 int bp = 0; 594 for (bp = 0; bp < 30; bp++) { 595 if ((cur_bin > lower) && (cur_bin < upper)) { 596 pilot_mask = pilot_mask | 0x1 << bp; 597 chan_mask = chan_mask | 0x1 << bp; 598 } 599 cur_bin += 100; 600 } 601 cur_bin += inc[i]; 602 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 603 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 604 } 605 606 /* ================================================= 607 * viterbi mask 1 based on channel magnitude 608 * four levels 0-3 609 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 610 * [1 2 2 1] for -9.6 or [1 2 1] for +16 611 * - enable_mask_ppm, all bins move with freq 612 * 613 * - mask_select, 8 bits for rates (reg 67,0x990c) 614 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 615 * choose which mask to use mask or mask2 616 */ 617 618 /* 619 * viterbi mask 2 2nd set for per data rate puncturing 620 * four levels 0-3 621 * - mask_select, 8 bits for rates (reg 67) 622 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 623 * [1 2 2 1] for -9.6 or [1 2 1] for +16 624 */ 625 cur_vit_mask = 6100; 626 upper = bin + 120; 627 lower = bin - 120; 628 629 for (i = 0; i < 123; i++) { 630 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 631 if ((abs(cur_vit_mask - bin)) < 75) { 632 mask_amt = 1; 633 } else { 634 mask_amt = 0; 635 } 636 if (cur_vit_mask < 0) { 637 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 638 } else { 639 mask_p[cur_vit_mask / 100] = mask_amt; 640 } 641 } 642 cur_vit_mask -= 100; 643 } 644 645 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 646 | (mask_m[48] << 26) | (mask_m[49] << 24) 647 | (mask_m[50] << 22) | (mask_m[51] << 20) 648 | (mask_m[52] << 18) | (mask_m[53] << 16) 649 | (mask_m[54] << 14) | (mask_m[55] << 12) 650 | (mask_m[56] << 10) | (mask_m[57] << 8) 651 | (mask_m[58] << 6) | (mask_m[59] << 4) 652 | (mask_m[60] << 2) | (mask_m[61] << 0); 653 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 654 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 655 656 tmp_mask = (mask_m[31] << 28) 657 | (mask_m[32] << 26) | (mask_m[33] << 24) 658 | (mask_m[34] << 22) | (mask_m[35] << 20) 659 | (mask_m[36] << 18) | (mask_m[37] << 16) 660 | (mask_m[48] << 14) | (mask_m[39] << 12) 661 | (mask_m[40] << 10) | (mask_m[41] << 8) 662 | (mask_m[42] << 6) | (mask_m[43] << 4) 663 | (mask_m[44] << 2) | (mask_m[45] << 0); 664 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 665 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 666 667 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 668 | (mask_m[18] << 26) | (mask_m[18] << 24) 669 | (mask_m[20] << 22) | (mask_m[20] << 20) 670 | (mask_m[22] << 18) | (mask_m[22] << 16) 671 | (mask_m[24] << 14) | (mask_m[24] << 12) 672 | (mask_m[25] << 10) | (mask_m[26] << 8) 673 | (mask_m[27] << 6) | (mask_m[28] << 4) 674 | (mask_m[29] << 2) | (mask_m[30] << 0); 675 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 676 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 677 678 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 679 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 680 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 681 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 682 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 683 | (mask_m[10] << 10) | (mask_m[11] << 8) 684 | (mask_m[12] << 6) | (mask_m[13] << 4) 685 | (mask_m[14] << 2) | (mask_m[15] << 0); 686 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 687 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 688 689 tmp_mask = (mask_p[15] << 28) 690 | (mask_p[14] << 26) | (mask_p[13] << 24) 691 | (mask_p[12] << 22) | (mask_p[11] << 20) 692 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 693 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 694 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 695 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 696 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 697 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 698 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 699 700 tmp_mask = (mask_p[30] << 28) 701 | (mask_p[29] << 26) | (mask_p[28] << 24) 702 | (mask_p[27] << 22) | (mask_p[26] << 20) 703 | (mask_p[25] << 18) | (mask_p[24] << 16) 704 | (mask_p[23] << 14) | (mask_p[22] << 12) 705 | (mask_p[21] << 10) | (mask_p[20] << 8) 706 | (mask_p[19] << 6) | (mask_p[18] << 4) 707 | (mask_p[17] << 2) | (mask_p[16] << 0); 708 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 709 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 710 711 tmp_mask = (mask_p[45] << 28) 712 | (mask_p[44] << 26) | (mask_p[43] << 24) 713 | (mask_p[42] << 22) | (mask_p[41] << 20) 714 | (mask_p[40] << 18) | (mask_p[39] << 16) 715 | (mask_p[38] << 14) | (mask_p[37] << 12) 716 | (mask_p[36] << 10) | (mask_p[35] << 8) 717 | (mask_p[34] << 6) | (mask_p[33] << 4) 718 | (mask_p[32] << 2) | (mask_p[31] << 0); 719 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 720 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 721 722 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 723 | (mask_p[59] << 26) | (mask_p[58] << 24) 724 | (mask_p[57] << 22) | (mask_p[56] << 20) 725 | (mask_p[55] << 18) | (mask_p[54] << 16) 726 | (mask_p[53] << 14) | (mask_p[52] << 12) 727 | (mask_p[51] << 10) | (mask_p[50] << 8) 728 | (mask_p[49] << 6) | (mask_p[48] << 4) 729 | (mask_p[47] << 2) | (mask_p[46] << 0); 730 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 731 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 732} 733 734/* 735 * Fill all software cached or static hardware state information. 736 * Return failure if capabilities are to come from EEPROM and 737 * cannot be read. 738 */ 739HAL_BOOL 740ar5416FillCapabilityInfo(struct ath_hal *ah) 741{ 742 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 743 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 744 uint16_t val; 745 746 /* Construct wireless mode from EEPROM */ 747 pCap->halWirelessModes = 0; 748 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 749 pCap->halWirelessModes |= HAL_MODE_11A 750 | HAL_MODE_11NA_HT20 751 | HAL_MODE_11NA_HT40PLUS 752 | HAL_MODE_11NA_HT40MINUS 753 ; 754 } 755 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 756 pCap->halWirelessModes |= HAL_MODE_11G 757 | HAL_MODE_11NG_HT20 758 | HAL_MODE_11NG_HT40PLUS 759 | HAL_MODE_11NG_HT40MINUS 760 ; 761 pCap->halWirelessModes |= HAL_MODE_11A 762 | HAL_MODE_11NA_HT20 763 | HAL_MODE_11NA_HT40PLUS 764 | HAL_MODE_11NA_HT40MINUS 765 ; 766 } 767 768 pCap->halLow2GhzChan = 2312; 769 pCap->halHigh2GhzChan = 2732; 770 771 pCap->halLow5GhzChan = 4915; 772 pCap->halHigh5GhzChan = 6100; 773 774 pCap->halCipherCkipSupport = AH_FALSE; 775 pCap->halCipherTkipSupport = AH_TRUE; 776 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 777 778 pCap->halMicCkipSupport = AH_FALSE; 779 pCap->halMicTkipSupport = AH_TRUE; 780 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 781 /* 782 * Starting with Griffin TX+RX mic keys can be combined 783 * in one key cache slot. 784 */ 785 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 786 pCap->halChanSpreadSupport = AH_TRUE; 787 pCap->halSleepAfterBeaconBroken = AH_TRUE; 788 789 pCap->halCompressSupport = AH_FALSE; 790 pCap->halBurstSupport = AH_TRUE; 791 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 792 pCap->halChapTuningSupport = AH_TRUE; 793 pCap->halTurboPrimeSupport = AH_TRUE; 794 795 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 796 797 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 798 pCap->halVEOLSupport = AH_TRUE; 799 pCap->halBssIdMaskSupport = AH_TRUE; 800 pCap->halMcastKeySrchSupport = AH_FALSE; 801 pCap->halTsfAddSupport = AH_TRUE; 802 803 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 804 pCap->halTotalQueues = val; 805 else 806 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 807 808 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 809 pCap->halKeyCacheSize = val; 810 else 811 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 812 813 /* XXX not needed */ 814 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 815 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 816 817 pCap->halTstampPrecision = 32; 818 pCap->halHwPhyCounterSupport = AH_TRUE; 819 pCap->halIntrMask = HAL_INT_COMMON 820 | HAL_INT_RX 821 | HAL_INT_TX 822 | HAL_INT_FATAL 823 | HAL_INT_BNR 824 | HAL_INT_BMISC 825 | HAL_INT_DTIMSYNC 826 | HAL_INT_TSFOOR 827 | HAL_INT_CST 828 | HAL_INT_GTT 829 ; 830 831 pCap->halFastCCSupport = AH_TRUE; 832 pCap->halNumGpioPins = 6; 833 pCap->halWowSupport = AH_FALSE; 834 pCap->halWowMatchPatternExact = AH_FALSE; 835 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 836 pCap->halAutoSleepSupport = AH_FALSE; 837 pCap->hal4kbSplitTransSupport = AH_TRUE; 838#if 0 /* XXX not yet */ 839 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 840 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 841#endif 842 pCap->halHTSupport = AH_TRUE; 843 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 844 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 845 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 846 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 847 pCap->halTxStreams = 2; 848 pCap->halRxStreams = 2; 849 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 850 pCap->halMbssidAggrSupport = AH_TRUE; 851 pCap->halForcePpmSupport = AH_TRUE; 852 pCap->halEnhancedPmSupport = AH_TRUE; 853 pCap->halBssidMatchSupport = AH_TRUE; 854 855 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 856 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 857 /* NB: enabled by default */ 858 ahpriv->ah_rfkillEnabled = AH_TRUE; 859 pCap->halRfSilentSupport = AH_TRUE; 860 } 861 862 ahpriv->ah_rxornIsFatal = AH_FALSE; 863 864 return AH_TRUE; 865} 866 867static const char* 868ar5416Probe(uint16_t vendorid, uint16_t devid) 869{ 870 if (vendorid == ATHEROS_VENDOR_ID && 871 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 872 return "Atheros 5416"; 873 return AH_NULL; 874} 875AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 876