ar5416_attach.c revision 217686
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17188970Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 217686 2011-01-21 07:26:53Z adrian $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25189747Ssam#include "ah_eeprom_v14.h" 26189747Ssam 27185377Ssam#include "ar5416/ar5416.h" 28185377Ssam#include "ar5416/ar5416reg.h" 29185377Ssam#include "ar5416/ar5416phy.h" 30185377Ssam 31185377Ssam#include "ar5416/ar5416.ini" 32185377Ssam 33188979Ssamstatic void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34189747Ssamstatic void ar5416WriteIni(struct ath_hal *ah, 35189747Ssam const struct ieee80211_channel *chan); 36189747Ssamstatic void ar5416SpurMitigate(struct ath_hal *ah, 37189747Ssam const struct ieee80211_channel *chan); 38188979Ssam 39185377Ssamstatic void 40185377Ssamar5416AniSetup(struct ath_hal *ah) 41185377Ssam{ 42185377Ssam static const struct ar5212AniParams aniparams = { 43185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 46185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 47185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 48185377Ssam .maxSpurImmunityLevel = 2, 49185377Ssam .cycPwrThr1 = { 2, 4, 6 }, 50185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 51185377Ssam .firstep = { 0, 4, 8 }, 52185377Ssam .ofdmTrigHigh = 500, 53185377Ssam .ofdmTrigLow = 200, 54185377Ssam .cckTrigHigh = 200, 55185377Ssam .cckTrigLow = 100, 56185377Ssam .rssiThrHigh = 40, 57185377Ssam .rssiThrLow = 7, 58185377Ssam .period = 100, 59185377Ssam }; 60185377Ssam /* NB: ANI is not enabled yet */ 61185377Ssam ar5212AniAttach(ah, &aniparams, &aniparams, AH_FALSE); 62185377Ssam} 63185377Ssam 64185377Ssam/* 65185377Ssam * Attach for an AR5416 part. 66185377Ssam */ 67185377Ssamvoid 68185377Ssamar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 69185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 70185377Ssam{ 71185377Ssam struct ath_hal_5212 *ahp; 72185377Ssam struct ath_hal *ah; 73185377Ssam 74185377Ssam ahp = &ahp5416->ah_5212; 75185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 76185377Ssam ah = &ahp->ah_priv.h; 77185377Ssam 78185377Ssam /* override 5212 methods for our needs */ 79185377Ssam ah->ah_magic = AR5416_MAGIC; 80185377Ssam ah->ah_getRateTable = ar5416GetRateTable; 81185377Ssam ah->ah_detach = ar5416Detach; 82185377Ssam 83185377Ssam /* Reset functions */ 84185377Ssam ah->ah_reset = ar5416Reset; 85185377Ssam ah->ah_phyDisable = ar5416PhyDisable; 86185377Ssam ah->ah_disable = ar5416Disable; 87188979Ssam ah->ah_configPCIE = ar5416ConfigPCIE; 88185377Ssam ah->ah_perCalibration = ar5416PerCalibration; 89185380Ssam ah->ah_perCalibrationN = ar5416PerCalibrationN, 90185380Ssam ah->ah_resetCalValid = ar5416ResetCalValid, 91185377Ssam ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 92203930Srpaulo ah->ah_setTxPower = ar5416SetTransmitPower; 93203930Srpaulo ah->ah_setBoardValues = ar5416SetBoardValues; 94185377Ssam 95185377Ssam /* Transmit functions */ 96185377Ssam ah->ah_stopTxDma = ar5416StopTxDma; 97185377Ssam ah->ah_setupTxDesc = ar5416SetupTxDesc; 98185377Ssam ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 99185377Ssam ah->ah_fillTxDesc = ar5416FillTxDesc; 100185377Ssam ah->ah_procTxDesc = ar5416ProcTxDesc; 101217621Sadrian ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 102185377Ssam 103185377Ssam /* Receive Functions */ 104185377Ssam ah->ah_startPcuReceive = ar5416StartPcuReceive; 105185377Ssam ah->ah_stopPcuReceive = ar5416StopPcuReceive; 106185377Ssam ah->ah_setupRxDesc = ar5416SetupRxDesc; 107185377Ssam ah->ah_procRxDesc = ar5416ProcRxDesc; 108217684Sadrian ah->ah_rxMonitor = ar5416RxMonitor, 109217684Sadrian ah->ah_aniPoll = ar5416AniPoll, 110185380Ssam ah->ah_procMibEvent = ar5416ProcessMibIntr, 111185377Ssam 112185377Ssam /* Misc Functions */ 113217686Sadrian ah->ah_getCapability = ar5416GetCapability; 114185377Ssam ah->ah_getDiagState = ar5416GetDiagState; 115185377Ssam ah->ah_setLedState = ar5416SetLedState; 116185377Ssam ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 117185377Ssam ah->ah_gpioCfgInput = ar5416GpioCfgInput; 118185377Ssam ah->ah_gpioGet = ar5416GpioGet; 119185377Ssam ah->ah_gpioSet = ar5416GpioSet; 120185377Ssam ah->ah_gpioSetIntr = ar5416GpioSetIntr; 121185377Ssam ah->ah_resetTsf = ar5416ResetTsf; 122185377Ssam ah->ah_getRfGain = ar5416GetRfgain; 123185377Ssam ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 124185377Ssam ah->ah_setDecompMask = ar5416SetDecompMask; 125185377Ssam ah->ah_setCoverageClass = ar5416SetCoverageClass; 126185377Ssam 127185377Ssam ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 128185377Ssam ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 129185377Ssam 130185377Ssam /* Power Management Functions */ 131185377Ssam ah->ah_setPowerMode = ar5416SetPowerMode; 132185377Ssam 133185377Ssam /* Beacon Management Functions */ 134185377Ssam ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 135185377Ssam ah->ah_beaconInit = ar5416BeaconInit; 136185377Ssam ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 137185377Ssam ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 138185377Ssam 139185377Ssam /* XXX 802.11n Functions */ 140185377Ssam#if 0 141185377Ssam ah->ah_chainTxDesc = ar5416ChainTxDesc; 142185377Ssam ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 143185377Ssam ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 144185377Ssam ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 145185377Ssam ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 146185377Ssam ah->ah_clr11nAggr = ar5416Clr11nAggr; 147185377Ssam ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 148185377Ssam ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 149185377Ssam ah->ah_set11nMac2040 = ar5416Set11nMac2040; 150185377Ssam ah->ah_get11nRxClear = ar5416Get11nRxClear; 151185377Ssam ah->ah_set11nRxClear = ar5416Set11nRxClear; 152185377Ssam#endif 153185377Ssam 154185377Ssam /* Interrupt functions */ 155185377Ssam ah->ah_isInterruptPending = ar5416IsInterruptPending; 156185377Ssam ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 157185377Ssam ah->ah_setInterrupts = ar5416SetInterrupts; 158185377Ssam 159185377Ssam ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 160185377Ssam ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 161185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 162185377Ssam ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 163185377Ssam#endif 164185377Ssam ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 165185377Ssam 166189747Ssam AH5416(ah)->ah_writeIni = ar5416WriteIni; 167189747Ssam AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 168185377Ssam /* 169185377Ssam * Start by setting all Owl devices to 2x2 170185377Ssam */ 171185377Ssam AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 172185377Ssam AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 173185377Ssam} 174185377Ssam 175188971Ssamuint32_t 176188971Ssamar5416GetRadioRev(struct ath_hal *ah) 177188971Ssam{ 178188971Ssam uint32_t val; 179188971Ssam int i; 180188971Ssam 181188971Ssam /* Read Radio Chip Rev Extract */ 182188971Ssam OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 183188971Ssam for (i = 0; i < 8; i++) 184188971Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 185188971Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 186188971Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 187188971Ssam return ath_hal_reverseBits(val, 8); 188188971Ssam} 189188971Ssam 190185377Ssam/* 191185377Ssam * Attach for an AR5416 part. 192185377Ssam */ 193188972Ssamstatic struct ath_hal * 194185377Ssamar5416Attach(uint16_t devid, HAL_SOFTC sc, 195217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 196217624Sadrian HAL_STATUS *status) 197185377Ssam{ 198185377Ssam struct ath_hal_5416 *ahp5416; 199185377Ssam struct ath_hal_5212 *ahp; 200185377Ssam struct ath_hal *ah; 201185377Ssam uint32_t val; 202185377Ssam HAL_STATUS ecode; 203185377Ssam HAL_BOOL rfStatus; 204185377Ssam 205185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 206185377Ssam __func__, sc, (void*) st, (void*) sh); 207185377Ssam 208185377Ssam /* NB: memory is returned zero'd */ 209185377Ssam ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 210185377Ssam /* extra space for Owl 2.1/2.2 WAR */ 211185377Ssam sizeof(ar5416Addac) 212185377Ssam ); 213185377Ssam if (ahp5416 == AH_NULL) { 214185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 215185377Ssam "%s: cannot allocate memory for state block\n", __func__); 216185377Ssam *status = HAL_ENOMEM; 217185377Ssam return AH_NULL; 218185377Ssam } 219185377Ssam ar5416InitState(ahp5416, devid, sc, st, sh, status); 220185377Ssam ahp = &ahp5416->ah_5212; 221185377Ssam ah = &ahp->ah_priv.h; 222185377Ssam 223185377Ssam if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 224185377Ssam /* reset chip */ 225185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 226185377Ssam ecode = HAL_EIO; 227185377Ssam goto bad; 228185377Ssam } 229185377Ssam 230185377Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 231185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 232185377Ssam ecode = HAL_EIO; 233185377Ssam goto bad; 234185377Ssam } 235185377Ssam /* Read Revisions from Chips before taking out of reset */ 236185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 237185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 238185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 239188979Ssam AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 240185377Ssam 241185377Ssam /* setup common ini data; rf backends handle remainder */ 242185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 243185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 244185377Ssam 245185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 246185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 247185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 248185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 249185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 250185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 251185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 252185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 253185377Ssam 254185377Ssam if (!IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 255185377Ssam struct ini { 256185377Ssam uint32_t *data; /* NB: !const */ 257185377Ssam int rows, cols; 258185377Ssam }; 259185377Ssam /* override CLKDRV value */ 260185377Ssam OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 261185377Ssam AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 262185377Ssam HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 263185377Ssam } 264185377Ssam 265188979Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 266188979Ssam ar5416AttachPCIE(ah); 267188979Ssam 268188973Ssam ecode = ath_hal_v14EepromAttach(ah); 269188973Ssam if (ecode != HAL_OK) 270188973Ssam goto bad; 271188973Ssam 272185377Ssam if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 273185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 274185377Ssam __func__); 275185377Ssam ecode = HAL_EIO; 276185377Ssam goto bad; 277185377Ssam } 278185377Ssam 279185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 280185377Ssam 281185377Ssam if (!ar5212ChipTest(ah)) { 282185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 283185377Ssam __func__); 284185377Ssam ecode = HAL_ESELFTEST; 285185377Ssam goto bad; 286185377Ssam } 287185377Ssam 288185377Ssam /* 289185377Ssam * Set correct Baseband to analog shift 290185377Ssam * setting to access analog chips. 291185377Ssam */ 292185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 293185377Ssam 294185377Ssam /* Read Radio Chip Rev Extract */ 295185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 296185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 297185377Ssam case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 298185377Ssam case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 299185377Ssam case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 300185377Ssam case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 301185377Ssam break; 302185377Ssam default: 303185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 304185377Ssam /* 305185377Ssam * When RF_Silen is used the analog chip is reset. 306185377Ssam * So when the system boots with radio switch off 307185377Ssam * the RF chip rev reads back as zero and we need 308185377Ssam * to use the mac+phy revs to set the radio rev. 309185377Ssam */ 310185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 311185377Ssam AR_RAD5133_SREV_MAJOR; 312185377Ssam break; 313185377Ssam } 314185377Ssam /* NB: silently accept anything in release code per Atheros */ 315185377Ssam#ifdef AH_DEBUG 316185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 317185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 318185377Ssam "this driver\n", __func__, 319185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 320185377Ssam ecode = HAL_ENOTSUPP; 321185377Ssam goto bad; 322185377Ssam#endif 323185377Ssam } 324185377Ssam 325185377Ssam /* 326185377Ssam * Got everything we need now to setup the capabilities. 327185377Ssam */ 328185377Ssam if (!ar5416FillCapabilityInfo(ah)) { 329185377Ssam ecode = HAL_EEREAD; 330185377Ssam goto bad; 331185377Ssam } 332185377Ssam 333185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 334185377Ssam if (ecode != HAL_OK) { 335185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 336185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 337185377Ssam goto bad; 338185377Ssam } 339185377Ssam /* XXX How about the serial number ? */ 340185377Ssam /* Read Reg Domain */ 341185377Ssam AH_PRIVATE(ah)->ah_currentRD = 342185377Ssam ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 343185377Ssam 344185377Ssam /* 345185377Ssam * ah_miscMode is populated by ar5416FillCapabilityInfo() 346185377Ssam * starting from griffin. Set here to make sure that 347185377Ssam * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 348185380Ssam * placed into hardware. 349185377Ssam */ 350185377Ssam if (ahp->ah_miscMode != 0) 351185377Ssam OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 352185377Ssam 353185377Ssam rfStatus = ar2133RfAttach(ah, &ecode); 354185377Ssam if (!rfStatus) { 355185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 356185377Ssam __func__, ecode); 357185377Ssam goto bad; 358185377Ssam } 359185377Ssam 360185377Ssam ar5416AniSetup(ah); /* Anti Noise Immunity */ 361203882Srpaulo ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 362185377Ssam 363185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 364185377Ssam 365185377Ssam return ah; 366185377Ssambad: 367185377Ssam if (ahp) 368185377Ssam ar5416Detach((struct ath_hal *) ahp); 369185377Ssam if (status) 370185377Ssam *status = ecode; 371185377Ssam return AH_NULL; 372185377Ssam} 373185377Ssam 374185377Ssamvoid 375185377Ssamar5416Detach(struct ath_hal *ah) 376185377Ssam{ 377185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 378185377Ssam 379185377Ssam HALASSERT(ah != AH_NULL); 380185377Ssam HALASSERT(ah->ah_magic == AR5416_MAGIC); 381185377Ssam 382185380Ssam ar5416AniDetach(ah); 383185377Ssam ar5212RfDetach(ah); 384185377Ssam ah->ah_disable(ah); 385185377Ssam ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 386185377Ssam ath_hal_eepromDetach(ah); 387185377Ssam ath_hal_free(ah); 388185377Ssam} 389185377Ssam 390188979Ssamvoid 391188979Ssamar5416AttachPCIE(struct ath_hal *ah) 392188979Ssam{ 393188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) 394188979Ssam ath_hal_configPCIE(ah, AH_FALSE); 395188979Ssam else 396188979Ssam ath_hal_disablePCIE(ah); 397188979Ssam} 398188979Ssam 399188979Ssamstatic void 400188979Ssamar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 401188979Ssam{ 402188979Ssam if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 403188979Ssam ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 404188979Ssam OS_DELAY(1000); 405188979Ssam OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 406188979Ssam OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 407188979Ssam } 408188979Ssam} 409188979Ssam 410189747Ssamstatic void 411189747Ssamar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 412189747Ssam{ 413189747Ssam u_int modesIndex, freqIndex; 414189747Ssam int regWrites = 0; 415189747Ssam 416189747Ssam /* Setup the indices for the next set of register array writes */ 417189747Ssam /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 418189747Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 419189747Ssam freqIndex = 2; 420189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 421189747Ssam modesIndex = 3; 422189747Ssam else if (IEEE80211_IS_CHAN_108G(chan)) 423189747Ssam modesIndex = 5; 424189747Ssam else 425189747Ssam modesIndex = 4; 426189747Ssam } else { 427189747Ssam freqIndex = 1; 428189747Ssam if (IEEE80211_IS_CHAN_HT40(chan) || 429189747Ssam IEEE80211_IS_CHAN_TURBO(chan)) 430189747Ssam modesIndex = 2; 431189747Ssam else 432189747Ssam modesIndex = 1; 433189747Ssam } 434189747Ssam 435189747Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 436189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 437189747Ssam 438189747Ssam /* 439189747Ssam * Write addac shifts 440189747Ssam */ 441189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 442189747Ssam#if 0 443189747Ssam /* NB: only required for Sowl */ 444189747Ssam ar5416EepromSetAddac(ah, chan); 445189747Ssam#endif 446189747Ssam regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 447189747Ssam regWrites); 448189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 449189747Ssam 450189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 451189747Ssam modesIndex, regWrites); 452189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 453189747Ssam 1, regWrites); 454189747Ssam 455189747Ssam /* XXX updated regWrites? */ 456189747Ssam AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 457189747Ssam} 458189747Ssam 459185377Ssam/* 460189747Ssam * Convert to baseband spur frequency given input channel frequency 461189747Ssam * and compute register settings below. 462189747Ssam */ 463189747Ssam 464189747Ssamstatic void 465189747Ssamar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 466189747Ssam{ 467189747Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 468189747Ssam static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 469189747Ssam AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 470189747Ssam static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 471189747Ssam AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 472189747Ssam static const int inc[4] = { 0, 100, 0, 0 }; 473189747Ssam 474189747Ssam int bb_spur = AR_NO_SPUR; 475189747Ssam int bin, cur_bin; 476189747Ssam int spur_freq_sd; 477189747Ssam int spur_delta_phase; 478189747Ssam int denominator; 479189747Ssam int upper, lower, cur_vit_mask; 480189747Ssam int tmp, new; 481189747Ssam int i; 482189747Ssam 483189747Ssam int8_t mask_m[123]; 484189747Ssam int8_t mask_p[123]; 485189747Ssam int8_t mask_amt; 486189747Ssam int tmp_mask; 487189747Ssam int cur_bb_spur; 488189747Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 489189747Ssam 490189747Ssam OS_MEMZERO(mask_m, sizeof(mask_m)); 491189747Ssam OS_MEMZERO(mask_p, sizeof(mask_p)); 492189747Ssam 493189747Ssam /* 494189747Ssam * Need to verify range +/- 9.5 for static ht20, otherwise spur 495189747Ssam * is out-of-band and can be ignored. 496189747Ssam */ 497189747Ssam /* XXX ath9k changes */ 498189747Ssam for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 499189747Ssam cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 500189747Ssam if (AR_NO_SPUR == cur_bb_spur) 501189747Ssam break; 502189747Ssam cur_bb_spur = cur_bb_spur - (freq * 10); 503189747Ssam if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 504189747Ssam bb_spur = cur_bb_spur; 505189747Ssam break; 506189747Ssam } 507189747Ssam } 508189747Ssam if (AR_NO_SPUR == bb_spur) 509189747Ssam return; 510189747Ssam 511189747Ssam bin = bb_spur * 32; 512189747Ssam 513189747Ssam tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 514189747Ssam new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 515189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 516189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 517189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 518189747Ssam 519189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 520189747Ssam 521189747Ssam new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 522189747Ssam AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 523189747Ssam AR_PHY_SPUR_REG_MASK_RATE_SELECT | 524189747Ssam AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 525189747Ssam SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 526189747Ssam OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 527189747Ssam /* 528189747Ssam * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 529189747Ssam * config, no offset for HT20. 530189747Ssam * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 531189747Ssam * /80 for dyn2040. 532189747Ssam */ 533189747Ssam spur_delta_phase = ((bb_spur * 524288) / 100) & 534189747Ssam AR_PHY_TIMING11_SPUR_DELTA_PHASE; 535189747Ssam /* 536189747Ssam * in 11A mode the denominator of spur_freq_sd should be 40 and 537189747Ssam * it should be 44 in 11G 538189747Ssam */ 539189747Ssam denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 540189747Ssam spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 541189747Ssam 542189747Ssam new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 543189747Ssam SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 544189747Ssam SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 545189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 546189747Ssam 547189747Ssam 548189747Ssam /* 549189747Ssam * ============================================ 550189747Ssam * pilot mask 1 [31:0] = +6..-26, no 0 bin 551189747Ssam * pilot mask 2 [19:0] = +26..+7 552189747Ssam * 553189747Ssam * channel mask 1 [31:0] = +6..-26, no 0 bin 554189747Ssam * channel mask 2 [19:0] = +26..+7 555189747Ssam */ 556189747Ssam //cur_bin = -26; 557189747Ssam cur_bin = -6000; 558189747Ssam upper = bin + 100; 559189747Ssam lower = bin - 100; 560189747Ssam 561189747Ssam for (i = 0; i < 4; i++) { 562189747Ssam int pilot_mask = 0; 563189747Ssam int chan_mask = 0; 564189747Ssam int bp = 0; 565189747Ssam for (bp = 0; bp < 30; bp++) { 566189747Ssam if ((cur_bin > lower) && (cur_bin < upper)) { 567189747Ssam pilot_mask = pilot_mask | 0x1 << bp; 568189747Ssam chan_mask = chan_mask | 0x1 << bp; 569189747Ssam } 570189747Ssam cur_bin += 100; 571189747Ssam } 572189747Ssam cur_bin += inc[i]; 573189747Ssam OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 574189747Ssam OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 575189747Ssam } 576189747Ssam 577189747Ssam /* ================================================= 578189747Ssam * viterbi mask 1 based on channel magnitude 579189747Ssam * four levels 0-3 580189747Ssam * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 581189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 582189747Ssam * - enable_mask_ppm, all bins move with freq 583189747Ssam * 584189747Ssam * - mask_select, 8 bits for rates (reg 67,0x990c) 585189747Ssam * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 586189747Ssam * choose which mask to use mask or mask2 587189747Ssam */ 588189747Ssam 589189747Ssam /* 590189747Ssam * viterbi mask 2 2nd set for per data rate puncturing 591189747Ssam * four levels 0-3 592189747Ssam * - mask_select, 8 bits for rates (reg 67) 593189747Ssam * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 594189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 595189747Ssam */ 596189747Ssam cur_vit_mask = 6100; 597189747Ssam upper = bin + 120; 598189747Ssam lower = bin - 120; 599189747Ssam 600189747Ssam for (i = 0; i < 123; i++) { 601189747Ssam if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 602189747Ssam if ((abs(cur_vit_mask - bin)) < 75) { 603189747Ssam mask_amt = 1; 604189747Ssam } else { 605189747Ssam mask_amt = 0; 606189747Ssam } 607189747Ssam if (cur_vit_mask < 0) { 608189747Ssam mask_m[abs(cur_vit_mask / 100)] = mask_amt; 609189747Ssam } else { 610189747Ssam mask_p[cur_vit_mask / 100] = mask_amt; 611189747Ssam } 612189747Ssam } 613189747Ssam cur_vit_mask -= 100; 614189747Ssam } 615189747Ssam 616189747Ssam tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 617189747Ssam | (mask_m[48] << 26) | (mask_m[49] << 24) 618189747Ssam | (mask_m[50] << 22) | (mask_m[51] << 20) 619189747Ssam | (mask_m[52] << 18) | (mask_m[53] << 16) 620189747Ssam | (mask_m[54] << 14) | (mask_m[55] << 12) 621189747Ssam | (mask_m[56] << 10) | (mask_m[57] << 8) 622189747Ssam | (mask_m[58] << 6) | (mask_m[59] << 4) 623189747Ssam | (mask_m[60] << 2) | (mask_m[61] << 0); 624189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 625189747Ssam OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 626189747Ssam 627189747Ssam tmp_mask = (mask_m[31] << 28) 628189747Ssam | (mask_m[32] << 26) | (mask_m[33] << 24) 629189747Ssam | (mask_m[34] << 22) | (mask_m[35] << 20) 630189747Ssam | (mask_m[36] << 18) | (mask_m[37] << 16) 631189747Ssam | (mask_m[48] << 14) | (mask_m[39] << 12) 632189747Ssam | (mask_m[40] << 10) | (mask_m[41] << 8) 633189747Ssam | (mask_m[42] << 6) | (mask_m[43] << 4) 634189747Ssam | (mask_m[44] << 2) | (mask_m[45] << 0); 635189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 636189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 637189747Ssam 638189747Ssam tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 639189747Ssam | (mask_m[18] << 26) | (mask_m[18] << 24) 640189747Ssam | (mask_m[20] << 22) | (mask_m[20] << 20) 641189747Ssam | (mask_m[22] << 18) | (mask_m[22] << 16) 642189747Ssam | (mask_m[24] << 14) | (mask_m[24] << 12) 643189747Ssam | (mask_m[25] << 10) | (mask_m[26] << 8) 644189747Ssam | (mask_m[27] << 6) | (mask_m[28] << 4) 645189747Ssam | (mask_m[29] << 2) | (mask_m[30] << 0); 646189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 647189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 648189747Ssam 649189747Ssam tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 650189747Ssam | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 651189747Ssam | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 652189747Ssam | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 653189747Ssam | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 654189747Ssam | (mask_m[10] << 10) | (mask_m[11] << 8) 655189747Ssam | (mask_m[12] << 6) | (mask_m[13] << 4) 656189747Ssam | (mask_m[14] << 2) | (mask_m[15] << 0); 657189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 658189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 659189747Ssam 660189747Ssam tmp_mask = (mask_p[15] << 28) 661189747Ssam | (mask_p[14] << 26) | (mask_p[13] << 24) 662189747Ssam | (mask_p[12] << 22) | (mask_p[11] << 20) 663189747Ssam | (mask_p[10] << 18) | (mask_p[ 9] << 16) 664189747Ssam | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 665189747Ssam | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 666189747Ssam | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 667189747Ssam | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 668189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 669189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 670189747Ssam 671189747Ssam tmp_mask = (mask_p[30] << 28) 672189747Ssam | (mask_p[29] << 26) | (mask_p[28] << 24) 673189747Ssam | (mask_p[27] << 22) | (mask_p[26] << 20) 674189747Ssam | (mask_p[25] << 18) | (mask_p[24] << 16) 675189747Ssam | (mask_p[23] << 14) | (mask_p[22] << 12) 676189747Ssam | (mask_p[21] << 10) | (mask_p[20] << 8) 677189747Ssam | (mask_p[19] << 6) | (mask_p[18] << 4) 678189747Ssam | (mask_p[17] << 2) | (mask_p[16] << 0); 679189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 680189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 681189747Ssam 682189747Ssam tmp_mask = (mask_p[45] << 28) 683189747Ssam | (mask_p[44] << 26) | (mask_p[43] << 24) 684189747Ssam | (mask_p[42] << 22) | (mask_p[41] << 20) 685189747Ssam | (mask_p[40] << 18) | (mask_p[39] << 16) 686189747Ssam | (mask_p[38] << 14) | (mask_p[37] << 12) 687189747Ssam | (mask_p[36] << 10) | (mask_p[35] << 8) 688189747Ssam | (mask_p[34] << 6) | (mask_p[33] << 4) 689189747Ssam | (mask_p[32] << 2) | (mask_p[31] << 0); 690189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 691189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 692189747Ssam 693189747Ssam tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 694189747Ssam | (mask_p[59] << 26) | (mask_p[58] << 24) 695189747Ssam | (mask_p[57] << 22) | (mask_p[56] << 20) 696189747Ssam | (mask_p[55] << 18) | (mask_p[54] << 16) 697189747Ssam | (mask_p[53] << 14) | (mask_p[52] << 12) 698189747Ssam | (mask_p[51] << 10) | (mask_p[50] << 8) 699189747Ssam | (mask_p[49] << 6) | (mask_p[48] << 4) 700189747Ssam | (mask_p[47] << 2) | (mask_p[46] << 0); 701189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 702189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 703189747Ssam} 704189747Ssam 705189747Ssam/* 706185377Ssam * Fill all software cached or static hardware state information. 707185377Ssam * Return failure if capabilities are to come from EEPROM and 708185377Ssam * cannot be read. 709185377Ssam */ 710185377SsamHAL_BOOL 711185377Ssamar5416FillCapabilityInfo(struct ath_hal *ah) 712185377Ssam{ 713185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 714185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 715185377Ssam uint16_t val; 716185377Ssam 717185377Ssam /* Construct wireless mode from EEPROM */ 718185377Ssam pCap->halWirelessModes = 0; 719185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 720185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 721185377Ssam | HAL_MODE_11NA_HT20 722185377Ssam | HAL_MODE_11NA_HT40PLUS 723185377Ssam | HAL_MODE_11NA_HT40MINUS 724185377Ssam ; 725185377Ssam } 726185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 727185377Ssam pCap->halWirelessModes |= HAL_MODE_11G 728185377Ssam | HAL_MODE_11NG_HT20 729185377Ssam | HAL_MODE_11NG_HT40PLUS 730185377Ssam | HAL_MODE_11NG_HT40MINUS 731185377Ssam ; 732185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 733185377Ssam | HAL_MODE_11NA_HT20 734185377Ssam | HAL_MODE_11NA_HT40PLUS 735185377Ssam | HAL_MODE_11NA_HT40MINUS 736185377Ssam ; 737185377Ssam } 738185377Ssam 739185377Ssam pCap->halLow2GhzChan = 2312; 740185377Ssam pCap->halHigh2GhzChan = 2732; 741185377Ssam 742185377Ssam pCap->halLow5GhzChan = 4915; 743185377Ssam pCap->halHigh5GhzChan = 6100; 744185377Ssam 745185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 746185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 747185377Ssam pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 748185377Ssam 749185377Ssam pCap->halMicCkipSupport = AH_FALSE; 750185377Ssam pCap->halMicTkipSupport = AH_TRUE; 751185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 752185377Ssam /* 753185377Ssam * Starting with Griffin TX+RX mic keys can be combined 754185377Ssam * in one key cache slot. 755185377Ssam */ 756185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 757185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 758185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 759185377Ssam 760185377Ssam pCap->halCompressSupport = AH_FALSE; 761185377Ssam pCap->halBurstSupport = AH_TRUE; 762185377Ssam pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 763185377Ssam pCap->halChapTuningSupport = AH_TRUE; 764185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 765185377Ssam 766185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 767185377Ssam 768185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 769185377Ssam pCap->halVEOLSupport = AH_TRUE; 770185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 771185377Ssam pCap->halMcastKeySrchSupport = AH_FALSE; 772185377Ssam pCap->halTsfAddSupport = AH_TRUE; 773185377Ssam 774185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 775185377Ssam pCap->halTotalQueues = val; 776185377Ssam else 777185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 778185377Ssam 779185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 780185377Ssam pCap->halKeyCacheSize = val; 781185377Ssam else 782185377Ssam pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 783185377Ssam 784185377Ssam /* XXX not needed */ 785185377Ssam pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 786185377Ssam pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 787185377Ssam 788185377Ssam pCap->halTstampPrecision = 32; 789185377Ssam pCap->halHwPhyCounterSupport = AH_TRUE; 790192396Ssam pCap->halIntrMask = HAL_INT_COMMON 791192396Ssam | HAL_INT_RX 792192396Ssam | HAL_INT_TX 793192396Ssam | HAL_INT_FATAL 794192396Ssam | HAL_INT_BNR 795192396Ssam | HAL_INT_BMISC 796192396Ssam | HAL_INT_DTIMSYNC 797192396Ssam | HAL_INT_TSFOOR 798192396Ssam | HAL_INT_CST 799192396Ssam | HAL_INT_GTT 800192396Ssam ; 801185377Ssam 802185377Ssam pCap->halFastCCSupport = AH_TRUE; 803185377Ssam pCap->halNumGpioPins = 6; 804185377Ssam pCap->halWowSupport = AH_FALSE; 805185377Ssam pCap->halWowMatchPatternExact = AH_FALSE; 806185377Ssam pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 807185377Ssam pCap->halAutoSleepSupport = AH_FALSE; 808185377Ssam#if 0 /* XXX not yet */ 809185377Ssam pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 810185377Ssam pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 811185377Ssam#endif 812185377Ssam pCap->halHTSupport = AH_TRUE; 813185377Ssam pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 814185377Ssam /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 815185377Ssam pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 816185377Ssam pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 817185377Ssam pCap->halMbssidAggrSupport = AH_TRUE; 818185377Ssam pCap->halForcePpmSupport = AH_TRUE; 819185377Ssam pCap->halEnhancedPmSupport = AH_TRUE; 820195114Ssam pCap->halBssidMatchSupport = AH_TRUE; 821185377Ssam 822185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 823185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 824185377Ssam /* NB: enabled by default */ 825185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 826185377Ssam pCap->halRfSilentSupport = AH_TRUE; 827185377Ssam } 828185377Ssam 829185377Ssam ahpriv->ah_rxornIsFatal = AH_FALSE; 830185377Ssam 831185377Ssam return AH_TRUE; 832185377Ssam} 833185406Ssam 834185406Ssamstatic const char* 835185406Ssamar5416Probe(uint16_t vendorid, uint16_t devid) 836185406Ssam{ 837185406Ssam if (vendorid == ATHEROS_VENDOR_ID && 838185406Ssam (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 839185406Ssam return "Atheros 5416"; 840185406Ssam return AH_NULL; 841185406Ssam} 842185418SsamAH_CHIP(AR5416, ar5416Probe, ar5416Attach); 843