ar5416_attach.c revision 203882
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 203882 2010-02-14 16:26:32Z rpaulo $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar5416/ar5416.ini" 32 33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34static void ar5416WriteIni(struct ath_hal *ah, 35 const struct ieee80211_channel *chan); 36static void ar5416SpurMitigate(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 39static void 40ar5416AniSetup(struct ath_hal *ah) 41{ 42 static const struct ar5212AniParams aniparams = { 43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45 .coarseHigh = { -14, -14, -14, -14, -12 }, 46 .coarseLow = { -64, -64, -64, -64, -70 }, 47 .firpwr = { -78, -78, -78, -78, -80 }, 48 .maxSpurImmunityLevel = 2, 49 .cycPwrThr1 = { 2, 4, 6 }, 50 .maxFirstepLevel = 2, /* levels 0..2 */ 51 .firstep = { 0, 4, 8 }, 52 .ofdmTrigHigh = 500, 53 .ofdmTrigLow = 200, 54 .cckTrigHigh = 200, 55 .cckTrigLow = 100, 56 .rssiThrHigh = 40, 57 .rssiThrLow = 7, 58 .period = 100, 59 }; 60 /* NB: ANI is not enabled yet */ 61 ar5212AniAttach(ah, &aniparams, &aniparams, AH_FALSE); 62} 63 64/* 65 * Attach for an AR5416 part. 66 */ 67void 68ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 69 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 70{ 71 struct ath_hal_5212 *ahp; 72 struct ath_hal *ah; 73 74 ahp = &ahp5416->ah_5212; 75 ar5212InitState(ahp, devid, sc, st, sh, status); 76 ah = &ahp->ah_priv.h; 77 78 /* override 5212 methods for our needs */ 79 ah->ah_magic = AR5416_MAGIC; 80 ah->ah_getRateTable = ar5416GetRateTable; 81 ah->ah_detach = ar5416Detach; 82 83 /* Reset functions */ 84 ah->ah_reset = ar5416Reset; 85 ah->ah_phyDisable = ar5416PhyDisable; 86 ah->ah_disable = ar5416Disable; 87 ah->ah_configPCIE = ar5416ConfigPCIE; 88 ah->ah_perCalibration = ar5416PerCalibration; 89 ah->ah_perCalibrationN = ar5416PerCalibrationN, 90 ah->ah_resetCalValid = ar5416ResetCalValid, 91 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 92 93 /* Transmit functions */ 94 ah->ah_stopTxDma = ar5416StopTxDma; 95 ah->ah_setupTxDesc = ar5416SetupTxDesc; 96 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 97 ah->ah_fillTxDesc = ar5416FillTxDesc; 98 ah->ah_procTxDesc = ar5416ProcTxDesc; 99 100 /* Receive Functions */ 101 ah->ah_startPcuReceive = ar5416StartPcuReceive; 102 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 103 ah->ah_setupRxDesc = ar5416SetupRxDesc; 104 ah->ah_procRxDesc = ar5416ProcRxDesc; 105 ah->ah_rxMonitor = ar5416AniPoll, 106 ah->ah_procMibEvent = ar5416ProcessMibIntr, 107 108 /* Misc Functions */ 109 ah->ah_getDiagState = ar5416GetDiagState; 110 ah->ah_setLedState = ar5416SetLedState; 111 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 112 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 113 ah->ah_gpioGet = ar5416GpioGet; 114 ah->ah_gpioSet = ar5416GpioSet; 115 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 116 ah->ah_resetTsf = ar5416ResetTsf; 117 ah->ah_getRfGain = ar5416GetRfgain; 118 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 119 ah->ah_setDecompMask = ar5416SetDecompMask; 120 ah->ah_setCoverageClass = ar5416SetCoverageClass; 121 122 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 123 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 124 125 /* Power Management Functions */ 126 ah->ah_setPowerMode = ar5416SetPowerMode; 127 128 /* Beacon Management Functions */ 129 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 130 ah->ah_beaconInit = ar5416BeaconInit; 131 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 132 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 133 134 /* XXX 802.11n Functions */ 135#if 0 136 ah->ah_chainTxDesc = ar5416ChainTxDesc; 137 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 138 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 139 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 140 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 141 ah->ah_clr11nAggr = ar5416Clr11nAggr; 142 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 143 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 144 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 145 ah->ah_get11nRxClear = ar5416Get11nRxClear; 146 ah->ah_set11nRxClear = ar5416Set11nRxClear; 147#endif 148 149 /* Interrupt functions */ 150 ah->ah_isInterruptPending = ar5416IsInterruptPending; 151 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 152 ah->ah_setInterrupts = ar5416SetInterrupts; 153 154 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 155 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 156#ifdef AH_SUPPORT_WRITE_EEPROM 157 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 158#endif 159 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 160 161 AH5416(ah)->ah_writeIni = ar5416WriteIni; 162 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 163 /* 164 * Start by setting all Owl devices to 2x2 165 */ 166 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 167 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 168} 169 170uint32_t 171ar5416GetRadioRev(struct ath_hal *ah) 172{ 173 uint32_t val; 174 int i; 175 176 /* Read Radio Chip Rev Extract */ 177 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 178 for (i = 0; i < 8; i++) 179 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 180 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 181 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 182 return ath_hal_reverseBits(val, 8); 183} 184 185/* 186 * Attach for an AR5416 part. 187 */ 188static struct ath_hal * 189ar5416Attach(uint16_t devid, HAL_SOFTC sc, 190 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 191{ 192 struct ath_hal_5416 *ahp5416; 193 struct ath_hal_5212 *ahp; 194 struct ath_hal *ah; 195 uint32_t val; 196 HAL_STATUS ecode; 197 HAL_BOOL rfStatus; 198 199 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 200 __func__, sc, (void*) st, (void*) sh); 201 202 /* NB: memory is returned zero'd */ 203 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 204 /* extra space for Owl 2.1/2.2 WAR */ 205 sizeof(ar5416Addac) 206 ); 207 if (ahp5416 == AH_NULL) { 208 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 209 "%s: cannot allocate memory for state block\n", __func__); 210 *status = HAL_ENOMEM; 211 return AH_NULL; 212 } 213 ar5416InitState(ahp5416, devid, sc, st, sh, status); 214 ahp = &ahp5416->ah_5212; 215 ah = &ahp->ah_priv.h; 216 217 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 218 /* reset chip */ 219 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 220 ecode = HAL_EIO; 221 goto bad; 222 } 223 224 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 225 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 226 ecode = HAL_EIO; 227 goto bad; 228 } 229 /* Read Revisions from Chips before taking out of reset */ 230 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 231 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 232 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 233 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 234 235 /* setup common ini data; rf backends handle remainder */ 236 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 237 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 238 239 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 240 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 241 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 242 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 243 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 244 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 245 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 246 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 247 248 if (!IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 249 struct ini { 250 uint32_t *data; /* NB: !const */ 251 int rows, cols; 252 }; 253 /* override CLKDRV value */ 254 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 255 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 256 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 257 } 258 259 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 260 ar5416AttachPCIE(ah); 261 262 ecode = ath_hal_v14EepromAttach(ah); 263 if (ecode != HAL_OK) 264 goto bad; 265 266 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 267 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 268 __func__); 269 ecode = HAL_EIO; 270 goto bad; 271 } 272 273 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 274 275 if (!ar5212ChipTest(ah)) { 276 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 277 __func__); 278 ecode = HAL_ESELFTEST; 279 goto bad; 280 } 281 282 /* 283 * Set correct Baseband to analog shift 284 * setting to access analog chips. 285 */ 286 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 287 288 /* Read Radio Chip Rev Extract */ 289 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 290 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 291 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 292 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 293 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 294 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 295 break; 296 default: 297 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 298 /* 299 * When RF_Silen is used the analog chip is reset. 300 * So when the system boots with radio switch off 301 * the RF chip rev reads back as zero and we need 302 * to use the mac+phy revs to set the radio rev. 303 */ 304 AH_PRIVATE(ah)->ah_analog5GhzRev = 305 AR_RAD5133_SREV_MAJOR; 306 break; 307 } 308 /* NB: silently accept anything in release code per Atheros */ 309#ifdef AH_DEBUG 310 HALDEBUG(ah, HAL_DEBUG_ANY, 311 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 312 "this driver\n", __func__, 313 AH_PRIVATE(ah)->ah_analog5GhzRev); 314 ecode = HAL_ENOTSUPP; 315 goto bad; 316#endif 317 } 318 319 /* 320 * Got everything we need now to setup the capabilities. 321 */ 322 if (!ar5416FillCapabilityInfo(ah)) { 323 ecode = HAL_EEREAD; 324 goto bad; 325 } 326 327 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 328 if (ecode != HAL_OK) { 329 HALDEBUG(ah, HAL_DEBUG_ANY, 330 "%s: error getting mac address from EEPROM\n", __func__); 331 goto bad; 332 } 333 /* XXX How about the serial number ? */ 334 /* Read Reg Domain */ 335 AH_PRIVATE(ah)->ah_currentRD = 336 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 337 338 /* 339 * ah_miscMode is populated by ar5416FillCapabilityInfo() 340 * starting from griffin. Set here to make sure that 341 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 342 * placed into hardware. 343 */ 344 if (ahp->ah_miscMode != 0) 345 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 346 347 rfStatus = ar2133RfAttach(ah, &ecode); 348 if (!rfStatus) { 349 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 350 __func__, ecode); 351 goto bad; 352 } 353 354 ar5416AniSetup(ah); /* Anti Noise Immunity */ 355 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 356 357 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 358 359 return ah; 360bad: 361 if (ahp) 362 ar5416Detach((struct ath_hal *) ahp); 363 if (status) 364 *status = ecode; 365 return AH_NULL; 366} 367 368void 369ar5416Detach(struct ath_hal *ah) 370{ 371 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 372 373 HALASSERT(ah != AH_NULL); 374 HALASSERT(ah->ah_magic == AR5416_MAGIC); 375 376 ar5416AniDetach(ah); 377 ar5212RfDetach(ah); 378 ah->ah_disable(ah); 379 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 380 ath_hal_eepromDetach(ah); 381 ath_hal_free(ah); 382} 383 384void 385ar5416AttachPCIE(struct ath_hal *ah) 386{ 387 if (AH_PRIVATE(ah)->ah_ispcie) 388 ath_hal_configPCIE(ah, AH_FALSE); 389 else 390 ath_hal_disablePCIE(ah); 391} 392 393static void 394ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 395{ 396 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 397 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 398 OS_DELAY(1000); 399 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 400 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 401 } 402} 403 404static void 405ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 406{ 407 u_int modesIndex, freqIndex; 408 int regWrites = 0; 409 410 /* Setup the indices for the next set of register array writes */ 411 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 412 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 413 freqIndex = 2; 414 if (IEEE80211_IS_CHAN_HT40(chan)) 415 modesIndex = 3; 416 else if (IEEE80211_IS_CHAN_108G(chan)) 417 modesIndex = 5; 418 else 419 modesIndex = 4; 420 } else { 421 freqIndex = 1; 422 if (IEEE80211_IS_CHAN_HT40(chan) || 423 IEEE80211_IS_CHAN_TURBO(chan)) 424 modesIndex = 2; 425 else 426 modesIndex = 1; 427 } 428 429 /* Set correct Baseband to analog shift setting to access analog chips. */ 430 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 431 432 /* 433 * Write addac shifts 434 */ 435 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 436#if 0 437 /* NB: only required for Sowl */ 438 ar5416EepromSetAddac(ah, chan); 439#endif 440 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 441 regWrites); 442 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 443 444 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 445 modesIndex, regWrites); 446 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 447 1, regWrites); 448 449 /* XXX updated regWrites? */ 450 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 451} 452 453/* 454 * Convert to baseband spur frequency given input channel frequency 455 * and compute register settings below. 456 */ 457 458static void 459ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 460{ 461 uint16_t freq = ath_hal_gethwchannel(ah, chan); 462 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 463 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 464 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 465 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 466 static const int inc[4] = { 0, 100, 0, 0 }; 467 468 int bb_spur = AR_NO_SPUR; 469 int bin, cur_bin; 470 int spur_freq_sd; 471 int spur_delta_phase; 472 int denominator; 473 int upper, lower, cur_vit_mask; 474 int tmp, new; 475 int i; 476 477 int8_t mask_m[123]; 478 int8_t mask_p[123]; 479 int8_t mask_amt; 480 int tmp_mask; 481 int cur_bb_spur; 482 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 483 484 OS_MEMZERO(mask_m, sizeof(mask_m)); 485 OS_MEMZERO(mask_p, sizeof(mask_p)); 486 487 /* 488 * Need to verify range +/- 9.5 for static ht20, otherwise spur 489 * is out-of-band and can be ignored. 490 */ 491 /* XXX ath9k changes */ 492 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 493 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 494 if (AR_NO_SPUR == cur_bb_spur) 495 break; 496 cur_bb_spur = cur_bb_spur - (freq * 10); 497 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 498 bb_spur = cur_bb_spur; 499 break; 500 } 501 } 502 if (AR_NO_SPUR == bb_spur) 503 return; 504 505 bin = bb_spur * 32; 506 507 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 508 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 509 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 510 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 511 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 512 513 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 514 515 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 516 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 517 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 518 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 519 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 520 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 521 /* 522 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 523 * config, no offset for HT20. 524 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 525 * /80 for dyn2040. 526 */ 527 spur_delta_phase = ((bb_spur * 524288) / 100) & 528 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 529 /* 530 * in 11A mode the denominator of spur_freq_sd should be 40 and 531 * it should be 44 in 11G 532 */ 533 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 534 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 535 536 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 537 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 538 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 539 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 540 541 542 /* 543 * ============================================ 544 * pilot mask 1 [31:0] = +6..-26, no 0 bin 545 * pilot mask 2 [19:0] = +26..+7 546 * 547 * channel mask 1 [31:0] = +6..-26, no 0 bin 548 * channel mask 2 [19:0] = +26..+7 549 */ 550 //cur_bin = -26; 551 cur_bin = -6000; 552 upper = bin + 100; 553 lower = bin - 100; 554 555 for (i = 0; i < 4; i++) { 556 int pilot_mask = 0; 557 int chan_mask = 0; 558 int bp = 0; 559 for (bp = 0; bp < 30; bp++) { 560 if ((cur_bin > lower) && (cur_bin < upper)) { 561 pilot_mask = pilot_mask | 0x1 << bp; 562 chan_mask = chan_mask | 0x1 << bp; 563 } 564 cur_bin += 100; 565 } 566 cur_bin += inc[i]; 567 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 568 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 569 } 570 571 /* ================================================= 572 * viterbi mask 1 based on channel magnitude 573 * four levels 0-3 574 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 575 * [1 2 2 1] for -9.6 or [1 2 1] for +16 576 * - enable_mask_ppm, all bins move with freq 577 * 578 * - mask_select, 8 bits for rates (reg 67,0x990c) 579 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 580 * choose which mask to use mask or mask2 581 */ 582 583 /* 584 * viterbi mask 2 2nd set for per data rate puncturing 585 * four levels 0-3 586 * - mask_select, 8 bits for rates (reg 67) 587 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 588 * [1 2 2 1] for -9.6 or [1 2 1] for +16 589 */ 590 cur_vit_mask = 6100; 591 upper = bin + 120; 592 lower = bin - 120; 593 594 for (i = 0; i < 123; i++) { 595 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 596 if ((abs(cur_vit_mask - bin)) < 75) { 597 mask_amt = 1; 598 } else { 599 mask_amt = 0; 600 } 601 if (cur_vit_mask < 0) { 602 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 603 } else { 604 mask_p[cur_vit_mask / 100] = mask_amt; 605 } 606 } 607 cur_vit_mask -= 100; 608 } 609 610 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 611 | (mask_m[48] << 26) | (mask_m[49] << 24) 612 | (mask_m[50] << 22) | (mask_m[51] << 20) 613 | (mask_m[52] << 18) | (mask_m[53] << 16) 614 | (mask_m[54] << 14) | (mask_m[55] << 12) 615 | (mask_m[56] << 10) | (mask_m[57] << 8) 616 | (mask_m[58] << 6) | (mask_m[59] << 4) 617 | (mask_m[60] << 2) | (mask_m[61] << 0); 618 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 619 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 620 621 tmp_mask = (mask_m[31] << 28) 622 | (mask_m[32] << 26) | (mask_m[33] << 24) 623 | (mask_m[34] << 22) | (mask_m[35] << 20) 624 | (mask_m[36] << 18) | (mask_m[37] << 16) 625 | (mask_m[48] << 14) | (mask_m[39] << 12) 626 | (mask_m[40] << 10) | (mask_m[41] << 8) 627 | (mask_m[42] << 6) | (mask_m[43] << 4) 628 | (mask_m[44] << 2) | (mask_m[45] << 0); 629 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 630 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 631 632 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 633 | (mask_m[18] << 26) | (mask_m[18] << 24) 634 | (mask_m[20] << 22) | (mask_m[20] << 20) 635 | (mask_m[22] << 18) | (mask_m[22] << 16) 636 | (mask_m[24] << 14) | (mask_m[24] << 12) 637 | (mask_m[25] << 10) | (mask_m[26] << 8) 638 | (mask_m[27] << 6) | (mask_m[28] << 4) 639 | (mask_m[29] << 2) | (mask_m[30] << 0); 640 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 641 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 642 643 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 644 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 645 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 646 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 647 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 648 | (mask_m[10] << 10) | (mask_m[11] << 8) 649 | (mask_m[12] << 6) | (mask_m[13] << 4) 650 | (mask_m[14] << 2) | (mask_m[15] << 0); 651 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 652 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 653 654 tmp_mask = (mask_p[15] << 28) 655 | (mask_p[14] << 26) | (mask_p[13] << 24) 656 | (mask_p[12] << 22) | (mask_p[11] << 20) 657 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 658 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 659 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 660 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 661 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 662 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 663 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 664 665 tmp_mask = (mask_p[30] << 28) 666 | (mask_p[29] << 26) | (mask_p[28] << 24) 667 | (mask_p[27] << 22) | (mask_p[26] << 20) 668 | (mask_p[25] << 18) | (mask_p[24] << 16) 669 | (mask_p[23] << 14) | (mask_p[22] << 12) 670 | (mask_p[21] << 10) | (mask_p[20] << 8) 671 | (mask_p[19] << 6) | (mask_p[18] << 4) 672 | (mask_p[17] << 2) | (mask_p[16] << 0); 673 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 674 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 675 676 tmp_mask = (mask_p[45] << 28) 677 | (mask_p[44] << 26) | (mask_p[43] << 24) 678 | (mask_p[42] << 22) | (mask_p[41] << 20) 679 | (mask_p[40] << 18) | (mask_p[39] << 16) 680 | (mask_p[38] << 14) | (mask_p[37] << 12) 681 | (mask_p[36] << 10) | (mask_p[35] << 8) 682 | (mask_p[34] << 6) | (mask_p[33] << 4) 683 | (mask_p[32] << 2) | (mask_p[31] << 0); 684 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 685 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 686 687 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 688 | (mask_p[59] << 26) | (mask_p[58] << 24) 689 | (mask_p[57] << 22) | (mask_p[56] << 20) 690 | (mask_p[55] << 18) | (mask_p[54] << 16) 691 | (mask_p[53] << 14) | (mask_p[52] << 12) 692 | (mask_p[51] << 10) | (mask_p[50] << 8) 693 | (mask_p[49] << 6) | (mask_p[48] << 4) 694 | (mask_p[47] << 2) | (mask_p[46] << 0); 695 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 696 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 697} 698 699/* 700 * Fill all software cached or static hardware state information. 701 * Return failure if capabilities are to come from EEPROM and 702 * cannot be read. 703 */ 704HAL_BOOL 705ar5416FillCapabilityInfo(struct ath_hal *ah) 706{ 707 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 708 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 709 uint16_t val; 710 711 /* Construct wireless mode from EEPROM */ 712 pCap->halWirelessModes = 0; 713 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 714 pCap->halWirelessModes |= HAL_MODE_11A 715 | HAL_MODE_11NA_HT20 716 | HAL_MODE_11NA_HT40PLUS 717 | HAL_MODE_11NA_HT40MINUS 718 ; 719 } 720 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 721 pCap->halWirelessModes |= HAL_MODE_11G 722 | HAL_MODE_11NG_HT20 723 | HAL_MODE_11NG_HT40PLUS 724 | HAL_MODE_11NG_HT40MINUS 725 ; 726 pCap->halWirelessModes |= HAL_MODE_11A 727 | HAL_MODE_11NA_HT20 728 | HAL_MODE_11NA_HT40PLUS 729 | HAL_MODE_11NA_HT40MINUS 730 ; 731 } 732 733 pCap->halLow2GhzChan = 2312; 734 pCap->halHigh2GhzChan = 2732; 735 736 pCap->halLow5GhzChan = 4915; 737 pCap->halHigh5GhzChan = 6100; 738 739 pCap->halCipherCkipSupport = AH_FALSE; 740 pCap->halCipherTkipSupport = AH_TRUE; 741 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 742 743 pCap->halMicCkipSupport = AH_FALSE; 744 pCap->halMicTkipSupport = AH_TRUE; 745 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 746 /* 747 * Starting with Griffin TX+RX mic keys can be combined 748 * in one key cache slot. 749 */ 750 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 751 pCap->halChanSpreadSupport = AH_TRUE; 752 pCap->halSleepAfterBeaconBroken = AH_TRUE; 753 754 pCap->halCompressSupport = AH_FALSE; 755 pCap->halBurstSupport = AH_TRUE; 756 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 757 pCap->halChapTuningSupport = AH_TRUE; 758 pCap->halTurboPrimeSupport = AH_TRUE; 759 760 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 761 762 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 763 pCap->halVEOLSupport = AH_TRUE; 764 pCap->halBssIdMaskSupport = AH_TRUE; 765 pCap->halMcastKeySrchSupport = AH_FALSE; 766 pCap->halTsfAddSupport = AH_TRUE; 767 768 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 769 pCap->halTotalQueues = val; 770 else 771 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 772 773 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 774 pCap->halKeyCacheSize = val; 775 else 776 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 777 778 /* XXX not needed */ 779 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 780 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 781 782 pCap->halTstampPrecision = 32; 783 pCap->halHwPhyCounterSupport = AH_TRUE; 784 pCap->halIntrMask = HAL_INT_COMMON 785 | HAL_INT_RX 786 | HAL_INT_TX 787 | HAL_INT_FATAL 788 | HAL_INT_BNR 789 | HAL_INT_BMISC 790 | HAL_INT_DTIMSYNC 791 | HAL_INT_TSFOOR 792 | HAL_INT_CST 793 | HAL_INT_GTT 794 ; 795 796 pCap->halFastCCSupport = AH_TRUE; 797 pCap->halNumGpioPins = 6; 798 pCap->halWowSupport = AH_FALSE; 799 pCap->halWowMatchPatternExact = AH_FALSE; 800 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 801 pCap->halAutoSleepSupport = AH_FALSE; 802#if 0 /* XXX not yet */ 803 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 804 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 805#endif 806 pCap->halHTSupport = AH_TRUE; 807 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 808 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 809 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 810 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 811 pCap->halMbssidAggrSupport = AH_TRUE; 812 pCap->halForcePpmSupport = AH_TRUE; 813 pCap->halEnhancedPmSupport = AH_TRUE; 814 pCap->halBssidMatchSupport = AH_TRUE; 815 816 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 817 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 818 /* NB: enabled by default */ 819 ahpriv->ah_rfkillEnabled = AH_TRUE; 820 pCap->halRfSilentSupport = AH_TRUE; 821 } 822 823 ahpriv->ah_rxornIsFatal = AH_FALSE; 824 825 return AH_TRUE; 826} 827 828static const char* 829ar5416Probe(uint16_t vendorid, uint16_t devid) 830{ 831 if (vendorid == ATHEROS_VENDOR_ID && 832 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 833 return "Atheros 5416"; 834 return AH_NULL; 835} 836AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 837