1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17188970Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25189747Ssam#include "ah_eeprom_v14.h" 26189747Ssam 27185377Ssam#include "ar5416/ar5416.h" 28185377Ssam#include "ar5416/ar5416reg.h" 29185377Ssam#include "ar5416/ar5416phy.h" 30185377Ssam 31185377Ssam#include "ar5416/ar5416.ini" 32185377Ssam 33235972Sadrianstatic void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 34235972Sadrian HAL_BOOL power_off); 35235957Sadrianstatic void ar5416DisablePCIE(struct ath_hal *ah); 36189747Ssamstatic void ar5416WriteIni(struct ath_hal *ah, 37189747Ssam const struct ieee80211_channel *chan); 38189747Ssamstatic void ar5416SpurMitigate(struct ath_hal *ah, 39189747Ssam const struct ieee80211_channel *chan); 40188979Ssam 41185377Ssamstatic void 42185377Ssamar5416AniSetup(struct ath_hal *ah) 43185377Ssam{ 44185377Ssam static const struct ar5212AniParams aniparams = { 45185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 46185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 47185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 48185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 49185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 50242408Sadrian .maxSpurImmunityLevel = 7, 51242408Sadrian .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 52185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 53185377Ssam .firstep = { 0, 4, 8 }, 54185377Ssam .ofdmTrigHigh = 500, 55185377Ssam .ofdmTrigLow = 200, 56185377Ssam .cckTrigHigh = 200, 57185377Ssam .cckTrigLow = 100, 58185377Ssam .rssiThrHigh = 40, 59185377Ssam .rssiThrLow = 7, 60185377Ssam .period = 100, 61185377Ssam }; 62219979Sadrian /* NB: disable ANI noise immmunity for reliable RIFS rx */ 63222276Sadrian AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 64242411Sadrian ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 65185377Ssam} 66185377Ssam 67185377Ssam/* 68219393Sadrian * AR5416 doesn't do OLC or temperature compensation. 69219393Sadrian */ 70219393Sadrianstatic void 71219393Sadrianar5416olcInit(struct ath_hal *ah) 72219393Sadrian{ 73219393Sadrian} 74219393Sadrian 75219393Sadrianstatic void 76219393Sadrianar5416olcTempCompensation(struct ath_hal *ah) 77219393Sadrian{ 78219393Sadrian} 79219393Sadrian 80219393Sadrian/* 81185377Ssam * Attach for an AR5416 part. 82185377Ssam */ 83185377Ssamvoid 84185377Ssamar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 85185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 86185377Ssam{ 87185377Ssam struct ath_hal_5212 *ahp; 88185377Ssam struct ath_hal *ah; 89185377Ssam 90185377Ssam ahp = &ahp5416->ah_5212; 91185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 92185377Ssam ah = &ahp->ah_priv.h; 93185377Ssam 94185377Ssam /* override 5212 methods for our needs */ 95185377Ssam ah->ah_magic = AR5416_MAGIC; 96185377Ssam ah->ah_getRateTable = ar5416GetRateTable; 97185377Ssam ah->ah_detach = ar5416Detach; 98185377Ssam 99185377Ssam /* Reset functions */ 100185377Ssam ah->ah_reset = ar5416Reset; 101185377Ssam ah->ah_phyDisable = ar5416PhyDisable; 102185377Ssam ah->ah_disable = ar5416Disable; 103188979Ssam ah->ah_configPCIE = ar5416ConfigPCIE; 104235957Sadrian ah->ah_disablePCIE = ar5416DisablePCIE; 105185377Ssam ah->ah_perCalibration = ar5416PerCalibration; 106305615Spfg ah->ah_perCalibrationN = ar5416PerCalibrationN; 107305615Spfg ah->ah_resetCalValid = ar5416ResetCalValid; 108185377Ssam ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 109203930Srpaulo ah->ah_setTxPower = ar5416SetTransmitPower; 110203930Srpaulo ah->ah_setBoardValues = ar5416SetBoardValues; 111185377Ssam 112185377Ssam /* Transmit functions */ 113185377Ssam ah->ah_stopTxDma = ar5416StopTxDma; 114185377Ssam ah->ah_setupTxDesc = ar5416SetupTxDesc; 115185377Ssam ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 116185377Ssam ah->ah_fillTxDesc = ar5416FillTxDesc; 117185377Ssam ah->ah_procTxDesc = ar5416ProcTxDesc; 118217621Sadrian ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 119219792Sadrian ah->ah_setupTxQueue = ar5416SetupTxQueue; 120219792Sadrian ah->ah_resetTxQueue = ar5416ResetTxQueue; 121185377Ssam 122185377Ssam /* Receive Functions */ 123224512Sadrian ah->ah_getRxFilter = ar5416GetRxFilter; 124224512Sadrian ah->ah_setRxFilter = ar5416SetRxFilter; 125234747Sadrian ah->ah_stopDmaReceive = ar5416StopDmaReceive; 126185377Ssam ah->ah_startPcuReceive = ar5416StartPcuReceive; 127185377Ssam ah->ah_stopPcuReceive = ar5416StopPcuReceive; 128185377Ssam ah->ah_setupRxDesc = ar5416SetupRxDesc; 129185377Ssam ah->ah_procRxDesc = ar5416ProcRxDesc; 130217687Sadrian ah->ah_rxMonitor = ar5416RxMonitor; 131217687Sadrian ah->ah_aniPoll = ar5416AniPoll; 132217687Sadrian ah->ah_procMibEvent = ar5416ProcessMibIntr; 133185377Ssam 134185377Ssam /* Misc Functions */ 135217686Sadrian ah->ah_getCapability = ar5416GetCapability; 136231368Sadrian ah->ah_setCapability = ar5416SetCapability; 137185377Ssam ah->ah_getDiagState = ar5416GetDiagState; 138185377Ssam ah->ah_setLedState = ar5416SetLedState; 139185377Ssam ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 140185377Ssam ah->ah_gpioCfgInput = ar5416GpioCfgInput; 141185377Ssam ah->ah_gpioGet = ar5416GpioGet; 142185377Ssam ah->ah_gpioSet = ar5416GpioSet; 143185377Ssam ah->ah_gpioSetIntr = ar5416GpioSetIntr; 144225444Sadrian ah->ah_getTsf64 = ar5416GetTsf64; 145243424Sadrian ah->ah_setTsf64 = ar5416SetTsf64; 146185377Ssam ah->ah_resetTsf = ar5416ResetTsf; 147185377Ssam ah->ah_getRfGain = ar5416GetRfgain; 148185377Ssam ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 149185377Ssam ah->ah_setDecompMask = ar5416SetDecompMask; 150185377Ssam ah->ah_setCoverageClass = ar5416SetCoverageClass; 151222644Sadrian ah->ah_setQuiet = ar5416SetQuiet; 152234873Sadrian ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts; 153247286Sadrian ah->ah_setChainMasks = ar5416SetChainMasks; 154185377Ssam 155185377Ssam ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 156185377Ssam ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 157185377Ssam 158222584Sadrian /* DFS Functions */ 159222584Sadrian ah->ah_enableDfs = ar5416EnableDfs; 160222584Sadrian ah->ah_getDfsThresh = ar5416GetDfsThresh; 161239638Sadrian ah->ah_getDfsDefaultThresh = ar5416GetDfsDefaultThresh; 162222815Sadrian ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 163224709Sadrian ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 164222584Sadrian 165244943Sadrian /* Spectral Scan Functions */ 166244943Sadrian ah->ah_spectralConfigure = ar5416ConfigureSpectralScan; 167244943Sadrian ah->ah_spectralGetConfig = ar5416GetSpectralParams; 168244943Sadrian ah->ah_spectralStart = ar5416StartSpectralScan; 169244943Sadrian ah->ah_spectralStop = ar5416StopSpectralScan; 170244943Sadrian ah->ah_spectralIsEnabled = ar5416IsSpectralEnabled; 171244943Sadrian ah->ah_spectralIsActive = ar5416IsSpectralActive; 172244943Sadrian 173185377Ssam /* Power Management Functions */ 174185377Ssam ah->ah_setPowerMode = ar5416SetPowerMode; 175185377Ssam 176185377Ssam /* Beacon Management Functions */ 177185377Ssam ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 178185377Ssam ah->ah_beaconInit = ar5416BeaconInit; 179185377Ssam ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 180185377Ssam ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 181225444Sadrian ah->ah_getNextTBTT = ar5416GetNextTBTT; 182185377Ssam 183218066Sadrian /* 802.11n Functions */ 184185377Ssam ah->ah_chainTxDesc = ar5416ChainTxDesc; 185185377Ssam ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 186185377Ssam ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 187185377Ssam ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 188226767Sadrian ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 189185377Ssam ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 190226767Sadrian ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 191185377Ssam ah->ah_clr11nAggr = ar5416Clr11nAggr; 192185377Ssam ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 193185377Ssam ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 194185377Ssam ah->ah_set11nMac2040 = ar5416Set11nMac2040; 195185377Ssam ah->ah_get11nRxClear = ar5416Get11nRxClear; 196185377Ssam ah->ah_set11nRxClear = ar5416Set11nRxClear; 197247774Sadrian ah->ah_set11nVirtMoreFrag = ar5416Set11nVirtualMoreFrag; 198185377Ssam 199185377Ssam /* Interrupt functions */ 200185377Ssam ah->ah_isInterruptPending = ar5416IsInterruptPending; 201185377Ssam ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 202185377Ssam ah->ah_setInterrupts = ar5416SetInterrupts; 203185377Ssam 204243840Sadrian /* Bluetooth Coexistence functions */ 205243840Sadrian ah->ah_btCoexSetInfo = ar5416SetBTCoexInfo; 206243840Sadrian ah->ah_btCoexSetConfig = ar5416BTCoexConfig; 207243840Sadrian ah->ah_btCoexSetQcuThresh = ar5416BTCoexSetQcuThresh; 208243840Sadrian ah->ah_btCoexSetWeights = ar5416BTCoexSetWeights; 209243840Sadrian ah->ah_btCoexSetBmissThresh = ar5416BTCoexSetupBmissThresh; 210251483Sadrian ah->ah_btCoexSetParameter = ar5416BTCoexSetParameter; 211243840Sadrian ah->ah_btCoexDisable = ar5416BTCoexDisable; 212243840Sadrian ah->ah_btCoexEnable = ar5416BTCoexEnable; 213243843Sadrian AH5416(ah)->ah_btCoexSetDiversity = ar5416BTCoexAntennaDiversity; 214243840Sadrian 215185377Ssam ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 216185377Ssam ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 217185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 218185377Ssam ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 219185377Ssam#endif 220185377Ssam ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 221185377Ssam 222219393Sadrian /* Internal ops */ 223189747Ssam AH5416(ah)->ah_writeIni = ar5416WriteIni; 224189747Ssam AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 225219393Sadrian 226220990Sadrian /* Internal baseband ops */ 227220990Sadrian AH5416(ah)->ah_initPLL = ar5416InitPLL; 228220990Sadrian 229219480Sadrian /* Internal calibration ops */ 230219480Sadrian AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 231219480Sadrian 232219393Sadrian /* Internal TX power control related operations */ 233219393Sadrian AH5416(ah)->ah_olcInit = ar5416olcInit; 234219393Sadrian AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 235219393Sadrian AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 236219393Sadrian 237185377Ssam /* 238185377Ssam * Start by setting all Owl devices to 2x2 239185377Ssam */ 240185377Ssam AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 241185377Ssam AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 242218763Sadrian 243218763Sadrian /* Enable all ANI functions to begin with */ 244222276Sadrian AH5416(ah)->ah_ani_function = 0xffffffff; 245222265Sadrian 246247033Sadrian /* Set overridable ANI methods */ 247247033Sadrian AH5212(ah)->ah_aniControl = ar5416AniControl; 248247033Sadrian 249247092Sadrian /* 250247092Sadrian * Default FIFO Trigger levels 251247092Sadrian * 252247092Sadrian * These define how filled the TX FIFO needs to be before 253247092Sadrian * the baseband begins to be given some data. 254247092Sadrian * 255247092Sadrian * To be paranoid, we ensure that the TX trigger level always 256247092Sadrian * has at least enough space for two TX DMA to occur. 257247092Sadrian * The TX DMA size is currently hard-coded to AR_TXCFG_DMASZ_128B. 258247092Sadrian * That means we need to leave at least 256 bytes available in 259247092Sadrian * the TX DMA FIFO. 260247092Sadrian */ 261247033Sadrian#define AR_FTRIG_512B 0x00000080 // 5 bits total 262247092Sadrian /* 263247092Sadrian * AR9285/AR9271 have half the size TX FIFO compared to 264247092Sadrian * other devices 265247092Sadrian */ 266247033Sadrian if (AR_SREV_KITE(ah) || AR_SREV_9271(ah)) { 267247033Sadrian AH5212(ah)->ah_txTrigLev = (AR_FTRIG_256B >> AR_FTRIG_S); 268247033Sadrian AH5212(ah)->ah_maxTxTrigLev = ((2048 / 64) - 1); 269247033Sadrian } else { 270247033Sadrian AH5212(ah)->ah_txTrigLev = (AR_FTRIG_512B >> AR_FTRIG_S); 271247033Sadrian AH5212(ah)->ah_maxTxTrigLev = ((4096 / 64) - 1); 272247033Sadrian } 273247033Sadrian#undef AR_FTRIG_512B 274247092Sadrian 275247092Sadrian /* And now leave some headspace - 256 bytes */ 276247092Sadrian AH5212(ah)->ah_maxTxTrigLev -= 4; 277185377Ssam} 278185377Ssam 279188971Ssamuint32_t 280188971Ssamar5416GetRadioRev(struct ath_hal *ah) 281188971Ssam{ 282188971Ssam uint32_t val; 283188971Ssam int i; 284188971Ssam 285188971Ssam /* Read Radio Chip Rev Extract */ 286188971Ssam OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 287188971Ssam for (i = 0; i < 8; i++) 288188971Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 289188971Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 290188971Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 291188971Ssam return ath_hal_reverseBits(val, 8); 292188971Ssam} 293188971Ssam 294185377Ssam/* 295185377Ssam * Attach for an AR5416 part. 296185377Ssam */ 297188972Ssamstatic struct ath_hal * 298185377Ssamar5416Attach(uint16_t devid, HAL_SOFTC sc, 299217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 300217624Sadrian HAL_STATUS *status) 301185377Ssam{ 302185377Ssam struct ath_hal_5416 *ahp5416; 303185377Ssam struct ath_hal_5212 *ahp; 304185377Ssam struct ath_hal *ah; 305185377Ssam uint32_t val; 306185377Ssam HAL_STATUS ecode; 307185377Ssam HAL_BOOL rfStatus; 308185377Ssam 309225883Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 310185377Ssam __func__, sc, (void*) st, (void*) sh); 311185377Ssam 312185377Ssam /* NB: memory is returned zero'd */ 313185377Ssam ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 314185377Ssam /* extra space for Owl 2.1/2.2 WAR */ 315185377Ssam sizeof(ar5416Addac) 316185377Ssam ); 317185377Ssam if (ahp5416 == AH_NULL) { 318225883Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 319185377Ssam "%s: cannot allocate memory for state block\n", __func__); 320185377Ssam *status = HAL_ENOMEM; 321185377Ssam return AH_NULL; 322185377Ssam } 323185377Ssam ar5416InitState(ahp5416, devid, sc, st, sh, status); 324185377Ssam ahp = &ahp5416->ah_5212; 325185377Ssam ah = &ahp->ah_priv.h; 326185377Ssam 327185377Ssam if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 328185377Ssam /* reset chip */ 329185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 330185377Ssam ecode = HAL_EIO; 331185377Ssam goto bad; 332185377Ssam } 333185377Ssam 334185377Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 335185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 336185377Ssam ecode = HAL_EIO; 337185377Ssam goto bad; 338185377Ssam } 339185377Ssam /* Read Revisions from Chips before taking out of reset */ 340185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 341185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 342185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 343188979Ssam AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 344185377Ssam 345185377Ssam /* setup common ini data; rf backends handle remainder */ 346185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 347185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 348185377Ssam 349185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 350185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 351185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 352185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 353185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 354185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 355185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 356185377Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 357185377Ssam 358219840Sadrian if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 359219839Sadrian ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 360185377Ssam struct ini { 361185377Ssam uint32_t *data; /* NB: !const */ 362185377Ssam int rows, cols; 363185377Ssam }; 364185377Ssam /* override CLKDRV value */ 365185377Ssam OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 366185377Ssam AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 367185377Ssam HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 368185377Ssam } 369185377Ssam 370188979Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 371188979Ssam ar5416AttachPCIE(ah); 372188979Ssam 373188973Ssam ecode = ath_hal_v14EepromAttach(ah); 374188973Ssam if (ecode != HAL_OK) 375188973Ssam goto bad; 376188973Ssam 377185377Ssam if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 378185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 379185377Ssam __func__); 380185377Ssam ecode = HAL_EIO; 381185377Ssam goto bad; 382185377Ssam } 383185377Ssam 384185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 385185377Ssam 386185377Ssam if (!ar5212ChipTest(ah)) { 387185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 388185377Ssam __func__); 389185377Ssam ecode = HAL_ESELFTEST; 390185377Ssam goto bad; 391185377Ssam } 392185377Ssam 393185377Ssam /* 394185377Ssam * Set correct Baseband to analog shift 395185377Ssam * setting to access analog chips. 396185377Ssam */ 397185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 398185377Ssam 399185377Ssam /* Read Radio Chip Rev Extract */ 400228515Sadrian AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 401185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 402185377Ssam case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 403185377Ssam case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 404185377Ssam case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 405185377Ssam case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 406185377Ssam break; 407185377Ssam default: 408185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 409185377Ssam /* 410185377Ssam * When RF_Silen is used the analog chip is reset. 411185377Ssam * So when the system boots with radio switch off 412185377Ssam * the RF chip rev reads back as zero and we need 413185377Ssam * to use the mac+phy revs to set the radio rev. 414185377Ssam */ 415185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 416185377Ssam AR_RAD5133_SREV_MAJOR; 417185377Ssam break; 418185377Ssam } 419185377Ssam /* NB: silently accept anything in release code per Atheros */ 420185377Ssam#ifdef AH_DEBUG 421185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 422185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 423185377Ssam "this driver\n", __func__, 424185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 425185377Ssam ecode = HAL_ENOTSUPP; 426185377Ssam goto bad; 427185377Ssam#endif 428185377Ssam } 429185377Ssam 430185377Ssam /* 431185377Ssam * Got everything we need now to setup the capabilities. 432185377Ssam */ 433185377Ssam if (!ar5416FillCapabilityInfo(ah)) { 434185377Ssam ecode = HAL_EEREAD; 435185377Ssam goto bad; 436185377Ssam } 437185377Ssam 438185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 439185377Ssam if (ecode != HAL_OK) { 440185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 441185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 442185377Ssam goto bad; 443185377Ssam } 444185377Ssam /* XXX How about the serial number ? */ 445185377Ssam /* Read Reg Domain */ 446185377Ssam AH_PRIVATE(ah)->ah_currentRD = 447185377Ssam ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 448221596Sadrian AH_PRIVATE(ah)->ah_currentRDext = 449221596Sadrian ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 450185377Ssam 451185377Ssam /* 452185377Ssam * ah_miscMode is populated by ar5416FillCapabilityInfo() 453185377Ssam * starting from griffin. Set here to make sure that 454185377Ssam * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 455185380Ssam * placed into hardware. 456185377Ssam */ 457185377Ssam if (ahp->ah_miscMode != 0) 458219771Sadrian OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 459185377Ssam 460185377Ssam rfStatus = ar2133RfAttach(ah, &ecode); 461185377Ssam if (!rfStatus) { 462185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 463185377Ssam __func__, ecode); 464185377Ssam goto bad; 465185377Ssam } 466185377Ssam 467185377Ssam ar5416AniSetup(ah); /* Anti Noise Immunity */ 468218068Sadrian 469218068Sadrian AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 470218068Sadrian AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 471218068Sadrian AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 472218068Sadrian AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 473218068Sadrian AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 474218068Sadrian AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 475218068Sadrian 476203882Srpaulo ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 477185377Ssam 478185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 479185377Ssam 480185377Ssam return ah; 481185377Ssambad: 482185377Ssam if (ahp) 483185377Ssam ar5416Detach((struct ath_hal *) ahp); 484185377Ssam if (status) 485185377Ssam *status = ecode; 486185377Ssam return AH_NULL; 487185377Ssam} 488185377Ssam 489185377Ssamvoid 490185377Ssamar5416Detach(struct ath_hal *ah) 491185377Ssam{ 492185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 493185377Ssam 494185377Ssam HALASSERT(ah != AH_NULL); 495185377Ssam HALASSERT(ah->ah_magic == AR5416_MAGIC); 496185377Ssam 497221777Sadrian /* Make sure that chip is awake before writing to it */ 498221777Sadrian if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 499221777Sadrian HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 500221777Sadrian "%s: failed to wake up chip\n", 501221777Sadrian __func__); 502221777Sadrian 503185380Ssam ar5416AniDetach(ah); 504185377Ssam ar5212RfDetach(ah); 505185377Ssam ah->ah_disable(ah); 506185377Ssam ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 507185377Ssam ath_hal_eepromDetach(ah); 508185377Ssam ath_hal_free(ah); 509185377Ssam} 510185377Ssam 511188979Ssamvoid 512188979Ssamar5416AttachPCIE(struct ath_hal *ah) 513188979Ssam{ 514188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) 515235972Sadrian ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 516188979Ssam else 517188979Ssam ath_hal_disablePCIE(ah); 518188979Ssam} 519188979Ssam 520188979Ssamstatic void 521235972Sadrianar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 522188979Ssam{ 523236017Sadrian 524236017Sadrian /* This is only applicable for AR5418 (AR5416 PCIe) */ 525236017Sadrian if (! AH_PRIVATE(ah)->ah_ispcie) 526236017Sadrian return; 527236017Sadrian 528236017Sadrian if (! restore) { 529188979Ssam ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 530188979Ssam OS_DELAY(1000); 531236017Sadrian } 532236017Sadrian 533236017Sadrian if (power_off) { /* Power-off */ 534236017Sadrian /* clear bit 19 to disable L1 */ 535236017Sadrian OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 536236017Sadrian } else { /* Power-on */ 537236017Sadrian /* Set default WAR values for Owl */ 538236017Sadrian OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 539236017Sadrian 540236017Sadrian /* set bit 19 to allow forcing of pcie core into L1 state */ 541188979Ssam OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 542188979Ssam } 543188979Ssam} 544188979Ssam 545236017Sadrian/* 546236017Sadrian * Disable PCIe PHY if PCIe isn't used. 547236017Sadrian */ 548189747Ssamstatic void 549235957Sadrianar5416DisablePCIE(struct ath_hal *ah) 550235957Sadrian{ 551236017Sadrian 552236017Sadrian /* PCIe? Don't */ 553236017Sadrian if (AH_PRIVATE(ah)->ah_ispcie) 554236017Sadrian return; 555236017Sadrian 556236017Sadrian /* .. Only applicable for AR5416v2 or later */ 557236017Sadrian if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah))) 558236017Sadrian return; 559236017Sadrian 560236017Sadrian OS_REG_WRITE_BUFFER_ENABLE(ah); 561236017Sadrian 562236017Sadrian /* 563236017Sadrian * Disable the PCIe PHY. 564236017Sadrian */ 565236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 566236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 567236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 568236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 569236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 570236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 571236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 572236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 573236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 574236017Sadrian 575236017Sadrian /* Load the new settings */ 576236017Sadrian OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 577236017Sadrian 578236017Sadrian OS_REG_WRITE_BUFFER_FLUSH(ah); 579236017Sadrian OS_REG_WRITE_BUFFER_DISABLE(ah); 580235957Sadrian} 581235957Sadrian 582235957Sadrianstatic void 583189747Ssamar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 584189747Ssam{ 585189747Ssam u_int modesIndex, freqIndex; 586189747Ssam int regWrites = 0; 587189747Ssam 588189747Ssam /* Setup the indices for the next set of register array writes */ 589189747Ssam /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 590189747Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 591189747Ssam freqIndex = 2; 592189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 593189747Ssam modesIndex = 3; 594189747Ssam else if (IEEE80211_IS_CHAN_108G(chan)) 595189747Ssam modesIndex = 5; 596189747Ssam else 597189747Ssam modesIndex = 4; 598189747Ssam } else { 599189747Ssam freqIndex = 1; 600189747Ssam if (IEEE80211_IS_CHAN_HT40(chan) || 601189747Ssam IEEE80211_IS_CHAN_TURBO(chan)) 602189747Ssam modesIndex = 2; 603189747Ssam else 604189747Ssam modesIndex = 1; 605189747Ssam } 606189747Ssam 607189747Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 608189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 609189747Ssam 610189747Ssam /* 611189747Ssam * Write addac shifts 612189747Ssam */ 613189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 614219863Sadrian 615189747Ssam /* NB: only required for Sowl */ 616219863Sadrian if (AR_SREV_SOWL(ah)) 617219863Sadrian ar5416EepromSetAddac(ah, chan); 618219863Sadrian 619189747Ssam regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 620189747Ssam regWrites); 621189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 622189747Ssam 623189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 624189747Ssam modesIndex, regWrites); 625189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 626189747Ssam 1, regWrites); 627189747Ssam 628189747Ssam /* XXX updated regWrites? */ 629189747Ssam AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 630189747Ssam} 631189747Ssam 632185377Ssam/* 633189747Ssam * Convert to baseband spur frequency given input channel frequency 634189747Ssam * and compute register settings below. 635189747Ssam */ 636189747Ssam 637189747Ssamstatic void 638189747Ssamar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 639189747Ssam{ 640189747Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 641189747Ssam static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 642189747Ssam AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 643189747Ssam static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 644189747Ssam AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 645189747Ssam static const int inc[4] = { 0, 100, 0, 0 }; 646189747Ssam 647189747Ssam int bb_spur = AR_NO_SPUR; 648189747Ssam int bin, cur_bin; 649189747Ssam int spur_freq_sd; 650189747Ssam int spur_delta_phase; 651189747Ssam int denominator; 652189747Ssam int upper, lower, cur_vit_mask; 653189747Ssam int tmp, new; 654189747Ssam int i; 655189747Ssam 656189747Ssam int8_t mask_m[123]; 657189747Ssam int8_t mask_p[123]; 658189747Ssam int8_t mask_amt; 659189747Ssam int tmp_mask; 660189747Ssam int cur_bb_spur; 661189747Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 662189747Ssam 663189747Ssam OS_MEMZERO(mask_m, sizeof(mask_m)); 664189747Ssam OS_MEMZERO(mask_p, sizeof(mask_p)); 665189747Ssam 666189747Ssam /* 667189747Ssam * Need to verify range +/- 9.5 for static ht20, otherwise spur 668189747Ssam * is out-of-band and can be ignored. 669189747Ssam */ 670189747Ssam /* XXX ath9k changes */ 671189747Ssam for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 672189747Ssam cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 673189747Ssam if (AR_NO_SPUR == cur_bb_spur) 674189747Ssam break; 675189747Ssam cur_bb_spur = cur_bb_spur - (freq * 10); 676189747Ssam if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 677189747Ssam bb_spur = cur_bb_spur; 678189747Ssam break; 679189747Ssam } 680189747Ssam } 681189747Ssam if (AR_NO_SPUR == bb_spur) 682189747Ssam return; 683189747Ssam 684189747Ssam bin = bb_spur * 32; 685189747Ssam 686189747Ssam tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 687189747Ssam new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 688189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 689189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 690189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 691189747Ssam 692234664Sadrian OS_REG_WRITE_BUFFER_ENABLE(ah); 693234664Sadrian 694189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 695189747Ssam 696189747Ssam new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 697189747Ssam AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 698189747Ssam AR_PHY_SPUR_REG_MASK_RATE_SELECT | 699189747Ssam AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 700189747Ssam SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 701189747Ssam OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 702189747Ssam /* 703189747Ssam * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 704189747Ssam * config, no offset for HT20. 705189747Ssam * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 706189747Ssam * /80 for dyn2040. 707189747Ssam */ 708189747Ssam spur_delta_phase = ((bb_spur * 524288) / 100) & 709189747Ssam AR_PHY_TIMING11_SPUR_DELTA_PHASE; 710189747Ssam /* 711189747Ssam * in 11A mode the denominator of spur_freq_sd should be 40 and 712189747Ssam * it should be 44 in 11G 713189747Ssam */ 714189747Ssam denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 715189747Ssam spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 716189747Ssam 717189747Ssam new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 718189747Ssam SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 719189747Ssam SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 720189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 721189747Ssam 722189747Ssam 723189747Ssam /* 724189747Ssam * ============================================ 725189747Ssam * pilot mask 1 [31:0] = +6..-26, no 0 bin 726189747Ssam * pilot mask 2 [19:0] = +26..+7 727189747Ssam * 728189747Ssam * channel mask 1 [31:0] = +6..-26, no 0 bin 729189747Ssam * channel mask 2 [19:0] = +26..+7 730189747Ssam */ 731189747Ssam //cur_bin = -26; 732189747Ssam cur_bin = -6000; 733189747Ssam upper = bin + 100; 734189747Ssam lower = bin - 100; 735189747Ssam 736189747Ssam for (i = 0; i < 4; i++) { 737189747Ssam int pilot_mask = 0; 738189747Ssam int chan_mask = 0; 739189747Ssam int bp = 0; 740189747Ssam for (bp = 0; bp < 30; bp++) { 741189747Ssam if ((cur_bin > lower) && (cur_bin < upper)) { 742189747Ssam pilot_mask = pilot_mask | 0x1 << bp; 743189747Ssam chan_mask = chan_mask | 0x1 << bp; 744189747Ssam } 745189747Ssam cur_bin += 100; 746189747Ssam } 747189747Ssam cur_bin += inc[i]; 748189747Ssam OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 749189747Ssam OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 750189747Ssam } 751189747Ssam 752189747Ssam /* ================================================= 753189747Ssam * viterbi mask 1 based on channel magnitude 754189747Ssam * four levels 0-3 755189747Ssam * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 756189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 757189747Ssam * - enable_mask_ppm, all bins move with freq 758189747Ssam * 759189747Ssam * - mask_select, 8 bits for rates (reg 67,0x990c) 760189747Ssam * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 761189747Ssam * choose which mask to use mask or mask2 762189747Ssam */ 763189747Ssam 764189747Ssam /* 765189747Ssam * viterbi mask 2 2nd set for per data rate puncturing 766189747Ssam * four levels 0-3 767189747Ssam * - mask_select, 8 bits for rates (reg 67) 768189747Ssam * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 769189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 770189747Ssam */ 771189747Ssam cur_vit_mask = 6100; 772189747Ssam upper = bin + 120; 773189747Ssam lower = bin - 120; 774189747Ssam 775189747Ssam for (i = 0; i < 123; i++) { 776189747Ssam if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 777189747Ssam if ((abs(cur_vit_mask - bin)) < 75) { 778189747Ssam mask_amt = 1; 779189747Ssam } else { 780189747Ssam mask_amt = 0; 781189747Ssam } 782189747Ssam if (cur_vit_mask < 0) { 783189747Ssam mask_m[abs(cur_vit_mask / 100)] = mask_amt; 784189747Ssam } else { 785189747Ssam mask_p[cur_vit_mask / 100] = mask_amt; 786189747Ssam } 787189747Ssam } 788189747Ssam cur_vit_mask -= 100; 789189747Ssam } 790189747Ssam 791189747Ssam tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 792189747Ssam | (mask_m[48] << 26) | (mask_m[49] << 24) 793189747Ssam | (mask_m[50] << 22) | (mask_m[51] << 20) 794189747Ssam | (mask_m[52] << 18) | (mask_m[53] << 16) 795189747Ssam | (mask_m[54] << 14) | (mask_m[55] << 12) 796189747Ssam | (mask_m[56] << 10) | (mask_m[57] << 8) 797189747Ssam | (mask_m[58] << 6) | (mask_m[59] << 4) 798189747Ssam | (mask_m[60] << 2) | (mask_m[61] << 0); 799189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 800189747Ssam OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 801189747Ssam 802189747Ssam tmp_mask = (mask_m[31] << 28) 803189747Ssam | (mask_m[32] << 26) | (mask_m[33] << 24) 804189747Ssam | (mask_m[34] << 22) | (mask_m[35] << 20) 805189747Ssam | (mask_m[36] << 18) | (mask_m[37] << 16) 806189747Ssam | (mask_m[48] << 14) | (mask_m[39] << 12) 807189747Ssam | (mask_m[40] << 10) | (mask_m[41] << 8) 808189747Ssam | (mask_m[42] << 6) | (mask_m[43] << 4) 809189747Ssam | (mask_m[44] << 2) | (mask_m[45] << 0); 810189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 811189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 812189747Ssam 813189747Ssam tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 814189747Ssam | (mask_m[18] << 26) | (mask_m[18] << 24) 815189747Ssam | (mask_m[20] << 22) | (mask_m[20] << 20) 816189747Ssam | (mask_m[22] << 18) | (mask_m[22] << 16) 817189747Ssam | (mask_m[24] << 14) | (mask_m[24] << 12) 818189747Ssam | (mask_m[25] << 10) | (mask_m[26] << 8) 819189747Ssam | (mask_m[27] << 6) | (mask_m[28] << 4) 820189747Ssam | (mask_m[29] << 2) | (mask_m[30] << 0); 821189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 822189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 823189747Ssam 824189747Ssam tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 825189747Ssam | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 826189747Ssam | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 827189747Ssam | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 828189747Ssam | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 829189747Ssam | (mask_m[10] << 10) | (mask_m[11] << 8) 830189747Ssam | (mask_m[12] << 6) | (mask_m[13] << 4) 831189747Ssam | (mask_m[14] << 2) | (mask_m[15] << 0); 832189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 833189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 834189747Ssam 835189747Ssam tmp_mask = (mask_p[15] << 28) 836189747Ssam | (mask_p[14] << 26) | (mask_p[13] << 24) 837189747Ssam | (mask_p[12] << 22) | (mask_p[11] << 20) 838189747Ssam | (mask_p[10] << 18) | (mask_p[ 9] << 16) 839189747Ssam | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 840189747Ssam | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 841189747Ssam | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 842189747Ssam | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 843189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 844189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 845189747Ssam 846189747Ssam tmp_mask = (mask_p[30] << 28) 847189747Ssam | (mask_p[29] << 26) | (mask_p[28] << 24) 848189747Ssam | (mask_p[27] << 22) | (mask_p[26] << 20) 849189747Ssam | (mask_p[25] << 18) | (mask_p[24] << 16) 850189747Ssam | (mask_p[23] << 14) | (mask_p[22] << 12) 851189747Ssam | (mask_p[21] << 10) | (mask_p[20] << 8) 852189747Ssam | (mask_p[19] << 6) | (mask_p[18] << 4) 853189747Ssam | (mask_p[17] << 2) | (mask_p[16] << 0); 854189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 855189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 856189747Ssam 857189747Ssam tmp_mask = (mask_p[45] << 28) 858189747Ssam | (mask_p[44] << 26) | (mask_p[43] << 24) 859189747Ssam | (mask_p[42] << 22) | (mask_p[41] << 20) 860189747Ssam | (mask_p[40] << 18) | (mask_p[39] << 16) 861189747Ssam | (mask_p[38] << 14) | (mask_p[37] << 12) 862189747Ssam | (mask_p[36] << 10) | (mask_p[35] << 8) 863189747Ssam | (mask_p[34] << 6) | (mask_p[33] << 4) 864189747Ssam | (mask_p[32] << 2) | (mask_p[31] << 0); 865189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 866189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 867189747Ssam 868189747Ssam tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 869189747Ssam | (mask_p[59] << 26) | (mask_p[58] << 24) 870189747Ssam | (mask_p[57] << 22) | (mask_p[56] << 20) 871189747Ssam | (mask_p[55] << 18) | (mask_p[54] << 16) 872189747Ssam | (mask_p[53] << 14) | (mask_p[52] << 12) 873189747Ssam | (mask_p[51] << 10) | (mask_p[50] << 8) 874189747Ssam | (mask_p[49] << 6) | (mask_p[48] << 4) 875189747Ssam | (mask_p[47] << 2) | (mask_p[46] << 0); 876189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 877189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 878234664Sadrian 879234664Sadrian OS_REG_WRITE_BUFFER_FLUSH(ah); 880234664Sadrian OS_REG_WRITE_BUFFER_DISABLE(ah); 881189747Ssam} 882189747Ssam 883189747Ssam/* 884185377Ssam * Fill all software cached or static hardware state information. 885185377Ssam * Return failure if capabilities are to come from EEPROM and 886185377Ssam * cannot be read. 887185377Ssam */ 888185377SsamHAL_BOOL 889185377Ssamar5416FillCapabilityInfo(struct ath_hal *ah) 890185377Ssam{ 891185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 892185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 893185377Ssam uint16_t val; 894185377Ssam 895185377Ssam /* Construct wireless mode from EEPROM */ 896185377Ssam pCap->halWirelessModes = 0; 897185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 898185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 899185377Ssam | HAL_MODE_11NA_HT20 900185377Ssam | HAL_MODE_11NA_HT40PLUS 901185377Ssam | HAL_MODE_11NA_HT40MINUS 902185377Ssam ; 903185377Ssam } 904185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 905185377Ssam pCap->halWirelessModes |= HAL_MODE_11G 906185377Ssam | HAL_MODE_11NG_HT20 907185377Ssam | HAL_MODE_11NG_HT40PLUS 908185377Ssam | HAL_MODE_11NG_HT40MINUS 909185377Ssam ; 910185377Ssam pCap->halWirelessModes |= HAL_MODE_11A 911185377Ssam | HAL_MODE_11NA_HT20 912185377Ssam | HAL_MODE_11NA_HT40PLUS 913185377Ssam | HAL_MODE_11NA_HT40MINUS 914185377Ssam ; 915185377Ssam } 916185377Ssam 917185377Ssam pCap->halLow2GhzChan = 2312; 918185377Ssam pCap->halHigh2GhzChan = 2732; 919185377Ssam 920185377Ssam pCap->halLow5GhzChan = 4915; 921185377Ssam pCap->halHigh5GhzChan = 6100; 922185377Ssam 923185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 924185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 925185377Ssam pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 926185377Ssam 927185377Ssam pCap->halMicCkipSupport = AH_FALSE; 928185377Ssam pCap->halMicTkipSupport = AH_TRUE; 929185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 930185377Ssam /* 931185377Ssam * Starting with Griffin TX+RX mic keys can be combined 932185377Ssam * in one key cache slot. 933185377Ssam */ 934185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 935185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 936185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 937185377Ssam 938185377Ssam pCap->halCompressSupport = AH_FALSE; 939185377Ssam pCap->halBurstSupport = AH_TRUE; 940244529Sadrian /* 941244529Sadrian * This is disabled for now; the net80211 layer needs to be 942244529Sadrian * taught when it is and isn't appropriate to enable FF processing 943244529Sadrian * with 802.11n NICs (it tries to enable both A-MPDU and 944244529Sadrian * fast frames, with very tragic crash-y results.) 945244529Sadrian */ 946244529Sadrian pCap->halFastFramesSupport = AH_FALSE; 947185377Ssam pCap->halChapTuningSupport = AH_TRUE; 948185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 949185377Ssam 950185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 951185377Ssam 952185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 953238858Sadrian pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 954239643Sadrian pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 955185377Ssam pCap->halVEOLSupport = AH_TRUE; 956185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 957222020Sadrian pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 958185377Ssam pCap->halTsfAddSupport = AH_TRUE; 959221603Sadrian pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 960244943Sadrian pCap->halSpectralScanSupport = AH_FALSE; /* AR9280 and later */ 961185377Ssam 962185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 963185377Ssam pCap->halTotalQueues = val; 964185377Ssam else 965185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 966185377Ssam 967185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 968185377Ssam pCap->halKeyCacheSize = val; 969185377Ssam else 970185377Ssam pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 971185377Ssam 972240448Sadrian /* XXX Which chips? */ 973240448Sadrian pCap->halChanHalfRate = AH_TRUE; 974240448Sadrian pCap->halChanQuarterRate = AH_TRUE; 975185377Ssam 976185377Ssam pCap->halTstampPrecision = 32; 977185377Ssam pCap->halHwPhyCounterSupport = AH_TRUE; 978192396Ssam pCap->halIntrMask = HAL_INT_COMMON 979192396Ssam | HAL_INT_RX 980192396Ssam | HAL_INT_TX 981192396Ssam | HAL_INT_FATAL 982192396Ssam | HAL_INT_BNR 983192396Ssam | HAL_INT_BMISC 984192396Ssam | HAL_INT_DTIMSYNC 985192396Ssam | HAL_INT_TSFOOR 986192396Ssam | HAL_INT_CST 987192396Ssam | HAL_INT_GTT 988192396Ssam ; 989185377Ssam 990185377Ssam pCap->halFastCCSupport = AH_TRUE; 991228893Sadrian pCap->halNumGpioPins = 14; 992185377Ssam pCap->halWowSupport = AH_FALSE; 993185377Ssam pCap->halWowMatchPatternExact = AH_FALSE; 994185377Ssam pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 995185377Ssam pCap->halAutoSleepSupport = AH_FALSE; 996218441Sadrian pCap->hal4kbSplitTransSupport = AH_TRUE; 997220324Sadrian /* Disable this so Block-ACK works correctly */ 998220324Sadrian pCap->halHasRxSelfLinkedTail = AH_FALSE; 999185377Ssam#if 0 /* XXX not yet */ 1000185377Ssam pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 1001185377Ssam pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 1002185377Ssam#endif 1003185377Ssam pCap->halHTSupport = AH_TRUE; 1004185377Ssam pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 1005185377Ssam /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 1006185377Ssam pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 1007218150Sadrian /* AR5416 may have 3 antennas but is a 2x2 stream device */ 1008218150Sadrian pCap->halTxStreams = 2; 1009218150Sadrian pCap->halRxStreams = 2; 1010231368Sadrian 1011230847Sadrian /* 1012230847Sadrian * If the TX or RX chainmask has less than 2 chains active, 1013230847Sadrian * mark it as a 1-stream device for the relevant stream. 1014230847Sadrian */ 1015230847Sadrian if (owl_get_ntxchains(pCap->halTxChainMask) == 1) 1016230847Sadrian pCap->halTxStreams = 1; 1017230847Sadrian /* XXX Eww */ 1018230847Sadrian if (owl_get_ntxchains(pCap->halRxChainMask) == 1) 1019230847Sadrian pCap->halRxStreams = 1; 1020185377Ssam pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 1021221603Sadrian pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 1022185377Ssam pCap->halForcePpmSupport = AH_TRUE; 1023185377Ssam pCap->halEnhancedPmSupport = AH_TRUE; 1024195114Ssam pCap->halBssidMatchSupport = AH_TRUE; 1025221603Sadrian pCap->halGTTSupport = AH_TRUE; 1026221603Sadrian pCap->halCSTSupport = AH_TRUE; 1027222584Sadrian pCap->halEnhancedDfsSupport = AH_FALSE; 1028225444Sadrian /* Hardware supports 32 bit TSF values in the RX descriptor */ 1029225444Sadrian pCap->halHasLongRxDescTsf = AH_TRUE; 1030226488Sadrian /* 1031226488Sadrian * BB Read WAR: this is only for AR5008/AR9001 NICs 1032226488Sadrian * It is also set individually in the AR91xx attach functions. 1033226488Sadrian */ 1034226488Sadrian if (AR_SREV_OWL(ah)) 1035226488Sadrian pCap->halHasBBReadWar = AH_TRUE; 1036185377Ssam 1037185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 1038185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 1039185377Ssam /* NB: enabled by default */ 1040185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 1041185377Ssam pCap->halRfSilentSupport = AH_TRUE; 1042185377Ssam } 1043185377Ssam 1044227410Sadrian /* 1045227410Sadrian * The MAC will mark frames as RXed if there's a descriptor 1046227410Sadrian * to write them to. So if it hits a self-linked final descriptor, 1047227410Sadrian * it'll keep ACKing frames even though they're being silently 1048227410Sadrian * dropped. Thus, this particular feature of the driver can't 1049227410Sadrian * be used for 802.11n devices. 1050227410Sadrian */ 1051185377Ssam ahpriv->ah_rxornIsFatal = AH_FALSE; 1052185377Ssam 1053227410Sadrian /* 1054227410Sadrian * If it's a PCI NIC, ask the HAL OS layer to serialise 1055227410Sadrian * register access, or SMP machines may cause the hardware 1056227410Sadrian * to hang. This is applicable to AR5416 and AR9220; I'm not 1057227410Sadrian * sure about AR9160 or AR9227. 1058227410Sadrian */ 1059227410Sadrian if (! AH_PRIVATE(ah)->ah_ispcie) 1060227410Sadrian pCap->halSerialiseRegWar = 1; 1061227410Sadrian 1062185377Ssam return AH_TRUE; 1063185377Ssam} 1064185406Ssam 1065185406Ssamstatic const char* 1066185406Ssamar5416Probe(uint16_t vendorid, uint16_t devid) 1067185406Ssam{ 1068227372Sadrian if (vendorid == ATHEROS_VENDOR_ID) { 1069227372Sadrian if (devid == AR5416_DEVID_PCI) 1070227372Sadrian return "Atheros 5416"; 1071227372Sadrian if (devid == AR5416_DEVID_PCIE) 1072227372Sadrian return "Atheros 5418"; 1073227372Sadrian } 1074185406Ssam return AH_NULL; 1075185406Ssam} 1076185418SsamAH_CHIP(AR5416, ar5416Probe, ar5416Attach); 1077