ar5212_attach.c revision 239642
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 239642 2012-08-24 07:32:35Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ar5212/ar5212.h" 26#include "ar5212/ar5212reg.h" 27#include "ar5212/ar5212phy.h" 28 29#define AH_5212_COMMON 30#include "ar5212/ar5212.ini" 31 32static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 33 HAL_BOOL power_off); 34static void ar5212DisablePCIE(struct ath_hal *ah); 35 36static const struct ath_hal_private ar5212hal = {{ 37 .ah_magic = AR5212_MAGIC, 38 39 .ah_getRateTable = ar5212GetRateTable, 40 .ah_detach = ar5212Detach, 41 42 /* Reset Functions */ 43 .ah_reset = ar5212Reset, 44 .ah_phyDisable = ar5212PhyDisable, 45 .ah_disable = ar5212Disable, 46 .ah_configPCIE = ar5212ConfigPCIE, 47 .ah_disablePCIE = ar5212DisablePCIE, 48 .ah_setPCUConfig = ar5212SetPCUConfig, 49 .ah_perCalibration = ar5212PerCalibration, 50 .ah_perCalibrationN = ar5212PerCalibrationN, 51 .ah_resetCalValid = ar5212ResetCalValid, 52 .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 53 .ah_getChanNoise = ath_hal_getChanNoise, 54 55 /* Transmit functions */ 56 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 57 .ah_setupTxQueue = ar5212SetupTxQueue, 58 .ah_setTxQueueProps = ar5212SetTxQueueProps, 59 .ah_getTxQueueProps = ar5212GetTxQueueProps, 60 .ah_releaseTxQueue = ar5212ReleaseTxQueue, 61 .ah_resetTxQueue = ar5212ResetTxQueue, 62 .ah_getTxDP = ar5212GetTxDP, 63 .ah_setTxDP = ar5212SetTxDP, 64 .ah_numTxPending = ar5212NumTxPending, 65 .ah_startTxDma = ar5212StartTxDma, 66 .ah_stopTxDma = ar5212StopTxDma, 67 .ah_setupTxDesc = ar5212SetupTxDesc, 68 .ah_setupXTxDesc = ar5212SetupXTxDesc, 69 .ah_fillTxDesc = ar5212FillTxDesc, 70 .ah_procTxDesc = ar5212ProcTxDesc, 71 .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 72 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 73 .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 74 .ah_setTxDescLink = ar5212SetTxDescLink, 75 .ah_getTxDescLink = ar5212GetTxDescLink, 76 .ah_getTxDescLinkPtr = ar5212GetTxDescLinkPtr, 77 78 /* RX Functions */ 79 .ah_getRxDP = ar5212GetRxDP, 80 .ah_setRxDP = ar5212SetRxDP, 81 .ah_enableReceive = ar5212EnableReceive, 82 .ah_stopDmaReceive = ar5212StopDmaReceive, 83 .ah_startPcuReceive = ar5212StartPcuReceive, 84 .ah_stopPcuReceive = ar5212StopPcuReceive, 85 .ah_setMulticastFilter = ar5212SetMulticastFilter, 86 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 87 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 88 .ah_getRxFilter = ar5212GetRxFilter, 89 .ah_setRxFilter = ar5212SetRxFilter, 90 .ah_setupRxDesc = ar5212SetupRxDesc, 91 .ah_procRxDesc = ar5212ProcRxDesc, 92 .ah_rxMonitor = ar5212RxMonitor, 93 .ah_aniPoll = ar5212AniPoll, 94 .ah_procMibEvent = ar5212ProcessMibIntr, 95 96 /* Misc Functions */ 97 .ah_getCapability = ar5212GetCapability, 98 .ah_setCapability = ar5212SetCapability, 99 .ah_getDiagState = ar5212GetDiagState, 100 .ah_getMacAddress = ar5212GetMacAddress, 101 .ah_setMacAddress = ar5212SetMacAddress, 102 .ah_getBssIdMask = ar5212GetBssIdMask, 103 .ah_setBssIdMask = ar5212SetBssIdMask, 104 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 105 .ah_setLedState = ar5212SetLedState, 106 .ah_writeAssocid = ar5212WriteAssocid, 107 .ah_gpioCfgInput = ar5212GpioCfgInput, 108 .ah_gpioCfgOutput = ar5212GpioCfgOutput, 109 .ah_gpioGet = ar5212GpioGet, 110 .ah_gpioSet = ar5212GpioSet, 111 .ah_gpioSetIntr = ar5212GpioSetIntr, 112 .ah_getTsf32 = ar5212GetTsf32, 113 .ah_getTsf64 = ar5212GetTsf64, 114 .ah_resetTsf = ar5212ResetTsf, 115 .ah_detectCardPresent = ar5212DetectCardPresent, 116 .ah_updateMibCounters = ar5212UpdateMibCounters, 117 .ah_getRfGain = ar5212GetRfgain, 118 .ah_getDefAntenna = ar5212GetDefAntenna, 119 .ah_setDefAntenna = ar5212SetDefAntenna, 120 .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 121 .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 122 .ah_setSifsTime = ar5212SetSifsTime, 123 .ah_getSifsTime = ar5212GetSifsTime, 124 .ah_setSlotTime = ar5212SetSlotTime, 125 .ah_getSlotTime = ar5212GetSlotTime, 126 .ah_setAckTimeout = ar5212SetAckTimeout, 127 .ah_getAckTimeout = ar5212GetAckTimeout, 128 .ah_setAckCTSRate = ar5212SetAckCTSRate, 129 .ah_getAckCTSRate = ar5212GetAckCTSRate, 130 .ah_setCTSTimeout = ar5212SetCTSTimeout, 131 .ah_getCTSTimeout = ar5212GetCTSTimeout, 132 .ah_setDecompMask = ar5212SetDecompMask, 133 .ah_setCoverageClass = ar5212SetCoverageClass, 134 .ah_setQuiet = ar5212SetQuiet, 135 .ah_getMibCycleCounts = ar5212GetMibCycleCounts, 136 137 /* DFS Functions */ 138 .ah_enableDfs = ar5212EnableDfs, 139 .ah_getDfsThresh = ar5212GetDfsThresh, 140 .ah_getDfsDefaultThresh = ar5212GetDfsDefaultThresh, 141 .ah_procRadarEvent = ar5212ProcessRadarEvent, 142 .ah_isFastClockEnabled = ar5212IsFastClockEnabled, 143 .ah_get11nExtBusy = ar5212Get11nExtBusy, 144 145 /* Key Cache Functions */ 146 .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 147 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 148 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 149 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 150 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 151 152 /* Power Management Functions */ 153 .ah_setPowerMode = ar5212SetPowerMode, 154 .ah_getPowerMode = ar5212GetPowerMode, 155 156 /* Beacon Functions */ 157 .ah_setBeaconTimers = ar5212SetBeaconTimers, 158 .ah_beaconInit = ar5212BeaconInit, 159 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 160 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 161 .ah_getNextTBTT = ar5212GetNextTBTT, 162 163 /* Interrupt Functions */ 164 .ah_isInterruptPending = ar5212IsInterruptPending, 165 .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 166 .ah_getInterrupts = ar5212GetInterrupts, 167 .ah_setInterrupts = ar5212SetInterrupts }, 168 169 .ah_getChannelEdges = ar5212GetChannelEdges, 170 .ah_getWirelessModes = ar5212GetWirelessModes, 171 .ah_eepromRead = ar5212EepromRead, 172#ifdef AH_SUPPORT_WRITE_EEPROM 173 .ah_eepromWrite = ar5212EepromWrite, 174#endif 175 .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 176}; 177 178uint32_t 179ar5212GetRadioRev(struct ath_hal *ah) 180{ 181 uint32_t val; 182 int i; 183 184 /* Read Radio Chip Rev Extract */ 185 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 186 for (i = 0; i < 8; i++) 187 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 188 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 189 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 190 return ath_hal_reverseBits(val, 8); 191} 192 193static void 194ar5212AniSetup(struct ath_hal *ah) 195{ 196 static const struct ar5212AniParams aniparams = { 197 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 198 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 199 .coarseHigh = { -14, -14, -14, -14, -12 }, 200 .coarseLow = { -64, -64, -64, -64, -70 }, 201 .firpwr = { -78, -78, -78, -78, -80 }, 202 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 203 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 204 .maxFirstepLevel = 2, /* levels 0..2 */ 205 .firstep = { 0, 4, 8 }, 206 .ofdmTrigHigh = 500, 207 .ofdmTrigLow = 200, 208 .cckTrigHigh = 200, 209 .cckTrigLow = 100, 210 .rssiThrHigh = 40, 211 .rssiThrLow = 7, 212 .period = 100, 213 }; 214 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 215 struct ar5212AniParams tmp; 216 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 217 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 218 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 219 } else 220 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 221 222 /* Set overridable ANI methods */ 223 AH5212(ah)->ah_aniControl = ar5212AniControl; 224} 225 226/* 227 * Attach for an AR5212 part. 228 */ 229void 230ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 231 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 232{ 233#define N(a) (sizeof(a)/sizeof(a[0])) 234 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 235 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 236 struct ath_hal *ah; 237 238 ah = &ahp->ah_priv.h; 239 /* set initial values */ 240 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 241 ah->ah_sc = sc; 242 ah->ah_st = st; 243 ah->ah_sh = sh; 244 245 ah->ah_devid = devid; /* NB: for alq */ 246 AH_PRIVATE(ah)->ah_devid = devid; 247 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 248 249 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 250 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 251 252 ahp->ah_antControl = HAL_ANT_VARIABLE; 253 ahp->ah_diversity = AH_TRUE; 254 ahp->ah_bIQCalibration = AH_FALSE; 255 /* 256 * Enable MIC handling. 257 */ 258 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 259 ahp->ah_rssiThr = INIT_RSSI_THR; 260 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 261 ahp->ah_phyPowerOn = AH_FALSE; 262 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 263 | SM(MAX_RATE_POWER, AR_TPC_CTS) 264 | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 265 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 266 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 267 ahp->ah_slottime = (u_int) -1; 268 ahp->ah_acktimeout = (u_int) -1; 269 ahp->ah_ctstimeout = (u_int) -1; 270 ahp->ah_sifstime = (u_int) -1; 271 ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD, 272 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD, 273 274 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 275#undef N 276} 277 278/* 279 * Validate MAC version and revision. 280 */ 281static HAL_BOOL 282ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 283{ 284#define N(a) (sizeof(a)/sizeof(a[0])) 285 static const struct { 286 uint8_t version; 287 uint8_t revMin, revMax; 288 } macs[] = { 289 { AR_SREV_VERSION_VENICE, 290 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 291 { AR_SREV_VERSION_GRIFFIN, 292 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 293 { AR_SREV_5413, 294 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 295 { AR_SREV_5424, 296 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 297 { AR_SREV_2425, 298 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 299 { AR_SREV_2417, 300 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 301 }; 302 int i; 303 304 for (i = 0; i < N(macs); i++) 305 if (macs[i].version == macVersion && 306 macs[i].revMin <= macRev && macRev <= macs[i].revMax) 307 return AH_TRUE; 308 return AH_FALSE; 309#undef N 310} 311 312/* 313 * Attach for an AR5212 part. 314 */ 315static struct ath_hal * 316ar5212Attach(uint16_t devid, HAL_SOFTC sc, 317 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 318 HAL_STATUS *status) 319{ 320#define AH_EEPROM_PROTECT(ah) \ 321 (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 322 struct ath_hal_5212 *ahp; 323 struct ath_hal *ah; 324 struct ath_hal_rf *rf; 325 uint32_t val; 326 uint16_t eeval; 327 HAL_STATUS ecode; 328 329 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 330 __func__, sc, (void*) st, (void*) sh); 331 332 /* NB: memory is returned zero'd */ 333 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 334 if (ahp == AH_NULL) { 335 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 336 "%s: cannot allocate memory for state block\n", __func__); 337 *status = HAL_ENOMEM; 338 return AH_NULL; 339 } 340 ar5212InitState(ahp, devid, sc, st, sh, status); 341 ah = &ahp->ah_priv.h; 342 343 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 344 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 345 __func__); 346 ecode = HAL_EIO; 347 goto bad; 348 } 349 /* Read Revisions from Chips before taking out of reset */ 350 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 351 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 352 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 353 AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 354 355 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 356 HALDEBUG(ah, HAL_DEBUG_ANY, 357 "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 358 __func__, AH_PRIVATE(ah)->ah_macVersion, 359 AH_PRIVATE(ah)->ah_macRev); 360 ecode = HAL_ENOTSUPP; 361 goto bad; 362 } 363 364 /* setup common ini data; rf backends handle remainder */ 365 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 366 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 367 368 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 369 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 370 ecode = HAL_EIO; 371 goto bad; 372 } 373 374 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 375 376 if (AH_PRIVATE(ah)->ah_ispcie) { 377 /* XXX: build flag to disable this? */ 378 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 379 } 380 381 if (!ar5212ChipTest(ah)) { 382 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 383 __func__); 384 ecode = HAL_ESELFTEST; 385 goto bad; 386 } 387 388 /* Enable PCI core retry fix in software for Hainan and up */ 389 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 390 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 391 392 /* 393 * Set correct Baseband to analog shift 394 * setting to access analog chips. 395 */ 396 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 397 398 /* Read Radio Chip Rev Extract */ 399 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 400 401 rf = ath_hal_rfprobe(ah, &ecode); 402 if (rf == AH_NULL) 403 goto bad; 404 405 /* NB: silently accept anything in release code per Atheros */ 406 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 407 case AR_RAD5111_SREV_MAJOR: 408 case AR_RAD5112_SREV_MAJOR: 409 case AR_RAD2112_SREV_MAJOR: 410 case AR_RAD2111_SREV_MAJOR: 411 case AR_RAD2413_SREV_MAJOR: 412 case AR_RAD5413_SREV_MAJOR: 413 case AR_RAD5424_SREV_MAJOR: 414 break; 415 default: 416 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 417 /* 418 * When RF_Silent is used, the 419 * analog chip is reset. So when the system boots 420 * up with the radio switch off we cannot determine 421 * the RF chip rev. To workaround this check the 422 * mac+phy revs and if Hainan, set the radio rev 423 * to Derby. 424 */ 425 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 426 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 427 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 428 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 429 break; 430 } 431 if (IS_2413(ah)) { /* Griffin */ 432 AH_PRIVATE(ah)->ah_analog5GhzRev = 433 AR_RAD2413_SREV_MAJOR | 0x1; 434 break; 435 } 436 if (IS_5413(ah)) { /* Eagle */ 437 AH_PRIVATE(ah)->ah_analog5GhzRev = 438 AR_RAD5413_SREV_MAJOR | 0x2; 439 break; 440 } 441 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 442 AH_PRIVATE(ah)->ah_analog5GhzRev = 443 AR_RAD5424_SREV_MAJOR | 0x2; 444 break; 445 } 446 } 447#ifdef AH_DEBUG 448 HALDEBUG(ah, HAL_DEBUG_ANY, 449 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 450 "this driver\n", 451 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 452 ecode = HAL_ENOTSUPP; 453 goto bad; 454#endif 455 } 456 if (IS_RAD5112_REV1(ah)) { 457 HALDEBUG(ah, HAL_DEBUG_ANY, 458 "%s: 5112 Rev 1 is not supported by this " 459 "driver (analog5GhzRev 0x%x)\n", __func__, 460 AH_PRIVATE(ah)->ah_analog5GhzRev); 461 ecode = HAL_ENOTSUPP; 462 goto bad; 463 } 464 465 val = OS_REG_READ(ah, AR_PCICFG); 466 val = MS(val, AR_PCICFG_EEPROM_SIZE); 467 if (val == 0) { 468 if (!AH_PRIVATE(ah)->ah_ispcie) { 469 HALDEBUG(ah, HAL_DEBUG_ANY, 470 "%s: unsupported EEPROM size %u (0x%x) found\n", 471 __func__, val, val); 472 ecode = HAL_EESIZE; 473 goto bad; 474 } 475 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 476 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 477 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 478 HALDEBUG(ah, HAL_DEBUG_ANY, 479 "%s: unsupported EEPROM size %u (0x%x) found\n", 480 __func__, val, val); 481 ecode = HAL_EESIZE; 482 goto bad; 483 } 484 HALDEBUG(ah, HAL_DEBUG_ANY, 485 "%s: EEPROM size = %d. Must be %d (16k).\n", 486 __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 487 ecode = HAL_EESIZE; 488 goto bad; 489 } 490 ecode = ath_hal_legacyEepromAttach(ah); 491 if (ecode != HAL_OK) { 492 goto bad; 493 } 494 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 495 496 /* 497 * If Bmode and AR5212, verify 2.4 analog exists 498 */ 499 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 500 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 501 /* 502 * Set correct Baseband to analog shift 503 * setting to access analog chips. 504 */ 505 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 506 OS_DELAY(2000); 507 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 508 509 /* Set baseband for 5GHz chip */ 510 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 511 OS_DELAY(2000); 512 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 513 HALDEBUG(ah, HAL_DEBUG_ANY, 514 "%s: 2G Radio Chip Rev 0x%02X is not " 515 "supported by this driver\n", __func__, 516 AH_PRIVATE(ah)->ah_analog2GhzRev); 517 ecode = HAL_ENOTSUPP; 518 goto bad; 519 } 520 } 521 522 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 523 if (ecode != HAL_OK) { 524 HALDEBUG(ah, HAL_DEBUG_ANY, 525 "%s: cannot read regulatory domain from EEPROM\n", 526 __func__); 527 goto bad; 528 } 529 AH_PRIVATE(ah)->ah_currentRD = eeval; 530 /* XXX record serial number */ 531 532 /* 533 * Got everything we need now to setup the capabilities. 534 */ 535 if (!ar5212FillCapabilityInfo(ah)) { 536 HALDEBUG(ah, HAL_DEBUG_ANY, 537 "%s: failed ar5212FillCapabilityInfo\n", __func__); 538 ecode = HAL_EEREAD; 539 goto bad; 540 } 541 542 if (!rf->attach(ah, &ecode)) { 543 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 544 __func__, ecode); 545 goto bad; 546 } 547 /* 548 * Set noise floor adjust method; we arrange a 549 * direct call instead of thunking. 550 */ 551 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 552 553 /* Initialize gain ladder thermal calibration structure */ 554 ar5212InitializeGainValues(ah); 555 556 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 557 if (ecode != HAL_OK) { 558 HALDEBUG(ah, HAL_DEBUG_ANY, 559 "%s: error getting mac address from EEPROM\n", __func__); 560 goto bad; 561 } 562 563 ar5212AniSetup(ah); 564 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 565 ar5212InitNfCalHistBuffer(ah); 566 567 /* XXX EAR stuff goes here */ 568 569 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 570 571 return ah; 572 573bad: 574 if (ahp) 575 ar5212Detach((struct ath_hal *) ahp); 576 if (status) 577 *status = ecode; 578 return AH_NULL; 579#undef AH_EEPROM_PROTECT 580} 581 582void 583ar5212Detach(struct ath_hal *ah) 584{ 585 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 586 587 HALASSERT(ah != AH_NULL); 588 HALASSERT(ah->ah_magic == AR5212_MAGIC); 589 590 ar5212AniDetach(ah); 591 ar5212RfDetach(ah); 592 ar5212Disable(ah); 593 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 594 595 ath_hal_eepromDetach(ah); 596 ath_hal_free(ah); 597} 598 599HAL_BOOL 600ar5212ChipTest(struct ath_hal *ah) 601{ 602 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 603 uint32_t regHold[2]; 604 uint32_t patternData[4] = 605 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 606 int i, j; 607 608 /* Test PHY & MAC registers */ 609 for (i = 0; i < 2; i++) { 610 uint32_t addr = regAddr[i]; 611 uint32_t wrData, rdData; 612 613 regHold[i] = OS_REG_READ(ah, addr); 614 for (j = 0; j < 0x100; j++) { 615 wrData = (j << 16) | j; 616 OS_REG_WRITE(ah, addr, wrData); 617 rdData = OS_REG_READ(ah, addr); 618 if (rdData != wrData) { 619 HALDEBUG(ah, HAL_DEBUG_ANY, 620"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 621 __func__, addr, wrData, rdData); 622 return AH_FALSE; 623 } 624 } 625 for (j = 0; j < 4; j++) { 626 wrData = patternData[j]; 627 OS_REG_WRITE(ah, addr, wrData); 628 rdData = OS_REG_READ(ah, addr); 629 if (wrData != rdData) { 630 HALDEBUG(ah, HAL_DEBUG_ANY, 631"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 632 __func__, addr, wrData, rdData); 633 return AH_FALSE; 634 } 635 } 636 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 637 } 638 OS_DELAY(100); 639 return AH_TRUE; 640} 641 642/* 643 * Store the channel edges for the requested operational mode 644 */ 645HAL_BOOL 646ar5212GetChannelEdges(struct ath_hal *ah, 647 uint16_t flags, uint16_t *low, uint16_t *high) 648{ 649 if (flags & IEEE80211_CHAN_5GHZ) { 650 *low = 4915; 651 *high = 6100; 652 return AH_TRUE; 653 } 654 if ((flags & IEEE80211_CHAN_2GHZ) && 655 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 656 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 657 *low = 2312; 658 *high = 2732; 659 return AH_TRUE; 660 } 661 return AH_FALSE; 662} 663 664/* 665 * Disable PLL when in L0s as well as receiver clock when in L1. 666 * This power saving option must be enabled through the Serdes. 667 * 668 * Programming the Serdes must go through the same 288 bit serial shift 669 * register as the other analog registers. Hence the 9 writes. 670 * 671 * XXX Clean up the magic numbers. 672 */ 673static void 674ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 675{ 676 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 677 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 678 679 /* RX shut off when elecidle is asserted */ 680 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 681 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 682 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 683 684 /* Shut off PLL and CLKREQ active in L1 */ 685 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 686 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 687 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 688 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 689 690 /* Load the new settings */ 691 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 692} 693 694static void 695ar5212DisablePCIE(struct ath_hal *ah) 696{ 697 /* NB: fill in for 9100 */ 698} 699 700/* 701 * Fill all software cached or static hardware state information. 702 * Return failure if capabilities are to come from EEPROM and 703 * cannot be read. 704 */ 705HAL_BOOL 706ar5212FillCapabilityInfo(struct ath_hal *ah) 707{ 708#define AR_KEYTABLE_SIZE 128 709#define IS_GRIFFIN_LITE(ah) \ 710 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 711 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 712#define IS_COBRA(ah) \ 713 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 714#define IS_2112(ah) \ 715 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 716 717 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 718 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 719 uint16_t capField, val; 720 721 /* Read the capability EEPROM location */ 722 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 723 HALDEBUG(ah, HAL_DEBUG_ANY, 724 "%s: unable to read caps from eeprom\n", __func__); 725 return AH_FALSE; 726 } 727 if (IS_2112(ah)) 728 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 729 if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 730 /* 731 * For griffin-lite cards with unprogrammed capabilities. 732 */ 733 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 734 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 735 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 736 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 737 HALDEBUG(ah, HAL_DEBUG_ATTACH, 738 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 739 __func__, capField); 740 } 741 742 /* Modify reg domain on newer cards that need to work with older sw */ 743 if (ahpriv->ah_opmode != HAL_M_HOSTAP && 744 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 745 if (ahpriv->ah_currentRD == 0x64 || 746 ahpriv->ah_currentRD == 0x65) 747 ahpriv->ah_currentRD += 5; 748 else if (ahpriv->ah_currentRD == 0x41) 749 ahpriv->ah_currentRD = 0x43; 750 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 751 __func__, ahpriv->ah_currentRD); 752 } 753 754 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 755 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 756 HALDEBUG(ah, HAL_DEBUG_ATTACH, 757 "%s: enable Bmode and disable turbo for Swan/Nala\n", 758 __func__); 759 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 760 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 761 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 762 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 763 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 764 } 765 766 /* Construct wireless mode from EEPROM */ 767 pCap->halWirelessModes = 0; 768 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 769 pCap->halWirelessModes |= HAL_MODE_11A; 770 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 771 pCap->halWirelessModes |= HAL_MODE_TURBO; 772 } 773 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 774 pCap->halWirelessModes |= HAL_MODE_11B; 775 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 776 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 777 pCap->halWirelessModes |= HAL_MODE_11G; 778 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 779 pCap->halWirelessModes |= HAL_MODE_108G; 780 } 781 782 pCap->halLow2GhzChan = 2312; 783 /* XXX 2417 too? */ 784 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 785 pCap->halHigh2GhzChan = 2500; 786 else 787 pCap->halHigh2GhzChan = 2732; 788 789 pCap->halLow5GhzChan = 4915; 790 pCap->halHigh5GhzChan = 6100; 791 792 pCap->halCipherCkipSupport = AH_FALSE; 793 pCap->halCipherTkipSupport = AH_TRUE; 794 pCap->halCipherAesCcmSupport = 795 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 796 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 797 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 798 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 799 800 pCap->halMicCkipSupport = AH_FALSE; 801 pCap->halMicTkipSupport = AH_TRUE; 802 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 803 /* 804 * Starting with Griffin TX+RX mic keys can be combined 805 * in one key cache slot. 806 */ 807 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 808 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 809 else 810 pCap->halTkipMicTxRxKeySupport = AH_FALSE; 811 pCap->halChanSpreadSupport = AH_TRUE; 812 pCap->halSleepAfterBeaconBroken = AH_TRUE; 813 814 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 815 pCap->halCompressSupport = 816 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 817 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 818 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 819 pCap->halFastFramesSupport = 820 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 821 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 822 pCap->halChapTuningSupport = AH_TRUE; 823 pCap->halTurboPrimeSupport = AH_TRUE; 824 } 825 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 826 827 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 828 pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 829 pCap->halVEOLSupport = AH_TRUE; 830 pCap->halBssIdMaskSupport = AH_TRUE; 831 pCap->halMcastKeySrchSupport = AH_TRUE; 832 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 833 ahpriv->ah_macRev == 8) || 834 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 835 pCap->halTsfAddSupport = AH_TRUE; 836 837 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 838 pCap->halTotalQueues = val; 839 else 840 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 841 842 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 843 pCap->halKeyCacheSize = val; 844 else 845 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 846 847 pCap->halChanHalfRate = AH_TRUE; 848 pCap->halChanQuarterRate = AH_TRUE; 849 850 /* 851 * RSSI uses the combined field; some 11n NICs may use 852 * the control chain RSSI. 853 */ 854 pCap->halUseCombinedRadarRssi = AH_TRUE; 855 856 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 857 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 858 /* NB: enabled by default */ 859 ahpriv->ah_rfkillEnabled = AH_TRUE; 860 pCap->halRfSilentSupport = AH_TRUE; 861 } 862 863 /* NB: this is a guess, noone seems to know the answer */ 864 ahpriv->ah_rxornIsFatal = 865 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 866 867 /* enable features that first appeared in Hainan */ 868 if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 869 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 870 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 871 /* h/w phy counters */ 872 pCap->halHwPhyCounterSupport = AH_TRUE; 873 /* bssid match disable */ 874 pCap->halBssidMatchSupport = AH_TRUE; 875 } 876 877 pCap->halTstampPrecision = 15; 878 pCap->halIntrMask = HAL_INT_COMMON 879 | HAL_INT_RX 880 | HAL_INT_TX 881 | HAL_INT_FATAL 882 | HAL_INT_BNR 883 | HAL_INT_BMISC 884 ; 885 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 886 pCap->halIntrMask &= ~HAL_INT_TBTT; 887 888 pCap->hal4kbSplitTransSupport = AH_TRUE; 889 pCap->halHasRxSelfLinkedTail = AH_TRUE; 890 891 return AH_TRUE; 892#undef IS_COBRA 893#undef IS_GRIFFIN_LITE 894#undef AR_KEYTABLE_SIZE 895} 896 897static const char* 898ar5212Probe(uint16_t vendorid, uint16_t devid) 899{ 900 if (vendorid == ATHEROS_VENDOR_ID || 901 vendorid == ATHEROS_3COM_VENDOR_ID || 902 vendorid == ATHEROS_3COM2_VENDOR_ID) { 903 switch (devid) { 904 case AR5212_FPGA: 905 return "Atheros 5212 (FPGA)"; 906 case AR5212_DEVID: 907 case AR5212_DEVID_IBM: 908 case AR5212_DEFAULT: 909 return "Atheros 5212"; 910 case AR5212_AR2413: 911 return "Atheros 2413"; 912 case AR5212_AR2417: 913 return "Atheros 2417"; 914 case AR5212_AR5413: 915 return "Atheros 5413"; 916 case AR5212_AR5424: 917 return "Atheros 5424/2424"; 918 } 919 } 920 return AH_NULL; 921} 922AH_CHIP(AR5212, ar5212Probe, ar5212Attach); 923