ar5212_attach.c revision 238858 
1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 238858 2012-07-28 07:28:08Z adrian $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ar5212/ar5212.h"
26#include "ar5212/ar5212reg.h"
27#include "ar5212/ar5212phy.h"
28
29#define AH_5212_COMMON
30#include "ar5212/ar5212.ini"
31
32static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
33		HAL_BOOL power_off);
34static void ar5212DisablePCIE(struct ath_hal *ah);
35
36static const struct ath_hal_private ar5212hal = {{
37	.ah_magic			= AR5212_MAGIC,
38
39	.ah_getRateTable		= ar5212GetRateTable,
40	.ah_detach			= ar5212Detach,
41
42	/* Reset Functions */
43	.ah_reset			= ar5212Reset,
44	.ah_phyDisable			= ar5212PhyDisable,
45	.ah_disable			= ar5212Disable,
46	.ah_configPCIE			= ar5212ConfigPCIE,
47	.ah_disablePCIE			= ar5212DisablePCIE,
48	.ah_setPCUConfig		= ar5212SetPCUConfig,
49	.ah_perCalibration		= ar5212PerCalibration,
50	.ah_perCalibrationN		= ar5212PerCalibrationN,
51	.ah_resetCalValid		= ar5212ResetCalValid,
52	.ah_setTxPowerLimit		= ar5212SetTxPowerLimit,
53	.ah_getChanNoise		= ath_hal_getChanNoise,
54
55	/* Transmit functions */
56	.ah_updateTxTrigLevel		= ar5212UpdateTxTrigLevel,
57	.ah_setupTxQueue		= ar5212SetupTxQueue,
58	.ah_setTxQueueProps             = ar5212SetTxQueueProps,
59	.ah_getTxQueueProps             = ar5212GetTxQueueProps,
60	.ah_releaseTxQueue		= ar5212ReleaseTxQueue,
61	.ah_resetTxQueue		= ar5212ResetTxQueue,
62	.ah_getTxDP			= ar5212GetTxDP,
63	.ah_setTxDP			= ar5212SetTxDP,
64	.ah_numTxPending		= ar5212NumTxPending,
65	.ah_startTxDma			= ar5212StartTxDma,
66	.ah_stopTxDma			= ar5212StopTxDma,
67	.ah_setupTxDesc			= ar5212SetupTxDesc,
68	.ah_setupXTxDesc		= ar5212SetupXTxDesc,
69	.ah_fillTxDesc			= ar5212FillTxDesc,
70	.ah_procTxDesc			= ar5212ProcTxDesc,
71	.ah_getTxIntrQueue		= ar5212GetTxIntrQueue,
72	.ah_reqTxIntrDesc 		= ar5212IntrReqTxDesc,
73	.ah_getTxCompletionRates	= ar5212GetTxCompletionRates,
74	.ah_setTxDescLink		= ar5212SetTxDescLink,
75	.ah_getTxDescLink		= ar5212GetTxDescLink,
76	.ah_getTxDescLinkPtr		= ar5212GetTxDescLinkPtr,
77
78	/* RX Functions */
79	.ah_getRxDP			= ar5212GetRxDP,
80	.ah_setRxDP			= ar5212SetRxDP,
81	.ah_enableReceive		= ar5212EnableReceive,
82	.ah_stopDmaReceive		= ar5212StopDmaReceive,
83	.ah_startPcuReceive		= ar5212StartPcuReceive,
84	.ah_stopPcuReceive		= ar5212StopPcuReceive,
85	.ah_setMulticastFilter		= ar5212SetMulticastFilter,
86	.ah_setMulticastFilterIndex	= ar5212SetMulticastFilterIndex,
87	.ah_clrMulticastFilterIndex	= ar5212ClrMulticastFilterIndex,
88	.ah_getRxFilter			= ar5212GetRxFilter,
89	.ah_setRxFilter			= ar5212SetRxFilter,
90	.ah_setupRxDesc			= ar5212SetupRxDesc,
91	.ah_procRxDesc			= ar5212ProcRxDesc,
92	.ah_rxMonitor			= ar5212RxMonitor,
93	.ah_aniPoll			= ar5212AniPoll,
94	.ah_procMibEvent		= ar5212ProcessMibIntr,
95
96	/* Misc Functions */
97	.ah_getCapability		= ar5212GetCapability,
98	.ah_setCapability		= ar5212SetCapability,
99	.ah_getDiagState		= ar5212GetDiagState,
100	.ah_getMacAddress		= ar5212GetMacAddress,
101	.ah_setMacAddress		= ar5212SetMacAddress,
102	.ah_getBssIdMask		= ar5212GetBssIdMask,
103	.ah_setBssIdMask		= ar5212SetBssIdMask,
104	.ah_setRegulatoryDomain		= ar5212SetRegulatoryDomain,
105	.ah_setLedState			= ar5212SetLedState,
106	.ah_writeAssocid		= ar5212WriteAssocid,
107	.ah_gpioCfgInput		= ar5212GpioCfgInput,
108	.ah_gpioCfgOutput		= ar5212GpioCfgOutput,
109	.ah_gpioGet			= ar5212GpioGet,
110	.ah_gpioSet			= ar5212GpioSet,
111	.ah_gpioSetIntr			= ar5212GpioSetIntr,
112	.ah_getTsf32			= ar5212GetTsf32,
113	.ah_getTsf64			= ar5212GetTsf64,
114	.ah_resetTsf			= ar5212ResetTsf,
115	.ah_detectCardPresent		= ar5212DetectCardPresent,
116	.ah_updateMibCounters		= ar5212UpdateMibCounters,
117	.ah_getRfGain			= ar5212GetRfgain,
118	.ah_getDefAntenna		= ar5212GetDefAntenna,
119	.ah_setDefAntenna		= ar5212SetDefAntenna,
120	.ah_getAntennaSwitch		= ar5212GetAntennaSwitch,
121	.ah_setAntennaSwitch		= ar5212SetAntennaSwitch,
122	.ah_setSifsTime			= ar5212SetSifsTime,
123	.ah_getSifsTime			= ar5212GetSifsTime,
124	.ah_setSlotTime			= ar5212SetSlotTime,
125	.ah_getSlotTime			= ar5212GetSlotTime,
126	.ah_setAckTimeout		= ar5212SetAckTimeout,
127	.ah_getAckTimeout		= ar5212GetAckTimeout,
128	.ah_setAckCTSRate		= ar5212SetAckCTSRate,
129	.ah_getAckCTSRate		= ar5212GetAckCTSRate,
130	.ah_setCTSTimeout		= ar5212SetCTSTimeout,
131	.ah_getCTSTimeout		= ar5212GetCTSTimeout,
132	.ah_setDecompMask		= ar5212SetDecompMask,
133	.ah_setCoverageClass		= ar5212SetCoverageClass,
134	.ah_setQuiet			= ar5212SetQuiet,
135	.ah_getMibCycleCounts		= ar5212GetMibCycleCounts,
136
137	/* DFS Functions */
138	.ah_enableDfs			= ar5212EnableDfs,
139	.ah_getDfsThresh		= ar5212GetDfsThresh,
140	.ah_procRadarEvent		= ar5212ProcessRadarEvent,
141	.ah_isFastClockEnabled		= ar5212IsFastClockEnabled,
142	.ah_get11nExtBusy		= ar5212Get11nExtBusy,
143
144	/* Key Cache Functions */
145	.ah_getKeyCacheSize		= ar5212GetKeyCacheSize,
146	.ah_resetKeyCacheEntry		= ar5212ResetKeyCacheEntry,
147	.ah_isKeyCacheEntryValid	= ar5212IsKeyCacheEntryValid,
148	.ah_setKeyCacheEntry		= ar5212SetKeyCacheEntry,
149	.ah_setKeyCacheEntryMac		= ar5212SetKeyCacheEntryMac,
150
151	/* Power Management Functions */
152	.ah_setPowerMode		= ar5212SetPowerMode,
153	.ah_getPowerMode		= ar5212GetPowerMode,
154
155	/* Beacon Functions */
156	.ah_setBeaconTimers		= ar5212SetBeaconTimers,
157	.ah_beaconInit			= ar5212BeaconInit,
158	.ah_setStationBeaconTimers	= ar5212SetStaBeaconTimers,
159	.ah_resetStationBeaconTimers	= ar5212ResetStaBeaconTimers,
160	.ah_getNextTBTT			= ar5212GetNextTBTT,
161
162	/* Interrupt Functions */
163	.ah_isInterruptPending		= ar5212IsInterruptPending,
164	.ah_getPendingInterrupts	= ar5212GetPendingInterrupts,
165	.ah_getInterrupts		= ar5212GetInterrupts,
166	.ah_setInterrupts		= ar5212SetInterrupts },
167
168	.ah_getChannelEdges		= ar5212GetChannelEdges,
169	.ah_getWirelessModes		= ar5212GetWirelessModes,
170	.ah_eepromRead			= ar5212EepromRead,
171#ifdef AH_SUPPORT_WRITE_EEPROM
172	.ah_eepromWrite			= ar5212EepromWrite,
173#endif
174	.ah_getChipPowerLimits		= ar5212GetChipPowerLimits,
175};
176
177uint32_t
178ar5212GetRadioRev(struct ath_hal *ah)
179{
180	uint32_t val;
181	int i;
182
183	/* Read Radio Chip Rev Extract */
184	OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16);
185	for (i = 0; i < 8; i++)
186		OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
187	val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
188	val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
189	return ath_hal_reverseBits(val, 8);
190}
191
192static void
193ar5212AniSetup(struct ath_hal *ah)
194{
195	static const struct ar5212AniParams aniparams = {
196		.maxNoiseImmunityLevel	= 4,	/* levels 0..4 */
197		.totalSizeDesired	= { -55, -55, -55, -55, -62 },
198		.coarseHigh		= { -14, -14, -14, -14, -12 },
199		.coarseLow		= { -64, -64, -64, -64, -70 },
200		.firpwr			= { -78, -78, -78, -78, -80 },
201		.maxSpurImmunityLevel	= 2,	/* NB: depends on chip rev */
202		.cycPwrThr1		= { 2, 4, 6, 8, 10, 12, 14, 16 },
203		.maxFirstepLevel	= 2,	/* levels 0..2 */
204		.firstep		= { 0, 4, 8 },
205		.ofdmTrigHigh		= 500,
206		.ofdmTrigLow		= 200,
207		.cckTrigHigh		= 200,
208		.cckTrigLow		= 100,
209		.rssiThrHigh		= 40,
210		.rssiThrLow		= 7,
211		.period			= 100,
212	};
213	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) {
214		struct ar5212AniParams tmp;
215		OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams));
216		tmp.maxSpurImmunityLevel = 7;	/* Venice and earlier */
217		ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE);
218	} else
219		ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
220
221	/* Set overridable ANI methods */
222	AH5212(ah)->ah_aniControl = ar5212AniControl;
223}
224
225/*
226 * Attach for an AR5212 part.
227 */
228void
229ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc,
230	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
231{
232#define	N(a)	(sizeof(a)/sizeof(a[0]))
233	static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] =
234		{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
235	struct ath_hal *ah;
236
237	ah = &ahp->ah_priv.h;
238	/* set initial values */
239	OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private));
240	ah->ah_sc = sc;
241	ah->ah_st = st;
242	ah->ah_sh = sh;
243
244	ah->ah_devid = devid;			/* NB: for alq */
245	AH_PRIVATE(ah)->ah_devid = devid;
246	AH_PRIVATE(ah)->ah_subvendorid = 0;	/* XXX */
247
248	AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
249	AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX;	/* no scaling */
250
251	ahp->ah_antControl = HAL_ANT_VARIABLE;
252	ahp->ah_diversity = AH_TRUE;
253	ahp->ah_bIQCalibration = AH_FALSE;
254	/*
255	 * Enable MIC handling.
256	 */
257	ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
258	ahp->ah_rssiThr = INIT_RSSI_THR;
259	ahp->ah_tpcEnabled = AH_FALSE;		/* disabled by default */
260	ahp->ah_phyPowerOn = AH_FALSE;
261	ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK)
262		       | SM(MAX_RATE_POWER, AR_TPC_CTS)
263		       | SM(MAX_RATE_POWER, AR_TPC_CHIRP);
264	ahp->ah_beaconInterval = 100;		/* XXX [20..1000] */
265	ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */
266	ahp->ah_slottime = (u_int) -1;
267	ahp->ah_acktimeout = (u_int) -1;
268	ahp->ah_ctstimeout = (u_int) -1;
269	ahp->ah_sifstime = (u_int) -1;
270	ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD,
271	ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD,
272
273	OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
274#undef N
275}
276
277/*
278 * Validate MAC version and revision.
279 */
280static HAL_BOOL
281ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev)
282{
283#define	N(a)	(sizeof(a)/sizeof(a[0]))
284	static const struct {
285		uint8_t	version;
286		uint8_t	revMin, revMax;
287	} macs[] = {
288	    { AR_SREV_VERSION_VENICE,
289	      AR_SREV_D2PLUS,		AR_SREV_REVISION_MAX },
290	    { AR_SREV_VERSION_GRIFFIN,
291	      AR_SREV_D2PLUS,		AR_SREV_REVISION_MAX },
292	    { AR_SREV_5413,
293	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
294	    { AR_SREV_5424,
295	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
296	    { AR_SREV_2425,
297	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
298	    { AR_SREV_2417,
299	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
300	};
301	int i;
302
303	for (i = 0; i < N(macs); i++)
304		if (macs[i].version == macVersion &&
305		    macs[i].revMin <= macRev && macRev <= macs[i].revMax)
306			return AH_TRUE;
307	return AH_FALSE;
308#undef N
309}
310
311/*
312 * Attach for an AR5212 part.
313 */
314static struct ath_hal *
315ar5212Attach(uint16_t devid, HAL_SOFTC sc,
316	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
317	HAL_STATUS *status)
318{
319#define	AH_EEPROM_PROTECT(ah) \
320	(AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
321	struct ath_hal_5212 *ahp;
322	struct ath_hal *ah;
323	struct ath_hal_rf *rf;
324	uint32_t val;
325	uint16_t eeval;
326	HAL_STATUS ecode;
327
328	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
329	    __func__, sc, (void*) st, (void*) sh);
330
331	/* NB: memory is returned zero'd */
332	ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
333	if (ahp == AH_NULL) {
334		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
335		    "%s: cannot allocate memory for state block\n", __func__);
336		*status = HAL_ENOMEM;
337		return AH_NULL;
338	}
339	ar5212InitState(ahp, devid, sc, st, sh, status);
340	ah = &ahp->ah_priv.h;
341
342	if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
343		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
344		    __func__);
345		ecode = HAL_EIO;
346		goto bad;
347	}
348	/* Read Revisions from Chips before taking out of reset */
349	val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
350	AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
351	AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
352	AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah);
353
354	if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) {
355		HALDEBUG(ah, HAL_DEBUG_ANY,
356		    "%s: Mac Chip Rev 0x%02x.%x not supported\n" ,
357		    __func__, AH_PRIVATE(ah)->ah_macVersion,
358		    AH_PRIVATE(ah)->ah_macRev);
359		ecode = HAL_ENOTSUPP;
360		goto bad;
361	}
362
363	/* setup common ini data; rf backends handle remainder */
364	HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
365	HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);
366
367	if (!ar5212ChipReset(ah, AH_NULL)) {	/* reset chip */
368		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
369		ecode = HAL_EIO;
370		goto bad;
371	}
372
373	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
374
375	if (AH_PRIVATE(ah)->ah_ispcie) {
376		/* XXX: build flag to disable this? */
377		ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE);
378	}
379
380	if (!ar5212ChipTest(ah)) {
381		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
382		    __func__);
383		ecode = HAL_ESELFTEST;
384		goto bad;
385	}
386
387	/* Enable PCI core retry fix in software for Hainan and up */
388	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE)
389		OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN);
390
391	/*
392	 * Set correct Baseband to analog shift
393	 * setting to access analog chips.
394	 */
395	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
396
397	/* Read Radio Chip Rev Extract */
398	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
399
400	rf = ath_hal_rfprobe(ah, &ecode);
401	if (rf == AH_NULL)
402		goto bad;
403
404	/* NB: silently accept anything in release code per Atheros */
405	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
406	case AR_RAD5111_SREV_MAJOR:
407	case AR_RAD5112_SREV_MAJOR:
408	case AR_RAD2112_SREV_MAJOR:
409	case AR_RAD2111_SREV_MAJOR:
410	case AR_RAD2413_SREV_MAJOR:
411	case AR_RAD5413_SREV_MAJOR:
412	case AR_RAD5424_SREV_MAJOR:
413		break;
414	default:
415		if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
416			/*
417			 * When RF_Silent is used, the
418			 * analog chip is reset.  So when the system boots
419			 * up with the radio switch off we cannot determine
420			 * the RF chip rev.  To workaround this check the
421			 * mac+phy revs and if Hainan, set the radio rev
422			 * to Derby.
423			 */
424			if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
425			    AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN &&
426			    AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) {
427				AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN;
428				break;
429			}
430			if (IS_2413(ah)) {		/* Griffin */
431				AH_PRIVATE(ah)->ah_analog5GhzRev =
432				    AR_RAD2413_SREV_MAJOR | 0x1;
433				break;
434			}
435			if (IS_5413(ah)) {		/* Eagle */
436				AH_PRIVATE(ah)->ah_analog5GhzRev =
437				    AR_RAD5413_SREV_MAJOR | 0x2;
438				break;
439			}
440			if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */
441				AH_PRIVATE(ah)->ah_analog5GhzRev =
442				    AR_RAD5424_SREV_MAJOR | 0x2;
443				break;
444			}
445		}
446#ifdef AH_DEBUG
447		HALDEBUG(ah, HAL_DEBUG_ANY,
448		    "%s: 5G Radio Chip Rev 0x%02X is not supported by "
449		    "this driver\n",
450		    __func__, AH_PRIVATE(ah)->ah_analog5GhzRev);
451		ecode = HAL_ENOTSUPP;
452		goto bad;
453#endif
454	}
455	if (IS_RAD5112_REV1(ah)) {
456		HALDEBUG(ah, HAL_DEBUG_ANY,
457		    "%s: 5112 Rev 1 is not supported by this "
458		    "driver (analog5GhzRev 0x%x)\n", __func__,
459		    AH_PRIVATE(ah)->ah_analog5GhzRev);
460		ecode = HAL_ENOTSUPP;
461		goto bad;
462	}
463
464	val = OS_REG_READ(ah, AR_PCICFG);
465	val = MS(val, AR_PCICFG_EEPROM_SIZE);
466	if (val == 0) {
467		if (!AH_PRIVATE(ah)->ah_ispcie) {
468			HALDEBUG(ah, HAL_DEBUG_ANY,
469			    "%s: unsupported EEPROM size %u (0x%x) found\n",
470			    __func__, val, val);
471			ecode = HAL_EESIZE;
472			goto bad;
473		}
474		/* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */
475	} else if (val != AR_PCICFG_EEPROM_SIZE_16K) {
476		if (AR_PCICFG_EEPROM_SIZE_FAILED == val) {
477			HALDEBUG(ah, HAL_DEBUG_ANY,
478			    "%s: unsupported EEPROM size %u (0x%x) found\n",
479			    __func__, val, val);
480			ecode = HAL_EESIZE;
481			goto bad;
482		}
483		HALDEBUG(ah, HAL_DEBUG_ANY,
484		    "%s: EEPROM size = %d. Must be %d (16k).\n",
485		    __func__, val, AR_PCICFG_EEPROM_SIZE_16K);
486		ecode = HAL_EESIZE;
487		goto bad;
488	}
489	ecode = ath_hal_legacyEepromAttach(ah);
490	if (ecode != HAL_OK) {
491		goto bad;
492	}
493	ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON);
494
495	/*
496	 * If Bmode and AR5212, verify 2.4 analog exists
497	 */
498	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&
499	    (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {
500		/*
501		 * Set correct Baseband to analog shift
502		 * setting to access analog chips.
503		 */
504		OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);
505		OS_DELAY(2000);
506		AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);
507
508		/* Set baseband for 5GHz chip */
509		OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
510		OS_DELAY(2000);
511		if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {
512			HALDEBUG(ah, HAL_DEBUG_ANY,
513			    "%s: 2G Radio Chip Rev 0x%02X is not "
514			    "supported by this driver\n", __func__,
515			    AH_PRIVATE(ah)->ah_analog2GhzRev);
516			ecode = HAL_ENOTSUPP;
517			goto bad;
518		}
519	}
520
521	ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
522	if (ecode != HAL_OK) {
523		HALDEBUG(ah, HAL_DEBUG_ANY,
524		    "%s: cannot read regulatory domain from EEPROM\n",
525		    __func__);
526		goto bad;
527        }
528	AH_PRIVATE(ah)->ah_currentRD = eeval;
529	/* XXX record serial number */
530
531	/*
532	 * Got everything we need now to setup the capabilities.
533	 */
534	if (!ar5212FillCapabilityInfo(ah)) {
535		HALDEBUG(ah, HAL_DEBUG_ANY,
536		    "%s: failed ar5212FillCapabilityInfo\n", __func__);
537		ecode = HAL_EEREAD;
538		goto bad;
539	}
540
541	if (!rf->attach(ah, &ecode)) {
542		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
543		    __func__, ecode);
544		goto bad;
545	}
546	/*
547	 * Set noise floor adjust method; we arrange a
548	 * direct call instead of thunking.
549	 */
550	AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;
551
552	/* Initialize gain ladder thermal calibration structure */
553	ar5212InitializeGainValues(ah);
554
555	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
556	if (ecode != HAL_OK) {
557		HALDEBUG(ah, HAL_DEBUG_ANY,
558		    "%s: error getting mac address from EEPROM\n", __func__);
559		goto bad;
560        }
561
562	ar5212AniSetup(ah);
563	/* Setup of Radar/AR structures happens in ath_hal_initchannels*/
564	ar5212InitNfCalHistBuffer(ah);
565
566	/* XXX EAR stuff goes here */
567
568	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
569
570	return ah;
571
572bad:
573	if (ahp)
574		ar5212Detach((struct ath_hal *) ahp);
575	if (status)
576		*status = ecode;
577	return AH_NULL;
578#undef AH_EEPROM_PROTECT
579}
580
581void
582ar5212Detach(struct ath_hal *ah)
583{
584	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
585
586	HALASSERT(ah != AH_NULL);
587	HALASSERT(ah->ah_magic == AR5212_MAGIC);
588
589	ar5212AniDetach(ah);
590	ar5212RfDetach(ah);
591	ar5212Disable(ah);
592	ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
593
594	ath_hal_eepromDetach(ah);
595	ath_hal_free(ah);
596}
597
598HAL_BOOL
599ar5212ChipTest(struct ath_hal *ah)
600{
601	uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
602	uint32_t regHold[2];
603	uint32_t patternData[4] =
604	    { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
605	int i, j;
606
607	/* Test PHY & MAC registers */
608	for (i = 0; i < 2; i++) {
609		uint32_t addr = regAddr[i];
610		uint32_t wrData, rdData;
611
612		regHold[i] = OS_REG_READ(ah, addr);
613		for (j = 0; j < 0x100; j++) {
614			wrData = (j << 16) | j;
615			OS_REG_WRITE(ah, addr, wrData);
616			rdData = OS_REG_READ(ah, addr);
617			if (rdData != wrData) {
618				HALDEBUG(ah, HAL_DEBUG_ANY,
619"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
620				__func__, addr, wrData, rdData);
621				return AH_FALSE;
622			}
623		}
624		for (j = 0; j < 4; j++) {
625			wrData = patternData[j];
626			OS_REG_WRITE(ah, addr, wrData);
627			rdData = OS_REG_READ(ah, addr);
628			if (wrData != rdData) {
629				HALDEBUG(ah, HAL_DEBUG_ANY,
630"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
631					__func__, addr, wrData, rdData);
632				return AH_FALSE;
633			}
634		}
635		OS_REG_WRITE(ah, regAddr[i], regHold[i]);
636	}
637	OS_DELAY(100);
638	return AH_TRUE;
639}
640
641/*
642 * Store the channel edges for the requested operational mode
643 */
644HAL_BOOL
645ar5212GetChannelEdges(struct ath_hal *ah,
646	uint16_t flags, uint16_t *low, uint16_t *high)
647{
648	if (flags & IEEE80211_CHAN_5GHZ) {
649		*low = 4915;
650		*high = 6100;
651		return AH_TRUE;
652	}
653	if ((flags & IEEE80211_CHAN_2GHZ) &&
654	    (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) ||
655	     ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) {
656		*low = 2312;
657		*high = 2732;
658		return AH_TRUE;
659	}
660	return AH_FALSE;
661}
662
663/*
664 * Disable PLL when in L0s as well as receiver clock when in L1.
665 * This power saving option must be enabled through the Serdes.
666 *
667 * Programming the Serdes must go through the same 288 bit serial shift
668 * register as the other analog registers.  Hence the 9 writes.
669 *
670 * XXX Clean up the magic numbers.
671 */
672static void
673ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
674{
675	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
676	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
677
678	/* RX shut off when elecidle is asserted */
679	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
680	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
681	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
682
683	/* Shut off PLL and CLKREQ active in L1 */
684	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
685	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
686	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
687	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
688
689	/* Load the new settings */
690	OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
691}
692
693static void
694ar5212DisablePCIE(struct ath_hal *ah)
695{
696	/* NB: fill in for 9100 */
697}
698
699/*
700 * Fill all software cached or static hardware state information.
701 * Return failure if capabilities are to come from EEPROM and
702 * cannot be read.
703 */
704HAL_BOOL
705ar5212FillCapabilityInfo(struct ath_hal *ah)
706{
707#define	AR_KEYTABLE_SIZE	128
708#define	IS_GRIFFIN_LITE(ah) \
709    (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \
710     AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE)
711#define	IS_COBRA(ah) \
712    (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA)
713#define IS_2112(ah) \
714	((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR)
715
716	struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
717	HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
718	uint16_t capField, val;
719
720	/* Read the capability EEPROM location */
721	if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) {
722		HALDEBUG(ah, HAL_DEBUG_ANY,
723		    "%s: unable to read caps from eeprom\n", __func__);
724		return AH_FALSE;
725	}
726	if (IS_2112(ah))
727		ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE);
728	if (capField == 0 && IS_GRIFFIN_LITE(ah)) {
729		/*
730		 * For griffin-lite cards with unprogrammed capabilities.
731		 */
732		ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
733		ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
734		ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
735		ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
736		HALDEBUG(ah, HAL_DEBUG_ATTACH,
737		    "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n",
738		    __func__, capField);
739	}
740
741	/* Modify reg domain on newer cards that need to work with older sw */
742	if (ahpriv->ah_opmode != HAL_M_HOSTAP &&
743	    ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
744		if (ahpriv->ah_currentRD == 0x64 ||
745		    ahpriv->ah_currentRD == 0x65)
746			ahpriv->ah_currentRD += 5;
747		else if (ahpriv->ah_currentRD == 0x41)
748			ahpriv->ah_currentRD = 0x43;
749		HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n",
750		    __func__, ahpriv->ah_currentRD);
751	}
752
753	if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 ||
754	    AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) {
755		HALDEBUG(ah, HAL_DEBUG_ATTACH,
756		    "%s: enable Bmode and disable turbo for Swan/Nala\n",
757		    __func__);
758		ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE);
759		ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
760		ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
761		ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
762		ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
763	}
764
765	/* Construct wireless mode from EEPROM */
766	pCap->halWirelessModes = 0;
767	if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
768		pCap->halWirelessModes |= HAL_MODE_11A;
769		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
770			pCap->halWirelessModes |= HAL_MODE_TURBO;
771	}
772	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
773		pCap->halWirelessModes |= HAL_MODE_11B;
774	if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
775	    ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
776		pCap->halWirelessModes |= HAL_MODE_11G;
777		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
778			pCap->halWirelessModes |= HAL_MODE_108G;
779	}
780
781	pCap->halLow2GhzChan = 2312;
782	/* XXX 2417 too? */
783	if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) ||  IS_2417(ah))
784		pCap->halHigh2GhzChan = 2500;
785	else
786		pCap->halHigh2GhzChan = 2732;
787
788	pCap->halLow5GhzChan = 4915;
789	pCap->halHigh5GhzChan = 6100;
790
791	pCap->halCipherCkipSupport = AH_FALSE;
792	pCap->halCipherTkipSupport = AH_TRUE;
793	pCap->halCipherAesCcmSupport =
794		(ath_hal_eepromGetFlag(ah, AR_EEP_AES) &&
795		 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) ||
796		  ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) &&
797		   (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU))));
798
799	pCap->halMicCkipSupport    = AH_FALSE;
800	pCap->halMicTkipSupport    = AH_TRUE;
801	pCap->halMicAesCcmSupport  = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
802	/*
803	 * Starting with Griffin TX+RX mic keys can be combined
804	 * in one key cache slot.
805	 */
806	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN)
807		pCap->halTkipMicTxRxKeySupport = AH_TRUE;
808	else
809		pCap->halTkipMicTxRxKeySupport = AH_FALSE;
810	pCap->halChanSpreadSupport = AH_TRUE;
811	pCap->halSleepAfterBeaconBroken = AH_TRUE;
812
813	if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) {
814		pCap->halCompressSupport   =
815			ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) &&
816			(pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
817		pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST);
818		pCap->halFastFramesSupport =
819			ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) &&
820			(pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
821		pCap->halChapTuningSupport = AH_TRUE;
822		pCap->halTurboPrimeSupport = AH_TRUE;
823	}
824	pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
825
826	pCap->halPSPollBroken = AH_TRUE;	/* XXX fixed in later revs? */
827	pCap->halNumMRRetries = 4;		/* Hardware supports 4 MRR */
828	pCap->halVEOLSupport = AH_TRUE;
829	pCap->halBssIdMaskSupport = AH_TRUE;
830	pCap->halMcastKeySrchSupport = AH_TRUE;
831	if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE &&
832	     ahpriv->ah_macRev == 8) ||
833	    ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE)
834		pCap->halTsfAddSupport = AH_TRUE;
835
836	if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
837		pCap->halTotalQueues = val;
838	else
839		pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
840
841	if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
842		pCap->halKeyCacheSize = val;
843	else
844		pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
845
846	pCap->halChanHalfRate = AH_TRUE;
847	pCap->halChanQuarterRate = AH_TRUE;
848
849	/*
850	 * RSSI uses the combined field; some 11n NICs may use
851	 * the control chain RSSI.
852	 */
853	pCap->halUseCombinedRadarRssi = AH_TRUE;
854
855	if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
856	    ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
857		/* NB: enabled by default */
858		ahpriv->ah_rfkillEnabled = AH_TRUE;
859		pCap->halRfSilentSupport = AH_TRUE;
860	}
861
862	/* NB: this is a guess, noone seems to know the answer */
863	ahpriv->ah_rxornIsFatal =
864	    (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);
865
866	/* enable features that first appeared in Hainan */
867	if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
868	     AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||
869	    AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) {
870		/* h/w phy counters */
871		pCap->halHwPhyCounterSupport = AH_TRUE;
872		/* bssid match disable */
873		pCap->halBssidMatchSupport = AH_TRUE;
874	}
875
876	pCap->halTstampPrecision = 15;
877	pCap->halIntrMask = HAL_INT_COMMON
878			| HAL_INT_RX
879			| HAL_INT_TX
880			| HAL_INT_FATAL
881			| HAL_INT_BNR
882			| HAL_INT_BMISC
883			;
884	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)
885		pCap->halIntrMask &= ~HAL_INT_TBTT;
886
887	pCap->hal4kbSplitTransSupport = AH_TRUE;
888	pCap->halHasRxSelfLinkedTail = AH_TRUE;
889
890	return AH_TRUE;
891#undef IS_COBRA
892#undef IS_GRIFFIN_LITE
893#undef AR_KEYTABLE_SIZE
894}
895
896static const char*
897ar5212Probe(uint16_t vendorid, uint16_t devid)
898{
899	if (vendorid == ATHEROS_VENDOR_ID ||
900	    vendorid == ATHEROS_3COM_VENDOR_ID ||
901	    vendorid == ATHEROS_3COM2_VENDOR_ID) {
902		switch (devid) {
903		case AR5212_FPGA:
904			return "Atheros 5212 (FPGA)";
905		case AR5212_DEVID:
906		case AR5212_DEVID_IBM:
907		case AR5212_DEFAULT:
908			return "Atheros 5212";
909		case AR5212_AR2413:
910			return "Atheros 2413";
911		case AR5212_AR2417:
912			return "Atheros 2417";
913		case AR5212_AR5413:
914			return "Atheros 5413";
915		case AR5212_AR5424:
916			return "Atheros 5424/2424";
917		}
918	}
919	return AH_NULL;
920}
921AH_CHIP(AR5212, ar5212Probe, ar5212Attach);
922