ar5212_attach.c revision 234873 
1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 234873 2012-05-01 14:48:51Z adrian $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ar5212/ar5212.h"
26#include "ar5212/ar5212reg.h"
27#include "ar5212/ar5212phy.h"
28
29#define AH_5212_COMMON
30#include "ar5212/ar5212.ini"
31
32static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
33static void ar5212DisablePCIE(struct ath_hal *ah);
34
35static const struct ath_hal_private ar5212hal = {{
36	.ah_magic			= AR5212_MAGIC,
37
38	.ah_getRateTable		= ar5212GetRateTable,
39	.ah_detach			= ar5212Detach,
40
41	/* Reset Functions */
42	.ah_reset			= ar5212Reset,
43	.ah_phyDisable			= ar5212PhyDisable,
44	.ah_disable			= ar5212Disable,
45	.ah_configPCIE			= ar5212ConfigPCIE,
46	.ah_disablePCIE			= ar5212DisablePCIE,
47	.ah_setPCUConfig		= ar5212SetPCUConfig,
48	.ah_perCalibration		= ar5212PerCalibration,
49	.ah_perCalibrationN		= ar5212PerCalibrationN,
50	.ah_resetCalValid		= ar5212ResetCalValid,
51	.ah_setTxPowerLimit		= ar5212SetTxPowerLimit,
52	.ah_getChanNoise		= ath_hal_getChanNoise,
53
54	/* Transmit functions */
55	.ah_updateTxTrigLevel		= ar5212UpdateTxTrigLevel,
56	.ah_setupTxQueue		= ar5212SetupTxQueue,
57	.ah_setTxQueueProps             = ar5212SetTxQueueProps,
58	.ah_getTxQueueProps             = ar5212GetTxQueueProps,
59	.ah_releaseTxQueue		= ar5212ReleaseTxQueue,
60	.ah_resetTxQueue		= ar5212ResetTxQueue,
61	.ah_getTxDP			= ar5212GetTxDP,
62	.ah_setTxDP			= ar5212SetTxDP,
63	.ah_numTxPending		= ar5212NumTxPending,
64	.ah_startTxDma			= ar5212StartTxDma,
65	.ah_stopTxDma			= ar5212StopTxDma,
66	.ah_setupTxDesc			= ar5212SetupTxDesc,
67	.ah_setupXTxDesc		= ar5212SetupXTxDesc,
68	.ah_fillTxDesc			= ar5212FillTxDesc,
69	.ah_procTxDesc			= ar5212ProcTxDesc,
70	.ah_getTxIntrQueue		= ar5212GetTxIntrQueue,
71	.ah_reqTxIntrDesc 		= ar5212IntrReqTxDesc,
72	.ah_getTxCompletionRates	= ar5212GetTxCompletionRates,
73
74	/* RX Functions */
75	.ah_getRxDP			= ar5212GetRxDP,
76	.ah_setRxDP			= ar5212SetRxDP,
77	.ah_enableReceive		= ar5212EnableReceive,
78	.ah_stopDmaReceive		= ar5212StopDmaReceive,
79	.ah_startPcuReceive		= ar5212StartPcuReceive,
80	.ah_stopPcuReceive		= ar5212StopPcuReceive,
81	.ah_setMulticastFilter		= ar5212SetMulticastFilter,
82	.ah_setMulticastFilterIndex	= ar5212SetMulticastFilterIndex,
83	.ah_clrMulticastFilterIndex	= ar5212ClrMulticastFilterIndex,
84	.ah_getRxFilter			= ar5212GetRxFilter,
85	.ah_setRxFilter			= ar5212SetRxFilter,
86	.ah_setupRxDesc			= ar5212SetupRxDesc,
87	.ah_procRxDesc			= ar5212ProcRxDesc,
88	.ah_rxMonitor			= ar5212RxMonitor,
89	.ah_aniPoll			= ar5212AniPoll,
90	.ah_procMibEvent		= ar5212ProcessMibIntr,
91
92	/* Misc Functions */
93	.ah_getCapability		= ar5212GetCapability,
94	.ah_setCapability		= ar5212SetCapability,
95	.ah_getDiagState		= ar5212GetDiagState,
96	.ah_getMacAddress		= ar5212GetMacAddress,
97	.ah_setMacAddress		= ar5212SetMacAddress,
98	.ah_getBssIdMask		= ar5212GetBssIdMask,
99	.ah_setBssIdMask		= ar5212SetBssIdMask,
100	.ah_setRegulatoryDomain		= ar5212SetRegulatoryDomain,
101	.ah_setLedState			= ar5212SetLedState,
102	.ah_writeAssocid		= ar5212WriteAssocid,
103	.ah_gpioCfgInput		= ar5212GpioCfgInput,
104	.ah_gpioCfgOutput		= ar5212GpioCfgOutput,
105	.ah_gpioGet			= ar5212GpioGet,
106	.ah_gpioSet			= ar5212GpioSet,
107	.ah_gpioSetIntr			= ar5212GpioSetIntr,
108	.ah_getTsf32			= ar5212GetTsf32,
109	.ah_getTsf64			= ar5212GetTsf64,
110	.ah_resetTsf			= ar5212ResetTsf,
111	.ah_detectCardPresent		= ar5212DetectCardPresent,
112	.ah_updateMibCounters		= ar5212UpdateMibCounters,
113	.ah_getRfGain			= ar5212GetRfgain,
114	.ah_getDefAntenna		= ar5212GetDefAntenna,
115	.ah_setDefAntenna		= ar5212SetDefAntenna,
116	.ah_getAntennaSwitch		= ar5212GetAntennaSwitch,
117	.ah_setAntennaSwitch		= ar5212SetAntennaSwitch,
118	.ah_setSifsTime			= ar5212SetSifsTime,
119	.ah_getSifsTime			= ar5212GetSifsTime,
120	.ah_setSlotTime			= ar5212SetSlotTime,
121	.ah_getSlotTime			= ar5212GetSlotTime,
122	.ah_setAckTimeout		= ar5212SetAckTimeout,
123	.ah_getAckTimeout		= ar5212GetAckTimeout,
124	.ah_setAckCTSRate		= ar5212SetAckCTSRate,
125	.ah_getAckCTSRate		= ar5212GetAckCTSRate,
126	.ah_setCTSTimeout		= ar5212SetCTSTimeout,
127	.ah_getCTSTimeout		= ar5212GetCTSTimeout,
128	.ah_setDecompMask		= ar5212SetDecompMask,
129	.ah_setCoverageClass		= ar5212SetCoverageClass,
130	.ah_setQuiet			= ar5212SetQuiet,
131	.ah_getMibCycleCounts		= ar5212GetMibCycleCounts,
132
133	/* DFS Functions */
134	.ah_enableDfs			= ar5212EnableDfs,
135	.ah_getDfsThresh		= ar5212GetDfsThresh,
136	.ah_procRadarEvent		= ar5212ProcessRadarEvent,
137	.ah_isFastClockEnabled		= ar5212IsFastClockEnabled,
138	.ah_get11nExtBusy		= ar5212Get11nExtBusy,
139
140	/* Key Cache Functions */
141	.ah_getKeyCacheSize		= ar5212GetKeyCacheSize,
142	.ah_resetKeyCacheEntry		= ar5212ResetKeyCacheEntry,
143	.ah_isKeyCacheEntryValid	= ar5212IsKeyCacheEntryValid,
144	.ah_setKeyCacheEntry		= ar5212SetKeyCacheEntry,
145	.ah_setKeyCacheEntryMac		= ar5212SetKeyCacheEntryMac,
146
147	/* Power Management Functions */
148	.ah_setPowerMode		= ar5212SetPowerMode,
149	.ah_getPowerMode		= ar5212GetPowerMode,
150
151	/* Beacon Functions */
152	.ah_setBeaconTimers		= ar5212SetBeaconTimers,
153	.ah_beaconInit			= ar5212BeaconInit,
154	.ah_setStationBeaconTimers	= ar5212SetStaBeaconTimers,
155	.ah_resetStationBeaconTimers	= ar5212ResetStaBeaconTimers,
156	.ah_getNextTBTT			= ar5212GetNextTBTT,
157
158	/* Interrupt Functions */
159	.ah_isInterruptPending		= ar5212IsInterruptPending,
160	.ah_getPendingInterrupts	= ar5212GetPendingInterrupts,
161	.ah_getInterrupts		= ar5212GetInterrupts,
162	.ah_setInterrupts		= ar5212SetInterrupts },
163
164	.ah_getChannelEdges		= ar5212GetChannelEdges,
165	.ah_getWirelessModes		= ar5212GetWirelessModes,
166	.ah_eepromRead			= ar5212EepromRead,
167#ifdef AH_SUPPORT_WRITE_EEPROM
168	.ah_eepromWrite			= ar5212EepromWrite,
169#endif
170	.ah_getChipPowerLimits		= ar5212GetChipPowerLimits,
171};
172
173uint32_t
174ar5212GetRadioRev(struct ath_hal *ah)
175{
176	uint32_t val;
177	int i;
178
179	/* Read Radio Chip Rev Extract */
180	OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16);
181	for (i = 0; i < 8; i++)
182		OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
183	val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
184	val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
185	return ath_hal_reverseBits(val, 8);
186}
187
188static void
189ar5212AniSetup(struct ath_hal *ah)
190{
191	static const struct ar5212AniParams aniparams = {
192		.maxNoiseImmunityLevel	= 4,	/* levels 0..4 */
193		.totalSizeDesired	= { -55, -55, -55, -55, -62 },
194		.coarseHigh		= { -14, -14, -14, -14, -12 },
195		.coarseLow		= { -64, -64, -64, -64, -70 },
196		.firpwr			= { -78, -78, -78, -78, -80 },
197		.maxSpurImmunityLevel	= 2,	/* NB: depends on chip rev */
198		.cycPwrThr1		= { 2, 4, 6, 8, 10, 12, 14, 16 },
199		.maxFirstepLevel	= 2,	/* levels 0..2 */
200		.firstep		= { 0, 4, 8 },
201		.ofdmTrigHigh		= 500,
202		.ofdmTrigLow		= 200,
203		.cckTrigHigh		= 200,
204		.cckTrigLow		= 100,
205		.rssiThrHigh		= 40,
206		.rssiThrLow		= 7,
207		.period			= 100,
208	};
209	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) {
210		struct ar5212AniParams tmp;
211		OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams));
212		tmp.maxSpurImmunityLevel = 7;	/* Venice and earlier */
213		ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE);
214	} else
215		ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
216
217	/* Set overridable ANI methods */
218	AH5212(ah)->ah_aniControl = ar5212AniControl;
219}
220
221/*
222 * Attach for an AR5212 part.
223 */
224void
225ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc,
226	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
227{
228#define	N(a)	(sizeof(a)/sizeof(a[0]))
229	static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] =
230		{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
231	struct ath_hal *ah;
232
233	ah = &ahp->ah_priv.h;
234	/* set initial values */
235	OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private));
236	ah->ah_sc = sc;
237	ah->ah_st = st;
238	ah->ah_sh = sh;
239
240	ah->ah_devid = devid;			/* NB: for alq */
241	AH_PRIVATE(ah)->ah_devid = devid;
242	AH_PRIVATE(ah)->ah_subvendorid = 0;	/* XXX */
243
244	AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
245	AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX;	/* no scaling */
246
247	ahp->ah_antControl = HAL_ANT_VARIABLE;
248	ahp->ah_diversity = AH_TRUE;
249	ahp->ah_bIQCalibration = AH_FALSE;
250	/*
251	 * Enable MIC handling.
252	 */
253	ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
254	ahp->ah_rssiThr = INIT_RSSI_THR;
255	ahp->ah_tpcEnabled = AH_FALSE;		/* disabled by default */
256	ahp->ah_phyPowerOn = AH_FALSE;
257	ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK)
258		       | SM(MAX_RATE_POWER, AR_TPC_CTS)
259		       | SM(MAX_RATE_POWER, AR_TPC_CHIRP);
260	ahp->ah_beaconInterval = 100;		/* XXX [20..1000] */
261	ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */
262	ahp->ah_slottime = (u_int) -1;
263	ahp->ah_acktimeout = (u_int) -1;
264	ahp->ah_ctstimeout = (u_int) -1;
265	ahp->ah_sifstime = (u_int) -1;
266	ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD,
267	ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD,
268
269	OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
270#undef N
271}
272
273/*
274 * Validate MAC version and revision.
275 */
276static HAL_BOOL
277ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev)
278{
279#define	N(a)	(sizeof(a)/sizeof(a[0]))
280	static const struct {
281		uint8_t	version;
282		uint8_t	revMin, revMax;
283	} macs[] = {
284	    { AR_SREV_VERSION_VENICE,
285	      AR_SREV_D2PLUS,		AR_SREV_REVISION_MAX },
286	    { AR_SREV_VERSION_GRIFFIN,
287	      AR_SREV_D2PLUS,		AR_SREV_REVISION_MAX },
288	    { AR_SREV_5413,
289	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
290	    { AR_SREV_5424,
291	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
292	    { AR_SREV_2425,
293	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
294	    { AR_SREV_2417,
295	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
296	};
297	int i;
298
299	for (i = 0; i < N(macs); i++)
300		if (macs[i].version == macVersion &&
301		    macs[i].revMin <= macRev && macRev <= macs[i].revMax)
302			return AH_TRUE;
303	return AH_FALSE;
304#undef N
305}
306
307/*
308 * Attach for an AR5212 part.
309 */
310static struct ath_hal *
311ar5212Attach(uint16_t devid, HAL_SOFTC sc,
312	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
313	HAL_STATUS *status)
314{
315#define	AH_EEPROM_PROTECT(ah) \
316	(AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
317	struct ath_hal_5212 *ahp;
318	struct ath_hal *ah;
319	struct ath_hal_rf *rf;
320	uint32_t val;
321	uint16_t eeval;
322	HAL_STATUS ecode;
323
324	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
325	    __func__, sc, (void*) st, (void*) sh);
326
327	/* NB: memory is returned zero'd */
328	ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
329	if (ahp == AH_NULL) {
330		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
331		    "%s: cannot allocate memory for state block\n", __func__);
332		*status = HAL_ENOMEM;
333		return AH_NULL;
334	}
335	ar5212InitState(ahp, devid, sc, st, sh, status);
336	ah = &ahp->ah_priv.h;
337
338	if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
339		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
340		    __func__);
341		ecode = HAL_EIO;
342		goto bad;
343	}
344	/* Read Revisions from Chips before taking out of reset */
345	val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
346	AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
347	AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
348	AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah);
349
350	if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) {
351		HALDEBUG(ah, HAL_DEBUG_ANY,
352		    "%s: Mac Chip Rev 0x%02x.%x not supported\n" ,
353		    __func__, AH_PRIVATE(ah)->ah_macVersion,
354		    AH_PRIVATE(ah)->ah_macRev);
355		ecode = HAL_ENOTSUPP;
356		goto bad;
357	}
358
359	/* setup common ini data; rf backends handle remainder */
360	HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
361	HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);
362
363	if (!ar5212ChipReset(ah, AH_NULL)) {	/* reset chip */
364		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
365		ecode = HAL_EIO;
366		goto bad;
367	}
368
369	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
370
371	if (AH_PRIVATE(ah)->ah_ispcie) {
372		/* XXX: build flag to disable this? */
373		ath_hal_configPCIE(ah, AH_FALSE);
374	}
375
376	if (!ar5212ChipTest(ah)) {
377		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
378		    __func__);
379		ecode = HAL_ESELFTEST;
380		goto bad;
381	}
382
383	/* Enable PCI core retry fix in software for Hainan and up */
384	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE)
385		OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN);
386
387	/*
388	 * Set correct Baseband to analog shift
389	 * setting to access analog chips.
390	 */
391	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
392
393	/* Read Radio Chip Rev Extract */
394	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
395
396	rf = ath_hal_rfprobe(ah, &ecode);
397	if (rf == AH_NULL)
398		goto bad;
399
400	/* NB: silently accept anything in release code per Atheros */
401	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
402	case AR_RAD5111_SREV_MAJOR:
403	case AR_RAD5112_SREV_MAJOR:
404	case AR_RAD2112_SREV_MAJOR:
405	case AR_RAD2111_SREV_MAJOR:
406	case AR_RAD2413_SREV_MAJOR:
407	case AR_RAD5413_SREV_MAJOR:
408	case AR_RAD5424_SREV_MAJOR:
409		break;
410	default:
411		if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
412			/*
413			 * When RF_Silent is used, the
414			 * analog chip is reset.  So when the system boots
415			 * up with the radio switch off we cannot determine
416			 * the RF chip rev.  To workaround this check the
417			 * mac+phy revs and if Hainan, set the radio rev
418			 * to Derby.
419			 */
420			if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
421			    AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN &&
422			    AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) {
423				AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN;
424				break;
425			}
426			if (IS_2413(ah)) {		/* Griffin */
427				AH_PRIVATE(ah)->ah_analog5GhzRev =
428				    AR_RAD2413_SREV_MAJOR | 0x1;
429				break;
430			}
431			if (IS_5413(ah)) {		/* Eagle */
432				AH_PRIVATE(ah)->ah_analog5GhzRev =
433				    AR_RAD5413_SREV_MAJOR | 0x2;
434				break;
435			}
436			if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */
437				AH_PRIVATE(ah)->ah_analog5GhzRev =
438				    AR_RAD5424_SREV_MAJOR | 0x2;
439				break;
440			}
441		}
442#ifdef AH_DEBUG
443		HALDEBUG(ah, HAL_DEBUG_ANY,
444		    "%s: 5G Radio Chip Rev 0x%02X is not supported by "
445		    "this driver\n",
446		    __func__, AH_PRIVATE(ah)->ah_analog5GhzRev);
447		ecode = HAL_ENOTSUPP;
448		goto bad;
449#endif
450	}
451	if (IS_RAD5112_REV1(ah)) {
452		HALDEBUG(ah, HAL_DEBUG_ANY,
453		    "%s: 5112 Rev 1 is not supported by this "
454		    "driver (analog5GhzRev 0x%x)\n", __func__,
455		    AH_PRIVATE(ah)->ah_analog5GhzRev);
456		ecode = HAL_ENOTSUPP;
457		goto bad;
458	}
459
460	val = OS_REG_READ(ah, AR_PCICFG);
461	val = MS(val, AR_PCICFG_EEPROM_SIZE);
462	if (val == 0) {
463		if (!AH_PRIVATE(ah)->ah_ispcie) {
464			HALDEBUG(ah, HAL_DEBUG_ANY,
465			    "%s: unsupported EEPROM size %u (0x%x) found\n",
466			    __func__, val, val);
467			ecode = HAL_EESIZE;
468			goto bad;
469		}
470		/* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */
471	} else if (val != AR_PCICFG_EEPROM_SIZE_16K) {
472		if (AR_PCICFG_EEPROM_SIZE_FAILED == val) {
473			HALDEBUG(ah, HAL_DEBUG_ANY,
474			    "%s: unsupported EEPROM size %u (0x%x) found\n",
475			    __func__, val, val);
476			ecode = HAL_EESIZE;
477			goto bad;
478		}
479		HALDEBUG(ah, HAL_DEBUG_ANY,
480		    "%s: EEPROM size = %d. Must be %d (16k).\n",
481		    __func__, val, AR_PCICFG_EEPROM_SIZE_16K);
482		ecode = HAL_EESIZE;
483		goto bad;
484	}
485	ecode = ath_hal_legacyEepromAttach(ah);
486	if (ecode != HAL_OK) {
487		goto bad;
488	}
489	ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON);
490
491	/*
492	 * If Bmode and AR5212, verify 2.4 analog exists
493	 */
494	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&
495	    (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {
496		/*
497		 * Set correct Baseband to analog shift
498		 * setting to access analog chips.
499		 */
500		OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);
501		OS_DELAY(2000);
502		AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);
503
504		/* Set baseband for 5GHz chip */
505		OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
506		OS_DELAY(2000);
507		if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {
508			HALDEBUG(ah, HAL_DEBUG_ANY,
509			    "%s: 2G Radio Chip Rev 0x%02X is not "
510			    "supported by this driver\n", __func__,
511			    AH_PRIVATE(ah)->ah_analog2GhzRev);
512			ecode = HAL_ENOTSUPP;
513			goto bad;
514		}
515	}
516
517	ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
518	if (ecode != HAL_OK) {
519		HALDEBUG(ah, HAL_DEBUG_ANY,
520		    "%s: cannot read regulatory domain from EEPROM\n",
521		    __func__);
522		goto bad;
523        }
524	AH_PRIVATE(ah)->ah_currentRD = eeval;
525	/* XXX record serial number */
526
527	/*
528	 * Got everything we need now to setup the capabilities.
529	 */
530	if (!ar5212FillCapabilityInfo(ah)) {
531		HALDEBUG(ah, HAL_DEBUG_ANY,
532		    "%s: failed ar5212FillCapabilityInfo\n", __func__);
533		ecode = HAL_EEREAD;
534		goto bad;
535	}
536
537	if (!rf->attach(ah, &ecode)) {
538		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
539		    __func__, ecode);
540		goto bad;
541	}
542	/*
543	 * Set noise floor adjust method; we arrange a
544	 * direct call instead of thunking.
545	 */
546	AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;
547
548	/* Initialize gain ladder thermal calibration structure */
549	ar5212InitializeGainValues(ah);
550
551	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
552	if (ecode != HAL_OK) {
553		HALDEBUG(ah, HAL_DEBUG_ANY,
554		    "%s: error getting mac address from EEPROM\n", __func__);
555		goto bad;
556        }
557
558	ar5212AniSetup(ah);
559	/* Setup of Radar/AR structures happens in ath_hal_initchannels*/
560	ar5212InitNfCalHistBuffer(ah);
561
562	/* XXX EAR stuff goes here */
563
564	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
565
566	return ah;
567
568bad:
569	if (ahp)
570		ar5212Detach((struct ath_hal *) ahp);
571	if (status)
572		*status = ecode;
573	return AH_NULL;
574#undef AH_EEPROM_PROTECT
575}
576
577void
578ar5212Detach(struct ath_hal *ah)
579{
580	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
581
582	HALASSERT(ah != AH_NULL);
583	HALASSERT(ah->ah_magic == AR5212_MAGIC);
584
585	ar5212AniDetach(ah);
586	ar5212RfDetach(ah);
587	ar5212Disable(ah);
588	ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
589
590	ath_hal_eepromDetach(ah);
591	ath_hal_free(ah);
592}
593
594HAL_BOOL
595ar5212ChipTest(struct ath_hal *ah)
596{
597	uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
598	uint32_t regHold[2];
599	uint32_t patternData[4] =
600	    { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
601	int i, j;
602
603	/* Test PHY & MAC registers */
604	for (i = 0; i < 2; i++) {
605		uint32_t addr = regAddr[i];
606		uint32_t wrData, rdData;
607
608		regHold[i] = OS_REG_READ(ah, addr);
609		for (j = 0; j < 0x100; j++) {
610			wrData = (j << 16) | j;
611			OS_REG_WRITE(ah, addr, wrData);
612			rdData = OS_REG_READ(ah, addr);
613			if (rdData != wrData) {
614				HALDEBUG(ah, HAL_DEBUG_ANY,
615"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
616				__func__, addr, wrData, rdData);
617				return AH_FALSE;
618			}
619		}
620		for (j = 0; j < 4; j++) {
621			wrData = patternData[j];
622			OS_REG_WRITE(ah, addr, wrData);
623			rdData = OS_REG_READ(ah, addr);
624			if (wrData != rdData) {
625				HALDEBUG(ah, HAL_DEBUG_ANY,
626"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
627					__func__, addr, wrData, rdData);
628				return AH_FALSE;
629			}
630		}
631		OS_REG_WRITE(ah, regAddr[i], regHold[i]);
632	}
633	OS_DELAY(100);
634	return AH_TRUE;
635}
636
637/*
638 * Store the channel edges for the requested operational mode
639 */
640HAL_BOOL
641ar5212GetChannelEdges(struct ath_hal *ah,
642	uint16_t flags, uint16_t *low, uint16_t *high)
643{
644	if (flags & IEEE80211_CHAN_5GHZ) {
645		*low = 4915;
646		*high = 6100;
647		return AH_TRUE;
648	}
649	if ((flags & IEEE80211_CHAN_2GHZ) &&
650	    (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) ||
651	     ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) {
652		*low = 2312;
653		*high = 2732;
654		return AH_TRUE;
655	}
656	return AH_FALSE;
657}
658
659/*
660 * Disable PLL when in L0s as well as receiver clock when in L1.
661 * This power saving option must be enabled through the Serdes.
662 *
663 * Programming the Serdes must go through the same 288 bit serial shift
664 * register as the other analog registers.  Hence the 9 writes.
665 *
666 * XXX Clean up the magic numbers.
667 */
668static void
669ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
670{
671	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
672	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
673
674	/* RX shut off when elecidle is asserted */
675	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
676	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
677	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
678
679	/* Shut off PLL and CLKREQ active in L1 */
680	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
681	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
682	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
683	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
684
685	/* Load the new settings */
686	OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
687}
688
689static void
690ar5212DisablePCIE(struct ath_hal *ah)
691{
692	/* NB: fill in for 9100 */
693}
694
695/*
696 * Fill all software cached or static hardware state information.
697 * Return failure if capabilities are to come from EEPROM and
698 * cannot be read.
699 */
700HAL_BOOL
701ar5212FillCapabilityInfo(struct ath_hal *ah)
702{
703#define	AR_KEYTABLE_SIZE	128
704#define	IS_GRIFFIN_LITE(ah) \
705    (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \
706     AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE)
707#define	IS_COBRA(ah) \
708    (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA)
709#define IS_2112(ah) \
710	((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR)
711
712	struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
713	HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
714	uint16_t capField, val;
715
716	/* Read the capability EEPROM location */
717	if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) {
718		HALDEBUG(ah, HAL_DEBUG_ANY,
719		    "%s: unable to read caps from eeprom\n", __func__);
720		return AH_FALSE;
721	}
722	if (IS_2112(ah))
723		ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE);
724	if (capField == 0 && IS_GRIFFIN_LITE(ah)) {
725		/*
726		 * For griffin-lite cards with unprogrammed capabilities.
727		 */
728		ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
729		ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
730		ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
731		ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
732		HALDEBUG(ah, HAL_DEBUG_ATTACH,
733		    "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n",
734		    __func__, capField);
735	}
736
737	/* Modify reg domain on newer cards that need to work with older sw */
738	if (ahpriv->ah_opmode != HAL_M_HOSTAP &&
739	    ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
740		if (ahpriv->ah_currentRD == 0x64 ||
741		    ahpriv->ah_currentRD == 0x65)
742			ahpriv->ah_currentRD += 5;
743		else if (ahpriv->ah_currentRD == 0x41)
744			ahpriv->ah_currentRD = 0x43;
745		HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n",
746		    __func__, ahpriv->ah_currentRD);
747	}
748
749	if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 ||
750	    AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) {
751		HALDEBUG(ah, HAL_DEBUG_ATTACH,
752		    "%s: enable Bmode and disable turbo for Swan/Nala\n",
753		    __func__);
754		ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE);
755		ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
756		ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
757		ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
758		ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
759	}
760
761	/* Construct wireless mode from EEPROM */
762	pCap->halWirelessModes = 0;
763	if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
764		pCap->halWirelessModes |= HAL_MODE_11A;
765		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
766			pCap->halWirelessModes |= HAL_MODE_TURBO;
767	}
768	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
769		pCap->halWirelessModes |= HAL_MODE_11B;
770	if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
771	    ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
772		pCap->halWirelessModes |= HAL_MODE_11G;
773		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
774			pCap->halWirelessModes |= HAL_MODE_108G;
775	}
776
777	pCap->halLow2GhzChan = 2312;
778	/* XXX 2417 too? */
779	if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) ||  IS_2417(ah))
780		pCap->halHigh2GhzChan = 2500;
781	else
782		pCap->halHigh2GhzChan = 2732;
783
784	pCap->halLow5GhzChan = 4915;
785	pCap->halHigh5GhzChan = 6100;
786
787	pCap->halCipherCkipSupport = AH_FALSE;
788	pCap->halCipherTkipSupport = AH_TRUE;
789	pCap->halCipherAesCcmSupport =
790		(ath_hal_eepromGetFlag(ah, AR_EEP_AES) &&
791		 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) ||
792		  ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) &&
793		   (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU))));
794
795	pCap->halMicCkipSupport    = AH_FALSE;
796	pCap->halMicTkipSupport    = AH_TRUE;
797	pCap->halMicAesCcmSupport  = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
798	/*
799	 * Starting with Griffin TX+RX mic keys can be combined
800	 * in one key cache slot.
801	 */
802	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN)
803		pCap->halTkipMicTxRxKeySupport = AH_TRUE;
804	else
805		pCap->halTkipMicTxRxKeySupport = AH_FALSE;
806	pCap->halChanSpreadSupport = AH_TRUE;
807	pCap->halSleepAfterBeaconBroken = AH_TRUE;
808
809	if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) {
810		pCap->halCompressSupport   =
811			ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) &&
812			(pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
813		pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST);
814		pCap->halFastFramesSupport =
815			ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) &&
816			(pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
817		pCap->halChapTuningSupport = AH_TRUE;
818		pCap->halTurboPrimeSupport = AH_TRUE;
819	}
820	pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
821
822	pCap->halPSPollBroken = AH_TRUE;	/* XXX fixed in later revs? */
823	pCap->halVEOLSupport = AH_TRUE;
824	pCap->halBssIdMaskSupport = AH_TRUE;
825	pCap->halMcastKeySrchSupport = AH_TRUE;
826	if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE &&
827	     ahpriv->ah_macRev == 8) ||
828	    ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE)
829		pCap->halTsfAddSupport = AH_TRUE;
830
831	if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
832		pCap->halTotalQueues = val;
833	else
834		pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
835
836	if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
837		pCap->halKeyCacheSize = val;
838	else
839		pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
840
841	pCap->halChanHalfRate = AH_TRUE;
842	pCap->halChanQuarterRate = AH_TRUE;
843
844	/*
845	 * RSSI uses the combined field; some 11n NICs may use
846	 * the control chain RSSI.
847	 */
848	pCap->halUseCombinedRadarRssi = AH_TRUE;
849
850	if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
851	    ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
852		/* NB: enabled by default */
853		ahpriv->ah_rfkillEnabled = AH_TRUE;
854		pCap->halRfSilentSupport = AH_TRUE;
855	}
856
857	/* NB: this is a guess, noone seems to know the answer */
858	ahpriv->ah_rxornIsFatal =
859	    (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);
860
861	/* enable features that first appeared in Hainan */
862	if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
863	     AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||
864	    AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) {
865		/* h/w phy counters */
866		pCap->halHwPhyCounterSupport = AH_TRUE;
867		/* bssid match disable */
868		pCap->halBssidMatchSupport = AH_TRUE;
869	}
870
871	pCap->halTstampPrecision = 15;
872	pCap->halIntrMask = HAL_INT_COMMON
873			| HAL_INT_RX
874			| HAL_INT_TX
875			| HAL_INT_FATAL
876			| HAL_INT_BNR
877			| HAL_INT_BMISC
878			;
879	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)
880		pCap->halIntrMask &= ~HAL_INT_TBTT;
881
882	pCap->hal4kbSplitTransSupport = AH_TRUE;
883	pCap->halHasRxSelfLinkedTail = AH_TRUE;
884
885	return AH_TRUE;
886#undef IS_COBRA
887#undef IS_GRIFFIN_LITE
888#undef AR_KEYTABLE_SIZE
889}
890
891static const char*
892ar5212Probe(uint16_t vendorid, uint16_t devid)
893{
894	if (vendorid == ATHEROS_VENDOR_ID ||
895	    vendorid == ATHEROS_3COM_VENDOR_ID ||
896	    vendorid == ATHEROS_3COM2_VENDOR_ID) {
897		switch (devid) {
898		case AR5212_FPGA:
899			return "Atheros 5212 (FPGA)";
900		case AR5212_DEVID:
901		case AR5212_DEVID_IBM:
902		case AR5212_DEFAULT:
903			return "Atheros 5212";
904		case AR5212_AR2413:
905			return "Atheros 2413";
906		case AR5212_AR2417:
907			return "Atheros 2417";
908		case AR5212_AR5413:
909			return "Atheros 5413";
910		case AR5212_AR5424:
911			return "Atheros 5424/2424";
912		}
913	}
914	return AH_NULL;
915}
916AH_CHIP(AR5212, ar5212Probe, ar5212Attach);
917