ar5212_attach.c revision 217624
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 217624 2011-01-20 07:56:09Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ar5212/ar5212.h" 26#include "ar5212/ar5212reg.h" 27#include "ar5212/ar5212phy.h" 28 29#define AH_5212_COMMON 30#include "ar5212/ar5212.ini" 31 32static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 33static void ar5212DisablePCIE(struct ath_hal *ah); 34 35static const struct ath_hal_private ar5212hal = {{ 36 .ah_magic = AR5212_MAGIC, 37 38 .ah_getRateTable = ar5212GetRateTable, 39 .ah_detach = ar5212Detach, 40 41 /* Reset Functions */ 42 .ah_reset = ar5212Reset, 43 .ah_phyDisable = ar5212PhyDisable, 44 .ah_disable = ar5212Disable, 45 .ah_configPCIE = ar5212ConfigPCIE, 46 .ah_disablePCIE = ar5212DisablePCIE, 47 .ah_setPCUConfig = ar5212SetPCUConfig, 48 .ah_perCalibration = ar5212PerCalibration, 49 .ah_perCalibrationN = ar5212PerCalibrationN, 50 .ah_resetCalValid = ar5212ResetCalValid, 51 .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 52 .ah_getChanNoise = ath_hal_getChanNoise, 53 54 /* Transmit functions */ 55 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 56 .ah_setupTxQueue = ar5212SetupTxQueue, 57 .ah_setTxQueueProps = ar5212SetTxQueueProps, 58 .ah_getTxQueueProps = ar5212GetTxQueueProps, 59 .ah_releaseTxQueue = ar5212ReleaseTxQueue, 60 .ah_resetTxQueue = ar5212ResetTxQueue, 61 .ah_getTxDP = ar5212GetTxDP, 62 .ah_setTxDP = ar5212SetTxDP, 63 .ah_numTxPending = ar5212NumTxPending, 64 .ah_startTxDma = ar5212StartTxDma, 65 .ah_stopTxDma = ar5212StopTxDma, 66 .ah_setupTxDesc = ar5212SetupTxDesc, 67 .ah_setupXTxDesc = ar5212SetupXTxDesc, 68 .ah_fillTxDesc = ar5212FillTxDesc, 69 .ah_procTxDesc = ar5212ProcTxDesc, 70 .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 71 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 72 .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 73 74 /* RX Functions */ 75 .ah_getRxDP = ar5212GetRxDP, 76 .ah_setRxDP = ar5212SetRxDP, 77 .ah_enableReceive = ar5212EnableReceive, 78 .ah_stopDmaReceive = ar5212StopDmaReceive, 79 .ah_startPcuReceive = ar5212StartPcuReceive, 80 .ah_stopPcuReceive = ar5212StopPcuReceive, 81 .ah_setMulticastFilter = ar5212SetMulticastFilter, 82 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 83 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 84 .ah_getRxFilter = ar5212GetRxFilter, 85 .ah_setRxFilter = ar5212SetRxFilter, 86 .ah_setupRxDesc = ar5212SetupRxDesc, 87 .ah_procRxDesc = ar5212ProcRxDesc, 88 .ah_rxMonitor = ar5212AniPoll, 89 .ah_procMibEvent = ar5212ProcessMibIntr, 90 91 /* Misc Functions */ 92 .ah_getCapability = ar5212GetCapability, 93 .ah_setCapability = ar5212SetCapability, 94 .ah_getDiagState = ar5212GetDiagState, 95 .ah_getMacAddress = ar5212GetMacAddress, 96 .ah_setMacAddress = ar5212SetMacAddress, 97 .ah_getBssIdMask = ar5212GetBssIdMask, 98 .ah_setBssIdMask = ar5212SetBssIdMask, 99 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 100 .ah_setLedState = ar5212SetLedState, 101 .ah_writeAssocid = ar5212WriteAssocid, 102 .ah_gpioCfgInput = ar5212GpioCfgInput, 103 .ah_gpioCfgOutput = ar5212GpioCfgOutput, 104 .ah_gpioGet = ar5212GpioGet, 105 .ah_gpioSet = ar5212GpioSet, 106 .ah_gpioSetIntr = ar5212GpioSetIntr, 107 .ah_getTsf32 = ar5212GetTsf32, 108 .ah_getTsf64 = ar5212GetTsf64, 109 .ah_resetTsf = ar5212ResetTsf, 110 .ah_detectCardPresent = ar5212DetectCardPresent, 111 .ah_updateMibCounters = ar5212UpdateMibCounters, 112 .ah_getRfGain = ar5212GetRfgain, 113 .ah_getDefAntenna = ar5212GetDefAntenna, 114 .ah_setDefAntenna = ar5212SetDefAntenna, 115 .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 116 .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 117 .ah_setSifsTime = ar5212SetSifsTime, 118 .ah_getSifsTime = ar5212GetSifsTime, 119 .ah_setSlotTime = ar5212SetSlotTime, 120 .ah_getSlotTime = ar5212GetSlotTime, 121 .ah_setAckTimeout = ar5212SetAckTimeout, 122 .ah_getAckTimeout = ar5212GetAckTimeout, 123 .ah_setAckCTSRate = ar5212SetAckCTSRate, 124 .ah_getAckCTSRate = ar5212GetAckCTSRate, 125 .ah_setCTSTimeout = ar5212SetCTSTimeout, 126 .ah_getCTSTimeout = ar5212GetCTSTimeout, 127 .ah_setDecompMask = ar5212SetDecompMask, 128 .ah_setCoverageClass = ar5212SetCoverageClass, 129 130 /* Key Cache Functions */ 131 .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 132 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 133 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 134 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 135 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 136 137 /* Power Management Functions */ 138 .ah_setPowerMode = ar5212SetPowerMode, 139 .ah_getPowerMode = ar5212GetPowerMode, 140 141 /* Beacon Functions */ 142 .ah_setBeaconTimers = ar5212SetBeaconTimers, 143 .ah_beaconInit = ar5212BeaconInit, 144 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 145 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 146 147 /* Interrupt Functions */ 148 .ah_isInterruptPending = ar5212IsInterruptPending, 149 .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 150 .ah_getInterrupts = ar5212GetInterrupts, 151 .ah_setInterrupts = ar5212SetInterrupts }, 152 153 .ah_getChannelEdges = ar5212GetChannelEdges, 154 .ah_getWirelessModes = ar5212GetWirelessModes, 155 .ah_eepromRead = ar5212EepromRead, 156#ifdef AH_SUPPORT_WRITE_EEPROM 157 .ah_eepromWrite = ar5212EepromWrite, 158#endif 159 .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 160}; 161 162uint32_t 163ar5212GetRadioRev(struct ath_hal *ah) 164{ 165 uint32_t val; 166 int i; 167 168 /* Read Radio Chip Rev Extract */ 169 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 170 for (i = 0; i < 8; i++) 171 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 172 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 173 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 174 return ath_hal_reverseBits(val, 8); 175} 176 177static void 178ar5212AniSetup(struct ath_hal *ah) 179{ 180 static const struct ar5212AniParams aniparams = { 181 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 182 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 183 .coarseHigh = { -14, -14, -14, -14, -12 }, 184 .coarseLow = { -64, -64, -64, -64, -70 }, 185 .firpwr = { -78, -78, -78, -78, -80 }, 186 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 187 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 188 .maxFirstepLevel = 2, /* levels 0..2 */ 189 .firstep = { 0, 4, 8 }, 190 .ofdmTrigHigh = 500, 191 .ofdmTrigLow = 200, 192 .cckTrigHigh = 200, 193 .cckTrigLow = 100, 194 .rssiThrHigh = 40, 195 .rssiThrLow = 7, 196 .period = 100, 197 }; 198 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 199 struct ar5212AniParams tmp; 200 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 201 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 202 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 203 } else 204 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 205} 206 207/* 208 * Attach for an AR5212 part. 209 */ 210void 211ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 212 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 213{ 214#define N(a) (sizeof(a)/sizeof(a[0])) 215 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 216 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 217 struct ath_hal *ah; 218 219 ah = &ahp->ah_priv.h; 220 /* set initial values */ 221 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 222 ah->ah_sc = sc; 223 ah->ah_st = st; 224 ah->ah_sh = sh; 225 226 ah->ah_devid = devid; /* NB: for alq */ 227 AH_PRIVATE(ah)->ah_devid = devid; 228 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 229 230 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 231 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 232 233 ahp->ah_antControl = HAL_ANT_VARIABLE; 234 ahp->ah_diversity = AH_TRUE; 235 ahp->ah_bIQCalibration = AH_FALSE; 236 /* 237 * Enable MIC handling. 238 */ 239 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 240 ahp->ah_rssiThr = INIT_RSSI_THR; 241 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 242 ahp->ah_phyPowerOn = AH_FALSE; 243 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 244 | SM(MAX_RATE_POWER, AR_TPC_CTS) 245 | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 246 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 247 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 248 ahp->ah_slottime = (u_int) -1; 249 ahp->ah_acktimeout = (u_int) -1; 250 ahp->ah_ctstimeout = (u_int) -1; 251 ahp->ah_sifstime = (u_int) -1; 252 ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD, 253 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD, 254 255 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 256#undef N 257} 258 259/* 260 * Validate MAC version and revision. 261 */ 262static HAL_BOOL 263ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 264{ 265#define N(a) (sizeof(a)/sizeof(a[0])) 266 static const struct { 267 uint8_t version; 268 uint8_t revMin, revMax; 269 } macs[] = { 270 { AR_SREV_VERSION_VENICE, 271 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 272 { AR_SREV_VERSION_GRIFFIN, 273 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 274 { AR_SREV_5413, 275 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 276 { AR_SREV_5424, 277 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 278 { AR_SREV_2425, 279 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 280 { AR_SREV_2417, 281 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 282 }; 283 int i; 284 285 for (i = 0; i < N(macs); i++) 286 if (macs[i].version == macVersion && 287 macs[i].revMin <= macRev && macRev <= macs[i].revMax) 288 return AH_TRUE; 289 return AH_FALSE; 290#undef N 291} 292 293/* 294 * Attach for an AR5212 part. 295 */ 296static struct ath_hal * 297ar5212Attach(uint16_t devid, HAL_SOFTC sc, 298 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 299 HAL_STATUS *status) 300{ 301#define AH_EEPROM_PROTECT(ah) \ 302 (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 303 struct ath_hal_5212 *ahp; 304 struct ath_hal *ah; 305 struct ath_hal_rf *rf; 306 uint32_t val; 307 uint16_t eeval; 308 HAL_STATUS ecode; 309 310 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 311 __func__, sc, (void*) st, (void*) sh); 312 313 /* NB: memory is returned zero'd */ 314 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 315 if (ahp == AH_NULL) { 316 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 317 "%s: cannot allocate memory for state block\n", __func__); 318 *status = HAL_ENOMEM; 319 return AH_NULL; 320 } 321 ar5212InitState(ahp, devid, sc, st, sh, status); 322 ah = &ahp->ah_priv.h; 323 324 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 325 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 326 __func__); 327 ecode = HAL_EIO; 328 goto bad; 329 } 330 /* Read Revisions from Chips before taking out of reset */ 331 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 332 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 333 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 334 AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 335 336 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 337 HALDEBUG(ah, HAL_DEBUG_ANY, 338 "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 339 __func__, AH_PRIVATE(ah)->ah_macVersion, 340 AH_PRIVATE(ah)->ah_macRev); 341 ecode = HAL_ENOTSUPP; 342 goto bad; 343 } 344 345 /* setup common ini data; rf backends handle remainder */ 346 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 347 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 348 349 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 350 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 351 ecode = HAL_EIO; 352 goto bad; 353 } 354 355 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 356 357 if (AH_PRIVATE(ah)->ah_ispcie) { 358 /* XXX: build flag to disable this? */ 359 ath_hal_configPCIE(ah, AH_FALSE); 360 } 361 362 if (!ar5212ChipTest(ah)) { 363 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 364 __func__); 365 ecode = HAL_ESELFTEST; 366 goto bad; 367 } 368 369 /* Enable PCI core retry fix in software for Hainan and up */ 370 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 371 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 372 373 /* 374 * Set correct Baseband to analog shift 375 * setting to access analog chips. 376 */ 377 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 378 379 /* Read Radio Chip Rev Extract */ 380 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 381 382 rf = ath_hal_rfprobe(ah, &ecode); 383 if (rf == AH_NULL) 384 goto bad; 385 386 /* NB: silently accept anything in release code per Atheros */ 387 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 388 case AR_RAD5111_SREV_MAJOR: 389 case AR_RAD5112_SREV_MAJOR: 390 case AR_RAD2112_SREV_MAJOR: 391 case AR_RAD2111_SREV_MAJOR: 392 case AR_RAD2413_SREV_MAJOR: 393 case AR_RAD5413_SREV_MAJOR: 394 case AR_RAD5424_SREV_MAJOR: 395 break; 396 default: 397 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 398 /* 399 * When RF_Silent is used, the 400 * analog chip is reset. So when the system boots 401 * up with the radio switch off we cannot determine 402 * the RF chip rev. To workaround this check the 403 * mac+phy revs and if Hainan, set the radio rev 404 * to Derby. 405 */ 406 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 407 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 408 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 409 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 410 break; 411 } 412 if (IS_2413(ah)) { /* Griffin */ 413 AH_PRIVATE(ah)->ah_analog5GhzRev = 414 AR_RAD2413_SREV_MAJOR | 0x1; 415 break; 416 } 417 if (IS_5413(ah)) { /* Eagle */ 418 AH_PRIVATE(ah)->ah_analog5GhzRev = 419 AR_RAD5413_SREV_MAJOR | 0x2; 420 break; 421 } 422 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 423 AH_PRIVATE(ah)->ah_analog5GhzRev = 424 AR_RAD5424_SREV_MAJOR | 0x2; 425 break; 426 } 427 } 428#ifdef AH_DEBUG 429 HALDEBUG(ah, HAL_DEBUG_ANY, 430 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 431 "this driver\n", 432 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 433 ecode = HAL_ENOTSUPP; 434 goto bad; 435#endif 436 } 437 if (IS_RAD5112_REV1(ah)) { 438 HALDEBUG(ah, HAL_DEBUG_ANY, 439 "%s: 5112 Rev 1 is not supported by this " 440 "driver (analog5GhzRev 0x%x)\n", __func__, 441 AH_PRIVATE(ah)->ah_analog5GhzRev); 442 ecode = HAL_ENOTSUPP; 443 goto bad; 444 } 445 446 val = OS_REG_READ(ah, AR_PCICFG); 447 val = MS(val, AR_PCICFG_EEPROM_SIZE); 448 if (val == 0) { 449 if (!AH_PRIVATE(ah)->ah_ispcie) { 450 HALDEBUG(ah, HAL_DEBUG_ANY, 451 "%s: unsupported EEPROM size %u (0x%x) found\n", 452 __func__, val, val); 453 ecode = HAL_EESIZE; 454 goto bad; 455 } 456 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 457 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 458 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 459 HALDEBUG(ah, HAL_DEBUG_ANY, 460 "%s: unsupported EEPROM size %u (0x%x) found\n", 461 __func__, val, val); 462 ecode = HAL_EESIZE; 463 goto bad; 464 } 465 HALDEBUG(ah, HAL_DEBUG_ANY, 466 "%s: EEPROM size = %d. Must be %d (16k).\n", 467 __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 468 ecode = HAL_EESIZE; 469 goto bad; 470 } 471 ecode = ath_hal_legacyEepromAttach(ah); 472 if (ecode != HAL_OK) { 473 goto bad; 474 } 475 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 476 477 /* 478 * If Bmode and AR5212, verify 2.4 analog exists 479 */ 480 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 481 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 482 /* 483 * Set correct Baseband to analog shift 484 * setting to access analog chips. 485 */ 486 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 487 OS_DELAY(2000); 488 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 489 490 /* Set baseband for 5GHz chip */ 491 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 492 OS_DELAY(2000); 493 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 494 HALDEBUG(ah, HAL_DEBUG_ANY, 495 "%s: 2G Radio Chip Rev 0x%02X is not " 496 "supported by this driver\n", __func__, 497 AH_PRIVATE(ah)->ah_analog2GhzRev); 498 ecode = HAL_ENOTSUPP; 499 goto bad; 500 } 501 } 502 503 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 504 if (ecode != HAL_OK) { 505 HALDEBUG(ah, HAL_DEBUG_ANY, 506 "%s: cannot read regulatory domain from EEPROM\n", 507 __func__); 508 goto bad; 509 } 510 AH_PRIVATE(ah)->ah_currentRD = eeval; 511 /* XXX record serial number */ 512 513 /* 514 * Got everything we need now to setup the capabilities. 515 */ 516 if (!ar5212FillCapabilityInfo(ah)) { 517 HALDEBUG(ah, HAL_DEBUG_ANY, 518 "%s: failed ar5212FillCapabilityInfo\n", __func__); 519 ecode = HAL_EEREAD; 520 goto bad; 521 } 522 523 if (!rf->attach(ah, &ecode)) { 524 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 525 __func__, ecode); 526 goto bad; 527 } 528 /* 529 * Set noise floor adjust method; we arrange a 530 * direct call instead of thunking. 531 */ 532 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 533 534 /* Initialize gain ladder thermal calibration structure */ 535 ar5212InitializeGainValues(ah); 536 537 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 538 if (ecode != HAL_OK) { 539 HALDEBUG(ah, HAL_DEBUG_ANY, 540 "%s: error getting mac address from EEPROM\n", __func__); 541 goto bad; 542 } 543 544 ar5212AniSetup(ah); 545 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 546 ar5212InitNfCalHistBuffer(ah); 547 548 /* XXX EAR stuff goes here */ 549 550 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 551 552 return ah; 553 554bad: 555 if (ahp) 556 ar5212Detach((struct ath_hal *) ahp); 557 if (status) 558 *status = ecode; 559 return AH_NULL; 560#undef AH_EEPROM_PROTECT 561} 562 563void 564ar5212Detach(struct ath_hal *ah) 565{ 566 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 567 568 HALASSERT(ah != AH_NULL); 569 HALASSERT(ah->ah_magic == AR5212_MAGIC); 570 571 ar5212AniDetach(ah); 572 ar5212RfDetach(ah); 573 ar5212Disable(ah); 574 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 575 576 ath_hal_eepromDetach(ah); 577 ath_hal_free(ah); 578} 579 580HAL_BOOL 581ar5212ChipTest(struct ath_hal *ah) 582{ 583 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 584 uint32_t regHold[2]; 585 uint32_t patternData[4] = 586 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 587 int i, j; 588 589 /* Test PHY & MAC registers */ 590 for (i = 0; i < 2; i++) { 591 uint32_t addr = regAddr[i]; 592 uint32_t wrData, rdData; 593 594 regHold[i] = OS_REG_READ(ah, addr); 595 for (j = 0; j < 0x100; j++) { 596 wrData = (j << 16) | j; 597 OS_REG_WRITE(ah, addr, wrData); 598 rdData = OS_REG_READ(ah, addr); 599 if (rdData != wrData) { 600 HALDEBUG(ah, HAL_DEBUG_ANY, 601"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 602 __func__, addr, wrData, rdData); 603 return AH_FALSE; 604 } 605 } 606 for (j = 0; j < 4; j++) { 607 wrData = patternData[j]; 608 OS_REG_WRITE(ah, addr, wrData); 609 rdData = OS_REG_READ(ah, addr); 610 if (wrData != rdData) { 611 HALDEBUG(ah, HAL_DEBUG_ANY, 612"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 613 __func__, addr, wrData, rdData); 614 return AH_FALSE; 615 } 616 } 617 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 618 } 619 OS_DELAY(100); 620 return AH_TRUE; 621} 622 623/* 624 * Store the channel edges for the requested operational mode 625 */ 626HAL_BOOL 627ar5212GetChannelEdges(struct ath_hal *ah, 628 uint16_t flags, uint16_t *low, uint16_t *high) 629{ 630 if (flags & IEEE80211_CHAN_5GHZ) { 631 *low = 4915; 632 *high = 6100; 633 return AH_TRUE; 634 } 635 if ((flags & IEEE80211_CHAN_2GHZ) && 636 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 637 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 638 *low = 2312; 639 *high = 2732; 640 return AH_TRUE; 641 } 642 return AH_FALSE; 643} 644 645/* 646 * Disable PLL when in L0s as well as receiver clock when in L1. 647 * This power saving option must be enabled through the Serdes. 648 * 649 * Programming the Serdes must go through the same 288 bit serial shift 650 * register as the other analog registers. Hence the 9 writes. 651 * 652 * XXX Clean up the magic numbers. 653 */ 654static void 655ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 656{ 657 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 658 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 659 660 /* RX shut off when elecidle is asserted */ 661 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 662 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 663 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 664 665 /* Shut off PLL and CLKREQ active in L1 */ 666 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 667 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 668 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 669 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 670 671 /* Load the new settings */ 672 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 673} 674 675static void 676ar5212DisablePCIE(struct ath_hal *ah) 677{ 678 /* NB: fill in for 9100 */ 679} 680 681/* 682 * Fill all software cached or static hardware state information. 683 * Return failure if capabilities are to come from EEPROM and 684 * cannot be read. 685 */ 686HAL_BOOL 687ar5212FillCapabilityInfo(struct ath_hal *ah) 688{ 689#define AR_KEYTABLE_SIZE 128 690#define IS_GRIFFIN_LITE(ah) \ 691 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 692 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 693#define IS_COBRA(ah) \ 694 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 695#define IS_2112(ah) \ 696 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 697 698 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 699 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 700 uint16_t capField, val; 701 702 /* Read the capability EEPROM location */ 703 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 704 HALDEBUG(ah, HAL_DEBUG_ANY, 705 "%s: unable to read caps from eeprom\n", __func__); 706 return AH_FALSE; 707 } 708 if (IS_2112(ah)) 709 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 710 if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 711 /* 712 * For griffin-lite cards with unprogrammed capabilities. 713 */ 714 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 715 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 716 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 717 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 718 HALDEBUG(ah, HAL_DEBUG_ATTACH, 719 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 720 __func__, capField); 721 } 722 723 /* Modify reg domain on newer cards that need to work with older sw */ 724 if (ahpriv->ah_opmode != HAL_M_HOSTAP && 725 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 726 if (ahpriv->ah_currentRD == 0x64 || 727 ahpriv->ah_currentRD == 0x65) 728 ahpriv->ah_currentRD += 5; 729 else if (ahpriv->ah_currentRD == 0x41) 730 ahpriv->ah_currentRD = 0x43; 731 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 732 __func__, ahpriv->ah_currentRD); 733 } 734 735 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 736 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 737 HALDEBUG(ah, HAL_DEBUG_ATTACH, 738 "%s: enable Bmode and disable turbo for Swan/Nala\n", 739 __func__); 740 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 741 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 742 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 743 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 744 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 745 } 746 747 /* Construct wireless mode from EEPROM */ 748 pCap->halWirelessModes = 0; 749 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 750 pCap->halWirelessModes |= HAL_MODE_11A; 751 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 752 pCap->halWirelessModes |= HAL_MODE_TURBO; 753 } 754 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 755 pCap->halWirelessModes |= HAL_MODE_11B; 756 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 757 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 758 pCap->halWirelessModes |= HAL_MODE_11G; 759 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 760 pCap->halWirelessModes |= HAL_MODE_108G; 761 } 762 763 pCap->halLow2GhzChan = 2312; 764 /* XXX 2417 too? */ 765 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 766 pCap->halHigh2GhzChan = 2500; 767 else 768 pCap->halHigh2GhzChan = 2732; 769 770 pCap->halLow5GhzChan = 4915; 771 pCap->halHigh5GhzChan = 6100; 772 773 pCap->halCipherCkipSupport = AH_FALSE; 774 pCap->halCipherTkipSupport = AH_TRUE; 775 pCap->halCipherAesCcmSupport = 776 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 777 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 778 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 779 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 780 781 pCap->halMicCkipSupport = AH_FALSE; 782 pCap->halMicTkipSupport = AH_TRUE; 783 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 784 /* 785 * Starting with Griffin TX+RX mic keys can be combined 786 * in one key cache slot. 787 */ 788 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 789 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 790 else 791 pCap->halTkipMicTxRxKeySupport = AH_FALSE; 792 pCap->halChanSpreadSupport = AH_TRUE; 793 pCap->halSleepAfterBeaconBroken = AH_TRUE; 794 795 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 796 pCap->halCompressSupport = 797 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 798 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 799 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 800 pCap->halFastFramesSupport = 801 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 802 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 803 pCap->halChapTuningSupport = AH_TRUE; 804 pCap->halTurboPrimeSupport = AH_TRUE; 805 } 806 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 807 808 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 809 pCap->halVEOLSupport = AH_TRUE; 810 pCap->halBssIdMaskSupport = AH_TRUE; 811 pCap->halMcastKeySrchSupport = AH_TRUE; 812 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 813 ahpriv->ah_macRev == 8) || 814 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 815 pCap->halTsfAddSupport = AH_TRUE; 816 817 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 818 pCap->halTotalQueues = val; 819 else 820 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 821 822 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 823 pCap->halKeyCacheSize = val; 824 else 825 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 826 827 pCap->halChanHalfRate = AH_TRUE; 828 pCap->halChanQuarterRate = AH_TRUE; 829 830 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 831 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 832 /* NB: enabled by default */ 833 ahpriv->ah_rfkillEnabled = AH_TRUE; 834 pCap->halRfSilentSupport = AH_TRUE; 835 } 836 837 /* NB: this is a guess, noone seems to know the answer */ 838 ahpriv->ah_rxornIsFatal = 839 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 840 841 /* enable features that first appeared in Hainan */ 842 if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 843 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 844 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 845 /* h/w phy counters */ 846 pCap->halHwPhyCounterSupport = AH_TRUE; 847 /* bssid match disable */ 848 pCap->halBssidMatchSupport = AH_TRUE; 849 } 850 851 pCap->halTstampPrecision = 15; 852 pCap->halIntrMask = HAL_INT_COMMON 853 | HAL_INT_RX 854 | HAL_INT_TX 855 | HAL_INT_FATAL 856 | HAL_INT_BNR 857 | HAL_INT_BMISC 858 ; 859 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 860 pCap->halIntrMask &= ~HAL_INT_TBTT; 861 862 return AH_TRUE; 863#undef IS_COBRA 864#undef IS_GRIFFIN_LITE 865#undef AR_KEYTABLE_SIZE 866} 867 868static const char* 869ar5212Probe(uint16_t vendorid, uint16_t devid) 870{ 871 if (vendorid == ATHEROS_VENDOR_ID || 872 vendorid == ATHEROS_3COM_VENDOR_ID || 873 vendorid == ATHEROS_3COM2_VENDOR_ID) { 874 switch (devid) { 875 case AR5212_FPGA: 876 return "Atheros 5212 (FPGA)"; 877 case AR5212_DEVID: 878 case AR5212_DEVID_IBM: 879 case AR5212_DEFAULT: 880 return "Atheros 5212"; 881 case AR5212_AR2413: 882 return "Atheros 2413"; 883 case AR5212_AR2417: 884 return "Atheros 2417"; 885 case AR5212_AR5413: 886 return "Atheros 5413"; 887 case AR5212_AR5424: 888 return "Atheros 5424/2424"; 889 } 890 } 891 return AH_NULL; 892} 893AH_CHIP(AR5212, ar5212Probe, ar5212Attach); 894