ar5212_attach.c revision 217621
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 217621 2011-01-20 05:49:15Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ar5212/ar5212.h" 26#include "ar5212/ar5212reg.h" 27#include "ar5212/ar5212phy.h" 28 29#define AH_5212_COMMON 30#include "ar5212/ar5212.ini" 31 32static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 33static void ar5212DisablePCIE(struct ath_hal *ah); 34 35static const struct ath_hal_private ar5212hal = {{ 36 .ah_magic = AR5212_MAGIC, 37 38 .ah_getRateTable = ar5212GetRateTable, 39 .ah_detach = ar5212Detach, 40 41 /* Reset Functions */ 42 .ah_reset = ar5212Reset, 43 .ah_phyDisable = ar5212PhyDisable, 44 .ah_disable = ar5212Disable, 45 .ah_configPCIE = ar5212ConfigPCIE, 46 .ah_disablePCIE = ar5212DisablePCIE, 47 .ah_setPCUConfig = ar5212SetPCUConfig, 48 .ah_perCalibration = ar5212PerCalibration, 49 .ah_perCalibrationN = ar5212PerCalibrationN, 50 .ah_resetCalValid = ar5212ResetCalValid, 51 .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 52 .ah_getChanNoise = ath_hal_getChanNoise, 53 54 /* Transmit functions */ 55 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 56 .ah_setupTxQueue = ar5212SetupTxQueue, 57 .ah_setTxQueueProps = ar5212SetTxQueueProps, 58 .ah_getTxQueueProps = ar5212GetTxQueueProps, 59 .ah_releaseTxQueue = ar5212ReleaseTxQueue, 60 .ah_resetTxQueue = ar5212ResetTxQueue, 61 .ah_getTxDP = ar5212GetTxDP, 62 .ah_setTxDP = ar5212SetTxDP, 63 .ah_numTxPending = ar5212NumTxPending, 64 .ah_startTxDma = ar5212StartTxDma, 65 .ah_stopTxDma = ar5212StopTxDma, 66 .ah_setupTxDesc = ar5212SetupTxDesc, 67 .ah_setupXTxDesc = ar5212SetupXTxDesc, 68 .ah_fillTxDesc = ar5212FillTxDesc, 69 .ah_procTxDesc = ar5212ProcTxDesc, 70 .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 71 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 72 .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 73 74 /* RX Functions */ 75 .ah_getRxDP = ar5212GetRxDP, 76 .ah_setRxDP = ar5212SetRxDP, 77 .ah_enableReceive = ar5212EnableReceive, 78 .ah_stopDmaReceive = ar5212StopDmaReceive, 79 .ah_startPcuReceive = ar5212StartPcuReceive, 80 .ah_stopPcuReceive = ar5212StopPcuReceive, 81 .ah_setMulticastFilter = ar5212SetMulticastFilter, 82 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 83 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 84 .ah_getRxFilter = ar5212GetRxFilter, 85 .ah_setRxFilter = ar5212SetRxFilter, 86 .ah_setupRxDesc = ar5212SetupRxDesc, 87 .ah_procRxDesc = ar5212ProcRxDesc, 88 .ah_rxMonitor = ar5212AniPoll, 89 .ah_procMibEvent = ar5212ProcessMibIntr, 90 91 /* Misc Functions */ 92 .ah_getCapability = ar5212GetCapability, 93 .ah_setCapability = ar5212SetCapability, 94 .ah_getDiagState = ar5212GetDiagState, 95 .ah_getMacAddress = ar5212GetMacAddress, 96 .ah_setMacAddress = ar5212SetMacAddress, 97 .ah_getBssIdMask = ar5212GetBssIdMask, 98 .ah_setBssIdMask = ar5212SetBssIdMask, 99 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 100 .ah_setLedState = ar5212SetLedState, 101 .ah_writeAssocid = ar5212WriteAssocid, 102 .ah_gpioCfgInput = ar5212GpioCfgInput, 103 .ah_gpioCfgOutput = ar5212GpioCfgOutput, 104 .ah_gpioGet = ar5212GpioGet, 105 .ah_gpioSet = ar5212GpioSet, 106 .ah_gpioSetIntr = ar5212GpioSetIntr, 107 .ah_getTsf32 = ar5212GetTsf32, 108 .ah_getTsf64 = ar5212GetTsf64, 109 .ah_resetTsf = ar5212ResetTsf, 110 .ah_detectCardPresent = ar5212DetectCardPresent, 111 .ah_updateMibCounters = ar5212UpdateMibCounters, 112 .ah_getRfGain = ar5212GetRfgain, 113 .ah_getDefAntenna = ar5212GetDefAntenna, 114 .ah_setDefAntenna = ar5212SetDefAntenna, 115 .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 116 .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 117 .ah_setSifsTime = ar5212SetSifsTime, 118 .ah_getSifsTime = ar5212GetSifsTime, 119 .ah_setSlotTime = ar5212SetSlotTime, 120 .ah_getSlotTime = ar5212GetSlotTime, 121 .ah_setAckTimeout = ar5212SetAckTimeout, 122 .ah_getAckTimeout = ar5212GetAckTimeout, 123 .ah_setAckCTSRate = ar5212SetAckCTSRate, 124 .ah_getAckCTSRate = ar5212GetAckCTSRate, 125 .ah_setCTSTimeout = ar5212SetCTSTimeout, 126 .ah_getCTSTimeout = ar5212GetCTSTimeout, 127 .ah_setDecompMask = ar5212SetDecompMask, 128 .ah_setCoverageClass = ar5212SetCoverageClass, 129 130 /* Key Cache Functions */ 131 .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 132 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 133 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 134 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 135 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 136 137 /* Power Management Functions */ 138 .ah_setPowerMode = ar5212SetPowerMode, 139 .ah_getPowerMode = ar5212GetPowerMode, 140 141 /* Beacon Functions */ 142 .ah_setBeaconTimers = ar5212SetBeaconTimers, 143 .ah_beaconInit = ar5212BeaconInit, 144 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 145 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 146 147 /* Interrupt Functions */ 148 .ah_isInterruptPending = ar5212IsInterruptPending, 149 .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 150 .ah_getInterrupts = ar5212GetInterrupts, 151 .ah_setInterrupts = ar5212SetInterrupts }, 152 153 .ah_getChannelEdges = ar5212GetChannelEdges, 154 .ah_getWirelessModes = ar5212GetWirelessModes, 155 .ah_eepromRead = ar5212EepromRead, 156#ifdef AH_SUPPORT_WRITE_EEPROM 157 .ah_eepromWrite = ar5212EepromWrite, 158#endif 159 .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 160}; 161 162uint32_t 163ar5212GetRadioRev(struct ath_hal *ah) 164{ 165 uint32_t val; 166 int i; 167 168 /* Read Radio Chip Rev Extract */ 169 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 170 for (i = 0; i < 8; i++) 171 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 172 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 173 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 174 return ath_hal_reverseBits(val, 8); 175} 176 177static void 178ar5212AniSetup(struct ath_hal *ah) 179{ 180 static const struct ar5212AniParams aniparams = { 181 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 182 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 183 .coarseHigh = { -14, -14, -14, -14, -12 }, 184 .coarseLow = { -64, -64, -64, -64, -70 }, 185 .firpwr = { -78, -78, -78, -78, -80 }, 186 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 187 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 188 .maxFirstepLevel = 2, /* levels 0..2 */ 189 .firstep = { 0, 4, 8 }, 190 .ofdmTrigHigh = 500, 191 .ofdmTrigLow = 200, 192 .cckTrigHigh = 200, 193 .cckTrigLow = 100, 194 .rssiThrHigh = 40, 195 .rssiThrLow = 7, 196 .period = 100, 197 }; 198 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 199 struct ar5212AniParams tmp; 200 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 201 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 202 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 203 } else 204 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 205} 206 207/* 208 * Attach for an AR5212 part. 209 */ 210void 211ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 212 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 213{ 214#define N(a) (sizeof(a)/sizeof(a[0])) 215 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 216 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 217 struct ath_hal *ah; 218 219 ah = &ahp->ah_priv.h; 220 /* set initial values */ 221 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 222 ah->ah_sc = sc; 223 ah->ah_st = st; 224 ah->ah_sh = sh; 225 226 ah->ah_devid = devid; /* NB: for alq */ 227 AH_PRIVATE(ah)->ah_devid = devid; 228 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 229 230 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 231 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 232 233 ahp->ah_antControl = HAL_ANT_VARIABLE; 234 ahp->ah_diversity = AH_TRUE; 235 ahp->ah_bIQCalibration = AH_FALSE; 236 /* 237 * Enable MIC handling. 238 */ 239 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 240 ahp->ah_rssiThr = INIT_RSSI_THR; 241 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 242 ahp->ah_phyPowerOn = AH_FALSE; 243 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 244 | SM(MAX_RATE_POWER, AR_TPC_CTS) 245 | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 246 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 247 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 248 ahp->ah_slottime = (u_int) -1; 249 ahp->ah_acktimeout = (u_int) -1; 250 ahp->ah_ctstimeout = (u_int) -1; 251 ahp->ah_sifstime = (u_int) -1; 252 ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD, 253 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD, 254 255 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 256#undef N 257} 258 259/* 260 * Validate MAC version and revision. 261 */ 262static HAL_BOOL 263ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 264{ 265#define N(a) (sizeof(a)/sizeof(a[0])) 266 static const struct { 267 uint8_t version; 268 uint8_t revMin, revMax; 269 } macs[] = { 270 { AR_SREV_VERSION_VENICE, 271 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 272 { AR_SREV_VERSION_GRIFFIN, 273 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 274 { AR_SREV_5413, 275 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 276 { AR_SREV_5424, 277 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 278 { AR_SREV_2425, 279 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 280 { AR_SREV_2417, 281 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 282 }; 283 int i; 284 285 for (i = 0; i < N(macs); i++) 286 if (macs[i].version == macVersion && 287 macs[i].revMin <= macRev && macRev <= macs[i].revMax) 288 return AH_TRUE; 289 return AH_FALSE; 290#undef N 291} 292 293/* 294 * Attach for an AR5212 part. 295 */ 296static struct ath_hal * 297ar5212Attach(uint16_t devid, HAL_SOFTC sc, 298 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 299{ 300#define AH_EEPROM_PROTECT(ah) \ 301 (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 302 struct ath_hal_5212 *ahp; 303 struct ath_hal *ah; 304 struct ath_hal_rf *rf; 305 uint32_t val; 306 uint16_t eeval; 307 HAL_STATUS ecode; 308 309 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 310 __func__, sc, (void*) st, (void*) sh); 311 312 /* NB: memory is returned zero'd */ 313 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 314 if (ahp == AH_NULL) { 315 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 316 "%s: cannot allocate memory for state block\n", __func__); 317 *status = HAL_ENOMEM; 318 return AH_NULL; 319 } 320 ar5212InitState(ahp, devid, sc, st, sh, status); 321 ah = &ahp->ah_priv.h; 322 323 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 324 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 325 __func__); 326 ecode = HAL_EIO; 327 goto bad; 328 } 329 /* Read Revisions from Chips before taking out of reset */ 330 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 331 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 332 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 333 AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 334 335 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 336 HALDEBUG(ah, HAL_DEBUG_ANY, 337 "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 338 __func__, AH_PRIVATE(ah)->ah_macVersion, 339 AH_PRIVATE(ah)->ah_macRev); 340 ecode = HAL_ENOTSUPP; 341 goto bad; 342 } 343 344 /* setup common ini data; rf backends handle remainder */ 345 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 346 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 347 348 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 349 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 350 ecode = HAL_EIO; 351 goto bad; 352 } 353 354 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 355 356 if (AH_PRIVATE(ah)->ah_ispcie) { 357 /* XXX: build flag to disable this? */ 358 ath_hal_configPCIE(ah, AH_FALSE); 359 } 360 361 if (!ar5212ChipTest(ah)) { 362 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 363 __func__); 364 ecode = HAL_ESELFTEST; 365 goto bad; 366 } 367 368 /* Enable PCI core retry fix in software for Hainan and up */ 369 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 370 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 371 372 /* 373 * Set correct Baseband to analog shift 374 * setting to access analog chips. 375 */ 376 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 377 378 /* Read Radio Chip Rev Extract */ 379 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 380 381 rf = ath_hal_rfprobe(ah, &ecode); 382 if (rf == AH_NULL) 383 goto bad; 384 385 /* NB: silently accept anything in release code per Atheros */ 386 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 387 case AR_RAD5111_SREV_MAJOR: 388 case AR_RAD5112_SREV_MAJOR: 389 case AR_RAD2112_SREV_MAJOR: 390 case AR_RAD2111_SREV_MAJOR: 391 case AR_RAD2413_SREV_MAJOR: 392 case AR_RAD5413_SREV_MAJOR: 393 case AR_RAD5424_SREV_MAJOR: 394 break; 395 default: 396 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 397 /* 398 * When RF_Silent is used, the 399 * analog chip is reset. So when the system boots 400 * up with the radio switch off we cannot determine 401 * the RF chip rev. To workaround this check the 402 * mac+phy revs and if Hainan, set the radio rev 403 * to Derby. 404 */ 405 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 406 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 407 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 408 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 409 break; 410 } 411 if (IS_2413(ah)) { /* Griffin */ 412 AH_PRIVATE(ah)->ah_analog5GhzRev = 413 AR_RAD2413_SREV_MAJOR | 0x1; 414 break; 415 } 416 if (IS_5413(ah)) { /* Eagle */ 417 AH_PRIVATE(ah)->ah_analog5GhzRev = 418 AR_RAD5413_SREV_MAJOR | 0x2; 419 break; 420 } 421 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 422 AH_PRIVATE(ah)->ah_analog5GhzRev = 423 AR_RAD5424_SREV_MAJOR | 0x2; 424 break; 425 } 426 } 427#ifdef AH_DEBUG 428 HALDEBUG(ah, HAL_DEBUG_ANY, 429 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 430 "this driver\n", 431 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 432 ecode = HAL_ENOTSUPP; 433 goto bad; 434#endif 435 } 436 if (IS_RAD5112_REV1(ah)) { 437 HALDEBUG(ah, HAL_DEBUG_ANY, 438 "%s: 5112 Rev 1 is not supported by this " 439 "driver (analog5GhzRev 0x%x)\n", __func__, 440 AH_PRIVATE(ah)->ah_analog5GhzRev); 441 ecode = HAL_ENOTSUPP; 442 goto bad; 443 } 444 445 val = OS_REG_READ(ah, AR_PCICFG); 446 val = MS(val, AR_PCICFG_EEPROM_SIZE); 447 if (val == 0) { 448 if (!AH_PRIVATE(ah)->ah_ispcie) { 449 HALDEBUG(ah, HAL_DEBUG_ANY, 450 "%s: unsupported EEPROM size %u (0x%x) found\n", 451 __func__, val, val); 452 ecode = HAL_EESIZE; 453 goto bad; 454 } 455 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 456 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 457 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 458 HALDEBUG(ah, HAL_DEBUG_ANY, 459 "%s: unsupported EEPROM size %u (0x%x) found\n", 460 __func__, val, val); 461 ecode = HAL_EESIZE; 462 goto bad; 463 } 464 HALDEBUG(ah, HAL_DEBUG_ANY, 465 "%s: EEPROM size = %d. Must be %d (16k).\n", 466 __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 467 ecode = HAL_EESIZE; 468 goto bad; 469 } 470 ecode = ath_hal_legacyEepromAttach(ah); 471 if (ecode != HAL_OK) { 472 goto bad; 473 } 474 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 475 476 /* 477 * If Bmode and AR5212, verify 2.4 analog exists 478 */ 479 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 480 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 481 /* 482 * Set correct Baseband to analog shift 483 * setting to access analog chips. 484 */ 485 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 486 OS_DELAY(2000); 487 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 488 489 /* Set baseband for 5GHz chip */ 490 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 491 OS_DELAY(2000); 492 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 493 HALDEBUG(ah, HAL_DEBUG_ANY, 494 "%s: 2G Radio Chip Rev 0x%02X is not " 495 "supported by this driver\n", __func__, 496 AH_PRIVATE(ah)->ah_analog2GhzRev); 497 ecode = HAL_ENOTSUPP; 498 goto bad; 499 } 500 } 501 502 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 503 if (ecode != HAL_OK) { 504 HALDEBUG(ah, HAL_DEBUG_ANY, 505 "%s: cannot read regulatory domain from EEPROM\n", 506 __func__); 507 goto bad; 508 } 509 AH_PRIVATE(ah)->ah_currentRD = eeval; 510 /* XXX record serial number */ 511 512 /* 513 * Got everything we need now to setup the capabilities. 514 */ 515 if (!ar5212FillCapabilityInfo(ah)) { 516 HALDEBUG(ah, HAL_DEBUG_ANY, 517 "%s: failed ar5212FillCapabilityInfo\n", __func__); 518 ecode = HAL_EEREAD; 519 goto bad; 520 } 521 522 if (!rf->attach(ah, &ecode)) { 523 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 524 __func__, ecode); 525 goto bad; 526 } 527 /* 528 * Set noise floor adjust method; we arrange a 529 * direct call instead of thunking. 530 */ 531 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 532 533 /* Initialize gain ladder thermal calibration structure */ 534 ar5212InitializeGainValues(ah); 535 536 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 537 if (ecode != HAL_OK) { 538 HALDEBUG(ah, HAL_DEBUG_ANY, 539 "%s: error getting mac address from EEPROM\n", __func__); 540 goto bad; 541 } 542 543 ar5212AniSetup(ah); 544 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 545 ar5212InitNfCalHistBuffer(ah); 546 547 /* XXX EAR stuff goes here */ 548 549 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 550 551 return ah; 552 553bad: 554 if (ahp) 555 ar5212Detach((struct ath_hal *) ahp); 556 if (status) 557 *status = ecode; 558 return AH_NULL; 559#undef AH_EEPROM_PROTECT 560} 561 562void 563ar5212Detach(struct ath_hal *ah) 564{ 565 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 566 567 HALASSERT(ah != AH_NULL); 568 HALASSERT(ah->ah_magic == AR5212_MAGIC); 569 570 ar5212AniDetach(ah); 571 ar5212RfDetach(ah); 572 ar5212Disable(ah); 573 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 574 575 ath_hal_eepromDetach(ah); 576 ath_hal_free(ah); 577} 578 579HAL_BOOL 580ar5212ChipTest(struct ath_hal *ah) 581{ 582 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 583 uint32_t regHold[2]; 584 uint32_t patternData[4] = 585 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 586 int i, j; 587 588 /* Test PHY & MAC registers */ 589 for (i = 0; i < 2; i++) { 590 uint32_t addr = regAddr[i]; 591 uint32_t wrData, rdData; 592 593 regHold[i] = OS_REG_READ(ah, addr); 594 for (j = 0; j < 0x100; j++) { 595 wrData = (j << 16) | j; 596 OS_REG_WRITE(ah, addr, wrData); 597 rdData = OS_REG_READ(ah, addr); 598 if (rdData != wrData) { 599 HALDEBUG(ah, HAL_DEBUG_ANY, 600"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 601 __func__, addr, wrData, rdData); 602 return AH_FALSE; 603 } 604 } 605 for (j = 0; j < 4; j++) { 606 wrData = patternData[j]; 607 OS_REG_WRITE(ah, addr, wrData); 608 rdData = OS_REG_READ(ah, addr); 609 if (wrData != rdData) { 610 HALDEBUG(ah, HAL_DEBUG_ANY, 611"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 612 __func__, addr, wrData, rdData); 613 return AH_FALSE; 614 } 615 } 616 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 617 } 618 OS_DELAY(100); 619 return AH_TRUE; 620} 621 622/* 623 * Store the channel edges for the requested operational mode 624 */ 625HAL_BOOL 626ar5212GetChannelEdges(struct ath_hal *ah, 627 uint16_t flags, uint16_t *low, uint16_t *high) 628{ 629 if (flags & IEEE80211_CHAN_5GHZ) { 630 *low = 4915; 631 *high = 6100; 632 return AH_TRUE; 633 } 634 if ((flags & IEEE80211_CHAN_2GHZ) && 635 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 636 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 637 *low = 2312; 638 *high = 2732; 639 return AH_TRUE; 640 } 641 return AH_FALSE; 642} 643 644/* 645 * Disable PLL when in L0s as well as receiver clock when in L1. 646 * This power saving option must be enabled through the Serdes. 647 * 648 * Programming the Serdes must go through the same 288 bit serial shift 649 * register as the other analog registers. Hence the 9 writes. 650 * 651 * XXX Clean up the magic numbers. 652 */ 653static void 654ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 655{ 656 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 657 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 658 659 /* RX shut off when elecidle is asserted */ 660 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 661 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 662 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 663 664 /* Shut off PLL and CLKREQ active in L1 */ 665 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 666 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 667 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 668 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 669 670 /* Load the new settings */ 671 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 672} 673 674static void 675ar5212DisablePCIE(struct ath_hal *ah) 676{ 677 /* NB: fill in for 9100 */ 678} 679 680/* 681 * Fill all software cached or static hardware state information. 682 * Return failure if capabilities are to come from EEPROM and 683 * cannot be read. 684 */ 685HAL_BOOL 686ar5212FillCapabilityInfo(struct ath_hal *ah) 687{ 688#define AR_KEYTABLE_SIZE 128 689#define IS_GRIFFIN_LITE(ah) \ 690 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 691 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 692#define IS_COBRA(ah) \ 693 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 694#define IS_2112(ah) \ 695 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 696 697 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 698 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 699 uint16_t capField, val; 700 701 /* Read the capability EEPROM location */ 702 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 703 HALDEBUG(ah, HAL_DEBUG_ANY, 704 "%s: unable to read caps from eeprom\n", __func__); 705 return AH_FALSE; 706 } 707 if (IS_2112(ah)) 708 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 709 if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 710 /* 711 * For griffin-lite cards with unprogrammed capabilities. 712 */ 713 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 714 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 715 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 716 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 717 HALDEBUG(ah, HAL_DEBUG_ATTACH, 718 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 719 __func__, capField); 720 } 721 722 /* Modify reg domain on newer cards that need to work with older sw */ 723 if (ahpriv->ah_opmode != HAL_M_HOSTAP && 724 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 725 if (ahpriv->ah_currentRD == 0x64 || 726 ahpriv->ah_currentRD == 0x65) 727 ahpriv->ah_currentRD += 5; 728 else if (ahpriv->ah_currentRD == 0x41) 729 ahpriv->ah_currentRD = 0x43; 730 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 731 __func__, ahpriv->ah_currentRD); 732 } 733 734 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 735 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 736 HALDEBUG(ah, HAL_DEBUG_ATTACH, 737 "%s: enable Bmode and disable turbo for Swan/Nala\n", 738 __func__); 739 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 740 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 741 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 742 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 743 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 744 } 745 746 /* Construct wireless mode from EEPROM */ 747 pCap->halWirelessModes = 0; 748 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 749 pCap->halWirelessModes |= HAL_MODE_11A; 750 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 751 pCap->halWirelessModes |= HAL_MODE_TURBO; 752 } 753 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 754 pCap->halWirelessModes |= HAL_MODE_11B; 755 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 756 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 757 pCap->halWirelessModes |= HAL_MODE_11G; 758 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 759 pCap->halWirelessModes |= HAL_MODE_108G; 760 } 761 762 pCap->halLow2GhzChan = 2312; 763 /* XXX 2417 too? */ 764 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 765 pCap->halHigh2GhzChan = 2500; 766 else 767 pCap->halHigh2GhzChan = 2732; 768 769 pCap->halLow5GhzChan = 4915; 770 pCap->halHigh5GhzChan = 6100; 771 772 pCap->halCipherCkipSupport = AH_FALSE; 773 pCap->halCipherTkipSupport = AH_TRUE; 774 pCap->halCipherAesCcmSupport = 775 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 776 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 777 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 778 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 779 780 pCap->halMicCkipSupport = AH_FALSE; 781 pCap->halMicTkipSupport = AH_TRUE; 782 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 783 /* 784 * Starting with Griffin TX+RX mic keys can be combined 785 * in one key cache slot. 786 */ 787 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 788 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 789 else 790 pCap->halTkipMicTxRxKeySupport = AH_FALSE; 791 pCap->halChanSpreadSupport = AH_TRUE; 792 pCap->halSleepAfterBeaconBroken = AH_TRUE; 793 794 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 795 pCap->halCompressSupport = 796 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 797 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 798 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 799 pCap->halFastFramesSupport = 800 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 801 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 802 pCap->halChapTuningSupport = AH_TRUE; 803 pCap->halTurboPrimeSupport = AH_TRUE; 804 } 805 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 806 807 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 808 pCap->halVEOLSupport = AH_TRUE; 809 pCap->halBssIdMaskSupport = AH_TRUE; 810 pCap->halMcastKeySrchSupport = AH_TRUE; 811 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 812 ahpriv->ah_macRev == 8) || 813 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 814 pCap->halTsfAddSupport = AH_TRUE; 815 816 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 817 pCap->halTotalQueues = val; 818 else 819 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 820 821 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 822 pCap->halKeyCacheSize = val; 823 else 824 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 825 826 pCap->halChanHalfRate = AH_TRUE; 827 pCap->halChanQuarterRate = AH_TRUE; 828 829 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 830 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 831 /* NB: enabled by default */ 832 ahpriv->ah_rfkillEnabled = AH_TRUE; 833 pCap->halRfSilentSupport = AH_TRUE; 834 } 835 836 /* NB: this is a guess, noone seems to know the answer */ 837 ahpriv->ah_rxornIsFatal = 838 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 839 840 /* enable features that first appeared in Hainan */ 841 if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 842 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 843 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 844 /* h/w phy counters */ 845 pCap->halHwPhyCounterSupport = AH_TRUE; 846 /* bssid match disable */ 847 pCap->halBssidMatchSupport = AH_TRUE; 848 } 849 850 pCap->halTstampPrecision = 15; 851 pCap->halIntrMask = HAL_INT_COMMON 852 | HAL_INT_RX 853 | HAL_INT_TX 854 | HAL_INT_FATAL 855 | HAL_INT_BNR 856 | HAL_INT_BMISC 857 ; 858 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 859 pCap->halIntrMask &= ~HAL_INT_TBTT; 860 861 return AH_TRUE; 862#undef IS_COBRA 863#undef IS_GRIFFIN_LITE 864#undef AR_KEYTABLE_SIZE 865} 866 867static const char* 868ar5212Probe(uint16_t vendorid, uint16_t devid) 869{ 870 if (vendorid == ATHEROS_VENDOR_ID || 871 vendorid == ATHEROS_3COM_VENDOR_ID || 872 vendorid == ATHEROS_3COM2_VENDOR_ID) { 873 switch (devid) { 874 case AR5212_FPGA: 875 return "Atheros 5212 (FPGA)"; 876 case AR5212_DEVID: 877 case AR5212_DEVID_IBM: 878 case AR5212_DEFAULT: 879 return "Atheros 5212"; 880 case AR5212_AR2413: 881 return "Atheros 2413"; 882 case AR5212_AR2417: 883 return "Atheros 2417"; 884 case AR5212_AR5413: 885 return "Atheros 5413"; 886 case AR5212_AR5424: 887 return "Atheros 5424/2424"; 888 } 889 } 890 return AH_NULL; 891} 892AH_CHIP(AR5212, ar5212Probe, ar5212Attach); 893