ar5212_attach.c revision 195114
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 195114 2009-06-27 20:06:56Z sam $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ar5212/ar5212.h" 26#include "ar5212/ar5212reg.h" 27#include "ar5212/ar5212phy.h" 28 29#define AH_5212_COMMON 30#include "ar5212/ar5212.ini" 31 32static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 33static void ar5212DisablePCIE(struct ath_hal *ah); 34 35static const struct ath_hal_private ar5212hal = {{ 36 .ah_magic = AR5212_MAGIC, 37 38 .ah_getRateTable = ar5212GetRateTable, 39 .ah_detach = ar5212Detach, 40 41 /* Reset Functions */ 42 .ah_reset = ar5212Reset, 43 .ah_phyDisable = ar5212PhyDisable, 44 .ah_disable = ar5212Disable, 45 .ah_configPCIE = ar5212ConfigPCIE, 46 .ah_disablePCIE = ar5212DisablePCIE, 47 .ah_setPCUConfig = ar5212SetPCUConfig, 48 .ah_perCalibration = ar5212PerCalibration, 49 .ah_perCalibrationN = ar5212PerCalibrationN, 50 .ah_resetCalValid = ar5212ResetCalValid, 51 .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 52 .ah_getChanNoise = ath_hal_getChanNoise, 53 54 /* Transmit functions */ 55 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 56 .ah_setupTxQueue = ar5212SetupTxQueue, 57 .ah_setTxQueueProps = ar5212SetTxQueueProps, 58 .ah_getTxQueueProps = ar5212GetTxQueueProps, 59 .ah_releaseTxQueue = ar5212ReleaseTxQueue, 60 .ah_resetTxQueue = ar5212ResetTxQueue, 61 .ah_getTxDP = ar5212GetTxDP, 62 .ah_setTxDP = ar5212SetTxDP, 63 .ah_numTxPending = ar5212NumTxPending, 64 .ah_startTxDma = ar5212StartTxDma, 65 .ah_stopTxDma = ar5212StopTxDma, 66 .ah_setupTxDesc = ar5212SetupTxDesc, 67 .ah_setupXTxDesc = ar5212SetupXTxDesc, 68 .ah_fillTxDesc = ar5212FillTxDesc, 69 .ah_procTxDesc = ar5212ProcTxDesc, 70 .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 71 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 72 73 /* RX Functions */ 74 .ah_getRxDP = ar5212GetRxDP, 75 .ah_setRxDP = ar5212SetRxDP, 76 .ah_enableReceive = ar5212EnableReceive, 77 .ah_stopDmaReceive = ar5212StopDmaReceive, 78 .ah_startPcuReceive = ar5212StartPcuReceive, 79 .ah_stopPcuReceive = ar5212StopPcuReceive, 80 .ah_setMulticastFilter = ar5212SetMulticastFilter, 81 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 82 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 83 .ah_getRxFilter = ar5212GetRxFilter, 84 .ah_setRxFilter = ar5212SetRxFilter, 85 .ah_setupRxDesc = ar5212SetupRxDesc, 86 .ah_procRxDesc = ar5212ProcRxDesc, 87 .ah_rxMonitor = ar5212AniPoll, 88 .ah_procMibEvent = ar5212ProcessMibIntr, 89 90 /* Misc Functions */ 91 .ah_getCapability = ar5212GetCapability, 92 .ah_setCapability = ar5212SetCapability, 93 .ah_getDiagState = ar5212GetDiagState, 94 .ah_getMacAddress = ar5212GetMacAddress, 95 .ah_setMacAddress = ar5212SetMacAddress, 96 .ah_getBssIdMask = ar5212GetBssIdMask, 97 .ah_setBssIdMask = ar5212SetBssIdMask, 98 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 99 .ah_setLedState = ar5212SetLedState, 100 .ah_writeAssocid = ar5212WriteAssocid, 101 .ah_gpioCfgInput = ar5212GpioCfgInput, 102 .ah_gpioCfgOutput = ar5212GpioCfgOutput, 103 .ah_gpioGet = ar5212GpioGet, 104 .ah_gpioSet = ar5212GpioSet, 105 .ah_gpioSetIntr = ar5212GpioSetIntr, 106 .ah_getTsf32 = ar5212GetTsf32, 107 .ah_getTsf64 = ar5212GetTsf64, 108 .ah_resetTsf = ar5212ResetTsf, 109 .ah_detectCardPresent = ar5212DetectCardPresent, 110 .ah_updateMibCounters = ar5212UpdateMibCounters, 111 .ah_getRfGain = ar5212GetRfgain, 112 .ah_getDefAntenna = ar5212GetDefAntenna, 113 .ah_setDefAntenna = ar5212SetDefAntenna, 114 .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 115 .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 116 .ah_setSifsTime = ar5212SetSifsTime, 117 .ah_getSifsTime = ar5212GetSifsTime, 118 .ah_setSlotTime = ar5212SetSlotTime, 119 .ah_getSlotTime = ar5212GetSlotTime, 120 .ah_setAckTimeout = ar5212SetAckTimeout, 121 .ah_getAckTimeout = ar5212GetAckTimeout, 122 .ah_setAckCTSRate = ar5212SetAckCTSRate, 123 .ah_getAckCTSRate = ar5212GetAckCTSRate, 124 .ah_setCTSTimeout = ar5212SetCTSTimeout, 125 .ah_getCTSTimeout = ar5212GetCTSTimeout, 126 .ah_setDecompMask = ar5212SetDecompMask, 127 .ah_setCoverageClass = ar5212SetCoverageClass, 128 129 /* Key Cache Functions */ 130 .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 131 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 132 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 133 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 134 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 135 136 /* Power Management Functions */ 137 .ah_setPowerMode = ar5212SetPowerMode, 138 .ah_getPowerMode = ar5212GetPowerMode, 139 140 /* Beacon Functions */ 141 .ah_setBeaconTimers = ar5212SetBeaconTimers, 142 .ah_beaconInit = ar5212BeaconInit, 143 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 144 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 145 146 /* Interrupt Functions */ 147 .ah_isInterruptPending = ar5212IsInterruptPending, 148 .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 149 .ah_getInterrupts = ar5212GetInterrupts, 150 .ah_setInterrupts = ar5212SetInterrupts }, 151 152 .ah_getChannelEdges = ar5212GetChannelEdges, 153 .ah_getWirelessModes = ar5212GetWirelessModes, 154 .ah_eepromRead = ar5212EepromRead, 155#ifdef AH_SUPPORT_WRITE_EEPROM 156 .ah_eepromWrite = ar5212EepromWrite, 157#endif 158 .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 159}; 160 161uint32_t 162ar5212GetRadioRev(struct ath_hal *ah) 163{ 164 uint32_t val; 165 int i; 166 167 /* Read Radio Chip Rev Extract */ 168 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 169 for (i = 0; i < 8; i++) 170 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 171 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 172 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 173 return ath_hal_reverseBits(val, 8); 174} 175 176static void 177ar5212AniSetup(struct ath_hal *ah) 178{ 179 static const struct ar5212AniParams aniparams = { 180 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 181 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 182 .coarseHigh = { -14, -14, -14, -14, -12 }, 183 .coarseLow = { -64, -64, -64, -64, -70 }, 184 .firpwr = { -78, -78, -78, -78, -80 }, 185 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 186 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 187 .maxFirstepLevel = 2, /* levels 0..2 */ 188 .firstep = { 0, 4, 8 }, 189 .ofdmTrigHigh = 500, 190 .ofdmTrigLow = 200, 191 .cckTrigHigh = 200, 192 .cckTrigLow = 100, 193 .rssiThrHigh = 40, 194 .rssiThrLow = 7, 195 .period = 100, 196 }; 197 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 198 struct ar5212AniParams tmp; 199 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 200 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 201 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 202 } else 203 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 204} 205 206/* 207 * Attach for an AR5212 part. 208 */ 209void 210ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 211 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 212{ 213#define N(a) (sizeof(a)/sizeof(a[0])) 214 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 215 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 216 struct ath_hal *ah; 217 218 ah = &ahp->ah_priv.h; 219 /* set initial values */ 220 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 221 ah->ah_sc = sc; 222 ah->ah_st = st; 223 ah->ah_sh = sh; 224 225 ah->ah_devid = devid; /* NB: for alq */ 226 AH_PRIVATE(ah)->ah_devid = devid; 227 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 228 229 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 230 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 231 232 ahp->ah_antControl = HAL_ANT_VARIABLE; 233 ahp->ah_diversity = AH_TRUE; 234 ahp->ah_bIQCalibration = AH_FALSE; 235 /* 236 * Enable MIC handling. 237 */ 238 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 239 ahp->ah_rssiThr = INIT_RSSI_THR; 240 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 241 ahp->ah_phyPowerOn = AH_FALSE; 242 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 243 | SM(MAX_RATE_POWER, AR_TPC_CTS) 244 | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 245 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 246 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 247 ahp->ah_slottime = (u_int) -1; 248 ahp->ah_acktimeout = (u_int) -1; 249 ahp->ah_ctstimeout = (u_int) -1; 250 ahp->ah_sifstime = (u_int) -1; 251 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 252#undef N 253} 254 255/* 256 * Validate MAC version and revision. 257 */ 258static HAL_BOOL 259ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 260{ 261#define N(a) (sizeof(a)/sizeof(a[0])) 262 static const struct { 263 uint8_t version; 264 uint8_t revMin, revMax; 265 } macs[] = { 266 { AR_SREV_VERSION_VENICE, 267 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 268 { AR_SREV_VERSION_GRIFFIN, 269 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 270 { AR_SREV_5413, 271 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 272 { AR_SREV_5424, 273 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 274 { AR_SREV_2425, 275 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 276 { AR_SREV_2417, 277 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 278 }; 279 int i; 280 281 for (i = 0; i < N(macs); i++) 282 if (macs[i].version == macVersion && 283 macs[i].revMin <= macRev && macRev <= macs[i].revMax) 284 return AH_TRUE; 285 return AH_FALSE; 286#undef N 287} 288 289/* 290 * Attach for an AR5212 part. 291 */ 292static struct ath_hal * 293ar5212Attach(uint16_t devid, HAL_SOFTC sc, 294 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 295{ 296#define AH_EEPROM_PROTECT(ah) \ 297 (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 298 struct ath_hal_5212 *ahp; 299 struct ath_hal *ah; 300 struct ath_hal_rf *rf; 301 uint32_t val; 302 uint16_t eeval; 303 HAL_STATUS ecode; 304 305 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 306 __func__, sc, (void*) st, (void*) sh); 307 308 /* NB: memory is returned zero'd */ 309 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 310 if (ahp == AH_NULL) { 311 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 312 "%s: cannot allocate memory for state block\n", __func__); 313 *status = HAL_ENOMEM; 314 return AH_NULL; 315 } 316 ar5212InitState(ahp, devid, sc, st, sh, status); 317 ah = &ahp->ah_priv.h; 318 319 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 320 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 321 __func__); 322 ecode = HAL_EIO; 323 goto bad; 324 } 325 /* Read Revisions from Chips before taking out of reset */ 326 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 327 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 328 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 329 AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 330 331 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 332 HALDEBUG(ah, HAL_DEBUG_ANY, 333 "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 334 __func__, AH_PRIVATE(ah)->ah_macVersion, 335 AH_PRIVATE(ah)->ah_macRev); 336 ecode = HAL_ENOTSUPP; 337 goto bad; 338 } 339 340 /* setup common ini data; rf backends handle remainder */ 341 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 342 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 343 344 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 345 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 346 ecode = HAL_EIO; 347 goto bad; 348 } 349 350 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 351 352 if (AH_PRIVATE(ah)->ah_ispcie) { 353 /* XXX: build flag to disable this? */ 354 ath_hal_configPCIE(ah, AH_FALSE); 355 } 356 357 if (!ar5212ChipTest(ah)) { 358 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 359 __func__); 360 ecode = HAL_ESELFTEST; 361 goto bad; 362 } 363 364 /* Enable PCI core retry fix in software for Hainan and up */ 365 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 366 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 367 368 /* 369 * Set correct Baseband to analog shift 370 * setting to access analog chips. 371 */ 372 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 373 374 /* Read Radio Chip Rev Extract */ 375 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 376 377 rf = ath_hal_rfprobe(ah, &ecode); 378 if (rf == AH_NULL) 379 goto bad; 380 381 /* NB: silently accept anything in release code per Atheros */ 382 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 383 case AR_RAD5111_SREV_MAJOR: 384 case AR_RAD5112_SREV_MAJOR: 385 case AR_RAD2112_SREV_MAJOR: 386 case AR_RAD2111_SREV_MAJOR: 387 case AR_RAD2413_SREV_MAJOR: 388 case AR_RAD5413_SREV_MAJOR: 389 case AR_RAD5424_SREV_MAJOR: 390 break; 391 default: 392 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 393 /* 394 * When RF_Silent is used, the 395 * analog chip is reset. So when the system boots 396 * up with the radio switch off we cannot determine 397 * the RF chip rev. To workaround this check the 398 * mac+phy revs and if Hainan, set the radio rev 399 * to Derby. 400 */ 401 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 402 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 403 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 404 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 405 break; 406 } 407 if (IS_2413(ah)) { /* Griffin */ 408 AH_PRIVATE(ah)->ah_analog5GhzRev = 409 AR_RAD2413_SREV_MAJOR | 0x1; 410 break; 411 } 412 if (IS_5413(ah)) { /* Eagle */ 413 AH_PRIVATE(ah)->ah_analog5GhzRev = 414 AR_RAD5413_SREV_MAJOR | 0x2; 415 break; 416 } 417 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 418 AH_PRIVATE(ah)->ah_analog5GhzRev = 419 AR_RAD5424_SREV_MAJOR | 0x2; 420 break; 421 } 422 } 423#ifdef AH_DEBUG 424 HALDEBUG(ah, HAL_DEBUG_ANY, 425 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 426 "this driver\n", 427 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 428 ecode = HAL_ENOTSUPP; 429 goto bad; 430#endif 431 } 432 if (IS_RAD5112_REV1(ah)) { 433 HALDEBUG(ah, HAL_DEBUG_ANY, 434 "%s: 5112 Rev 1 is not supported by this " 435 "driver (analog5GhzRev 0x%x)\n", __func__, 436 AH_PRIVATE(ah)->ah_analog5GhzRev); 437 ecode = HAL_ENOTSUPP; 438 goto bad; 439 } 440 441 val = OS_REG_READ(ah, AR_PCICFG); 442 val = MS(val, AR_PCICFG_EEPROM_SIZE); 443 if (val == 0) { 444 if (!AH_PRIVATE(ah)->ah_ispcie) { 445 HALDEBUG(ah, HAL_DEBUG_ANY, 446 "%s: unsupported EEPROM size %u (0x%x) found\n", 447 __func__, val, val); 448 ecode = HAL_EESIZE; 449 goto bad; 450 } 451 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 452 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 453 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 454 HALDEBUG(ah, HAL_DEBUG_ANY, 455 "%s: unsupported EEPROM size %u (0x%x) found\n", 456 __func__, val, val); 457 ecode = HAL_EESIZE; 458 goto bad; 459 } 460 HALDEBUG(ah, HAL_DEBUG_ANY, 461 "%s: EEPROM size = %d. Must be %d (16k).\n", 462 __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 463 ecode = HAL_EESIZE; 464 goto bad; 465 } 466 ecode = ath_hal_legacyEepromAttach(ah); 467 if (ecode != HAL_OK) { 468 goto bad; 469 } 470 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 471 472 /* 473 * If Bmode and AR5212, verify 2.4 analog exists 474 */ 475 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 476 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 477 /* 478 * Set correct Baseband to analog shift 479 * setting to access analog chips. 480 */ 481 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 482 OS_DELAY(2000); 483 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 484 485 /* Set baseband for 5GHz chip */ 486 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 487 OS_DELAY(2000); 488 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 489 HALDEBUG(ah, HAL_DEBUG_ANY, 490 "%s: 2G Radio Chip Rev 0x%02X is not " 491 "supported by this driver\n", __func__, 492 AH_PRIVATE(ah)->ah_analog2GhzRev); 493 ecode = HAL_ENOTSUPP; 494 goto bad; 495 } 496 } 497 498 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 499 if (ecode != HAL_OK) { 500 HALDEBUG(ah, HAL_DEBUG_ANY, 501 "%s: cannot read regulatory domain from EEPROM\n", 502 __func__); 503 goto bad; 504 } 505 AH_PRIVATE(ah)->ah_currentRD = eeval; 506 /* XXX record serial number */ 507 508 /* 509 * Got everything we need now to setup the capabilities. 510 */ 511 if (!ar5212FillCapabilityInfo(ah)) { 512 HALDEBUG(ah, HAL_DEBUG_ANY, 513 "%s: failed ar5212FillCapabilityInfo\n", __func__); 514 ecode = HAL_EEREAD; 515 goto bad; 516 } 517 518 if (!rf->attach(ah, &ecode)) { 519 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 520 __func__, ecode); 521 goto bad; 522 } 523 /* 524 * Set noise floor adjust method; we arrange a 525 * direct call instead of thunking. 526 */ 527 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 528 529 /* Initialize gain ladder thermal calibration structure */ 530 ar5212InitializeGainValues(ah); 531 532 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 533 if (ecode != HAL_OK) { 534 HALDEBUG(ah, HAL_DEBUG_ANY, 535 "%s: error getting mac address from EEPROM\n", __func__); 536 goto bad; 537 } 538 539 ar5212AniSetup(ah); 540 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 541 ar5212InitNfCalHistBuffer(ah); 542 543 /* XXX EAR stuff goes here */ 544 545 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 546 547 return ah; 548 549bad: 550 if (ahp) 551 ar5212Detach((struct ath_hal *) ahp); 552 if (status) 553 *status = ecode; 554 return AH_NULL; 555#undef AH_EEPROM_PROTECT 556} 557 558void 559ar5212Detach(struct ath_hal *ah) 560{ 561 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 562 563 HALASSERT(ah != AH_NULL); 564 HALASSERT(ah->ah_magic == AR5212_MAGIC); 565 566 ar5212AniDetach(ah); 567 ar5212RfDetach(ah); 568 ar5212Disable(ah); 569 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 570 571 ath_hal_eepromDetach(ah); 572 ath_hal_free(ah); 573} 574 575HAL_BOOL 576ar5212ChipTest(struct ath_hal *ah) 577{ 578 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 579 uint32_t regHold[2]; 580 uint32_t patternData[4] = 581 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 582 int i, j; 583 584 /* Test PHY & MAC registers */ 585 for (i = 0; i < 2; i++) { 586 uint32_t addr = regAddr[i]; 587 uint32_t wrData, rdData; 588 589 regHold[i] = OS_REG_READ(ah, addr); 590 for (j = 0; j < 0x100; j++) { 591 wrData = (j << 16) | j; 592 OS_REG_WRITE(ah, addr, wrData); 593 rdData = OS_REG_READ(ah, addr); 594 if (rdData != wrData) { 595 HALDEBUG(ah, HAL_DEBUG_ANY, 596"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 597 __func__, addr, wrData, rdData); 598 return AH_FALSE; 599 } 600 } 601 for (j = 0; j < 4; j++) { 602 wrData = patternData[j]; 603 OS_REG_WRITE(ah, addr, wrData); 604 rdData = OS_REG_READ(ah, addr); 605 if (wrData != rdData) { 606 HALDEBUG(ah, HAL_DEBUG_ANY, 607"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 608 __func__, addr, wrData, rdData); 609 return AH_FALSE; 610 } 611 } 612 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 613 } 614 OS_DELAY(100); 615 return AH_TRUE; 616} 617 618/* 619 * Store the channel edges for the requested operational mode 620 */ 621HAL_BOOL 622ar5212GetChannelEdges(struct ath_hal *ah, 623 uint16_t flags, uint16_t *low, uint16_t *high) 624{ 625 if (flags & IEEE80211_CHAN_5GHZ) { 626 *low = 4915; 627 *high = 6100; 628 return AH_TRUE; 629 } 630 if ((flags & IEEE80211_CHAN_2GHZ) && 631 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 632 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 633 *low = 2312; 634 *high = 2732; 635 return AH_TRUE; 636 } 637 return AH_FALSE; 638} 639 640/* 641 * Disable PLL when in L0s as well as receiver clock when in L1. 642 * This power saving option must be enabled through the Serdes. 643 * 644 * Programming the Serdes must go through the same 288 bit serial shift 645 * register as the other analog registers. Hence the 9 writes. 646 * 647 * XXX Clean up the magic numbers. 648 */ 649static void 650ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 651{ 652 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 653 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 654 655 /* RX shut off when elecidle is asserted */ 656 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 657 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 658 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 659 660 /* Shut off PLL and CLKREQ active in L1 */ 661 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 662 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 663 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 664 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 665 666 /* Load the new settings */ 667 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 668} 669 670static void 671ar5212DisablePCIE(struct ath_hal *ah) 672{ 673 /* NB: fill in for 9100 */ 674} 675 676/* 677 * Fill all software cached or static hardware state information. 678 * Return failure if capabilities are to come from EEPROM and 679 * cannot be read. 680 */ 681HAL_BOOL 682ar5212FillCapabilityInfo(struct ath_hal *ah) 683{ 684#define AR_KEYTABLE_SIZE 128 685#define IS_GRIFFIN_LITE(ah) \ 686 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 687 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 688#define IS_COBRA(ah) \ 689 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 690#define IS_2112(ah) \ 691 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 692 693 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 694 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 695 uint16_t capField, val; 696 697 /* Read the capability EEPROM location */ 698 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 699 HALDEBUG(ah, HAL_DEBUG_ANY, 700 "%s: unable to read caps from eeprom\n", __func__); 701 return AH_FALSE; 702 } 703 if (IS_2112(ah)) 704 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 705 if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 706 /* 707 * For griffin-lite cards with unprogrammed capabilities. 708 */ 709 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 710 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 711 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 712 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 713 HALDEBUG(ah, HAL_DEBUG_ATTACH, 714 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 715 __func__, capField); 716 } 717 718 /* Modify reg domain on newer cards that need to work with older sw */ 719 if (ahpriv->ah_opmode != HAL_M_HOSTAP && 720 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 721 if (ahpriv->ah_currentRD == 0x64 || 722 ahpriv->ah_currentRD == 0x65) 723 ahpriv->ah_currentRD += 5; 724 else if (ahpriv->ah_currentRD == 0x41) 725 ahpriv->ah_currentRD = 0x43; 726 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 727 __func__, ahpriv->ah_currentRD); 728 } 729 730 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 731 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 732 HALDEBUG(ah, HAL_DEBUG_ATTACH, 733 "%s: enable Bmode and disable turbo for Swan/Nala\n", 734 __func__); 735 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 736 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 737 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 738 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 739 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 740 } 741 742 /* Construct wireless mode from EEPROM */ 743 pCap->halWirelessModes = 0; 744 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 745 pCap->halWirelessModes |= HAL_MODE_11A; 746 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 747 pCap->halWirelessModes |= HAL_MODE_TURBO; 748 } 749 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 750 pCap->halWirelessModes |= HAL_MODE_11B; 751 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 752 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 753 pCap->halWirelessModes |= HAL_MODE_11G; 754 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 755 pCap->halWirelessModes |= HAL_MODE_108G; 756 } 757 758 pCap->halLow2GhzChan = 2312; 759 /* XXX 2417 too? */ 760 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 761 pCap->halHigh2GhzChan = 2500; 762 else 763 pCap->halHigh2GhzChan = 2732; 764 765 pCap->halLow5GhzChan = 4915; 766 pCap->halHigh5GhzChan = 6100; 767 768 pCap->halCipherCkipSupport = AH_FALSE; 769 pCap->halCipherTkipSupport = AH_TRUE; 770 pCap->halCipherAesCcmSupport = 771 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 772 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 773 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 774 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 775 776 pCap->halMicCkipSupport = AH_FALSE; 777 pCap->halMicTkipSupport = AH_TRUE; 778 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 779 /* 780 * Starting with Griffin TX+RX mic keys can be combined 781 * in one key cache slot. 782 */ 783 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 784 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 785 else 786 pCap->halTkipMicTxRxKeySupport = AH_FALSE; 787 pCap->halChanSpreadSupport = AH_TRUE; 788 pCap->halSleepAfterBeaconBroken = AH_TRUE; 789 790 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 791 pCap->halCompressSupport = 792 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 793 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 794 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 795 pCap->halFastFramesSupport = 796 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 797 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 798 pCap->halChapTuningSupport = AH_TRUE; 799 pCap->halTurboPrimeSupport = AH_TRUE; 800 } 801 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 802 803 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 804 pCap->halVEOLSupport = AH_TRUE; 805 pCap->halBssIdMaskSupport = AH_TRUE; 806 pCap->halMcastKeySrchSupport = AH_TRUE; 807 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 808 ahpriv->ah_macRev == 8) || 809 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 810 pCap->halTsfAddSupport = AH_TRUE; 811 812 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 813 pCap->halTotalQueues = val; 814 else 815 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 816 817 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 818 pCap->halKeyCacheSize = val; 819 else 820 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 821 822 pCap->halChanHalfRate = AH_TRUE; 823 pCap->halChanQuarterRate = AH_TRUE; 824 825 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 826 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 827 /* NB: enabled by default */ 828 ahpriv->ah_rfkillEnabled = AH_TRUE; 829 pCap->halRfSilentSupport = AH_TRUE; 830 } 831 832 /* NB: this is a guess, noone seems to know the answer */ 833 ahpriv->ah_rxornIsFatal = 834 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 835 836 /* enable features that first appeared in Hainan */ 837 if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 838 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 839 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 840 /* h/w phy counters */ 841 pCap->halHwPhyCounterSupport = AH_TRUE; 842 /* bssid match disable */ 843 pCap->halBssidMatchSupport = AH_TRUE; 844 } 845 846 pCap->halTstampPrecision = 15; 847 pCap->halIntrMask = HAL_INT_COMMON 848 | HAL_INT_RX 849 | HAL_INT_TX 850 | HAL_INT_FATAL 851 | HAL_INT_BNR 852 | HAL_INT_BMISC 853 ; 854 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 855 pCap->halIntrMask &= ~HAL_INT_TBTT; 856 857 return AH_TRUE; 858#undef IS_COBRA 859#undef IS_GRIFFIN_LITE 860#undef AR_KEYTABLE_SIZE 861} 862 863static const char* 864ar5212Probe(uint16_t vendorid, uint16_t devid) 865{ 866 if (vendorid == ATHEROS_VENDOR_ID || 867 vendorid == ATHEROS_3COM_VENDOR_ID || 868 vendorid == ATHEROS_3COM2_VENDOR_ID) { 869 switch (devid) { 870 case AR5212_FPGA: 871 return "Atheros 5212 (FPGA)"; 872 case AR5212_DEVID: 873 case AR5212_DEVID_IBM: 874 case AR5212_DEFAULT: 875 return "Atheros 5212"; 876 case AR5212_AR2413: 877 return "Atheros 2413"; 878 case AR5212_AR2417: 879 return "Atheros 2417"; 880 case AR5212_AR5413: 881 return "Atheros 5413"; 882 case AR5212_AR5424: 883 return "Atheros 5424/2424"; 884 } 885 } 886 return AH_NULL; 887} 888AH_CHIP(AR5212, ar5212Probe, ar5212Attach); 889