1219394Sadrian/* 2219394Sadrian * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3219394Sadrian * Copyright (c) 2005-2006 Atheros Communications, Inc. 4219394Sadrian * All rights reserved. 5219394Sadrian * 6219394Sadrian * Permission to use, copy, modify, and/or distribute this software for any 7219394Sadrian * purpose with or without fee is hereby granted, provided that the above 8219394Sadrian * copyright notice and this permission notice appear in all copies. 9219394Sadrian * 10219394Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11219394Sadrian * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12219394Sadrian * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13219394Sadrian * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14219394Sadrian * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15219394Sadrian * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16219394Sadrian * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17219394Sadrian * 18219394Sadrian * $FreeBSD$ 19219394Sadrian */ 20219394Sadrian#ifndef __AH_REGDOMAIN_H__ 21219394Sadrian#define __AH_REGDOMAIN_H__ 22219394Sadrian 23219394Sadrian/* 24219394Sadrian * BMLEN defines the size of the bitmask used to hold frequency 25219394Sadrian * band specifications. Note this must agree with the BM macro 26219394Sadrian * definition that's used to setup initializers. See also further 27219394Sadrian * comments below. 28219394Sadrian */ 29219394Sadrian#define BMLEN 2 /* 2 x 64 bits in each channel bitmask */ 30219394Sadriantypedef uint64_t chanbmask_t[BMLEN]; 31219394Sadrian 32219394Sadrian/* 33219442Sadrian * The following describe the bit masks for different passive scan 34219442Sadrian * capability/requirements per regdomain. 35219442Sadrian */ 36219442Sadrian#define NO_PSCAN 0x0ULL /* NB: must be zero */ 37219442Sadrian#define PSCAN_FCC 0x0000000000000001ULL 38219442Sadrian#define PSCAN_FCC_T 0x0000000000000002ULL 39219442Sadrian#define PSCAN_ETSI 0x0000000000000004ULL 40219442Sadrian#define PSCAN_MKK1 0x0000000000000008ULL 41219442Sadrian#define PSCAN_MKK2 0x0000000000000010ULL 42219442Sadrian#define PSCAN_MKKA 0x0000000000000020ULL 43219442Sadrian#define PSCAN_MKKA_G 0x0000000000000040ULL 44219442Sadrian#define PSCAN_ETSIA 0x0000000000000080ULL 45219442Sadrian#define PSCAN_ETSIB 0x0000000000000100ULL 46219442Sadrian#define PSCAN_ETSIC 0x0000000000000200ULL 47219442Sadrian#define PSCAN_WWR 0x0000000000000400ULL 48219442Sadrian#define PSCAN_MKKA1 0x0000000000000800ULL 49219442Sadrian#define PSCAN_MKKA1_G 0x0000000000001000ULL 50219442Sadrian#define PSCAN_MKKA2 0x0000000000002000ULL 51219442Sadrian#define PSCAN_MKKA2_G 0x0000000000004000ULL 52219442Sadrian#define PSCAN_MKK3 0x0000000000008000ULL 53219442Sadrian#define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL 54219442Sadrian#define IS_ECM_CHAN 0x8000000000000000ULL 55219442Sadrian 56219442Sadrian/* 57219442Sadrian * The following are flags for different requirements per reg domain. 58219442Sadrian * These requirements are either inhereted from the reg domain pair or 59219442Sadrian * from the unitary reg domain if the reg domain pair flags value is 0 60219442Sadrian */ 61219442Sadrianenum { 62219442Sadrian NO_REQ = 0x00000000, /* NB: must be zero */ 63219442Sadrian DISALLOW_ADHOC_11A = 0x00000001, /* adhoc not allowed in 5GHz */ 64219442Sadrian DISALLOW_ADHOC_11A_TURB = 0x00000002, /* not allowed w/ 5GHz turbo */ 65219442Sadrian NEED_NFC = 0x00000004, /* need noise floor check */ 66219442Sadrian ADHOC_PER_11D = 0x00000008, /* must receive 11d beacon */ 67219442Sadrian LIMIT_FRAME_4MS = 0x00000020, /* 4msec tx burst limit */ 68219442Sadrian NO_HOSTAP = 0x00000040, /* No HOSTAP mode opereation */ 69219442Sadrian}; 70219442Sadrian 71219442Sadrian/* Bit masks for DFS per regdomain */ 72219442Sadrianenum { 73219442Sadrian NO_DFS = 0x0000000000000000ULL, /* NB: must be zero */ 74219442Sadrian DFS_FCC3 = 0x0000000000000001ULL, 75219442Sadrian DFS_ETSI = 0x0000000000000002ULL, 76219442Sadrian DFS_MKK4 = 0x0000000000000004ULL, 77219442Sadrian}; 78219442Sadrian 79219442Sadrianenum { /* conformance test limits */ 80219442Sadrian FCC = 0x10, 81219442Sadrian MKK = 0x40, 82219442Sadrian ETSI = 0x30, 83219442Sadrian}; 84219442Sadrian 85219442Sadrian/* 86219394Sadrian * THE following table is the mapping of regdomain pairs specified by 87219394Sadrian * an 8 bit regdomain value to the individual unitary reg domains 88219394Sadrian */ 89219394Sadriantypedef struct regDomainPair { 90219394Sadrian HAL_REG_DOMAIN regDmnEnum; /* 16 bit reg domain pair */ 91219394Sadrian HAL_REG_DOMAIN regDmn5GHz; /* 5GHz reg domain */ 92219394Sadrian HAL_REG_DOMAIN regDmn2GHz; /* 2GHz reg domain */ 93219394Sadrian uint32_t flags5GHz; /* Requirements flags (AdHoc 94219394Sadrian disallow, noise floor cal needed, 95219394Sadrian etc) */ 96219394Sadrian uint32_t flags2GHz; /* Requirements flags (AdHoc 97219394Sadrian disallow, noise floor cal needed, 98219394Sadrian etc) */ 99219394Sadrian uint64_t pscanMask; /* Passive Scan flags which 100219394Sadrian can override unitary domain 101219394Sadrian passive scan flags. This 102219394Sadrian value is used as a mask on 103219394Sadrian the unitary flags*/ 104219394Sadrian uint16_t singleCC; /* Country code of single country if 105219394Sadrian a one-on-one mapping exists */ 106219394Sadrian} REG_DMN_PAIR_MAPPING; 107219394Sadrian 108219394Sadriantypedef struct { 109219394Sadrian HAL_CTRY_CODE countryCode; 110219394Sadrian HAL_REG_DOMAIN regDmnEnum; 111219394Sadrian} COUNTRY_CODE_TO_ENUM_RD; 112219394Sadrian 113219394Sadrian/* 114219394Sadrian * Frequency band collections are defined using bitmasks. Each bit 115219394Sadrian * in a mask is the index of an entry in one of the following tables. 116219394Sadrian * Bitmasks are BMLEN*64 bits so if a table grows beyond that the bit 117219394Sadrian * vectors must be enlarged or the tables split somehow (e.g. split 118219394Sadrian * 1/2 and 1/4 rate channels into a separate table). 119219394Sadrian * 120219394Sadrian * Beware of ordering; the indices are defined relative to the preceding 121219394Sadrian * entry so if things get off there will be confusion. A good way to 122219394Sadrian * check the indices is to collect them in a switch statement in a stub 123219394Sadrian * function so the compiler checks for duplicates. 124219394Sadrian */ 125219394Sadriantypedef struct { 126219394Sadrian uint16_t lowChannel; /* Low channel center in MHz */ 127219394Sadrian uint16_t highChannel; /* High Channel center in MHz */ 128219394Sadrian uint8_t powerDfs; /* Max power (dBm) for channel 129219394Sadrian range when using DFS */ 130219394Sadrian uint8_t antennaMax; /* Max allowed antenna gain */ 131219394Sadrian uint8_t channelBW; /* Bandwidth of the channel */ 132219394Sadrian uint8_t channelSep; /* Channel separation within 133219394Sadrian the band */ 134219394Sadrian uint64_t useDfs; /* Use DFS in the RegDomain 135219394Sadrian if corresponding bit is set */ 136219394Sadrian uint64_t usePassScan; /* Use Passive Scan in the RegDomain 137219394Sadrian if corresponding bit is set */ 138219394Sadrian} REG_DMN_FREQ_BAND; 139219394Sadrian 140219394Sadriantypedef struct regDomain { 141219394Sadrian uint16_t regDmnEnum; /* value from EnumRd table */ 142219394Sadrian uint8_t conformanceTestLimit; 143219394Sadrian uint32_t flags; /* Requirement flags (AdHoc disallow, 144219394Sadrian noise floor cal needed, etc) */ 145219394Sadrian uint64_t dfsMask; /* DFS bitmask for 5Ghz tables */ 146219394Sadrian uint64_t pscan; /* Bitmask for passive scan */ 147219394Sadrian chanbmask_t chan11a; /* 11a channels */ 148219394Sadrian chanbmask_t chan11a_turbo; /* 11a static turbo channels */ 149219394Sadrian chanbmask_t chan11a_dyn_turbo; /* 11a dynamic turbo channels */ 150219394Sadrian chanbmask_t chan11a_half; /* 11a 1/2 width channels */ 151219394Sadrian chanbmask_t chan11a_quarter; /* 11a 1/4 width channels */ 152219394Sadrian chanbmask_t chan11b; /* 11b channels */ 153219394Sadrian chanbmask_t chan11g; /* 11g channels */ 154219394Sadrian chanbmask_t chan11g_turbo; /* 11g dynamic turbo channels */ 155219394Sadrian chanbmask_t chan11g_half; /* 11g 1/2 width channels */ 156219394Sadrian chanbmask_t chan11g_quarter; /* 11g 1/4 width channels */ 157219394Sadrian} REG_DOMAIN; 158219394Sadrian 159219394Sadrianstruct cmode { 160219394Sadrian u_int mode; 161219394Sadrian u_int flags; 162219394Sadrian}; 163219394Sadrian#endif 164