1197948Srpaulo/* 2197948Srpaulo * Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org> 3197948Srpaulo * Copyright (c) 2008 Sam Leffler, Errno Consulting 4197948Srpaulo * Copyright (c) 2008 Atheros Communications, Inc. 5197948Srpaulo * 6197948Srpaulo * Permission to use, copy, modify, and/or distribute this software for any 7197948Srpaulo * purpose with or without fee is hereby granted, provided that the above 8197948Srpaulo * copyright notice and this permission notice appear in all copies. 9197948Srpaulo * 10197948Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11197948Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12197948Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13197948Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14197948Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15197948Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16197948Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17197948Srpaulo * 18197948Srpaulo * $FreeBSD$ 19197948Srpaulo */ 20197948Srpaulo#ifndef _AH_EEPROM_V4K_H_ 21197948Srpaulo#define _AH_EEPROM_V4K_H_ 22197948Srpaulo 23197948Srpaulo#include "ah_eeprom.h" 24197948Srpaulo#include "ah_eeprom_v14.h" 25197948Srpaulo 26217814Sadrian#if _BYTE_ORDER == _BIG_ENDIAN 27217814Sadrian#define __BIG_ENDIAN_BITFIELD 28217814Sadrian#endif 29217814Sadrian 30208711Srpaulo#define AR9285_RDEXT_DEFAULT 0x1F 31208711Srpaulo 32220946Sadrian#define AR5416_4K_EEP_PD_GAIN_BOUNDARY_DEFAULT 58 33220946Sadrian 34197948Srpaulo#undef owl_eep_start_loc 35197948Srpaulo#ifdef __LINUX_ARM_ARCH__ /* AP71 */ 36197948Srpaulo#define owl_eep_start_loc 0 37197948Srpaulo#else 38197948Srpaulo#define owl_eep_start_loc 64 39197948Srpaulo#endif 40197948Srpaulo 41197948Srpaulo// 16-bit offset location start of calibration struct 42197948Srpaulo#define AR5416_4K_EEP_START_LOC 64 43197948Srpaulo#define AR5416_4K_NUM_2G_CAL_PIERS 3 44197948Srpaulo#define AR5416_4K_NUM_2G_CCK_TARGET_POWERS 3 45197948Srpaulo#define AR5416_4K_NUM_2G_20_TARGET_POWERS 3 46197948Srpaulo#define AR5416_4K_NUM_2G_40_TARGET_POWERS 3 47197948Srpaulo#define AR5416_4K_NUM_CTLS 12 48197948Srpaulo#define AR5416_4K_NUM_BAND_EDGES 4 49197948Srpaulo#define AR5416_4K_NUM_PD_GAINS 2 50197948Srpaulo#define AR5416_4K_MAX_CHAINS 1 51197948Srpaulo 52197948Srpaulo/* 53197948Srpaulo * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version 54197948Srpaulo * and length are swapped). We reverse their position after reading 55197948Srpaulo * the data into host memory so the version field is at the same 56197948Srpaulo * offset as in previous EEPROM layouts. This makes utilities that 57197948Srpaulo * inspect the EEPROM contents work without looking at the PCI device 58197948Srpaulo * id which may or may not be reliable. 59197948Srpaulo */ 60197948Srpaulotypedef struct BaseEepHeader4k { 61197948Srpaulo uint16_t version; /* NB: length in EEPROM */ 62197948Srpaulo uint16_t checksum; 63197948Srpaulo uint16_t length; /* NB: version in EEPROM */ 64197948Srpaulo uint8_t opCapFlags; 65197948Srpaulo uint8_t eepMisc; 66197948Srpaulo uint16_t regDmn[2]; 67197948Srpaulo uint8_t macAddr[6]; 68197948Srpaulo uint8_t rxMask; 69197948Srpaulo uint8_t txMask; 70197948Srpaulo uint16_t rfSilent; 71197948Srpaulo uint16_t blueToothOptions; 72197948Srpaulo uint16_t deviceCap; 73197948Srpaulo uint32_t binBuildNumber; 74197948Srpaulo uint8_t deviceType; 75197948Srpaulo uint8_t txGainType; /* high power tx gain table support */ 76197948Srpaulo} __packed BASE_EEP4K_HEADER; // 32 B 77197948Srpaulo 78197948Srpaulotypedef struct ModalEepHeader4k { 79217814Sadrian uint32_t antCtrlChain[AR5416_4K_MAX_CHAINS]; // 4 80197948Srpaulo uint32_t antCtrlCommon; // 4 81197948Srpaulo int8_t antennaGainCh[AR5416_4K_MAX_CHAINS]; // 1 82197948Srpaulo uint8_t switchSettling; // 1 83217814Sadrian uint8_t txRxAttenCh[AR5416_4K_MAX_CHAINS]; // 1 84197948Srpaulo uint8_t rxTxMarginCh[AR5416_4K_MAX_CHAINS]; // 1 85197948Srpaulo uint8_t adcDesiredSize; // 1 86197948Srpaulo int8_t pgaDesiredSize; // 1 87217814Sadrian uint8_t xlnaGainCh[AR5416_4K_MAX_CHAINS]; // 1 88197948Srpaulo uint8_t txEndToXpaOff; // 1 89197948Srpaulo uint8_t txEndToRxOn; // 1 90197948Srpaulo uint8_t txFrameToXpaOn; // 1 91197948Srpaulo uint8_t thresh62; // 1 92197948Srpaulo uint8_t noiseFloorThreshCh[AR5416_4K_MAX_CHAINS]; // 1 93197948Srpaulo uint8_t xpdGain; // 1 94197948Srpaulo uint8_t xpd; // 1 95197948Srpaulo int8_t iqCalICh[AR5416_4K_MAX_CHAINS]; // 1 96197948Srpaulo int8_t iqCalQCh[AR5416_4K_MAX_CHAINS]; // 1 97217809Sadrian 98197948Srpaulo uint8_t pdGainOverlap; // 1 99217809Sadrian 100217814Sadrian#ifdef __BIG_ENDIAN_BITFIELD 101217814Sadrian uint8_t ob_1:4, ob_0:4; // 1 102217814Sadrian uint8_t db1_1:4, db1_0:4; // 1 103217809Sadrian#else 104217809Sadrian uint8_t ob_0:4, ob_1:4; 105217809Sadrian uint8_t db1_0:4, db1_1:4; 106217809Sadrian#endif 107217809Sadrian 108197948Srpaulo uint8_t xpaBiasLvl; // 1 109197948Srpaulo uint8_t txFrameToDataStart; // 1 110197948Srpaulo uint8_t txFrameToPaOn; // 1 111197948Srpaulo uint8_t ht40PowerIncForPdadc; // 1 112197948Srpaulo uint8_t bswAtten[AR5416_4K_MAX_CHAINS]; // 1 113197948Srpaulo uint8_t bswMargin[AR5416_4K_MAX_CHAINS]; // 1 114197948Srpaulo uint8_t swSettleHt40; // 1 115197948Srpaulo uint8_t xatten2Db[AR5416_4K_MAX_CHAINS]; // 1 116197948Srpaulo uint8_t xatten2Margin[AR5416_4K_MAX_CHAINS]; // 1 117197948Srpaulo 118217814Sadrian#ifdef __BIG_ENDIAN_BITFIELD 119217814Sadrian uint8_t db2_1:4, db2_0:4; // 1 120217809Sadrian#else 121217814Sadrian uint8_t db2_0:4, db2_1:4; // 1 122217809Sadrian#endif 123217809Sadrian 124217814Sadrian uint8_t version; // 1 125217809Sadrian 126217814Sadrian#ifdef __BIG_ENDIAN_BITFIELD 127217814Sadrian uint8_t ob_3:4, ob_2:4; // 1 128217814Sadrian uint8_t antdiv_ctl1:4, ob_4:4; // 1 129217814Sadrian uint8_t db1_3:4, db1_2:4; // 1 130217814Sadrian uint8_t antdiv_ctl2:4, db1_4:4; // 1 131217814Sadrian uint8_t db2_2:4, db2_3:4; // 1 132217814Sadrian uint8_t reserved:4, db2_4:4; // 1 133217809Sadrian#else 134217814Sadrian uint8_t ob_2:4, ob_3:4; 135217814Sadrian uint8_t ob_4:4, antdiv_ctl1:4; 136217814Sadrian uint8_t db1_2:4, db1_3:4; 137217814Sadrian uint8_t db1_4:4, antdiv_ctl2:4; 138217814Sadrian uint8_t db2_2:4, db2_3:4; 139217814Sadrian uint8_t db2_4:4, reserved:4; 140217809Sadrian#endif 141220589Sadrian uint8_t tx_diversity; 142220589Sadrian uint8_t flc_pwr_thresh; 143220589Sadrian uint8_t bb_scale_smrt_antenna; 144220589Sadrian#define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f 145220589Sadrian uint8_t futureModal[1]; 146217809Sadrian 147197948Srpaulo SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B 148217814Sadrian} __packed MODAL_EEP4K_HEADER; // == 68 B 149197948Srpaulo 150197948Srpaulotypedef struct CalCtlData4k { 151197948Srpaulo CAL_CTL_EDGES ctlEdges[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_BAND_EDGES]; 152197948Srpaulo} __packed CAL_CTL_DATA_4K; 153197948Srpaulo 154197948Srpaulotypedef struct calDataPerFreq4k { 155203159Srpaulo uint8_t pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 156203159Srpaulo uint8_t vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 157197948Srpaulo} __packed CAL_DATA_PER_FREQ_4K; 158197948Srpaulo 159197948Srpaulostruct ar5416eeprom_4k { 160197948Srpaulo BASE_EEP4K_HEADER baseEepHeader; // 32 B 161197948Srpaulo uint8_t custData[20]; // 20 B 162197948Srpaulo MODAL_EEP4K_HEADER modalHeader; // 68 B 163197948Srpaulo uint8_t calFreqPier2G[AR5416_4K_NUM_2G_CAL_PIERS]; 164197948Srpaulo CAL_DATA_PER_FREQ_4K calPierData2G[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_2G_CAL_PIERS]; 165197948Srpaulo CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_4K_NUM_2G_CCK_TARGET_POWERS]; 166197948Srpaulo CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_4K_NUM_2G_20_TARGET_POWERS]; 167197948Srpaulo CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_4K_NUM_2G_20_TARGET_POWERS]; 168197948Srpaulo CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_4K_NUM_2G_40_TARGET_POWERS]; 169197948Srpaulo uint8_t ctlIndex[AR5416_4K_NUM_CTLS]; 170197948Srpaulo CAL_CTL_DATA_4K ctlData[AR5416_4K_NUM_CTLS]; 171197948Srpaulo uint8_t padding; 172197948Srpaulo} __packed; 173197948Srpaulo 174197948Srpaulotypedef struct { 175197948Srpaulo struct ar5416eeprom_4k ee_base; 176197948Srpaulo#define NUM_EDGES 8 177197948Srpaulo uint16_t ee_numCtls; 178197948Srpaulo RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_4K_NUM_CTLS]; 179197948Srpaulo /* XXX these are dynamically calculated for use by shared code */ 180208711Srpaulo int8_t ee_antennaGainMax; 181197948Srpaulo} HAL_EEPROM_v4k; 182197948Srpaulo#endif /* _AH_EEPROM_V4K_H_ */ 183