1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17204644Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#ifndef _ATH_AH_EEPROM_V3_H_ 20185377Ssam#define _ATH_AH_EEPROM_V3_H_ 21185377Ssam 22185377Ssam#include "ah_eeprom.h" 23185377Ssam 24185377Ssam/* EEPROM defines for Version 2 & 3 AR5211 chips */ 25185377Ssam#define AR_EEPROM_RFSILENT 0x0f /* RF Silent/Clock Run Enable */ 26185377Ssam#define AR_EEPROM_MAC(i) (0x1d+(i)) /* MAC address word */ 27185377Ssam#define AR_EEPROM_MAGIC 0x3d /* magic number */ 28185377Ssam#define AR_EEPROM_PROTECT 0x3f /* EEPROM protect bits */ 29185377Ssam#define AR_EEPROM_PROTECT_PCIE 0x01 /* EEPROM protect bits for Condor/Swan*/ 30185377Ssam#define AR_EEPROM_REG_DOMAIN 0xbf /* current regulatory domain */ 31185377Ssam#define AR_EEPROM_ATHEROS_BASE 0xc0 /* Base of Atheros-specific data */ 32185377Ssam#define AR_EEPROM_ATHEROS(i) (AR_EEPROM_ATHEROS_BASE+(i)) 33185377Ssam#define AR_EEPROM_ATHEROS_MAX (0x400-AR_EEPROM_ATHEROS_BASE) 34185377Ssam#define AR_EEPROM_VERSION AR_EEPROM_ATHEROS(1) 35185377Ssam 36185377Ssam/* FLASH(EEPROM) Defines for AR531X chips */ 37185377Ssam#define AR_EEPROM_SIZE_LOWER 0x1b /* size info -- lower */ 38185377Ssam#define AR_EEPROM_SIZE_UPPER 0x1c /* size info -- upper */ 39185377Ssam#define AR_EEPROM_SIZE_UPPER_MASK 0xfff0 40185377Ssam#define AR_EEPROM_SIZE_UPPER_SHIFT 4 41185377Ssam#define AR_EEPROM_SIZE_ENDLOC_SHIFT 12 42185377Ssam#define AR_EEPROM_ATHEROS_MAX_LOC 0x400 43185377Ssam#define AR_EEPROM_ATHEROS_MAX_OFF (AR_EEPROM_ATHEROS_MAX_LOC-AR_EEPROM_ATHEROS_BASE) 44185377Ssam 45185377Ssam/* regulatory capabilities offsets */ 46185377Ssam#define AR_EEPROM_REG_CAPABILITIES_OFFSET 0xCA 47185377Ssam#define AR_EEPROM_REG_CAPABILITIES_OFFSET_PRE4_0 0xCF /* prior to 4.0 */ 48185377Ssam 49185377Ssam/* regulatory capabilities */ 50185377Ssam#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 51185377Ssam#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 52185377Ssam#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 53185377Ssam#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 54185377Ssam#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 55185377Ssam#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 56185377Ssam 57185377Ssam/* regulatory capabilities prior to eeprom version 4.0 */ 58185377Ssam#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 59185377Ssam#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 60185377Ssam 61185377Ssam/* 62185377Ssam * AR2413 (includes AR5413) 63185377Ssam */ 64185377Ssam#define AR_EEPROM_SERIAL_NUM_OFFSET 0xB0 /* EEPROM serial number */ 65185377Ssam#define AR_EEPROM_SERIAL_NUM_SIZE 12 /* EEPROM serial number size */ 66185377Ssam#define AR_EEPROM_CAPABILITIES_OFFSET 0xC9 /* EEPROM Location of capabilities */ 67185377Ssam 68185377Ssam#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 69185377Ssam#define AR_EEPROM_EEPCAP_AES_DIS 0x0002 70185377Ssam#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 71185377Ssam#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 72185377Ssam#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 73185377Ssam#define AR_EEPROM_EEPCAP_MAXQCU_S 4 74185377Ssam#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 75185377Ssam#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 76185377Ssam#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 77185377Ssam 78185377Ssam/* XXX used to index various EEPROM-derived data structures */ 79185377Ssamenum { 80185377Ssam headerInfo11A = 0, 81185377Ssam headerInfo11B = 1, 82185377Ssam headerInfo11G = 2, 83185377Ssam}; 84185377Ssam 85185377Ssam#define GROUPS_OFFSET3_2 0x100 /* groups offset for ver3.2 and earlier */ 86185377Ssam#define GROUPS_OFFSET3_3 0x150 /* groups offset for ver3.3 */ 87185377Ssam/* relative offset of GROUPi to GROUPS_OFFSET */ 88185377Ssam#define GROUP1_OFFSET 0x0 89185377Ssam#define GROUP2_OFFSET 0x5 90185377Ssam#define GROUP3_OFFSET 0x37 91185377Ssam#define GROUP4_OFFSET 0x46 92185377Ssam#define GROUP5_OFFSET 0x55 93185377Ssam#define GROUP6_OFFSET 0x65 94185377Ssam#define GROUP7_OFFSET 0x69 95185377Ssam#define GROUP8_OFFSET 0x6f 96185377Ssam 97185377Ssam/* RF silent fields in EEPROM */ 98185377Ssam#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c 99185377Ssam#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 100185377Ssam#define AR_EEPROM_RFSILENT_POLARITY 0x0002 101185377Ssam#define AR_EEPROM_RFSILENT_POLARITY_S 1 102185377Ssam 103185377Ssam/* Protect Bits RP is read protect, WP is write protect */ 104185377Ssam#define AR_EEPROM_PROTECT_RP_0_31 0x0001 105185377Ssam#define AR_EEPROM_PROTECT_WP_0_31 0x0002 106185377Ssam#define AR_EEPROM_PROTECT_RP_32_63 0x0004 107185377Ssam#define AR_EEPROM_PROTECT_WP_32_63 0x0008 108185377Ssam#define AR_EEPROM_PROTECT_RP_64_127 0x0010 109185377Ssam#define AR_EEPROM_PROTECT_WP_64_127 0x0020 110185377Ssam#define AR_EEPROM_PROTECT_RP_128_191 0x0040 111185377Ssam#define AR_EEPROM_PROTECT_WP_128_191 0x0080 112185377Ssam#define AR_EEPROM_PROTECT_RP_192_207 0x0100 113185377Ssam#define AR_EEPROM_PROTECT_WP_192_207 0x0200 114185377Ssam#define AR_EEPROM_PROTECT_RP_208_223 0x0400 115185377Ssam#define AR_EEPROM_PROTECT_WP_208_223 0x0800 116185377Ssam#define AR_EEPROM_PROTECT_RP_224_239 0x1000 117185377Ssam#define AR_EEPROM_PROTECT_WP_224_239 0x2000 118185377Ssam#define AR_EEPROM_PROTECT_RP_240_255 0x4000 119185377Ssam#define AR_EEPROM_PROTECT_WP_240_255 0x8000 120185377Ssam 121185377Ssam#define AR_EEPROM_MODAL_SPURS 5 122185377Ssam#define AR_SPUR_5413_1 1640 /* Freq 2464 */ 123185377Ssam#define AR_SPUR_5413_2 1200 /* Freq 2420 */ 124185377Ssam 125185377Ssam/* 126185377Ssam * EEPROM fixed point conversion scale factors. 127185377Ssam * NB: if you change one be sure to keep the other in sync. 128185377Ssam */ 129185377Ssam#define EEP_SCALE 100 /* conversion scale to avoid fp arith */ 130185377Ssam#define EEP_DELTA 10 /* SCALE/10, to avoid arith divide */ 131185377Ssam 132185377Ssam#define PWR_MIN 0 133185377Ssam#define PWR_MAX 3150 /* 31.5 * SCALE */ 134185377Ssam#define PWR_STEP 50 /* 0.5 * SCALE */ 135185377Ssam/* Keep 2 above defines together */ 136185377Ssam 137185377Ssam#define NUM_11A_EEPROM_CHANNELS 10 138185377Ssam#define NUM_2_4_EEPROM_CHANNELS 3 139185377Ssam#define NUM_PCDAC_VALUES 11 140185377Ssam#define NUM_TEST_FREQUENCIES 8 141185377Ssam#define NUM_EDGES 8 142185377Ssam#define NUM_INTERCEPTS 11 143185377Ssam#define FREQ_MASK 0x7f 144185377Ssam#define FREQ_MASK_3_3 0xff /* expanded in version 3.3 */ 145185377Ssam#define PCDAC_MASK 0x3f 146185377Ssam#define POWER_MASK 0x3f 147185377Ssam#define NON_EDGE_FLAG_MASK 0x40 148185377Ssam#define CHANNEL_POWER_INFO 8 149185377Ssam#define OBDB_UNSET 0xffff 150185377Ssam#define CHANNEL_UNUSED 0xff 151185377Ssam#define SCALE_OC_DELTA(_x) (((_x) * 2) / 10) 152185377Ssam 153185377Ssam/* Used during pcdac table construction */ 154185377Ssam#define PCDAC_START 1 155185377Ssam#define PCDAC_STOP 63 156185377Ssam#define PCDAC_STEP 1 157185377Ssam#define PWR_TABLE_SIZE 64 158185377Ssam#define MAX_RATE_POWER 63 159185377Ssam 160185377Ssam/* Used during power/rate table construction */ 161185377Ssam#define NUM_CTLS 16 162185377Ssam#define NUM_CTLS_3_3 32 /* expanded in version 3.3 */ 163185377Ssam#define NUM_CTLS_MAX NUM_CTLS_3_3 164185377Ssam 165185377Ssamtypedef struct fullPcdacStruct { 166185377Ssam uint16_t channelValue; 167185377Ssam uint16_t pcdacMin; 168185377Ssam uint16_t pcdacMax; 169185377Ssam uint16_t numPcdacValues; 170185377Ssam uint16_t PcdacValues[64]; 171185377Ssam /* power is 32bit since in dest it is scaled */ 172185377Ssam int16_t PwrValues[64]; 173185377Ssam} FULL_PCDAC_STRUCT; 174185377Ssam 175185377Ssamtypedef struct dataPerChannel { 176185377Ssam uint16_t channelValue; 177185377Ssam uint16_t pcdacMin; 178185377Ssam uint16_t pcdacMax; 179185377Ssam uint16_t numPcdacValues; 180185377Ssam uint16_t PcdacValues[NUM_PCDAC_VALUES]; 181185377Ssam /* NB: power is 32bit since in dest it is scaled */ 182185377Ssam int16_t PwrValues[NUM_PCDAC_VALUES]; 183185377Ssam} DATA_PER_CHANNEL; 184185377Ssam 185185377Ssam/* points to the appropriate pcdac structs in the above struct based on mode */ 186185377Ssamtypedef struct pcdacsEeprom { 187185377Ssam const uint16_t *pChannelList; 188185377Ssam uint16_t numChannels; 189185377Ssam const DATA_PER_CHANNEL *pDataPerChannel; 190185377Ssam} PCDACS_EEPROM; 191185377Ssam 192185377Ssamtypedef struct trgtPowerInfo { 193185377Ssam uint16_t twicePwr54; 194185377Ssam uint16_t twicePwr48; 195185377Ssam uint16_t twicePwr36; 196185377Ssam uint16_t twicePwr6_24; 197185377Ssam uint16_t testChannel; 198185377Ssam} TRGT_POWER_INFO; 199185377Ssam 200185377Ssamtypedef struct trgtPowerAllModes { 201185377Ssam uint16_t numTargetPwr_11a; 202185377Ssam TRGT_POWER_INFO trgtPwr_11a[NUM_TEST_FREQUENCIES]; 203185377Ssam uint16_t numTargetPwr_11g; 204185377Ssam TRGT_POWER_INFO trgtPwr_11g[3]; 205185377Ssam uint16_t numTargetPwr_11b; 206185377Ssam TRGT_POWER_INFO trgtPwr_11b[2]; 207185377Ssam} TRGT_POWER_ALL_MODES; 208185377Ssam 209185377Ssamtypedef struct cornerCalInfo { 210185377Ssam uint16_t gSel; 211185377Ssam uint16_t pd84; 212185377Ssam uint16_t pd90; 213185377Ssam uint16_t clip; 214185377Ssam} CORNER_CAL_INFO; 215185377Ssam 216185377Ssam/* 217185377Ssam * EEPROM version 4 definitions 218185377Ssam */ 219185377Ssam#define NUM_XPD_PER_CHANNEL 4 220185377Ssam#define NUM_POINTS_XPD0 4 221185377Ssam#define NUM_POINTS_XPD3 3 222185377Ssam#define IDEAL_10dB_INTERCEPT_2G 35 223185377Ssam#define IDEAL_10dB_INTERCEPT_5G 55 224185377Ssam 225185377Ssam#define TENX_OFDM_CCK_DELTA_INIT 15 /* power 1.5 dbm */ 226185377Ssam#define TENX_CH14_FILTER_CCK_DELTA_INIT 15 /* power 1.5 dbm */ 227185377Ssam#define CCK_OFDM_GAIN_DELTA 15 228185377Ssam 229185377Ssam#define NUM_TARGET_POWER_LOCATIONS_11B 4 230185377Ssam#define NUM_TARGET_POWER_LOCATIONS_11G 6 231185377Ssam 232185377Ssam 233185377Ssamtypedef struct { 234185377Ssam uint16_t xpd_gain; 235185377Ssam uint16_t numPcdacs; 236185377Ssam uint16_t pcdac[NUM_POINTS_XPD0]; 237185377Ssam int16_t pwr_t4[NUM_POINTS_XPD0]; /* or gainF */ 238185377Ssam} EXPN_DATA_PER_XPD_5112; 239185377Ssam 240185377Ssamtypedef struct { 241185377Ssam uint16_t channelValue; 242185377Ssam int16_t maxPower_t4; 243185377Ssam EXPN_DATA_PER_XPD_5112 pDataPerXPD[NUM_XPD_PER_CHANNEL]; 244185377Ssam} EXPN_DATA_PER_CHANNEL_5112; 245185377Ssam 246185377Ssamtypedef struct { 247185377Ssam uint16_t *pChannels; 248185377Ssam uint16_t numChannels; 249185377Ssam uint16_t xpdMask; /* mask of permitted xpd_gains */ 250185377Ssam EXPN_DATA_PER_CHANNEL_5112 *pDataPerChannel; 251185377Ssam} EEPROM_POWER_EXPN_5112; 252185377Ssam 253185377Ssamtypedef struct { 254185377Ssam uint16_t channelValue; 255185377Ssam uint16_t pcd1_xg0; 256185377Ssam int16_t pwr1_xg0; 257185377Ssam uint16_t pcd2_delta_xg0; 258185377Ssam int16_t pwr2_xg0; 259185377Ssam uint16_t pcd3_delta_xg0; 260185377Ssam int16_t pwr3_xg0; 261185377Ssam uint16_t pcd4_delta_xg0; 262185377Ssam int16_t pwr4_xg0; 263185377Ssam int16_t maxPower_t4; 264185377Ssam int16_t pwr1_xg3; /* pcdac = 20 */ 265185377Ssam int16_t pwr2_xg3; /* pcdac = 35 */ 266185377Ssam int16_t pwr3_xg3; /* pcdac = 63 */ 267185377Ssam /* XXX - Should be pwr1_xg2, etc to agree with documentation */ 268185377Ssam} EEPROM_DATA_PER_CHANNEL_5112; 269185377Ssam 270185377Ssamtypedef struct { 271185377Ssam uint16_t pChannels[NUM_11A_EEPROM_CHANNELS]; 272185377Ssam uint16_t numChannels; 273185377Ssam uint16_t xpdMask; /* mask of permitted xpd_gains */ 274185377Ssam EEPROM_DATA_PER_CHANNEL_5112 pDataPerChannel[NUM_11A_EEPROM_CHANNELS]; 275185377Ssam} EEPROM_POWER_5112; 276185377Ssam 277185377Ssam/* 278185377Ssam * EEPROM version 5 definitions (Griffin, et. al.). 279185377Ssam */ 280185377Ssam#define NUM_2_4_EEPROM_CHANNELS_2413 4 281185377Ssam#define NUM_11A_EEPROM_CHANNELS_2413 10 282185377Ssam#define PWR_TABLE_SIZE_2413 128 283185377Ssam 284185377Ssam/* Used during pdadc construction */ 285185377Ssam#define MAX_NUM_PDGAINS_PER_CHANNEL 4 286185377Ssam#define NUM_PDGAINS_PER_CHANNEL 2 287185377Ssam#define NUM_POINTS_LAST_PDGAIN 5 288185377Ssam#define NUM_POINTS_OTHER_PDGAINS 4 289185377Ssam#define XPD_GAIN1_GEN5 3 290185377Ssam#define XPD_GAIN2_GEN5 1 291185377Ssam#define MAX_PWR_RANGE_IN_HALF_DB 64 292185377Ssam#define PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB 4 293185377Ssam 294185377Ssamtypedef struct { 295185377Ssam uint16_t pd_gain; 296185377Ssam uint16_t numVpd; 297185377Ssam uint16_t Vpd[NUM_POINTS_LAST_PDGAIN]; 298185377Ssam int16_t pwr_t4[NUM_POINTS_LAST_PDGAIN]; /* or gainF */ 299185377Ssam} RAW_DATA_PER_PDGAIN_2413; 300185377Ssam 301185377Ssamtypedef struct { 302185377Ssam uint16_t channelValue; 303185377Ssam int16_t maxPower_t4; 304185377Ssam uint16_t numPdGains; /* # Pd Gains per channel */ 305185377Ssam RAW_DATA_PER_PDGAIN_2413 pDataPerPDGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 306185377Ssam} RAW_DATA_PER_CHANNEL_2413; 307185377Ssam 308185377Ssam/* XXX: assumes NUM_11A_EEPROM_CHANNELS_2413 >= NUM_2_4_EEPROM_CHANNELS_2413 ??? */ 309185377Ssamtypedef struct { 310185377Ssam uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413]; 311185377Ssam uint16_t numChannels; 312185377Ssam uint16_t xpd_mask; /* mask of permitted xpd_gains */ 313185377Ssam RAW_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413]; 314185377Ssam} RAW_DATA_STRUCT_2413; 315185377Ssam 316185377Ssamtypedef struct { 317185377Ssam uint16_t channelValue; 318185377Ssam uint16_t numPdGains; 319185377Ssam uint16_t Vpd_I[MAX_NUM_PDGAINS_PER_CHANNEL]; 320185377Ssam int16_t pwr_I[MAX_NUM_PDGAINS_PER_CHANNEL]; 321185377Ssam uint16_t Vpd_delta[NUM_POINTS_LAST_PDGAIN] 322185377Ssam [MAX_NUM_PDGAINS_PER_CHANNEL]; 323185377Ssam int16_t pwr_delta_t2[NUM_POINTS_LAST_PDGAIN] 324185377Ssam [MAX_NUM_PDGAINS_PER_CHANNEL]; 325185377Ssam int16_t maxPower_t4; 326185377Ssam} EEPROM_DATA_PER_CHANNEL_2413; 327185377Ssam 328185377Ssamtypedef struct { 329185377Ssam uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413]; 330185377Ssam uint16_t numChannels; 331185377Ssam uint16_t xpd_mask; /* mask of permitted xpd_gains */ 332185377Ssam EEPROM_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413]; 333185377Ssam} EEPROM_DATA_STRUCT_2413; 334185377Ssam 335185377Ssam/* 336185377Ssam * Information retrieved from EEPROM. 337185377Ssam */ 338185377Ssamtypedef struct { 339185377Ssam uint16_t ee_version; /* Version field */ 340185377Ssam uint16_t ee_protect; /* EEPROM protect field */ 341185377Ssam uint16_t ee_regdomain; /* Regulatory domain */ 342185377Ssam 343185377Ssam /* General Device Parameters */ 344185377Ssam uint16_t ee_turbo5Disable; 345185377Ssam uint16_t ee_turbo2Disable; 346185377Ssam uint16_t ee_rfKill; 347185377Ssam uint16_t ee_deviceType; 348185377Ssam uint16_t ee_turbo2WMaxPower5; 349185377Ssam uint16_t ee_turbo2WMaxPower2; 350185377Ssam uint16_t ee_xrTargetPower5; 351185377Ssam uint16_t ee_xrTargetPower2; 352185377Ssam uint16_t ee_Amode; 353185377Ssam uint16_t ee_regCap; 354185377Ssam uint16_t ee_Bmode; 355185377Ssam uint16_t ee_Gmode; 356185377Ssam int8_t ee_antennaGainMax[2]; 357185377Ssam uint16_t ee_xtnd5GSupport; 358185377Ssam uint8_t ee_cckOfdmPwrDelta; 359185377Ssam uint8_t ee_exist32kHzCrystal; 360185377Ssam uint16_t ee_targetPowersStart; 361185377Ssam uint16_t ee_fixedBias5; 362185377Ssam uint16_t ee_fixedBias2; 363185377Ssam uint16_t ee_cckOfdmGainDelta; 364185377Ssam uint16_t ee_scaledCh14FilterCckDelta; 365185377Ssam uint16_t ee_eepMap; 366185377Ssam uint16_t ee_earStart; 367185377Ssam 368185377Ssam /* 5 GHz / 2.4 GHz CKK / 2.4 GHz OFDM common parameters */ 369185377Ssam uint16_t ee_switchSettling[3]; 370185377Ssam uint16_t ee_txrxAtten[3]; 371185377Ssam uint16_t ee_txEndToXLNAOn[3]; 372185377Ssam uint16_t ee_thresh62[3]; 373185377Ssam uint16_t ee_txEndToXPAOff[3]; 374185377Ssam uint16_t ee_txFrameToXPAOn[3]; 375185377Ssam int8_t ee_adcDesiredSize[3]; /* 8-bit signed value */ 376185377Ssam int8_t ee_pgaDesiredSize[3]; /* 8-bit signed value */ 377185377Ssam int16_t ee_noiseFloorThresh[3]; 378185377Ssam uint16_t ee_xlnaGain[3]; 379185377Ssam uint16_t ee_xgain[3]; 380185377Ssam uint16_t ee_xpd[3]; 381185377Ssam uint16_t ee_antennaControl[11][3]; 382185377Ssam uint16_t ee_falseDetectBackoff[3]; 383185377Ssam uint16_t ee_gainI[3]; 384185377Ssam uint16_t ee_rxtxMargin[3]; 385185377Ssam 386185377Ssam /* new parameters added for the AR2413 */ 387185377Ssam HAL_BOOL ee_disableXr5; 388185377Ssam HAL_BOOL ee_disableXr2; 389185377Ssam uint16_t ee_eepMap2PowerCalStart; 390185377Ssam uint16_t ee_capField; 391185377Ssam 392185377Ssam uint16_t ee_switchSettlingTurbo[2]; 393185377Ssam uint16_t ee_txrxAttenTurbo[2]; 394185377Ssam int8_t ee_adcDesiredSizeTurbo[2]; 395185377Ssam int8_t ee_pgaDesiredSizeTurbo[2]; 396185377Ssam uint16_t ee_rxtxMarginTurbo[2]; 397185377Ssam 398185377Ssam /* 5 GHz parameters */ 399185377Ssam uint16_t ee_ob1; 400185377Ssam uint16_t ee_db1; 401185377Ssam uint16_t ee_ob2; 402185377Ssam uint16_t ee_db2; 403185377Ssam uint16_t ee_ob3; 404185377Ssam uint16_t ee_db3; 405185377Ssam uint16_t ee_ob4; 406185377Ssam uint16_t ee_db4; 407185377Ssam 408185377Ssam /* 2.4 GHz parameters */ 409185377Ssam uint16_t ee_obFor24; 410185377Ssam uint16_t ee_dbFor24; 411185377Ssam uint16_t ee_obFor24g; 412185377Ssam uint16_t ee_dbFor24g; 413185377Ssam uint16_t ee_ob2GHz[2]; 414185377Ssam uint16_t ee_db2GHz[2]; 415185377Ssam uint16_t ee_numCtls; 416185377Ssam uint16_t ee_ctl[NUM_CTLS_MAX]; 417185377Ssam uint16_t ee_iqCalI[2]; 418185377Ssam uint16_t ee_iqCalQ[2]; 419185377Ssam uint16_t ee_calPier11g[NUM_2_4_EEPROM_CHANNELS]; 420185377Ssam uint16_t ee_calPier11b[NUM_2_4_EEPROM_CHANNELS]; 421185377Ssam 422185377Ssam /* corner calibration information */ 423185377Ssam CORNER_CAL_INFO ee_cornerCal; 424185377Ssam 425185377Ssam uint16_t ee_opCap; 426185377Ssam 427185377Ssam /* 11a info */ 428185377Ssam uint16_t ee_channels11a[NUM_11A_EEPROM_CHANNELS]; 429185377Ssam uint16_t ee_numChannels11a; 430185377Ssam DATA_PER_CHANNEL ee_dataPerChannel11a[NUM_11A_EEPROM_CHANNELS]; 431185377Ssam 432185377Ssam uint16_t ee_numChannels2_4; 433185377Ssam uint16_t ee_channels11g[NUM_2_4_EEPROM_CHANNELS]; 434185377Ssam uint16_t ee_channels11b[NUM_2_4_EEPROM_CHANNELS]; 435185377Ssam uint16_t ee_spurChans[AR_EEPROM_MODAL_SPURS][2]; 436185377Ssam 437185377Ssam /* 11g info */ 438185377Ssam DATA_PER_CHANNEL ee_dataPerChannel11g[NUM_2_4_EEPROM_CHANNELS]; 439185377Ssam 440185377Ssam /* 11b info */ 441185377Ssam DATA_PER_CHANNEL ee_dataPerChannel11b[NUM_2_4_EEPROM_CHANNELS]; 442185377Ssam 443185377Ssam TRGT_POWER_ALL_MODES ee_tpow; 444185377Ssam 445185377Ssam RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*NUM_CTLS_MAX]; 446185377Ssam 447185377Ssam union { 448185377Ssam EEPROM_POWER_EXPN_5112 eu_modePowerArray5112[3]; 449185377Ssam RAW_DATA_STRUCT_2413 eu_rawDataset2413[3]; 450185377Ssam } ee_u; 451185377Ssam} HAL_EEPROM; 452185377Ssam 453185377Ssam/* write-around defines */ 454185377Ssam#define ee_numTargetPwr_11a ee_tpow.numTargetPwr_11a 455185377Ssam#define ee_trgtPwr_11a ee_tpow.trgtPwr_11a 456185377Ssam#define ee_numTargetPwr_11g ee_tpow.numTargetPwr_11g 457185377Ssam#define ee_trgtPwr_11g ee_tpow.trgtPwr_11g 458185377Ssam#define ee_numTargetPwr_11b ee_tpow.numTargetPwr_11b 459185377Ssam#define ee_trgtPwr_11b ee_tpow.trgtPwr_11b 460185377Ssam#define ee_modePowerArray5112 ee_u.eu_modePowerArray5112 461185377Ssam#define ee_rawDataset2413 ee_u.eu_rawDataset2413 462185377Ssam#endif /* _ATH_AH_EEPROM_V3_H_ */ 463