1185377Ssam/* 2185377Ssam * Copyright (c) 2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17203682Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#ifndef _AH_EEPROM_V14_H_ 20185377Ssam#define _AH_EEPROM_V14_H_ 21185377Ssam 22185377Ssam#include "ah_eeprom.h" 23185377Ssam 24185377Ssam/* reg_off = 4 * (eep_off) */ 25185377Ssam#define AR5416_EEPROM_S 2 26185377Ssam#define AR5416_EEPROM_OFFSET 0x2000 27185377Ssam#define AR5416_EEPROM_START_ADDR 0x503f1200 28185377Ssam#define AR5416_EEPROM_MAX 0xae0 /* Ignore for the moment used only on the flash implementations */ 29185377Ssam#define AR5416_EEPROM_MAGIC 0xa55a 30185377Ssam#define AR5416_EEPROM_MAGIC_OFFSET 0x0 31185377Ssam 32185377Ssam#define owl_get_ntxchains(_txchainmask) \ 33185377Ssam (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 34185377Ssam 35185377Ssam#ifdef __LINUX_ARM_ARCH__ /* AP71 */ 36185377Ssam#define owl_eep_start_loc 0 37185377Ssam#else 38185377Ssam#define owl_eep_start_loc 256 39185377Ssam#endif 40185377Ssam 41185377Ssam/* End temp defines */ 42185377Ssam 43185377Ssam#define AR5416_EEP_NO_BACK_VER 0x1 44185377Ssam#define AR5416_EEP_VER 0xE 45185377Ssam#define AR5416_EEP_VER_MINOR_MASK 0xFFF 46185377Ssam// Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc 47185377Ssam#define AR5416_EEP_MINOR_VER_2 0x2 48185377Ssam// Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable 49185377Ssam#define AR5416_EEP_MINOR_VER_3 0x3 50185377Ssam#define AR5416_EEP_MINOR_VER_7 0x7 51185377Ssam#define AR5416_EEP_MINOR_VER_9 0x9 52219441Sadrian#define AR5416_EEP_MINOR_VER_10 0xa 53185377Ssam#define AR5416_EEP_MINOR_VER_16 0x10 54185377Ssam#define AR5416_EEP_MINOR_VER_17 0x11 55185377Ssam#define AR5416_EEP_MINOR_VER_19 0x13 56217623Sadrian#define AR5416_EEP_MINOR_VER_20 0x14 57217623Sadrian#define AR5416_EEP_MINOR_VER_21 0x15 58217623Sadrian#define AR5416_EEP_MINOR_VER_22 0x16 59185377Ssam 60185377Ssam// 16-bit offset location start of calibration struct 61185377Ssam#define AR5416_EEP_START_LOC 256 62185377Ssam#define AR5416_NUM_5G_CAL_PIERS 8 63185377Ssam#define AR5416_NUM_2G_CAL_PIERS 4 64185377Ssam#define AR5416_NUM_5G_20_TARGET_POWERS 8 65185377Ssam#define AR5416_NUM_5G_40_TARGET_POWERS 8 66185377Ssam#define AR5416_NUM_2G_CCK_TARGET_POWERS 3 67185377Ssam#define AR5416_NUM_2G_20_TARGET_POWERS 4 68185377Ssam#define AR5416_NUM_2G_40_TARGET_POWERS 4 69185377Ssam#define AR5416_NUM_CTLS 24 70185377Ssam#define AR5416_NUM_BAND_EDGES 8 71185377Ssam#define AR5416_NUM_PD_GAINS 4 72185377Ssam#define AR5416_PD_GAINS_IN_MASK 4 73185377Ssam#define AR5416_PD_GAIN_ICEPTS 5 74185377Ssam#define AR5416_EEPROM_MODAL_SPURS 5 75185377Ssam#define AR5416_MAX_RATE_POWER 63 76185377Ssam#define AR5416_NUM_PDADC_VALUES 128 77185377Ssam#define AR5416_NUM_RATES 16 78185377Ssam#define AR5416_BCHAN_UNUSED 0xFF 79185377Ssam#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 80185377Ssam#define AR5416_EEPMISC_BIG_ENDIAN 0x01 81185377Ssam#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 82185377Ssam#define AR5416_MAX_CHAINS 3 83203682Srpaulo#define AR5416_PWR_TABLE_OFFSET_DB -5 84185377Ssam#define AR5416_ANT_16S 25 85185377Ssam 86185377Ssam#define AR5416_NUM_ANT_CHAIN_FIELDS 7 87185377Ssam#define AR5416_NUM_ANT_COMMON_FIELDS 4 88185377Ssam#define AR5416_SIZE_ANT_CHAIN_FIELD 3 89185377Ssam#define AR5416_SIZE_ANT_COMMON_FIELD 4 90185377Ssam#define AR5416_ANT_CHAIN_MASK 0x7 91185377Ssam#define AR5416_ANT_COMMON_MASK 0xf 92185377Ssam#define AR5416_CHAIN_0_IDX 0 93185377Ssam#define AR5416_CHAIN_1_IDX 1 94185377Ssam#define AR5416_CHAIN_2_IDX 2 95185377Ssam 96185377Ssam#define AR5416_OPFLAGS_11A 0x01 97185377Ssam#define AR5416_OPFLAGS_11G 0x02 98221622Sadrian#define AR5416_OPFLAGS_N_5G_HT40 0x04 /* If set, disable 5G HT40 */ 99221622Sadrian#define AR5416_OPFLAGS_N_2G_HT40 0x08 100221622Sadrian#define AR5416_OPFLAGS_N_5G_HT20 0x10 101221622Sadrian#define AR5416_OPFLAGS_N_2G_HT20 0x20 102185377Ssam 103185377Ssam/* RF silent fields in EEPROM */ 104185377Ssam#define EEP_RFSILENT_ENABLED 0x0001 /* enabled/disabled */ 105185377Ssam#define EEP_RFSILENT_ENABLED_S 0 106185377Ssam#define EEP_RFSILENT_POLARITY 0x0002 /* polarity */ 107185377Ssam#define EEP_RFSILENT_POLARITY_S 1 108185377Ssam#define EEP_RFSILENT_GPIO_SEL 0x001c /* gpio PIN */ 109185377Ssam#define EEP_RFSILENT_GPIO_SEL_S 2 110185377Ssam 111185377Ssam/* Rx gain type values */ 112185377Ssam#define AR5416_EEP_RXGAIN_23dB_BACKOFF 0 113185377Ssam#define AR5416_EEP_RXGAIN_13dB_BACKOFF 1 114185377Ssam#define AR5416_EEP_RXGAIN_ORIG 2 115185377Ssam 116185377Ssam/* Tx gain type values */ 117185377Ssam#define AR5416_EEP_TXGAIN_ORIG 0 118185377Ssam#define AR5416_EEP_TXGAIN_HIGH_POWER 1 119185377Ssam 120185377Ssamtypedef struct spurChanStruct { 121185377Ssam uint16_t spurChan; 122185377Ssam uint8_t spurRangeLow; 123185377Ssam uint8_t spurRangeHigh; 124185377Ssam} __packed SPUR_CHAN; 125185377Ssam 126185377Ssamtypedef struct CalTargetPowerLegacy { 127185377Ssam uint8_t bChannel; 128185377Ssam uint8_t tPow2x[4]; 129185377Ssam} __packed CAL_TARGET_POWER_LEG; 130185377Ssam 131185377Ssamtypedef struct CalTargetPowerHt { 132185377Ssam uint8_t bChannel; 133185377Ssam uint8_t tPow2x[8]; 134185377Ssam} __packed CAL_TARGET_POWER_HT; 135185377Ssam 136185377Ssamtypedef struct CalCtlEdges { 137185377Ssam uint8_t bChannel; 138185377Ssam uint8_t tPowerFlag; /* [0..5] tPower [6..7] flag */ 139185377Ssam#define CAL_CTL_EDGES_POWER 0x3f 140185377Ssam#define CAL_CTL_EDGES_POWER_S 0 141185377Ssam#define CAL_CTL_EDGES_FLAG 0xc0 142185377Ssam#define CAL_CTL_EDGES_FLAG_S 6 143185377Ssam} __packed CAL_CTL_EDGES; 144185377Ssam 145185377Ssam/* 146220947Sadrian * These are the secondary regulatory domain flags 147220947Sadrian * for regDmn[1]. 148220947Sadrian */ 149220947Sadrian#define AR5416_REGDMN_EN_FCC_MID 0x01 /* 5.47 - 5.7GHz operation */ 150220947Sadrian#define AR5416_REGDMN_EN_JAP_MID 0x02 /* 5.47 - 5.7GHz operation */ 151220947Sadrian#define AR5416_REGDMN_EN_FCC_DFS_HT40 0x04 /* FCC HT40 + DFS operation */ 152220947Sadrian#define AR5416_REGDMN_EN_JAP_HT40 0x08 /* JP HT40 operation */ 153220947Sadrian#define AR5416_REGDMN_EN_JAP_DFS_HT40 0x10 /* JP HT40 + DFS operation */ 154220947Sadrian 155220947Sadrian/* 156185377Ssam * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version 157185377Ssam * and length are swapped). We reverse their position after reading 158185377Ssam * the data into host memory so the version field is at the same 159185377Ssam * offset as in previous EEPROM layouts. This makes utilities that 160185377Ssam * inspect the EEPROM contents work without looking at the PCI device 161185377Ssam * id which may or may not be reliable. 162185377Ssam */ 163185377Ssamtypedef struct BaseEepHeader { 164185377Ssam uint16_t version; /* NB: length in EEPROM */ 165185377Ssam uint16_t checksum; 166185377Ssam uint16_t length; /* NB: version in EEPROM */ 167185377Ssam uint8_t opCapFlags; 168185377Ssam uint8_t eepMisc; 169185377Ssam uint16_t regDmn[2]; 170185377Ssam uint8_t macAddr[6]; 171185377Ssam uint8_t rxMask; 172185377Ssam uint8_t txMask; 173185377Ssam uint16_t rfSilent; 174185377Ssam uint16_t blueToothOptions; 175185377Ssam uint16_t deviceCap; 176185377Ssam uint32_t binBuildNumber; 177185377Ssam uint8_t deviceType; 178185377Ssam uint8_t pwdclkind; 179185377Ssam uint8_t fastClk5g; 180185377Ssam uint8_t divChain; 181185377Ssam uint8_t rxGainType; 182218419Sadrian uint8_t dacHiPwrMode_5G;/* use the DAC high power mode (MB91) */ 183185377Ssam uint8_t openLoopPwrCntl;/* 1: use open loop power control, 184185377Ssam 0: use closed loop power control */ 185185377Ssam uint8_t dacLpMode; 186185377Ssam uint8_t txGainType; /* high power tx gain table support */ 187185377Ssam uint8_t rcChainMask; /* "1" if the card is an HB93 1x2 */ 188218419Sadrian uint8_t desiredScaleCCK; 189218419Sadrian uint8_t pwr_table_offset; 190224519Sadrian uint8_t frac_n_5g; /* 191224519Sadrian * bit 0: indicates that fracN synth 192224519Sadrian * mode applies to all 5G channels 193224519Sadrian */ 194218419Sadrian uint8_t futureBase[21]; 195185377Ssam} __packed BASE_EEP_HEADER; // 64 B 196185377Ssam 197185377Ssamtypedef struct ModalEepHeader { 198185377Ssam uint32_t antCtrlChain[AR5416_MAX_CHAINS]; // 12 199185377Ssam uint32_t antCtrlCommon; // 4 200185377Ssam int8_t antennaGainCh[AR5416_MAX_CHAINS]; // 3 201185377Ssam uint8_t switchSettling; // 1 202185377Ssam uint8_t txRxAttenCh[AR5416_MAX_CHAINS]; // 3 203185377Ssam uint8_t rxTxMarginCh[AR5416_MAX_CHAINS]; // 3 204185377Ssam uint8_t adcDesiredSize; // 1 205185377Ssam int8_t pgaDesiredSize; // 1 206185377Ssam uint8_t xlnaGainCh[AR5416_MAX_CHAINS]; // 3 207185377Ssam uint8_t txEndToXpaOff; // 1 208185377Ssam uint8_t txEndToRxOn; // 1 209185377Ssam uint8_t txFrameToXpaOn; // 1 210185377Ssam uint8_t thresh62; // 1 211185377Ssam uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS]; // 3 212185377Ssam uint8_t xpdGain; // 1 213185377Ssam uint8_t xpd; // 1 214185377Ssam int8_t iqCalICh[AR5416_MAX_CHAINS]; // 1 215185377Ssam int8_t iqCalQCh[AR5416_MAX_CHAINS]; // 1 216185377Ssam uint8_t pdGainOverlap; // 1 217185377Ssam uint8_t ob; // 1 218185377Ssam uint8_t db; // 1 219185377Ssam uint8_t xpaBiasLvl; // 1 220185377Ssam uint8_t pwrDecreaseFor2Chain; // 1 221185377Ssam uint8_t pwrDecreaseFor3Chain; // 1 -> 48 B 222185377Ssam uint8_t txFrameToDataStart; // 1 223185377Ssam uint8_t txFrameToPaOn; // 1 224185377Ssam uint8_t ht40PowerIncForPdadc; // 1 225185377Ssam uint8_t bswAtten[AR5416_MAX_CHAINS]; // 3 226185377Ssam uint8_t bswMargin[AR5416_MAX_CHAINS]; // 3 227185377Ssam uint8_t swSettleHt40; // 1 228185377Ssam uint8_t xatten2Db[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 11:6) 229185377Ssam uint8_t xatten2Margin[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 21:17) 230185377Ssam uint8_t ob_ch1; // 1 -> ob and db become chain specific from AR9280 231185377Ssam uint8_t db_ch1; // 1 232185377Ssam uint8_t flagBits; // 1 233219980Sadrian#define AR5416_EEP_FLAG_USEANT1 0x80 /* +1 configured antenna */ 234219980Sadrian#define AR5416_EEP_FLAG_FORCEXPAON 0x40 /* force XPA bit for 5G */ 235219980Sadrian#define AR5416_EEP_FLAG_LOCALBIAS 0x20 /* enable local bias */ 236219980Sadrian#define AR5416_EEP_FLAG_FEMBANDSELECT 0x10 /* FEM band select used */ 237219980Sadrian#define AR5416_EEP_FLAG_XLNABUFIN 0x08 238219980Sadrian#define AR5416_EEP_FLAG_XLNAISEL1 0x04 239219980Sadrian#define AR5416_EEP_FLAG_XLNAISEL2 0x02 240219980Sadrian#define AR5416_EEP_FLAG_XLNABUFMODE 0x01 241185377Ssam uint8_t miscBits; // [0..1]: bb_tx_dac_scale_cck 242185377Ssam uint16_t xpaBiasLvlFreq[3]; // 3 243185377Ssam uint8_t futureModal[6]; // 6 244185377Ssam 245185377Ssam SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B 246185377Ssam} __packed MODAL_EEP_HEADER; // == 100 B 247185377Ssam 248185377Ssamtypedef struct calDataPerFreqOpLoop { 249185377Ssam uint8_t pwrPdg[2][5]; /* power measurement */ 250185377Ssam uint8_t vpdPdg[2][5]; /* pdadc voltage at power measurement */ 251185377Ssam uint8_t pcdac[2][5]; /* pcdac used for power measurement */ 252185377Ssam uint8_t empty[2][5]; /* future use */ 253185377Ssam} __packed CAL_DATA_PER_FREQ_OP_LOOP; 254185377Ssam 255185377Ssamtypedef struct CalCtlData { 256185377Ssam CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 257185377Ssam} __packed CAL_CTL_DATA; 258185377Ssam 259185377Ssamtypedef struct calDataPerFreq { 260185377Ssam uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 261185377Ssam uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 262185377Ssam} __packed CAL_DATA_PER_FREQ; 263185377Ssam 264185377Ssamstruct ar5416eeprom { 265185377Ssam BASE_EEP_HEADER baseEepHeader; // 64 B 266185377Ssam uint8_t custData[64]; // 64 B 267185377Ssam MODAL_EEP_HEADER modalHeader[2]; // 200 B 268185377Ssam uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 269185377Ssam uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 270185377Ssam CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; 271185377Ssam CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; 272185377Ssam CAL_TARGET_POWER_LEG calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; 273185377Ssam CAL_TARGET_POWER_HT calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 274185377Ssam CAL_TARGET_POWER_HT calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 275185377Ssam CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 276185377Ssam CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; 277185377Ssam CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 278185377Ssam CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 279185377Ssam uint8_t ctlIndex[AR5416_NUM_CTLS]; 280185377Ssam CAL_CTL_DATA ctlData[AR5416_NUM_CTLS]; 281185377Ssam uint8_t padding; 282185377Ssam} __packed; 283185377Ssam 284185377Ssamtypedef struct { 285185377Ssam struct ar5416eeprom ee_base; 286185377Ssam#define NUM_EDGES 8 287185377Ssam uint16_t ee_numCtls; 288185377Ssam RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_NUM_CTLS]; 289185377Ssam /* XXX these are dynamically calculated for use by shared code */ 290185377Ssam int8_t ee_antennaGainMax[2]; 291185377Ssam} HAL_EEPROM_v14; 292185377Ssam#endif /* _AH_EEPROM_V14_H_ */ 293