1183724Ssos/*- 2230132Suqs * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3183724Ssos * All rights reserved. 4183724Ssos * 5183724Ssos * Redistribution and use in source and binary forms, with or without 6183724Ssos * modification, are permitted provided that the following conditions 7183724Ssos * are met: 8183724Ssos * 1. Redistributions of source code must retain the above copyright 9183724Ssos * notice, this list of conditions and the following disclaimer, 10183724Ssos * without modification, immediately at the beginning of the file. 11183724Ssos * 2. Redistributions in binary form must reproduce the above copyright 12183724Ssos * notice, this list of conditions and the following disclaimer in the 13183724Ssos * documentation and/or other materials provided with the distribution. 14183724Ssos * 15183724Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183724Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17183724Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18183724Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19183724Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20183724Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21183724Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22183724Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23183724Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24183724Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25183724Ssos */ 26183724Ssos 27183724Ssos#include <sys/cdefs.h> 28183724Ssos__FBSDID("$FreeBSD$"); 29183724Ssos 30183724Ssos#include <sys/param.h> 31183724Ssos#include <sys/module.h> 32183724Ssos#include <sys/systm.h> 33183724Ssos#include <sys/kernel.h> 34183724Ssos#include <sys/ata.h> 35183724Ssos#include <sys/bus.h> 36183724Ssos#include <sys/endian.h> 37183724Ssos#include <sys/malloc.h> 38183724Ssos#include <sys/lock.h> 39183724Ssos#include <sys/mutex.h> 40183724Ssos#include <sys/sema.h> 41183724Ssos#include <sys/taskqueue.h> 42183724Ssos#include <vm/uma.h> 43183724Ssos#include <machine/stdarg.h> 44183724Ssos#include <machine/resource.h> 45183724Ssos#include <machine/bus.h> 46183724Ssos#include <sys/rman.h> 47183724Ssos#include <dev/pci/pcivar.h> 48183724Ssos#include <dev/pci/pcireg.h> 49183724Ssos#include <dev/ata/ata-all.h> 50183724Ssos#include <dev/ata/ata-pci.h> 51183724Ssos#include <ata_if.h> 52183724Ssos 53183724Ssos/* local prototypes */ 54183724Ssosstatic int ata_via_chipinit(device_t dev); 55188765Smavstatic int ata_via_ch_attach(device_t dev); 56188769Smavstatic int ata_via_ch_detach(device_t dev); 57183724Ssosstatic void ata_via_reset(device_t dev); 58214016Smavstatic int ata_via_status(device_t dev); 59200171Smavstatic int ata_via_old_setmode(device_t dev, int target, int mode); 60183724Ssosstatic void ata_via_southbridge_fixup(device_t dev); 61200171Smavstatic int ata_via_new_setmode(device_t dev, int target, int mode); 62200754Smavstatic int ata_via_sata_ch_attach(device_t dev); 63200754Smavstatic int ata_via_sata_getrev(device_t dev, int target); 64200754Smavstatic int ata_via_sata_setmode(device_t dev, int target, int mode); 65215449Smavstatic void ata_via_sata_reset(device_t dev); 66215449Smavstatic int ata_via_sata_scr_read(device_t dev, int port, int reg, 67215449Smav u_int32_t *result); 68215449Smavstatic int ata_via_sata_scr_write(device_t dev, int port, int reg, 69215449Smav u_int32_t value); 70215449Smavstatic int ata_via_sata_status(device_t dev); 71183724Ssos 72183724Ssos/* misc defines */ 73183724Ssos#define VIA33 0 74183724Ssos#define VIA66 1 75183724Ssos#define VIA100 2 76183724Ssos#define VIA133 3 77183724Ssos 78183724Ssos#define VIACLK 0x01 79183724Ssos#define VIABUG 0x02 80183724Ssos#define VIABAR 0x04 81200754Smav#define VIASATA 0x10 82183724Ssos 83183724Ssos/* 84183724Ssos * VIA Technologies Inc. chipset support functions 85183724Ssos */ 86183724Ssosstatic int 87183724Ssosata_via_probe(device_t dev) 88183724Ssos{ 89183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 90242625Sdim static const struct ata_chip_id ids[] = 91183724Ssos {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 92183724Ssos { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 93183724Ssos { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 94183724Ssos { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 95183724Ssos { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 96183724Ssos { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 97183724Ssos { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 98183724Ssos { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 99183724Ssos { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 100183724Ssos { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 101183724Ssos { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 102183724Ssos { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 103183724Ssos { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 104183724Ssos { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 105183724Ssos { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" }, 106198482Smav { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 107198482Smav { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 108183724Ssos { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 109200754Smav { ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" }, 110200754Smav { ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" }, 111200754Smav { ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" }, 112215428Smav { ATA_VIAVX900, 0x00, VIA133, VIASATA, ATA_SA300, "VX900" }, 113183724Ssos { 0, 0, 0, 0, 0, 0 }}; 114242625Sdim static const struct ata_chip_id new_ids[] = 115183724Ssos {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 116183724Ssos { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 117183724Ssos { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 118183724Ssos { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 119183724Ssos { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 120198481Smav { ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 121198481Smav { ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 122183724Ssos { 0, 0, 0, 0, 0, 0 }}; 123183724Ssos 124183724Ssos if (pci_get_vendor(dev) != ATA_VIA_ID) 125183724Ssos return ENXIO; 126183724Ssos 127200754Smav if (pci_get_devid(dev) == ATA_VIA82C571 || 128200754Smav pci_get_devid(dev) == ATA_VIACX700IDE || 129215428Smav pci_get_devid(dev) == ATA_VIASATAIDE || 130215428Smav pci_get_devid(dev) == ATA_VIASATAIDE2 || 131215428Smav pci_get_devid(dev) == ATA_VIASATAIDE3) { 132183724Ssos if (!(ctlr->chip = ata_find_chip(dev, ids, -99))) 133183724Ssos return ENXIO; 134183724Ssos } 135183724Ssos else { 136183724Ssos if (!(ctlr->chip = ata_match_chip(dev, new_ids))) 137183724Ssos return ENXIO; 138183724Ssos } 139183724Ssos 140183724Ssos ata_set_desc(dev); 141183724Ssos ctlr->chipinit = ata_via_chipinit; 142281140Smav return (BUS_PROBE_LOW_PRIORITY); 143183724Ssos} 144183724Ssos 145183724Ssosstatic int 146183724Ssosata_via_chipinit(device_t dev) 147183724Ssos{ 148183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 149183724Ssos 150183724Ssos if (ata_setup_interrupt(dev, ata_generic_intr)) 151183724Ssos return ENXIO; 152200754Smav 153215449Smav /* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */ 154200754Smav if (ctlr->chip->cfg2 & VIASATA) { 155200754Smav ctlr->ch_attach = ata_via_sata_ch_attach; 156200754Smav ctlr->setmode = ata_via_sata_setmode; 157200754Smav ctlr->getrev = ata_via_sata_getrev; 158215449Smav ctlr->reset = ata_via_sata_reset; 159200754Smav return 0; 160200754Smav } 161200754Smav /* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */ 162183724Ssos if (ctlr->chip->max_dma >= ATA_SA150) { 163183724Ssos ctlr->r_type2 = SYS_RES_IOPORT; 164183724Ssos ctlr->r_rid2 = PCIR_BAR(5); 165183724Ssos if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 166183724Ssos &ctlr->r_rid2, RF_ACTIVE))) { 167188765Smav ctlr->ch_attach = ata_via_ch_attach; 168188769Smav ctlr->ch_detach = ata_via_ch_detach; 169183724Ssos ctlr->reset = ata_via_reset; 170183724Ssos } 171183724Ssos if (ctlr->chip->cfg2 & VIABAR) { 172183724Ssos ctlr->channels = 3; 173183724Ssos ctlr->setmode = ata_via_new_setmode; 174200171Smav } else 175183724Ssos ctlr->setmode = ata_sata_setmode; 176200171Smav ctlr->getrev = ata_sata_getrev; 177183724Ssos return 0; 178183724Ssos } 179183724Ssos 180183724Ssos /* prepare for ATA-66 on the 82C686a and 82C596b */ 181183724Ssos if (ctlr->chip->cfg2 & VIACLK) 182183724Ssos pci_write_config(dev, 0x50, 0x030b030b, 4); 183183724Ssos 184183724Ssos /* the southbridge might need the data corruption fix */ 185183724Ssos if (ctlr->chip->cfg2 & VIABUG) 186183724Ssos ata_via_southbridge_fixup(dev); 187183724Ssos 188183724Ssos /* set fifo configuration half'n'half */ 189183724Ssos pci_write_config(dev, 0x43, 190183724Ssos (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 191183724Ssos 192183724Ssos /* set status register read retry */ 193183724Ssos pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 194183724Ssos 195183724Ssos /* set DMA read & end-of-sector fifo flush */ 196183724Ssos pci_write_config(dev, 0x46, 197183724Ssos (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 198183724Ssos 199183724Ssos /* set sector size */ 200183724Ssos pci_write_config(dev, 0x60, DEV_BSIZE, 2); 201183724Ssos pci_write_config(dev, 0x68, DEV_BSIZE, 2); 202183724Ssos 203183724Ssos ctlr->setmode = ata_via_old_setmode; 204183724Ssos return 0; 205183724Ssos} 206183724Ssos 207183724Ssosstatic int 208188765Smavata_via_ch_attach(device_t dev) 209183724Ssos{ 210183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 211183724Ssos struct ata_channel *ch = device_get_softc(dev); 212183724Ssos 213183724Ssos /* newer SATA chips has resources in one BAR for each channel */ 214183724Ssos if (ctlr->chip->cfg2 & VIABAR) { 215183724Ssos struct resource *r_io; 216183724Ssos int i, rid; 217183724Ssos 218188769Smav ata_pci_dmainit(dev); 219188769Smav 220183724Ssos rid = PCIR_BAR(ch->unit); 221183724Ssos if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 222183724Ssos SYS_RES_IOPORT, 223183724Ssos &rid, RF_ACTIVE))) 224183724Ssos return ENXIO; 225183724Ssos 226183724Ssos for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 227183724Ssos ch->r_io[i].res = r_io; 228183724Ssos ch->r_io[i].offset = i; 229183724Ssos } 230183724Ssos ch->r_io[ATA_CONTROL].res = r_io; 231183724Ssos ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 232183724Ssos ch->r_io[ATA_IDX_ADDR].res = r_io; 233183724Ssos ata_default_registers(dev); 234183724Ssos for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 235183724Ssos ch->r_io[i].res = ctlr->r_res1; 236183724Ssos ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 237183724Ssos } 238183724Ssos ata_pci_hw(dev); 239183724Ssos if (ch->unit >= 2) 240183724Ssos return 0; 241183724Ssos } 242183724Ssos else { 243183724Ssos /* setup the usual register normal pci style */ 244188765Smav if (ata_pci_ch_attach(dev)) 245183724Ssos return ENXIO; 246183724Ssos } 247183724Ssos 248183724Ssos ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 249183724Ssos ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 250183724Ssos ch->r_io[ATA_SERROR].res = ctlr->r_res2; 251183724Ssos ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 252183724Ssos ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 253183724Ssos ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 254214016Smav ch->hw.status = ata_via_status; 255183724Ssos ch->flags |= ATA_NO_SLAVE; 256200171Smav ch->flags |= ATA_SATA; 257214016Smav ch->flags |= ATA_PERIODIC_POLL; 258183724Ssos 259214016Smav ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff); 260214016Smav 261183724Ssos return 0; 262183724Ssos} 263183724Ssos 264188769Smavstatic int 265188769Smavata_via_ch_detach(device_t dev) 266188769Smav{ 267188769Smav struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 268188769Smav struct ata_channel *ch = device_get_softc(dev); 269188769Smav 270188769Smav /* newer SATA chips has resources in one BAR for each channel */ 271188769Smav if (ctlr->chip->cfg2 & VIABAR) { 272188769Smav int rid; 273188769Smav 274188769Smav rid = PCIR_BAR(ch->unit); 275188769Smav bus_release_resource(device_get_parent(dev), 276188769Smav SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res); 277188769Smav 278188769Smav ata_pci_dmafini(dev); 279188769Smav } 280188769Smav else { 281188769Smav /* setup the usual register normal pci style */ 282188769Smav if (ata_pci_ch_detach(dev)) 283188769Smav return ENXIO; 284188769Smav } 285188769Smav 286188769Smav return 0; 287188769Smav} 288188769Smav 289183724Ssosstatic void 290183724Ssosata_via_reset(device_t dev) 291183724Ssos{ 292183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 293183724Ssos struct ata_channel *ch = device_get_softc(dev); 294183724Ssos 295183724Ssos if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 296183724Ssos ata_generic_reset(dev); 297209884Smav else { 298190581Smav if (ata_sata_phy_reset(dev, -1, 1)) 299183724Ssos ata_generic_reset(dev); 300209884Smav else 301209884Smav ch->devices = 0; 302209884Smav } 303183724Ssos} 304183724Ssos 305200171Smavstatic int 306214016Smavata_via_status(device_t dev) 307214016Smav{ 308214016Smav 309214016Smav ata_sata_phy_check_events(dev, -1); 310214016Smav return (ata_pci_status(dev)); 311214016Smav} 312214016Smav 313214016Smavstatic int 314200171Smavata_via_new_setmode(device_t dev, int target, int mode) 315183724Ssos{ 316200171Smav device_t parent = device_get_parent(dev); 317200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 318200171Smav struct ata_channel *ch = device_get_softc(dev); 319183724Ssos 320200171Smav if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 321200171Smav int piomode; 322233282Smarius static const uint8_t pio_timings[] = 323233282Smarius { 0xa8, 0x65, 0x65, 0x32, 0x20 }; 324233282Smarius static const uint8_t dma_timings[] = 325233282Smarius { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 326183724Ssos 327200171Smav /* This chip can't do WDMA. */ 328200171Smav if (mode >= ATA_WDMA0 && mode < ATA_UDMA0) 329200171Smav mode = ATA_PIO4; 330200171Smav if (mode >= ATA_UDMA0) { 331200171Smav pci_write_config(parent, 0xb3, 332183724Ssos dma_timings[mode & ATA_MODE_MASK], 1); 333200171Smav piomode = ATA_PIO4; 334200171Smav } else 335200171Smav piomode = mode; 336200171Smav pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1); 337200171Smav } else 338200171Smav mode = ata_sata_setmode(dev, target, mode); 339200171Smav return (mode); 340183724Ssos} 341183724Ssos 342200171Smavstatic int 343200171Smavata_via_old_setmode(device_t dev, int target, int mode) 344183724Ssos{ 345200171Smav device_t parent = device_get_parent(dev); 346200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 347200171Smav struct ata_channel *ch = device_get_softc(dev); 348200171Smav int devno = (ch->unit << 1) + target; 349200171Smav int reg = 0x53 - devno; 350200171Smav int piomode; 351233282Smarius static const uint8_t timings[] = 352233282Smarius { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 }; 353233282Smarius static const uint8_t modes[][7] = { 354200171Smav { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 355200171Smav { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 356200171Smav { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 357200171Smav { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */ 358183724Ssos 359200171Smav mode = min(mode, ctlr->chip->max_dma); 360200171Smav /* Set UDMA timings */ 361200171Smav if (mode >= ATA_UDMA0) { 362200171Smav pci_write_config(parent, reg, 363200171Smav modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 364200171Smav piomode = ATA_PIO4; 365200171Smav } else { 366200171Smav pci_write_config(parent, reg, 0x8b, 1); 367200171Smav piomode = mode; 368200171Smav } 369200171Smav /* Set WDMA/PIO timings */ 370213301Smav pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1); 371200171Smav return (mode); 372183724Ssos} 373183724Ssos 374183724Ssosstatic void 375183724Ssosata_via_southbridge_fixup(device_t dev) 376183724Ssos{ 377183724Ssos device_t *children; 378183724Ssos int nchildren, i; 379183724Ssos 380183724Ssos if (device_get_children(device_get_parent(dev), &children, &nchildren)) 381183724Ssos return; 382183724Ssos 383183724Ssos for (i = 0; i < nchildren; i++) { 384183724Ssos if (pci_get_devid(children[i]) == ATA_VIA8363 || 385183724Ssos pci_get_devid(children[i]) == ATA_VIA8371 || 386183724Ssos pci_get_devid(children[i]) == ATA_VIA8662 || 387183724Ssos pci_get_devid(children[i]) == ATA_VIA8361) { 388183724Ssos u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 389183724Ssos 390183724Ssos if ((reg76 & 0xf0) != 0xd0) { 391183724Ssos device_printf(dev, 392183724Ssos "Correcting VIA config for southbridge data corruption bug\n"); 393183724Ssos pci_write_config(children[i], 0x75, 0x80, 1); 394183724Ssos pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 395183724Ssos } 396183724Ssos break; 397183724Ssos } 398183724Ssos } 399183724Ssos free(children, M_TEMP); 400183724Ssos} 401183724Ssos 402200754Smavstatic int 403200754Smavata_via_sata_ch_attach(device_t dev) 404200754Smav{ 405200754Smav struct ata_channel *ch = device_get_softc(dev); 406200754Smav 407200754Smav if (ata_pci_ch_attach(dev)) 408200754Smav return ENXIO; 409215449Smav if (ch->unit == 0) { 410215449Smav ch->hw.status = ata_via_sata_status; 411215449Smav ch->hw.pm_read = ata_via_sata_scr_read; 412215449Smav ch->hw.pm_write = ata_via_sata_scr_write; 413215449Smav ch->flags |= ATA_PERIODIC_POLL; 414200754Smav ch->flags |= ATA_SATA; 415215449Smav ata_sata_scr_write(ch, 0, ATA_SERROR, 0xffffffff); 416215449Smav ata_sata_scr_write(ch, 1, ATA_SERROR, 0xffffffff); 417215449Smav } 418200754Smav return (0); 419200754Smav} 420200754Smav 421200754Smavstatic int 422200754Smavata_via_sata_getrev(device_t dev, int target) 423200754Smav{ 424215449Smav device_t parent = device_get_parent(dev); 425200754Smav struct ata_channel *ch = device_get_softc(dev); 426200754Smav 427215449Smav if (ch->unit == 0) { 428215449Smav if (pci_read_config(parent, 0xa0 + target, 1) & 0x10) 429215449Smav return (2); 430215449Smav else 431215449Smav return (1); 432215449Smav } 433200754Smav return (0); 434200754Smav} 435200754Smav 436200754Smavstatic int 437200754Smavata_via_sata_setmode(device_t dev, int target, int mode) 438200754Smav{ 439200754Smav struct ata_channel *ch = device_get_softc(dev); 440200754Smav 441200754Smav if (ch->unit == 0) 442200754Smav return (mode); 443200754Smav return (ata_via_old_setmode(dev, target, mode)); 444200754Smav} 445200754Smav 446215449Smavstatic void 447215449Smavata_via_sata_reset(device_t dev) 448215449Smav{ 449215449Smav struct ata_channel *ch = device_get_softc(dev); 450215449Smav int devs; 451215449Smav 452215449Smav if (ch->unit == 0) { 453215449Smav devs = ata_sata_phy_reset(dev, 0, 0); 454215449Smav DELAY(10000); 455215449Smav devs += ata_sata_phy_reset(dev, 1, 0); 456215449Smav } else 457215449Smav devs = 1; 458215449Smav if (devs) 459215449Smav ata_generic_reset(dev); 460215451Smav else 461215451Smav ch->devices = 0; 462215449Smav} 463215449Smav 464215449Smavstatic int 465215449Smavata_via_sata_scr_read(device_t dev, int port, int reg, u_int32_t *result) 466215449Smav{ 467215449Smav device_t parent; 468215449Smav uint32_t val; 469215449Smav 470215449Smav parent = device_get_parent(dev); 471215449Smav port = (port == 1) ? 1 : 0; 472215449Smav switch (reg) { 473215449Smav case ATA_SSTATUS: 474215449Smav val = pci_read_config(parent, 0xa0 + port, 1); 475215449Smav *result = val & 0x03; 476215449Smav if (*result != ATA_SS_DET_NO_DEVICE) { 477215449Smav if (val & 0x04) 478215449Smav *result |= ATA_SS_IPM_PARTIAL; 479215449Smav else if (val & 0x08) 480215449Smav *result |= ATA_SS_IPM_SLUMBER; 481215449Smav else 482215449Smav *result |= ATA_SS_IPM_ACTIVE; 483215449Smav if (val & 0x10) 484215449Smav *result |= ATA_SS_SPD_GEN2; 485215449Smav else 486215449Smav *result |= ATA_SS_SPD_GEN1; 487215449Smav } 488215449Smav break; 489215449Smav case ATA_SERROR: 490215449Smav *result = pci_read_config(parent, 0xa8 + port * 4, 4); 491215449Smav break; 492215449Smav case ATA_SCONTROL: 493215449Smav val = pci_read_config(parent, 0xa4 + port, 1); 494215449Smav *result = 0; 495215449Smav if (val & 0x01) 496215449Smav *result |= ATA_SC_DET_RESET; 497215449Smav if (val & 0x02) 498215449Smav *result |= ATA_SC_DET_DISABLE; 499215449Smav if (val & 0x04) 500215449Smav *result |= ATA_SC_IPM_DIS_PARTIAL; 501215449Smav if (val & 0x08) 502215449Smav *result |= ATA_SC_IPM_DIS_SLUMBER; 503215449Smav break; 504215449Smav default: 505215449Smav return (EINVAL); 506215449Smav } 507215449Smav return (0); 508215449Smav} 509215449Smav 510215449Smavstatic int 511215449Smavata_via_sata_scr_write(device_t dev, int port, int reg, u_int32_t value) 512215449Smav{ 513215449Smav device_t parent; 514215449Smav uint32_t val; 515215449Smav 516215449Smav parent = device_get_parent(dev); 517215449Smav port = (port == 1) ? 1 : 0; 518215449Smav switch (reg) { 519215449Smav case ATA_SERROR: 520215449Smav pci_write_config(parent, 0xa8 + port * 4, value, 4); 521215449Smav break; 522215449Smav case ATA_SCONTROL: 523215449Smav val = 0; 524215449Smav if (value & ATA_SC_DET_RESET) 525215449Smav val |= 0x01; 526215449Smav if (value & ATA_SC_DET_DISABLE) 527215449Smav val |= 0x02; 528215449Smav if (value & ATA_SC_IPM_DIS_PARTIAL) 529215449Smav val |= 0x04; 530215449Smav if (value & ATA_SC_IPM_DIS_SLUMBER) 531215449Smav val |= 0x08; 532215449Smav pci_write_config(parent, 0xa4 + port, val, 1); 533215449Smav break; 534215449Smav default: 535215449Smav return (EINVAL); 536215449Smav } 537215449Smav return (0); 538215449Smav} 539215449Smav 540215449Smavstatic int 541215449Smavata_via_sata_status(device_t dev) 542215449Smav{ 543215449Smav 544215449Smav ata_sata_phy_check_events(dev, 0); 545215449Smav ata_sata_phy_check_events(dev, 1); 546215449Smav return (ata_pci_status(dev)); 547215449Smav} 548215449Smav 549183724SsosATA_DECLARE_DRIVER(ata_via); 550