1183724Ssos/*- 2230132Suqs * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3183724Ssos * All rights reserved. 4183724Ssos * 5183724Ssos * Redistribution and use in source and binary forms, with or without 6183724Ssos * modification, are permitted provided that the following conditions 7183724Ssos * are met: 8183724Ssos * 1. Redistributions of source code must retain the above copyright 9183724Ssos * notice, this list of conditions and the following disclaimer, 10183724Ssos * without modification, immediately at the beginning of the file. 11183724Ssos * 2. Redistributions in binary form must reproduce the above copyright 12183724Ssos * notice, this list of conditions and the following disclaimer in the 13183724Ssos * documentation and/or other materials provided with the distribution. 14183724Ssos * 15183724Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183724Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17183724Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18183724Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19183724Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20183724Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21183724Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22183724Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23183724Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24183724Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25183724Ssos */ 26183724Ssos 27183724Ssos#include <sys/cdefs.h> 28183724Ssos__FBSDID("$FreeBSD$"); 29183724Ssos 30183724Ssos#include <sys/param.h> 31183724Ssos#include <sys/module.h> 32183724Ssos#include <sys/systm.h> 33183724Ssos#include <sys/kernel.h> 34183724Ssos#include <sys/ata.h> 35183724Ssos#include <sys/bus.h> 36183724Ssos#include <sys/endian.h> 37183724Ssos#include <sys/malloc.h> 38183724Ssos#include <sys/lock.h> 39183724Ssos#include <sys/mutex.h> 40183724Ssos#include <sys/sema.h> 41183724Ssos#include <sys/taskqueue.h> 42183724Ssos#include <vm/uma.h> 43183724Ssos#include <machine/stdarg.h> 44183724Ssos#include <machine/resource.h> 45183724Ssos#include <machine/bus.h> 46183724Ssos#include <sys/rman.h> 47183724Ssos#include <dev/pci/pcivar.h> 48183724Ssos#include <dev/pci/pcireg.h> 49183724Ssos#include <dev/ata/ata-all.h> 50183724Ssos#include <dev/ata/ata-pci.h> 51183724Ssos#include <ata_if.h> 52183724Ssos 53183724Ssos/* local prototypes */ 54183724Ssosstatic int ata_nvidia_chipinit(device_t dev); 55188765Smavstatic int ata_nvidia_ch_attach(device_t dev); 56224603Smavstatic int ata_nvidia_ch_attach_dumb(device_t dev); 57183724Ssosstatic int ata_nvidia_status(device_t dev); 58183724Ssosstatic void ata_nvidia_reset(device_t dev); 59200171Smavstatic int ata_nvidia_setmode(device_t dev, int target, int mode); 60183724Ssos 61183724Ssos/* misc defines */ 62183724Ssos#define NV4 0x01 63183724Ssos#define NVQ 0x02 64188846Smav#define NVAHCI 0x04 65183724Ssos 66183724Ssos/* 67183724Ssos * nVidia chipset support functions 68183724Ssos */ 69183724Ssosstatic int 70183724Ssosata_nvidia_probe(device_t dev) 71183724Ssos{ 72183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 73242625Sdim static const struct ata_chip_id ids[] = 74183724Ssos {{ ATA_NFORCE1, 0, 0, 0, ATA_UDMA5, "nForce" }, 75183724Ssos { ATA_NFORCE2, 0, 0, 0, ATA_UDMA6, "nForce2" }, 76183724Ssos { ATA_NFORCE2_PRO, 0, 0, 0, ATA_UDMA6, "nForce2 Pro" }, 77183724Ssos { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 78183724Ssos { ATA_NFORCE3, 0, 0, 0, ATA_UDMA6, "nForce3" }, 79183724Ssos { ATA_NFORCE3_PRO, 0, 0, 0, ATA_UDMA6, "nForce3 Pro" }, 80183724Ssos { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 81183724Ssos { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 82183724Ssos { ATA_NFORCE_MCP04, 0, 0, 0, ATA_UDMA6, "nForce MCP" }, 83183724Ssos { ATA_NFORCE_MCP04_S1, 0, NV4, 0, ATA_SA150, "nForce MCP" }, 84183724Ssos { ATA_NFORCE_MCP04_S2, 0, NV4, 0, ATA_SA150, "nForce MCP" }, 85183724Ssos { ATA_NFORCE_CK804, 0, 0, 0, ATA_UDMA6, "nForce CK804" }, 86183724Ssos { ATA_NFORCE_CK804_S1, 0, NV4, 0, ATA_SA300, "nForce CK804" }, 87183724Ssos { ATA_NFORCE_CK804_S2, 0, NV4, 0, ATA_SA300, "nForce CK804" }, 88183724Ssos { ATA_NFORCE_MCP51, 0, 0, 0, ATA_UDMA6, "nForce MCP51" }, 89183724Ssos { ATA_NFORCE_MCP51_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" }, 90183724Ssos { ATA_NFORCE_MCP51_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" }, 91183724Ssos { ATA_NFORCE_MCP55, 0, 0, 0, ATA_UDMA6, "nForce MCP55" }, 92183724Ssos { ATA_NFORCE_MCP55_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" }, 93183724Ssos { ATA_NFORCE_MCP55_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" }, 94183724Ssos { ATA_NFORCE_MCP61, 0, 0, 0, ATA_UDMA6, "nForce MCP61" }, 95183724Ssos { ATA_NFORCE_MCP61_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 96183724Ssos { ATA_NFORCE_MCP61_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 97183724Ssos { ATA_NFORCE_MCP61_S3, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 98183724Ssos { ATA_NFORCE_MCP65, 0, 0, 0, ATA_UDMA6, "nForce MCP65" }, 99198818Smav { ATA_NFORCE_MCP65_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 100198818Smav { ATA_NFORCE_MCP65_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 101198818Smav { ATA_NFORCE_MCP65_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 102198818Smav { ATA_NFORCE_MCP65_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 103198818Smav { ATA_NFORCE_MCP65_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 104198818Smav { ATA_NFORCE_MCP65_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 105198818Smav { ATA_NFORCE_MCP65_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 106198818Smav { ATA_NFORCE_MCP65_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 107183724Ssos { ATA_NFORCE_MCP67, 0, 0, 0, ATA_UDMA6, "nForce MCP67" }, 108188846Smav { ATA_NFORCE_MCP67_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 109188846Smav { ATA_NFORCE_MCP67_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 110188846Smav { ATA_NFORCE_MCP67_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 111188846Smav { ATA_NFORCE_MCP67_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 112188846Smav { ATA_NFORCE_MCP67_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 113188846Smav { ATA_NFORCE_MCP67_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 114188846Smav { ATA_NFORCE_MCP67_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 115188846Smav { ATA_NFORCE_MCP67_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 116188846Smav { ATA_NFORCE_MCP67_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 117188846Smav { ATA_NFORCE_MCP67_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 118188846Smav { ATA_NFORCE_MCP67_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 119188846Smav { ATA_NFORCE_MCP67_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 120193716Sariff { ATA_NFORCE_MCP67_AC, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 121183724Ssos { ATA_NFORCE_MCP73, 0, 0, 0, ATA_UDMA6, "nForce MCP73" }, 122188846Smav { ATA_NFORCE_MCP73_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 123188846Smav { ATA_NFORCE_MCP73_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 124188846Smav { ATA_NFORCE_MCP73_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 125188846Smav { ATA_NFORCE_MCP73_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 126188846Smav { ATA_NFORCE_MCP73_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 127188846Smav { ATA_NFORCE_MCP73_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 128188846Smav { ATA_NFORCE_MCP73_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 129188846Smav { ATA_NFORCE_MCP73_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 130188846Smav { ATA_NFORCE_MCP73_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 131188846Smav { ATA_NFORCE_MCP73_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 132188846Smav { ATA_NFORCE_MCP73_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 133188846Smav { ATA_NFORCE_MCP73_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 134183724Ssos { ATA_NFORCE_MCP77, 0, 0, 0, ATA_UDMA6, "nForce MCP77" }, 135198818Smav { ATA_NFORCE_MCP77_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 136198818Smav { ATA_NFORCE_MCP77_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 137198818Smav { ATA_NFORCE_MCP77_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 138198818Smav { ATA_NFORCE_MCP77_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 139198818Smav { ATA_NFORCE_MCP77_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 140198818Smav { ATA_NFORCE_MCP77_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 141198818Smav { ATA_NFORCE_MCP77_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 142198818Smav { ATA_NFORCE_MCP77_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 143198818Smav { ATA_NFORCE_MCP77_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 144198818Smav { ATA_NFORCE_MCP77_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 145198818Smav { ATA_NFORCE_MCP77_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 146198818Smav { ATA_NFORCE_MCP77_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 147198818Smav { ATA_NFORCE_MCP79_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 148198818Smav { ATA_NFORCE_MCP79_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 149198818Smav { ATA_NFORCE_MCP79_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 150198818Smav { ATA_NFORCE_MCP79_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 151198818Smav { ATA_NFORCE_MCP79_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 152198818Smav { ATA_NFORCE_MCP79_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 153198818Smav { ATA_NFORCE_MCP79_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 154198818Smav { ATA_NFORCE_MCP79_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 155198818Smav { ATA_NFORCE_MCP79_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 156198818Smav { ATA_NFORCE_MCP79_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 157198818Smav { ATA_NFORCE_MCP79_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 158198818Smav { ATA_NFORCE_MCP79_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 159198818Smav { ATA_NFORCE_MCP89_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 160287016Smav { ATA_NFORCE_MCP89_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 161198818Smav { ATA_NFORCE_MCP89_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 162198818Smav { ATA_NFORCE_MCP89_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 163198818Smav { ATA_NFORCE_MCP89_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 164198818Smav { ATA_NFORCE_MCP89_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 165198818Smav { ATA_NFORCE_MCP89_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 166198818Smav { ATA_NFORCE_MCP89_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 167198818Smav { ATA_NFORCE_MCP89_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 168198818Smav { ATA_NFORCE_MCP89_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 169198818Smav { ATA_NFORCE_MCP89_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 170198818Smav { ATA_NFORCE_MCP89_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 171183724Ssos { 0, 0, 0, 0, 0, 0}} ; 172183724Ssos 173183724Ssos if (pci_get_vendor(dev) != ATA_NVIDIA_ID) 174183724Ssos return ENXIO; 175183724Ssos 176183724Ssos if (!(ctlr->chip = ata_match_chip(dev, ids))) 177183724Ssos return ENXIO; 178183724Ssos 179287016Smav if ((ctlr->chip->cfg1 & NVAHCI) && 180287016Smav pci_get_subclass(dev) != PCIS_STORAGE_IDE) 181287016Smav return (ENXIO); 182287016Smav 183183724Ssos ata_set_desc(dev); 184287016Smav ctlr->chipinit = ata_nvidia_chipinit; 185281140Smav return (BUS_PROBE_LOW_PRIORITY); 186183724Ssos} 187183724Ssos 188183724Ssosstatic int 189183724Ssosata_nvidia_chipinit(device_t dev) 190183724Ssos{ 191183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 192183724Ssos 193183724Ssos if (ata_setup_interrupt(dev, ata_generic_intr)) 194183724Ssos return ENXIO; 195183724Ssos 196224603Smav if (ctlr->chip->cfg1 & NVAHCI) { 197224603Smav ctlr->ch_attach = ata_nvidia_ch_attach_dumb; 198224603Smav ctlr->setmode = ata_sata_setmode; 199224603Smav } else if (ctlr->chip->max_dma >= ATA_SA150) { 200183724Ssos if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 201183724Ssos ctlr->r_type2 = SYS_RES_IOPORT; 202183724Ssos else 203183724Ssos ctlr->r_type2 = SYS_RES_MEMORY; 204183724Ssos ctlr->r_rid2 = PCIR_BAR(5); 205183724Ssos if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 206183724Ssos &ctlr->r_rid2, RF_ACTIVE))) { 207183724Ssos int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; 208183724Ssos 209188765Smav ctlr->ch_attach = ata_nvidia_ch_attach; 210188769Smav ctlr->ch_detach = ata_pci_ch_detach; 211183724Ssos ctlr->reset = ata_nvidia_reset; 212183724Ssos 213183724Ssos /* enable control access */ 214183724Ssos pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 215198479Smav /* MCP55 seems to need some time to allow r_res2 read. */ 216198479Smav DELAY(10); 217183724Ssos if (ctlr->chip->cfg1 & NVQ) { 218183724Ssos /* clear interrupt status */ 219183724Ssos ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 220183724Ssos 221183724Ssos /* enable device and PHY state change interrupts */ 222183724Ssos ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 223183724Ssos 224183724Ssos /* disable NCQ support */ 225183724Ssos ATA_OUTL(ctlr->r_res2, 0x0400, 226183724Ssos ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 227183724Ssos } 228183724Ssos else { 229183724Ssos /* clear interrupt status */ 230183724Ssos ATA_OUTB(ctlr->r_res2, offset, 0xff); 231183724Ssos 232183724Ssos /* enable device and PHY state change interrupts */ 233183724Ssos ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 234183724Ssos } 235183724Ssos } 236183724Ssos ctlr->setmode = ata_sata_setmode; 237200171Smav ctlr->getrev = ata_sata_getrev; 238183724Ssos } 239183724Ssos else { 240183724Ssos /* disable prefetch, postwrite */ 241183724Ssos pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 242183724Ssos ctlr->setmode = ata_nvidia_setmode; 243183724Ssos } 244183724Ssos return 0; 245183724Ssos} 246183724Ssos 247183724Ssosstatic int 248188765Smavata_nvidia_ch_attach(device_t dev) 249183724Ssos{ 250183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 251183724Ssos struct ata_channel *ch = device_get_softc(dev); 252183724Ssos 253183724Ssos /* setup the usual register normal pci style */ 254188765Smav if (ata_pci_ch_attach(dev)) 255183724Ssos return ENXIO; 256183724Ssos 257183724Ssos ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 258183724Ssos ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 259183724Ssos ch->r_io[ATA_SERROR].res = ctlr->r_res2; 260183724Ssos ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 261183724Ssos ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 262183724Ssos ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 263183724Ssos 264183724Ssos ch->hw.status = ata_nvidia_status; 265183724Ssos ch->flags |= ATA_NO_SLAVE; 266200171Smav ch->flags |= ATA_SATA; 267183724Ssos return 0; 268183724Ssos} 269183724Ssos 270224603Smavstatic int 271224603Smavata_nvidia_ch_attach_dumb(device_t dev) 272224603Smav{ 273224603Smav struct ata_channel *ch = device_get_softc(dev); 274224603Smav 275224603Smav if (ata_pci_ch_attach(dev)) 276224603Smav return ENXIO; 277224603Smav ch->flags |= ATA_SATA; 278224603Smav return 0; 279224603Smav} 280224603Smav 281183724Ssosstatic int 282183724Ssosata_nvidia_status(device_t dev) 283183724Ssos{ 284183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 285183724Ssos struct ata_channel *ch = device_get_softc(dev); 286183724Ssos int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; 287183724Ssos int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); 288183724Ssos u_int32_t istatus; 289183724Ssos 290183724Ssos /* get interrupt status */ 291183724Ssos if (ctlr->chip->cfg1 & NVQ) 292183724Ssos istatus = ATA_INL(ctlr->r_res2, offset); 293183724Ssos else 294183724Ssos istatus = ATA_INB(ctlr->r_res2, offset); 295183724Ssos 296183724Ssos /* do we have any PHY events ? */ 297183724Ssos if (istatus & (0x0c << shift)) 298214016Smav ata_sata_phy_check_events(dev, -1); 299183724Ssos 300183724Ssos /* clear interrupt(s) */ 301183724Ssos if (ctlr->chip->cfg1 & NVQ) 302183724Ssos ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0); 303183724Ssos else 304183724Ssos ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift)); 305183724Ssos 306183724Ssos /* do we have any device action ? */ 307183724Ssos return (istatus & (0x01 << shift)); 308183724Ssos} 309183724Ssos 310183724Ssosstatic void 311183724Ssosata_nvidia_reset(device_t dev) 312183724Ssos{ 313209884Smav struct ata_channel *ch = device_get_softc(dev); 314209884Smav 315190581Smav if (ata_sata_phy_reset(dev, -1, 1)) 316183724Ssos ata_generic_reset(dev); 317209884Smav else 318209884Smav ch->devices = 0; 319183724Ssos} 320183724Ssos 321200171Smavstatic int 322200171Smavata_nvidia_setmode(device_t dev, int target, int mode) 323183724Ssos{ 324200171Smav device_t parent = device_get_parent(dev); 325200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 326200171Smav struct ata_channel *ch = device_get_softc(dev); 327200171Smav int devno = (ch->unit << 1) + target; 328200171Smav int piomode; 329233282Smarius static const uint8_t timings[] = 330233282Smarius { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 }; 331233282Smarius static const uint8_t modes[] = 332233282Smarius { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }; 333200171Smav int reg = 0x63 - devno; 334183724Ssos 335200171Smav mode = min(mode, ctlr->chip->max_dma); 336183724Ssos 337200171Smav if (mode >= ATA_UDMA0) { 338200171Smav pci_write_config(parent, reg, modes[mode & ATA_MODE_MASK], 1); 339200171Smav piomode = ATA_PIO4; 340200171Smav } else { 341200171Smav pci_write_config(parent, reg, 0x8b, 1); 342200171Smav piomode = mode; 343200171Smav } 344200171Smav pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(piomode)], 1); 345200171Smav return (mode); 346183724Ssos} 347183724Ssos 348183724SsosATA_DECLARE_DRIVER(ata_nvidia); 349