amd_chipset.h revision 306815
1/*- 2 * Copyright (c) 2016 Andriy Gapon <avg@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/dev/amdsbwd/amd_chipset.h 306815 2016-10-07 18:51:04Z avg $ 27 */ 28 29/* 30 * The following registers, bits and magic values are defined in Register 31 * Reference Guide documents for SB600, SB7x0, SB8x0, SB9x0 southbridges and 32 * various versions of Fusion Controller Hubs (FCHs). FCHs integrated into 33 * CPUs are documented in BIOS and Kernel Development Guide documents for 34 * the corresponding processor families. 35 * 36 * At present there are three classes of supported chipsets: 37 * - SB600 and S7x0 southbridges where the SMBus controller device has 38 * a PCI Device ID of 0x43851002 and a revision less than 0x40 39 * - several types of southbridges and FCHs: 40 * o SB8x0, SB9x0 southbridges where the SMBus controller device has a PCI 41 * Device ID of 0x43851002 and a revision greater than or equal to 0x40 42 * o FCHs where the controller has an ID of 0x780b1022 and a revision less 43 * than 0x41 (various revisions of "Hudson" and "Bolton") 44 * o FCHs where the controller has an ID of 0x790b1022 and a revision less 45 * than 0x49 46 * - several types of southbridges and FCHs: 47 * o FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022 48 * and a revision greater than or equal to 0x41 (integrated into "Mullins" 49 * processors, code named "ML") 50 * o FCHs where the controller has an ID of 0x790b1022 and a revision greater 51 * than or equal to 0x49 (integrated into "Carrizo" processors, code named 52 * "KERNCZ" or "CZ") 53 * 54 * The register definitions are compatible within the classes and may be 55 * incompatible accross them. 56 */ 57 58/* 59 * IO registers for accessing the PMIO space. 60 * See SB7xx RRG 2.3.3.1.1, for instance. 61 */ 62#define AMDSB_PMIO_INDEX 0xcd6 63#define AMDSB_PMIO_DATA (PMIO_INDEX + 1) 64#define AMDSB_PMIO_WIDTH 2 65 66/* 67 * SB7x0 and compatible registers in the PMIO space. 68 * See SB7xx RRG 2.3.3.2. 69 */ 70#define AMDSB_PM_RESET_STATUS0 0x44 71#define AMDSB_PM_RESET_STATUS1 0x45 72#define AMDSB_WD_RST_STS 0x02 73#define AMDSB_PM_WDT_CTRL 0x69 74#define AMDSB_WDT_DISABLE 0x01 75#define AMDSB_WDT_RES_MASK (0x02 | 0x04) 76#define AMDSB_WDT_RES_32US 0x00 77#define AMDSB_WDT_RES_10MS 0x02 78#define AMDSB_WDT_RES_100MS 0x04 79#define AMDSB_WDT_RES_1S 0x06 80#define AMDSB_PM_WDT_BASE_LSB 0x6c 81#define AMDSB_PM_WDT_BASE_MSB 0x6f 82 83/* 84 * SB8x0 and compatible registers in the PMIO space. 85 * See SB8xx RRG 2.3.3, for instance. 86 */ 87#define AMDSB8_PM_SMBUS_EN 0x2c 88#define AMDSB8_SMBUS_EN 0x01 89#define AMDSB8_SMBUS_ADDR_MASK 0xffe0u 90#define AMDSB8_PM_WDT_EN 0x48 91#define AMDSB8_WDT_DEC_EN 0x01 92#define AMDSB8_WDT_DISABLE 0x02 93#define AMDSB8_PM_WDT_CTRL 0x4c 94#define AMDSB8_WDT_32KHZ 0x00 95#define AMDSB8_WDT_1HZ 0x03 96#define AMDSB8_WDT_RES_MASK 0x03 97#define AMDSB8_PM_RESET_STATUS0 0xc0 98#define AMDSB8_PM_RESET_STATUS1 0xc1 99#define AMDSB8_WD_RST_STS 0x20 100 101/* 102 * Newer FCH registers in the PMIO space. 103 * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04. 104 */ 105#define AMDFCH41_PM_DECODE_EN0 0x00 106#define AMDFCH41_SMBUS_EN 0x10 107#define AMDFCH41_WDT_EN 0x80 108#define AMDFCH41_PM_DECODE_EN1 0x01 109#define AMDFCH41_PM_DECODE_EN3 0x03 110#define AMDFCH41_WDT_RES_MASK 0x03 111#define AMDFCH41_WDT_RES_32US 0x00 112#define AMDFCH41_WDT_RES_10MS 0x01 113#define AMDFCH41_WDT_RES_100MS 0x02 114#define AMDFCH41_WDT_RES_1S 0x03 115#define AMDFCH41_WDT_EN_MASK 0x0c 116#define AMDFCH41_WDT_ENABLE 0x00 117#define AMDFCH41_PM_ISA_CTRL 0x04 118#define AMDFCH41_MMIO_EN 0x02 119 120/* 121 * Fixed MMIO addresses for accessing Watchdog and SMBus registers. 122 * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04. 123 */ 124#define AMDFCH41_WDT_FIXED_ADDR 0xfeb00000u 125#define AMDFCH41_MMIO_ADDR 0xfed80000u 126#define AMDFCH41_MMIO_SMBUS_OFF 0x0a00 127#define AMDFCH41_MMIO_WDT_OFF 0x0b00 128 129/* 130 * PCI Device IDs and revisions. 131 * SB600 RRG 2.3.1.1, 132 * SB7xx RRG 2.3.1.1, 133 * SB8xx RRG 2.3.1, 134 * BKDG for Family 16h Models 00h-0Fh 3.26.7.1, 135 * BKDG for Family 16h Models 30h-3Fh 3.26.7.1. 136 * Also, see i2c-piix4 aka piix4_smbus Linux driver. 137 */ 138#define AMDSB_SMBUS_DEVID 0x43851002 139#define AMDSB8_SMBUS_REVID 0x40 140#define AMDFCH_SMBUS_DEVID 0x780b1022 141#define AMDFCH41_SMBUS_REVID 0x41 142#define AMDCZ_SMBUS_DEVID 0x790b1022 143#define AMDCZ49_SMBUS_REVID 0x49 144 145