1256752Sbrooks/*- 2256752Sbrooks * Copyright (c) 2012 Bjoern A. Zeeb 3256752Sbrooks * All rights reserved. 4256752Sbrooks * 5256752Sbrooks * This software was developed by SRI International and the University of 6256752Sbrooks * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249) 7256752Sbrooks * ("MRC2"), as part of the DARPA MRC research programme. 8256752Sbrooks * 9256752Sbrooks * Redistribution and use in source and binary forms, with or without 10256752Sbrooks * modification, are permitted provided that the following conditions 11256752Sbrooks * are met: 12256752Sbrooks * 1. Redistributions of source code must retain the above copyright 13256752Sbrooks * notice, this list of conditions and the following disclaimer. 14256752Sbrooks * 2. Redistributions in binary form must reproduce the above copyright 15256752Sbrooks * notice, this list of conditions and the following disclaimer in the 16256752Sbrooks * documentation and/or other materials provided with the distribution. 17256752Sbrooks * 18256752Sbrooks * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19256752Sbrooks * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20256752Sbrooks * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21256752Sbrooks * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22256752Sbrooks * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23256752Sbrooks * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24256752Sbrooks * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25256752Sbrooks * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26256752Sbrooks * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27256752Sbrooks * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28256752Sbrooks * SUCH DAMAGE. 29256752Sbrooks * 30256752Sbrooks * $FreeBSD$ 31256752Sbrooks */ 32256752Sbrooks/* 33256752Sbrooks * Altera, Embedded Peripherals IP, User Guide, v. 11.0, June 2011. 34256752Sbrooks * UG-01085-11.0. 35256752Sbrooks */ 36256752Sbrooks 37256752Sbrooks#ifndef _A_API_H 38256752Sbrooks#define _A_API_H 39256752Sbrooks 40256752Sbrooks/* Table 16-1. Memory Map. */ 41256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_DATA 0x00 42256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_METADATA 0x04 43256752Sbrooks 44256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_SOP (1<<0) 45256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_EOP (1<<1) 46256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_EMPTY_MASK 0x000000f7 47256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT 2 48256752Sbrooks /* Reserved (1<<7) */ 49256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_CHANNEL_MASK 0x0000ff00 50256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_CHANNEL_SHIFT 8 51256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK 0x00ff0000 52256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT 16 53256752Sbrooks /* Reserved 0xff000000 */ 54256752Sbrooks 55256752Sbrooks/* Table 16-3. FIFO Status Register Memory Map. */ 56256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_FILL_LEVEL 0x00 57256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_I_STATUS 0x04 58256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT 0x08 59256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_INT_ENABLE 0x0c 60256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_ALMOSTFULL 0x10 61256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_ALMOSTEMPTY 0x14 62256752Sbrooks 63256752Sbrooks/* Table 16-5. Status Bit Field Descriptions. */ 64256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_FULL (1<<0) 65256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_EMPTY (1<<1) 66256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_ALMOSTFULL (1<<2) 67256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_ALMOSTEMPTY (1<<3) 68256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_OVERFLOW (1<<4) 69256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_STATUS_UNDERFLOW (1<<5) 70256752Sbrooks 71256752Sbrooks/* Table 16-6. Event Bit Field Descriptions. */ 72271969Sbz/* XXX Datasheet has incorrect bit fields. Validate. */ 73271969Sbz#define A_ONCHIP_FIFO_MEM_CORE_EVENT_FULL (1<<0) 74271969Sbz#define A_ONCHIP_FIFO_MEM_CORE_EVENT_EMPTY (1<<1) 75271969Sbz#define A_ONCHIP_FIFO_MEM_CORE_EVENT_ALMOSTFULL (1<<2) 76271969Sbz#define A_ONCHIP_FIFO_MEM_CORE_EVENT_ALMOSTEMPTY (1<<3) 77256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW (1<<4) 78256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW (1<<5) 79256752Sbrooks 80256752Sbrooks/* Table 16-7. InterruptEnable Bit Field Descriptions. */ 81271969Sbz/* XXX Datasheet has incorrect bit fields. Validate. */ 82271969Sbz#define A_ONCHIP_FIFO_MEM_CORE_INTR_FULL (1<<0) 83271969Sbz#define A_ONCHIP_FIFO_MEM_CORE_INTR_EMPTY (1<<1) 84271969Sbz#define A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTFULL (1<<2) 85271969Sbz#define A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTEMPTY (1<<3) 86256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW (1<<4) 87256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW (1<<5) 88256752Sbrooks#define A_ONCHIP_FIFO_MEM_CORE_INTR_ALL \ 89256752Sbrooks (A_ONCHIP_FIFO_MEM_CORE_INTR_EMPTY| \ 90256752Sbrooks A_ONCHIP_FIFO_MEM_CORE_INTR_FULL| \ 91256752Sbrooks A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTEMPTY| \ 92256752Sbrooks A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTFULL| \ 93256752Sbrooks A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW| \ 94256752Sbrooks A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW) 95256752Sbrooks 96256752Sbrooks#endif /* _A_API_H */ 97256752Sbrooks 98256752Sbrooks/* end */ 99