aic7xxx.h revision 63944
1/* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 63944 2000-07-27 23:17:52Z gibbs $ 34 */ 35 36#ifndef _AIC7XXX_H_ 37#define _AIC7XXX_H_ 38 39#include "opt_aic7xxx.h" /* for config options */ 40#include "aic7xxx_reg.h" 41 42#include <sys/bus.h> /* For device_t */ 43 44#ifndef MAX 45#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 46#endif 47 48#ifndef MIN 49#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 50#endif 51 52/* 53 * The maximum number of supported targets. 54 */ 55#define AHC_NUM_TARGETS 16 56 57/* 58 * The maximum number of supported luns. 59 * The identify message supports up to 64 luns in SPI3. 60 */ 61#define AHC_NUM_LUNS 64 62 63/* 64 * The maximum transfer per S/G segment. 65 */ 66#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 67 68/* 69 * The number of dma segments supported. The sequencer can handle any number 70 * of physically contiguous S/G entrys. To reduce the driver's memory 71 * consumption, we limit the number supported to be sufficient to handle 72 * the largest mapping supported by the kernel, MAXPHYS. Assuming the 73 * transfer is as fragmented as possible and unaligned, this turns out to 74 * be the number of paged sized transfers in MAXPHYS plus an extra element 75 * to handle any unaligned residual. The sequencer fetches SG elements 76 * in 128 byte chucks, so make the number per-transaction a nice multiple 77 * of 16 (8 byte S/G elements). 78 */ 79/* XXX Worth the space??? */ 80#define AHC_NSEG (roundup(btoc(MAXPHYS) + 1, 16)) 81 82#define AHC_SCB_MAX 255 /* 83 * Up to 255 SCBs on some types of aic7xxx 84 * based boards. The aic7870 have 16 internal 85 * SCBs, but external SRAM bumps this to 255. 86 * The aic7770 family have only 4, and the 87 * aic7850 has only 3. 88 */ 89 90#define AHC_TMODE_CMDS 256 /* 91 * Ring Buffer of incoming target commands. 92 * We allocate 256 to simplify the logic 93 * in the sequencer by using the natural 94 * wrap point of an 8bit counter. 95 */ 96 97/* 98 * The aic7xxx chips only support a 24bit length. We use the top 99 * byte of the length to store additional address bits as well 100 * as an indicator if this is the last SG segment in a transfer. 101 * This gives us an addressable range of 512GB on machines with 102 * 64bit PCI or with chips that can support dual address cycles 103 * on 32bit PCI busses. 104 */ 105struct ahc_dma_seg { 106 uint32_t addr; 107 uint32_t len; 108#define AHC_DMA_LAST_SEG 0x80000000 109#define AHC_SG_HIGH_ADDR_MASK 0x7F000000 110#define AHC_SG_LEN_MASK 0x00FFFFFF 111}; 112 113/* The chip order is from least sophisticated to most sophisticated */ 114typedef enum { 115 AHC_NONE = 0x0000, 116 AHC_CHIPID_MASK = 0x00FF, 117 AHC_AIC7770 = 0x0001, 118 AHC_AIC7850 = 0x0002, 119 AHC_AIC7855 = 0x0003, 120 AHC_AIC7859 = 0x0004, 121 AHC_AIC7860 = 0x0005, 122 AHC_AIC7870 = 0x0006, 123 AHC_AIC7880 = 0x0007, 124 AHC_AIC7895 = 0x0008, 125 AHC_AIC7890 = 0x0009, 126 AHC_AIC7896 = 0x000a, 127 AHC_AIC7892 = 0x000b, 128 AHC_AIC7899 = 0x000c, 129 AHC_VL = 0x0100, /* Bus type VL */ 130 AHC_EISA = 0x0200, /* Bus type EISA */ 131 AHC_PCI = 0x0400, /* Bus type PCI */ 132 AHC_BUS_MASK = 0x0F00 133} ahc_chip; 134 135extern char *ahc_chip_names[]; 136 137typedef enum { 138 AHC_FENONE = 0x0000, 139 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 140 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 141 AHC_WIDE = 0x0004, /* Wide Channel */ 142 AHC_TWIN = 0x0008, /* Twin Channel */ 143 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 144 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 145 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 146 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 147 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 148 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 149 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 150 AHC_DT = 0x0800, /* Double Transition transfers */ 151 AHC_NEW_TERMCTL = 0x1000, 152 AHC_MULTI_FUNC = 0x2000, /* Multi-Function Twin Channel Device */ 153 AHC_LARGE_SCBS = 0x4000, /* 64byte SCBs */ 154 AHC_AIC7770_FE = AHC_FENONE, 155 AHC_AIC7850_FE = AHC_SPIOCAP, 156 AHC_AIC7855_FE = AHC_AIC7850_FE, 157 AHC_AIC7859_FE = AHC_AIC7850_FE|AHC_ULTRA, 158 AHC_AIC7860_FE = AHC_AIC7859_FE, 159 AHC_AIC7870_FE = AHC_FENONE, 160 AHC_AIC7880_FE = AHC_ULTRA, 161 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 162 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 163 |AHC_NEW_TERMCTL|AHC_LARGE_SCBS, 164 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT, 165 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM 166 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 167 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 168 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 169 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 170} ahc_feature; 171 172typedef enum { 173 AHC_BUGNONE = 0x00, 174 /* 175 * On all chips prior to the U2 product line, 176 * the WIDEODD S/G segment feature does not 177 * work during scsi->HostBus transfers. 178 */ 179 AHC_TMODE_WIDEODD_BUG = 0x01, 180 /* 181 * On the aic7890/91 Rev 0 chips, the autoflush 182 * feature does not work. A manual flush of 183 * the DMA FIFO is required. 184 */ 185 AHC_AUTOFLUSH_BUG = 0x02, 186 /* 187 * On the aic7890/91 Rev 0 chips, cacheline 188 * streaming does not work. 189 */ 190 AHC_CACHETHEN_BUG = 0x04, 191 /* 192 * On the aic7896/97 chips, cacheline 193 * streaming must be enabled. 194 */ 195 AHC_CACHETHEN_DIS_BUG = 0x08 196} ahc_bug; 197 198typedef enum { 199 AHC_FNONE = 0x000, 200 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 201 AHC_CHANNEL_B_PRIMARY = 0x002,/* 202 * On twin channel adapters, probe 203 * channel B first since it is the 204 * primary bus. 205 */ 206 AHC_USEDEFAULTS = 0x004,/* 207 * For cards without an seeprom 208 * or a BIOS to initialize the chip's 209 * SRAM, we use the default target 210 * settings. 211 */ 212 AHC_SHARED_SRAM = 0x010, 213 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 214 AHC_RESET_BUS_A = 0x040, 215 AHC_RESET_BUS_B = 0x080, 216 AHC_EXTENDED_TRANS_A = 0x100, 217 AHC_EXTENDED_TRANS_B = 0x200, 218 AHC_TERM_ENB_A = 0x400, 219 AHC_TERM_ENB_B = 0x800, 220 AHC_INITIATORMODE = 0x1000,/* 221 * Allow initiator operations on 222 * this controller. 223 */ 224 AHC_TARGETMODE = 0x2000,/* 225 * Allow target operations on this 226 * controller. 227 */ 228 AHC_NEWEEPROM_FMT = 0x4000, 229 AHC_RESOURCE_SHORTAGE = 0x8000, 230 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 231 AHC_INT50_SPEEDFLEX = 0x20000,/* 232 * Internal 50pin connector 233 * sits behind an aic3860 234 */ 235 AHC_SCB_BTT = 0x40000 /* 236 * The busy targets table is 237 * stored in SCB space rather 238 * than SRAM. 239 */ 240} ahc_flag; 241 242struct ahc_probe_config { 243 const char *description; 244 char channel; 245 char channel_b; 246 ahc_chip chip; 247 ahc_feature features; 248 ahc_bug bugs; 249 ahc_flag flags; 250}; 251 252typedef enum { 253 SCB_FREE = 0x0000, 254 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 255 * Another device was active 256 * during the first timeout for 257 * this SCB so we gave ourselves 258 * an additional timeout period 259 * in case it was hogging the 260 * bus. 261 */ 262 SCB_DEVICE_RESET = 0x0004, 263 SCB_SENSE = 0x0008, 264 SCB_RECOVERY_SCB = 0x0040, 265 SCB_NEGOTIATE = 0x0080, 266 SCB_ABORT = 0x1000, 267 SCB_QUEUED_MSG = 0x2000, 268 SCB_ACTIVE = 0x4000, 269 SCB_TARGET_IMMEDIATE = 0x8000 270} scb_flag; 271 272/* 273 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 274 * consists of a "hardware SCB" mirroring the fields availible on the card 275 * and additional information the kernel stores for each transaction. 276 * 277 * To minimize space utilization, a portion of the hardware scb stores 278 * different data during different portions of a SCSI transaction. 279 * As initialized by the host driver for the initiator role, this area 280 * contains the SCSI cdb (or pointer to the cdb) to be executed. After 281 * the cdb has been presented to the target, this area serves to store 282 * residual transfer information and the SCSI status byte. 283 * For the target role, the contents of this area do not change, but 284 * still serve a different purpose than for the initiator role. See 285 * struct target_data for details. 286 */ 287 288struct status_pkt { 289 uint32_t residual_datacnt; 290 uint32_t residual_sg_ptr; 291 uint8_t scsi_status; 292}; 293 294struct target_data { 295 uint8_t target_phases; 296 uint8_t data_phase; 297 uint8_t scsi_status; 298 uint8_t initiator_tag; 299}; 300 301struct hardware_scb { 302/*0*/ uint8_t control; 303/*1*/ uint8_t scsiid; /* what to load in the SCSIID register */ 304/*2*/ uint8_t lun; 305/*3*/ uint8_t cdb_len; 306/*4*/ union { 307 /* 308 * 12 bytes of cdb information only 309 * used on chips with 32byte SCBs. 310 */ 311 uint8_t cdb[12]; 312 uint32_t cdb_ptr; 313 struct status_pkt status; 314 struct target_data tdata; 315 } shared_data; 316/* 317 * A word about residuals. The scb is presented to the sequencer with 318 * the dataptr and datacnt fields initialized to the contents of the 319 * first S/G element to transfer. The sgptr field is initialized to 320 * the bus address for the S/G element that follows the first in the 321 * in core S/G array or'ed with the SG_FULL_RESID flag. Sgptr may point 322 * to an invalid S/G entry for this transfer. If no transfer is to occur, 323 * sgptr is set to SG_LIST_NULL. The SG_FULL_RESID flag insures that 324 * the residual will be correctly noted even if no data transfers occur. 325 * Once the data phase is entered, the residual sgptr and datacnt are 326 * loaded from the sgptr and the datacnt fields. After each S/G element's 327 * dataptr and length are loaded into the hardware, the residual sgptr 328 * is advanced. After each S/G element is expired, its datacnt field 329 * is checked to see if the LAST_SEG flag is set. If so, SG_LIST_NULL 330 * is set in the residual sg ptr and the transfer is considered complete. 331 * If the sequencer determines that three is a residual in the tranfer, 332 * it will set the SG_RESID_VALID flag in sgptr and dma the scb back into 333 * host memory. To sumarize: 334 * 335 * Sequencer: 336 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 337 * or residual_sgptr does not have SG_LIST_NULL set. 338 * 339 * o We are transfering the last segment if residual_datacnt has 340 * the SG_LAST_SEG flag set. 341 * 342 * Host: 343 * o A residual has occurred if a completed scb has the 344 * SG_RESID_VALID flag set. 345 * 346 * o residual_sgptr and sgptr refer to the "next" sg entry 347 * and so may point beyond the last valid sg entry for the 348 * transfer. 349 */ 350/*16*/ uint32_t dataptr; 351/*20*/ uint32_t datacnt; /* 352 * The highest address byte is 353 * really the 5th. byte in the 354 * dataptr. 355 */ 356/*24*/ uint32_t sgptr; 357#define SG_PTR_MASK 0xFFFFFFF8 358/*28*/ uint8_t tag; /* Index into our kernel SCB array. 359 * Also used as the tag for tagged I/O 360 */ 361/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 362/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 363/*31*/ uint8_t next; /* Used for threading SCBs in the 364 * "Waiting for Selection" and 365 * "Disconnected SCB" lists down 366 * in the sequencer. 367 */ 368/*32*/ uint8_t cdb32[32]; /* 369 * CDB storage for controllers 370 * supporting 64 byte SCBs. 371 */ 372}; 373 374struct scb { 375 struct hardware_scb *hscb; 376 union { 377 SLIST_ENTRY(scb) sle; 378 TAILQ_ENTRY(scb) tqe; 379 } links; 380 union ccb *ccb; /* the ccb for this cmd */ 381 scb_flag flags; 382 bus_dmamap_t dmamap; 383 struct ahc_dma_seg *sg_list; 384 bus_addr_t sg_list_phys; 385 bus_addr_t cdb32_busaddr; 386 u_int sg_count;/* How full ahc_dma_seg is */ 387}; 388 389/* 390 * Connection desciptor for select-in requests in target mode. 391 * The first byte is the connecting target, followed by identify 392 * message and optional tag information, terminated by 0xFF. The 393 * remainder is the command to execute. The cmd_valid byte is on 394 * an 8 byte boundary to simplify setting it on aic7880 hardware 395 * which only has limited direct access to the DMA FIFO. 396 */ 397struct target_cmd { 398 uint8_t scsiid; 399 uint8_t identify; /* Identify message */ 400 uint8_t bytes[22]; 401 uint8_t cmd_valid; 402 uint8_t pad[7]; 403}; 404 405/* 406 * Number of events we can buffer up if we run out 407 * of immediate notify ccbs. 408 */ 409#define AHC_TMODE_EVENT_BUFFER_SIZE 8 410struct ahc_tmode_event { 411 uint8_t initiator_id; 412 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 413#define EVENT_TYPE_BUS_RESET 0xFF 414 uint8_t event_arg; 415}; 416 417/* 418 * Per lun target mode state including accept TIO CCB 419 * and immediate notify CCB pools. 420 */ 421struct tmode_lstate { 422 struct cam_path *path; 423 struct ccb_hdr_slist accept_tios; 424 struct ccb_hdr_slist immed_notifies; 425 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 426 uint8_t event_r_idx; 427 uint8_t event_w_idx; 428}; 429 430#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 431#define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 432#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 433#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 434 435struct ahc_transinfo { 436 uint8_t protocol_version; 437 uint8_t transport_version; 438 uint8_t width; 439 uint8_t period; 440 uint8_t offset; 441 uint8_t ppr_options; 442}; 443 444struct ahc_initiator_tinfo { 445 uint8_t scsirate; 446 struct ahc_transinfo current; 447 struct ahc_transinfo goal; 448 struct ahc_transinfo user; 449}; 450 451/* 452 * Per target mode enabled target state. Esentially just an array of 453 * pointers to lun target state as well as sync/wide negotiation information 454 * for each initiator<->target mapping (including the mapping for when we 455 * are the initiator). 456 */ 457struct tmode_tstate { 458 struct tmode_lstate* enabled_luns[64]; 459 struct ahc_initiator_tinfo transinfo[16]; 460 461 /* 462 * Per initiator state bitmasks. 463 */ 464 uint16_t ultraenb; /* Using ultra sync rate */ 465 uint16_t discenable; /* Disconnection allowed */ 466 uint16_t tagenable; /* Tagged Queuing allowed */ 467}; 468 469/* 470 * Define the format of the aic7XXX SEEPROM registers (16 bits). 471 */ 472 473struct seeprom_config { 474/* 475 * SCSI ID Configuration Flags 476 */ 477 uint16_t device_flags[16]; /* words 0-15 */ 478#define CFXFER 0x0007 /* synchronous transfer rate */ 479#define CFSYNCH 0x0008 /* enable synchronous transfer */ 480#define CFDISC 0x0010 /* enable disconnection */ 481#define CFWIDEB 0x0020 /* wide bus device */ 482#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 483#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 484#define CFSTART 0x0100 /* send start unit SCSI command */ 485#define CFINCBIOS 0x0200 /* include in BIOS scan */ 486#define CFRNFOUND 0x0400 /* report even if not found */ 487#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 488#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 489#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 490 491/* 492 * BIOS Control Bits 493 */ 494 uint16_t bios_control; /* word 16 */ 495#define CFSUPREM 0x0001 /* support all removeable drives */ 496#define CFSUPREMB 0x0002 /* support removeable boot drives */ 497#define CFBIOSEN 0x0004 /* BIOS enabled */ 498/* UNUSED 0x0008 */ 499#define CFSM2DRV 0x0010 /* support more than two drives */ 500#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 501#define CFSTPWLEVEL 0x0010 /* Termination level control */ 502#define CFEXTEND 0x0080 /* extended translation enabled */ 503#define CFSCAMEN 0x0100 /* SCAM enable */ 504/* UNUSED 0xff00 */ 505 506/* 507 * Host Adapter Control Bits 508 */ 509 uint16_t adapter_control; /* word 17 */ 510#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 511#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 512#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 513#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 514#define CFSTERM 0x0004 /* SCSI low byte termination */ 515#define CFWSTERM 0x0008 /* SCSI high byte termination */ 516#define CFSPARITY 0x0010 /* SCSI parity */ 517#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 518#define CFMULTILUN 0x0020 /* SCSI low byte term (284x cards) */ 519#define CFRESETB 0x0040 /* reset SCSI bus at boot */ 520#define CFCLUSTERENB 0x0080 /* Cluster Enable */ 521#define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 522#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 523#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 524#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 525#define CFDOMAINVAL 0x4000 /* Perform Domain Validation*/ 526 527/* 528 * Bus Release, Host Adapter ID 529 */ 530 uint16_t brtime_id; /* word 18 */ 531#define CFSCSIID 0x000f /* host adapter SCSI ID */ 532/* UNUSED 0x00f0 */ 533#define CFBRTIME 0xff00 /* bus release time */ 534 535/* 536 * Maximum targets 537 */ 538 uint16_t max_targets; /* word 19 */ 539#define CFMAXTARG 0x00ff /* maximum targets */ 540#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 541#define CFBOOTID 0xf000 /* Target to boot from */ 542 uint16_t res_1[10]; /* words 20-29 */ 543 uint16_t signature; /* Signature == 0x250 */ 544#define CFSIGNATURE 0x250 545 uint16_t checksum; /* word 31 */ 546}; 547 548struct ahc_syncrate { 549 u_int sxfr_u2; 550 u_int sxfr; 551 /* Rates in Ultra mode have bit 8 of sxfr set */ 552#define ULTRA_SXFR 0x100 553#define ST_SXFR 0x010 /* Rate Single Transition Only */ 554#define DT_SXFR 0x040 /* Rate Double Transition Only */ 555 uint8_t period; /* Period to send to SCSI target */ 556 char *rate; 557}; 558 559typedef enum { 560 MSG_TYPE_NONE = 0x00, 561 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 562 MSG_TYPE_INITIATOR_MSGIN = 0x02, 563 MSG_TYPE_TARGET_MSGOUT = 0x03, 564 MSG_TYPE_TARGET_MSGIN = 0x04 565} ahc_msg_type; 566 567struct sg_map_node { 568 bus_dmamap_t sg_dmamap; 569 bus_addr_t sg_physaddr; 570 struct ahc_dma_seg* sg_vaddr; 571 SLIST_ENTRY(sg_map_node) links; 572}; 573 574struct scb_data { 575 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 576 struct scb *scbarray; /* Array of kernel SCBs */ 577 SLIST_HEAD(, scb) free_scbs; /* 578 * Pool of SCBs ready to be assigned 579 * commands to execute. 580 */ 581 struct scsi_sense_data *sense; /* Per SCB sense data */ 582 583 /* 584 * "Bus" addresses of our data structures. 585 */ 586 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 587 bus_dmamap_t hscb_dmamap; 588 bus_addr_t hscb_busaddr; 589 bus_dma_tag_t sense_dmat; 590 bus_dmamap_t sense_dmamap; 591 bus_addr_t sense_busaddr; 592 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 593 SLIST_HEAD(, sg_map_node) sg_maps; 594 uint8_t numscbs; 595 uint8_t maxhscbs; /* Number of SCBs on the card */ 596 uint8_t init_level; /* 597 * How far we've initialized 598 * this structure. 599 */ 600}; 601 602TAILQ_HEAD(scb_tailq, scb); 603 604struct ahc_softc { 605 bus_space_tag_t tag; 606 bus_space_handle_t bsh; 607 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 608 struct scb_data *scb_data; 609 610 /* 611 * CCBs that have been sent to the controller 612 */ 613 LIST_HEAD(, ccb_hdr) pending_ccbs; 614 615 /* 616 * Counting lock for deferring the release of additional 617 * untagged transactions from the untagged_queues. When 618 * the lock is decremented to 0, all queues in the 619 * untagged_queues array are run. 620 */ 621 u_int untagged_queue_lock; 622 623 /* 624 * Per-target queue of untagged-transactions. The 625 * transaction at the head of the queue is the 626 * currently pending untagged transaction for the 627 * target. The driver only allows a single untagged 628 * transaction per target. 629 */ 630 struct scb_tailq untagged_queues[16]; 631 632 /* 633 * Target mode related state kept on a per enabled lun basis. 634 * Targets that are not enabled will have null entries. 635 * As an initiator, we keep one target entry for our initiator 636 * ID to store our sync/wide transfer settings. 637 */ 638 struct tmode_tstate* enabled_targets[16]; 639 640 /* 641 * The black hole device responsible for handling requests for 642 * disabled luns on enabled targets. 643 */ 644 struct tmode_lstate* black_hole; 645 646 /* 647 * Device instance currently on the bus awaiting a continue TIO 648 * for a command that was not given the disconnect priveledge. 649 */ 650 struct tmode_lstate* pending_device; 651 652 /* 653 * Card characteristics 654 */ 655 ahc_chip chip; 656 ahc_feature features; 657 ahc_bug bugs; 658 ahc_flag flags; 659 660 /* Values to store in the SEQCTL register for pause and unpause */ 661 uint8_t unpause; 662 uint8_t pause; 663 664 /* Command Queues */ 665 uint8_t qoutfifonext; 666 uint8_t qinfifonext; 667 uint8_t *qoutfifo; 668 uint8_t *qinfifo; 669 670 /* 671 * Hooks into the XPT. 672 */ 673 struct cam_sim *sim; 674 struct cam_sim *sim_b; 675 struct cam_path *path; 676 struct cam_path *path_b; 677 678 int unit; 679 680 /* Channel Names ('A', 'B', etc.) */ 681 char channel; 682 char channel_b; 683 684 /* Initiator Bus ID */ 685 uint8_t our_id; 686 uint8_t our_id_b; 687 688 /* Targets that need negotiation messages */ 689 uint16_t targ_msg_req; 690 691 /* 692 * PCI error detection and data for running the 693 * PCI error interrupt handler. 694 */ 695 int unsolicited_ints; 696 device_t device; 697 698 /* 699 * Target incoming command FIFO. 700 */ 701 struct target_cmd *targetcmds; 702 uint8_t tqinfifonext; 703 704 /* 705 * Incoming and outgoing message handling. 706 */ 707 uint8_t send_msg_perror; 708 ahc_msg_type msg_type; 709 uint8_t msgout_buf[8]; /* Message we are sending */ 710 uint8_t msgin_buf[8]; /* Message we are receiving */ 711 u_int msgout_len; /* Length of message to send */ 712 u_int msgout_index; /* Current index in msgout */ 713 u_int msgin_index; /* Current index in msgin */ 714 715 int regs_res_type; 716 int regs_res_id; 717 int irq_res_type; 718 struct resource *regs; 719 struct resource *irq; 720 void *ih; 721 bus_dma_tag_t parent_dmat; 722 bus_dma_tag_t shared_data_dmat; 723 bus_dmamap_t shared_data_dmamap; 724 bus_addr_t shared_data_busaddr; 725 bus_addr_t dma_bug_buf; 726 727 /* Number of enabled target mode device on this card */ 728 u_int enabled_luns; 729 730 /* Initialization level of this data structure */ 731 u_int init_level; 732 733 uint16_t user_discenable;/* Disconnection allowed */ 734 uint16_t user_tagenable;/* Tagged Queuing allowed */ 735}; 736 737struct full_ahc_softc { 738 struct ahc_softc softc; 739 struct scb_data scb_data_storage; 740}; 741 742/* #define AHC_DEBUG */ 743#ifdef AHC_DEBUG 744/* Different debugging levels used when AHC_DEBUG is defined */ 745#define AHC_SHOWMISC 0x0001 746#define AHC_SHOWCMDS 0x0002 747#define AHC_SHOWSCBS 0x0004 748#define AHC_SHOWABORTS 0x0008 749#define AHC_SHOWSENSE 0x0010 750#define AHC_SHOWSCBCNT 0x0020 751 752extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 753#endif 754 755#define ahc_inb(ahc, port) \ 756 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 757 758#define ahc_outb(ahc, port, value) \ 759 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 760 761#define ahc_outsb(ahc, port, valp, count) \ 762 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 763 764#define ahc_insb(ahc, port, valp, count) \ 765 bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 766 767char *ahc_name(struct ahc_softc *ahc); 768 769void ahc_init_probe_config(struct ahc_probe_config *config); 770struct ahc_softc* 771 ahc_alloc(device_t dev, struct resource *regs, int regs_type, 772 int regs_id, bus_dma_tag_t parent_dmat, 773 struct ahc_probe_config *config, struct scb_data *scb_data); 774int ahc_reset(struct ahc_softc *ahc); 775void ahc_free(struct ahc_softc *); 776int ahc_probe_scbs(struct ahc_softc *); 777int ahc_init(struct ahc_softc *); 778int ahc_attach(struct ahc_softc *); 779void ahc_intr(void *arg); 780static __inline int sequencer_paused(struct ahc_softc *ahc); 781static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc); 782static __inline void pause_sequencer(struct ahc_softc *ahc); 783static __inline void unpause_sequencer(struct ahc_softc *ahc); 784 785static __inline void 786ahc_pause_bug_fix(struct ahc_softc *ahc) 787{ 788 /* 789 * Clear the CIOBUS stretch signal by reading a register that will 790 * set this signal and deassert it. Without this workaround, if 791 * the chip is paused, by an interrupt or manual pause, while 792 * accessing scb ram, then accesses to certain registers will hang 793 * the system (infinite pci retries). 794 */ 795 if ((ahc->features & AHC_ULTRA2) != 0) 796 (void)ahc_inb(ahc, CCSCBCTL); 797} 798 799static __inline int 800sequencer_paused(struct ahc_softc *ahc) 801{ 802 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 803} 804 805static __inline void 806pause_sequencer(struct ahc_softc *ahc) 807{ 808 ahc_outb(ahc, HCNTRL, ahc->pause); 809 810 /* 811 * Since the sequencer can disable pausing in a critical section, we 812 * must loop until it actually stops. 813 */ 814 while (sequencer_paused(ahc) == 0) 815 ; 816 817 ahc_pause_bug_fix(ahc); 818} 819 820static __inline void 821unpause_sequencer(struct ahc_softc *ahc) 822{ 823 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 824 ahc_outb(ahc, HCNTRL, ahc->unpause); 825} 826 827#endif /* _AIC7XXX_H_ */ 828