aic7xxx.h revision 41646
1/* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $Id: aic7xxx.h,v 1.2 1998/11/23 01:33:47 gibbs Exp $ 38 */ 39 40#ifndef _AIC7XXX_H_ 41#define _AIC7XXX_H_ 42 43#include "ahc.h" /* for NAHC from config */ 44#include "opt_aic7xxx.h" /* for config options */ 45 46#include <pci/pcivar.h> /* for pcici_t */ 47 48#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 49#define AHC_NSEG 32 /* The number of dma segments supported. 50 * AHC_NSEG can be maxed out at 256 entries, 51 * but the kernel will never need to transfer 52 * such a large (1MB) request. To reduce the 53 * driver's memory consumption, we reduce the 54 * max to 32. 16 would work if all transfers 55 * are paged alined since the kernel will only 56 * generate at most a 64k transfer, but to 57 * handle non-page aligned transfers, you need 58 * 17, so we round to the next power of two 59 * to make allocating SG space easy and 60 * efficient. 61 */ 62 63#define AHC_SCB_MAX 255 /* 64 * Up to 255 SCBs on some types of aic7xxx 65 * based boards. The aic7870 have 16 internal 66 * SCBs, but external SRAM bumps this to 255. 67 * The aic7770 family have only 4, and the 68 * aic7850 has only 3. 69 */ 70 71#define AHC_TMODE_CMDS 256 /* 72 * Ring Buffer of incoming target commands. 73 * We allocate 256 to simplify the logic 74 * in the sequencer by using the natural 75 * wrap point of an 8bit counter. 76 */ 77 78#if defined(__FreeBSD__) 79extern u_long ahc_unit; 80#endif 81 82struct ahc_dma_seg { 83 u_int32_t addr; 84 u_int32_t len; 85}; 86 87typedef enum { 88 AHC_NONE = 0x0000, 89 AHC_CHIPID_MASK = 0x00FF, 90 AHC_AIC7770 = 0x0001, 91 AHC_AIC7850 = 0x0002, 92 AHC_AIC7860 = 0x0003, 93 AHC_AIC7870 = 0x0004, 94 AHC_AIC7880 = 0x0005, 95 AHC_AIC7890 = 0x0006, 96 AHC_AIC7895 = 0x0007, 97 AHC_AIC7896 = 0x0008, 98 AHC_VL = 0x0100, /* Bus type VL */ 99 AHC_EISA = 0x0200, /* Bus type EISA */ 100 AHC_PCI = 0x0400, /* Bus type PCI */ 101} ahc_chip; 102 103typedef enum { 104 AHC_FENONE = 0x0000, 105 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 106 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 107 AHC_WIDE = 0x0004, /* Wide Channel */ 108 AHC_TWIN = 0x0008, /* Twin Channel */ 109 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 110 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 111 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 112 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 113 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 114 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 115 AHC_AIC7770_FE = AHC_FENONE, 116 AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP, 117 AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP, 118 AHC_AIC7870_FE = AHC_FENONE, 119 AHC_AIC7880_FE = AHC_ULTRA, 120 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID, 121 AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA, 122 AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID, 123} ahc_feature; 124 125typedef enum { 126 AHC_FNONE = 0x000, 127 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 128 AHC_CHANNEL_B_PRIMARY = 0x002,/* 129 * On twin channel adapters, probe 130 * channel B first since it is the 131 * primary bus. 132 */ 133 AHC_USEDEFAULTS = 0x004,/* 134 * For cards without an seeprom 135 * or a BIOS to initialize the chip's 136 * SRAM, we use the default target 137 * settings. 138 */ 139 AHC_INDIRECT_PAGING = 0x008, 140 AHC_SHARED_SRAM = 0x010, 141 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 142 AHC_EXTENDED_TRANS_A = 0x100, 143 AHC_EXTENDED_TRANS_B = 0x200, 144 AHC_TERM_ENB_A = 0x400, 145 AHC_TERM_ENB_B = 0x800, 146 AHC_INITIATORMODE = 0x1000,/* 147 * Allow initiator operations on 148 * this controller. 149 */ 150 AHC_TARGETMODE = 0x2000,/* 151 * Allow target operations on this 152 * controller. 153 */ 154 AHC_NEWEEPROM_FMT = 0x4000, 155 AHC_RESOURCE_SHORTAGE = 0x8000 156} ahc_flag; 157 158typedef enum { 159 SCB_FREE = 0x0000, 160 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 161 * Another device was active 162 * during the first timeout for 163 * this SCB so we gave ourselves 164 * an additional timeout period 165 * in case it was hogging the 166 * bus. 167 */ 168 SCB_DEVICE_RESET = 0x0004, 169 SCB_SENSE = 0x0008, 170 SCB_RECOVERY_SCB = 0x0040, 171 SCB_ABORT = 0x1000, 172 SCB_QUEUED_MSG = 0x2000, 173 SCB_ACTIVE = 0x4000, 174 SCB_TARGET_IMMEDIATE = 0x8000 175} scb_flag; 176 177/* 178 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 179 * consists of a "hardware SCB" mirroring the fields availible on the card 180 * and additional information the kernel stores for each transaction. 181 */ 182struct hardware_scb { 183/*0*/ u_int8_t control; 184/*1*/ u_int8_t tcl; /* 4/1/3 bits */ 185/*2*/ u_int8_t status; 186/*3*/ u_int8_t SG_count; 187/*4*/ u_int32_t SG_pointer; 188/*8*/ u_int8_t residual_SG_count; 189/*9*/ u_int8_t residual_data_count[3]; 190/*12*/ u_int32_t data; 191/*16*/ u_int32_t datalen; /* Really only three bytes, but its 192 * faster to treat it as a long on 193 * a quad boundary. 194 */ 195/*20*/ u_int32_t cmdpointer; 196/*24*/ u_int8_t cmdlen; 197/*25*/ u_int8_t tag; /* Index into our kernel SCB array. 198 * Also used as the tag for tagged I/O 199 */ 200/*26*/ u_int8_t next; /* Used for threading SCBs in the 201 * "Waiting for Selection" and 202 * "Disconnected SCB" lists down 203 * in the sequencer. 204 */ 205/*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 206/*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 207/*29*/ u_int8_t spare[3]; /* 208 * Spare space available on 209 * all controller types. 210 */ 211/*32*/ u_int8_t cmdstore[16]; /* 212 * CDB storage for controllers 213 * supporting 64 byte SCBs. 214 */ 215/*48*/ u_int32_t cmdstore_busaddr; /* 216 * Address of command store for 217 * 32byte SCB adapters 218 */ 219/*48*/ u_int8_t spare_64[12]; /* 220 * Pad to 64 bytes. 221 */ 222}; 223 224struct scb { 225 struct hardware_scb *hscb; 226 STAILQ_ENTRY(scb) links; /* for chaining */ 227 union ccb *ccb; /* the ccb for this cmd */ 228 scb_flag flags; 229 bus_dmamap_t dmamap; 230 struct ahc_dma_seg *ahc_dma;/* Pointer to SG segments */ 231 u_int32_t ahc_dmaphys;/* Phsical address of SG list */ 232 u_int sg_count;/* How full ahc_dma_seg is */ 233}; 234 235struct scb_data { 236 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 237 struct scb *scbarray[AHC_SCB_MAX]; /* Array of kernel SCBs */ 238 STAILQ_HEAD(, scb) free_scbs; /* 239 * Pool of SCBs ready to be assigned 240 * commands to execute. 241 */ 242 u_int8_t numscbs; 243 u_int8_t maxhscbs; /* Number of SCBs on the card */ 244 u_int8_t maxscbs; /* 245 * Max SCBs we allocate total including 246 * any that will force us to page SCBs 247 */ 248}; 249 250/* 251 * Connection desciptor for select-in requests in target mode. 252 * The first byte is the connecting target, followed by identify 253 * message and optional tag information, terminated by 0xFF. The 254 * remainder is the command to execute. The cmd_valid byte is on 255 * an 8 byte boundary to simplify setting it on aic7880 hardware 256 * which only has limited direct access to the DMA FIFO. 257 */ 258struct target_cmd { 259 u_int8_t initiator_channel; 260 u_int8_t targ_id; /* Target ID we were selected at */ 261 u_int8_t identify; /* Identify message */ 262 u_int8_t bytes[21]; 263 u_int8_t cmd_valid; 264 u_int8_t pad[7]; 265}; 266 267/* 268 * Per lun target mode state including accept TIO CCB 269 * and immediate notify CCB pools. 270 */ 271struct tmode_lstate { 272 SLIST_HEAD(, ccb_hdr) accept_tios; 273 SLIST_HEAD(, ccb_hdr) immed_notifies; 274}; 275 276/* 277 * Per target mode enabled target state. Esentially just an array of 278 * pointers to lun target state. 279 */ 280struct tmode_tstate { 281 struct tmode_lstate* enabled_luns[8]; 282}; 283 284/* 285 * Define the format of the aic7XX0 SEEPROM registers (16 bits). 286 */ 287 288struct seeprom_config { 289/* 290 * SCSI ID Configuration Flags 291 */ 292 u_int16_t device_flags[16]; /* words 0-15 */ 293#define CFXFER 0x0007 /* synchronous transfer rate */ 294#define CFSYNCH 0x0008 /* enable synchronous transfer */ 295#define CFDISC 0x0010 /* enable disconnection */ 296#define CFWIDEB 0x0020 /* wide bus device */ 297#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 298/* UNUSED 0x0080 */ 299#define CFSTART 0x0100 /* send start unit SCSI command */ 300#define CFINCBIOS 0x0200 /* include in BIOS scan */ 301#define CFRNFOUND 0x0400 /* report even if not found */ 302#define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 303/* UNUSED 0xf000 */ 304 305/* 306 * BIOS Control Bits 307 */ 308 u_int16_t bios_control; /* word 16 */ 309#define CFSUPREM 0x0001 /* support all removeable drives */ 310#define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 311#define CFBIOSEN 0x0004 /* BIOS enabled */ 312/* UNUSED 0x0008 */ 313#define CFSM2DRV 0x0010 /* support more than two drives */ 314#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 315/* UNUSED 0x0060 */ 316#define CFEXTEND 0x0080 /* extended translation enabled */ 317/* UNUSED 0xff00 */ 318 319/* 320 * Host Adapter Control Bits 321 */ 322 u_int16_t adapter_control; /* word 17 */ 323#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 324#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 325#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 326#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 327#define CFSTERM 0x0004 /* SCSI low byte termination */ 328#define CFWSTERM 0x0008 /* SCSI high byte termination */ 329#define CFSPARITY 0x0010 /* SCSI parity */ 330#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 331#define CFRESETB 0x0040 /* reset SCSI bus at boot */ 332#define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 333#define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 334#define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 335/* UNUSED 0xf080 */ 336 337/* 338 * Bus Release, Host Adapter ID 339 */ 340 u_int16_t brtime_id; /* word 18 */ 341#define CFSCSIID 0x000f /* host adapter SCSI ID */ 342/* UNUSED 0x00f0 */ 343#define CFBRTIME 0xff00 /* bus release time */ 344 345/* 346 * Maximum targets 347 */ 348 u_int16_t max_targets; /* word 19 */ 349#define CFMAXTARG 0x00ff /* maximum targets */ 350/* UNUSED 0xff00 */ 351 u_int16_t res_1[11]; /* words 20-30 */ 352 u_int16_t checksum; /* word 31 */ 353}; 354 355#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 356#define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 357#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 358#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 359 360struct ahc_transinfo { 361 u_int8_t width; 362 u_int8_t period; 363 u_int8_t offset; 364}; 365 366struct ahc_target_tinfo { 367 u_int8_t scsirate; 368 struct ahc_transinfo current; 369 struct ahc_transinfo goal; 370 struct ahc_transinfo user; 371}; 372 373struct ahc_syncrate { 374 int sxfr_ultra2; 375 int sxfr; 376 /* Rates in Ultra mode have bit 8 of sxfr set */ 377#define ULTRA_SXFR 0x100 378 u_int8_t period; /* Period to send to SCSI target */ 379 char *rate; 380}; 381 382typedef enum { 383 MSG_TYPE_NONE = 0x00, 384 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 385 MSG_TYPE_INITIATOR_MSGIN = 0x02, 386 MSG_TYPE_TARGET_MSGOUT = 0x03, 387 MSG_TYPE_TARGET_MSGIN = 0x04 388} ahc_msg_type; 389 390struct ahc_softc { 391 bus_space_tag_t tag; 392 bus_space_handle_t bsh; 393 bus_dma_tag_t dmat; 394 struct scb_data *scb_data; 395 396 /* 397 * CCBs that have been send to the controller 398 */ 399 LIST_HEAD(, ccb_hdr) pending_ccbs; 400 401 /* 402 * Target mode related state kept on a per enabled lun basis. 403 * Targets that are not enabled will have null entries. 404 */ 405 struct tmode_tstate* enabled_targets[16]; 406 407 /* 408 * Device instance currently on the bus awaiting a continue TIO 409 * for a command that was not given the disconnect priveledge. 410 */ 411 struct tmode_lstate* pending_device; 412 413 /* 414 * Card characteristics 415 */ 416 ahc_chip chip; 417 ahc_feature features; 418 ahc_flag flags; 419 420 /* Values to store in the SEQCTL register for pause and unpause */ 421 u_int8_t unpause; 422 u_int8_t pause; 423 424 /* Command Queues */ 425 u_int8_t qoutfifonext; 426 u_int8_t qinfifonext; 427 u_int8_t qoutfifo[256]; 428 u_int8_t qinfifo[256]; 429 430 /* 431 * 256 byte array storing the SCBID of outstanding 432 * untagged SCBs indexed by TCL. 433 */ 434 u_int8_t untagged_scbs[256]; 435 436 /* 437 * User/Current/Active Negotiation settings 438 */ 439 struct ahc_target_tinfo transinfo[16]; 440 441 /* 442 * Per target state bitmasks. 443 */ 444 u_int16_t ultraenb; /* Using ultra sync rate */ 445 u_int16_t discenable; /* Disconnection allowed */ 446 u_int16_t tagenable; /* Tagged Queuing allowed */ 447 u_int16_t targ_msg_req; /* Need negotiation messages */ 448 449 /* 450 * Hooks into the XPT. 451 */ 452 struct cam_sim *sim; 453 struct cam_sim *sim_b; 454 struct cam_path *path; 455 struct cam_path *path_b; 456 457 int unit; 458 459 /* Channel Names ('A', 'B', etc.) */ 460 char channel; 461 char channel_b; 462 463 /* Initiator Bus ID */ 464 u_int8_t our_id; 465 u_int8_t our_id_b; 466 467 /* 468 * PCI error detection and data for running the 469 * PCI error interrupt handler. 470 */ 471 int unsolicited_ints; 472 pcici_t pci_config_id; 473 474 /* 475 * Target incoming command FIFO. 476 */ 477 struct target_cmd *targetcmds; 478 u_int8_t tqinfifonext; 479 480 /* 481 * Incoming and outgoing message handling. 482 */ 483 u_int8_t send_msg_perror; 484 ahc_msg_type msg_type; 485 u_int8_t msgout_buf[8]; /* Message we are sending */ 486 u_int8_t msgin_buf[8]; /* Message we are receiving */ 487 u_int msgout_len; /* Length of message to send */ 488 u_int msgout_index; /* Current index in msgout */ 489 u_int msgin_index; /* Current index in msgin */ 490 491 /* 492 * "Bus" addresses of our data structures. 493 */ 494 u_int32_t hscb_busaddr; 495}; 496 497struct full_ahc_softc { 498 struct ahc_softc softc; 499 struct scb_data scb_data_storage; 500}; 501 502/* #define AHC_DEBUG */ 503#ifdef AHC_DEBUG 504/* Different debugging levels used when AHC_DEBUG is defined */ 505#define AHC_SHOWMISC 0x0001 506#define AHC_SHOWCMDS 0x0002 507#define AHC_SHOWSCBS 0x0004 508#define AHC_SHOWABORTS 0x0008 509#define AHC_SHOWSENSE 0x0010 510#define AHC_SHOWSCBCNT 0x0020 511 512extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 513#endif 514 515char *ahc_name(struct ahc_softc *ahc); 516 517struct ahc_softc *ahc_alloc(int unit, u_int32_t io_base, 518 vm_offset_t maddr, ahc_chip chip, 519 ahc_feature features, ahc_flag flags, 520 struct scb_data *scb_data); 521int ahc_reset(struct ahc_softc *ahc); 522void ahc_free(struct ahc_softc *); 523int ahc_probe_scbs(struct ahc_softc *); 524int ahc_init(struct ahc_softc *); 525int ahc_attach(struct ahc_softc *); 526void ahc_intr(void *arg); 527 528#define ahc_inb(ahc, port) \ 529 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 530 531#define ahc_outb(ahc, port, value) \ 532 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 533 534#define ahc_outsb(ahc, port, valp, count) \ 535 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 536 537#endif /* _AIC7XXX_H_ */ 538