aic7xxx.h revision 107420
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#62 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 107420 2002-11-30 19:30:09Z scottl $ 43 */ 44 45#ifndef _AIC7XXX_H_ 46#define _AIC7XXX_H_ 47 48/* Register Definitions */ 49#include "aic7xxx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahc_platform_data; 53struct scb_platform_data; 54struct seeprom_descriptor; 55 56/****************************** Useful Macros *********************************/ 57#ifndef MAX 58#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 59#endif 60 61#ifndef MIN 62#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 63#endif 64 65#ifndef TRUE 66#define TRUE 1 67#endif 68#ifndef FALSE 69#define FALSE 0 70#endif 71 72#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 73 74#define ALL_CHANNELS '\0' 75#define ALL_TARGETS_MASK 0xFFFF 76#define INITIATOR_WILDCARD (~0) 77 78#define SCSIID_TARGET(ahc, scsiid) \ 79 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 80 >> TID_SHIFT) 81#define SCSIID_OUR_ID(scsiid) \ 82 ((scsiid) & OID) 83#define SCSIID_CHANNEL(ahc, scsiid) \ 84 ((((ahc)->features & AHC_TWIN) != 0) \ 85 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 86 : 'A') 87#define SCB_IS_SCSIBUS_B(ahc, scb) \ 88 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 89#define SCB_GET_OUR_ID(scb) \ 90 SCSIID_OUR_ID((scb)->hscb->scsiid) 91#define SCB_GET_TARGET(ahc, scb) \ 92 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 93#define SCB_GET_CHANNEL(ahc, scb) \ 94 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 95#define SCB_GET_LUN(scb) \ 96 ((scb)->hscb->lun) 97#define SCB_GET_TARGET_OFFSET(ahc, scb) \ 98 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 99#define SCB_GET_TARGET_MASK(ahc, scb) \ 100 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 101#define TCL_TARGET_OFFSET(tcl) \ 102 ((((tcl) >> 4) & TID) >> 4) 103#define TCL_LUN(tcl) \ 104 (tcl & (AHC_NUM_LUNS - 1)) 105#define BUILD_TCL(scsiid, lun) \ 106 ((lun) | (((scsiid) & TID) << 4)) 107 108#ifndef AHC_TARGET_MODE 109#undef AHC_TMODE_ENABLE 110#define AHC_TMODE_ENABLE 0 111#endif 112 113/**************************** Driver Constants ********************************/ 114/* 115 * The maximum number of supported targets. 116 */ 117#define AHC_NUM_TARGETS 16 118 119/* 120 * The maximum number of supported luns. 121 * The identify message only supports 64 luns in SPI3. 122 * You can have 2^64 luns when information unit transfers are enabled, 123 * but it is doubtful this driver will ever support IUTs. 124 */ 125#define AHC_NUM_LUNS 64 126 127/* 128 * The maximum transfer per S/G segment. 129 */ 130#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 131 132/* 133 * The maximum amount of SCB storage in hardware on a controller. 134 * This value represents an upper bound. Controllers vary in the number 135 * they actually support. 136 */ 137#define AHC_SCB_MAX 255 138 139/* 140 * The maximum number of concurrent transactions supported per driver instance. 141 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 142 * the space for SCBs on the host adapter varies by model, the driver will 143 * page the SCBs between host and controller memory as needed. We are limited 144 * to 253 because: 145 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 146 * 2) We reserve one value, 255, to represent the invalid element. 147 * 3) Our input queue scheme requires one SCB to always be reserved 148 * in advance of queuing any SCBs. This takes us down to 254. 149 * 4) To handle our output queue correctly on machines that only 150 * support 32bit stores, we must clear the array 4 bytes at a 151 * time. To avoid colliding with a DMA write from the sequencer, 152 * we must be sure that 4 slots are empty when we write to clear 153 * the queue. This reduces us to 253 SCBs: 1 that just completed 154 * and the known three additional empty slots in the queue that 155 * precede it. 156 */ 157#define AHC_MAX_QUEUE 253 158 159/* 160 * The maximum amount of SCB storage we allocate in host memory. This 161 * number should reflect the 1 additional SCB we require to handle our 162 * qinfifo mechanism. 163 */ 164#define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 165 166/* 167 * Ring Buffer of incoming target commands. 168 * We allocate 256 to simplify the logic in the sequencer 169 * by using the natural wrap point of an 8bit counter. 170 */ 171#define AHC_TMODE_CMDS 256 172 173/* Reset line assertion time in us */ 174#define AHC_BUSRESET_DELAY 25 175 176/******************* Chip Characteristics/Operating Settings *****************/ 177/* 178 * Chip Type 179 * The chip order is from least sophisticated to most sophisticated. 180 */ 181typedef enum { 182 AHC_NONE = 0x0000, 183 AHC_CHIPID_MASK = 0x00FF, 184 AHC_AIC7770 = 0x0001, 185 AHC_AIC7850 = 0x0002, 186 AHC_AIC7855 = 0x0003, 187 AHC_AIC7859 = 0x0004, 188 AHC_AIC7860 = 0x0005, 189 AHC_AIC7870 = 0x0006, 190 AHC_AIC7880 = 0x0007, 191 AHC_AIC7895 = 0x0008, 192 AHC_AIC7895C = 0x0009, 193 AHC_AIC7890 = 0x000a, 194 AHC_AIC7896 = 0x000b, 195 AHC_AIC7892 = 0x000c, 196 AHC_AIC7899 = 0x000d, 197 AHC_VL = 0x0100, /* Bus type VL */ 198 AHC_EISA = 0x0200, /* Bus type EISA */ 199 AHC_PCI = 0x0400, /* Bus type PCI */ 200 AHC_BUS_MASK = 0x0F00 201} ahc_chip; 202 203/* 204 * Features available in each chip type. 205 */ 206typedef enum { 207 AHC_FENONE = 0x00000, 208 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 209 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 210 AHC_WIDE = 0x00004, /* Wide Channel */ 211 AHC_TWIN = 0x00008, /* Twin Channel */ 212 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 213 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 214 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 215 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 216 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 217 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 218 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 219 AHC_DT = 0x00800, /* Double Transition transfers */ 220 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 221 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 222 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 223 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 224 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 225 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 226 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 227 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 228 AHC_AIC7770_FE = AHC_FENONE, 229 /* 230 * The real 7850 does not support Ultra modes, but there are 231 * several cards that use the generic 7850 PCI ID even though 232 * they are using an Ultra capable chip (7859/7860). We start 233 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 234 * register to determine if the capability is really present. 235 */ 236 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 237 AHC_AIC7860_FE = AHC_AIC7850_FE, 238 AHC_AIC7870_FE = AHC_TARGETMODE, 239 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 240 /* 241 * Although we have space for both the initiator and 242 * target roles on ULTRA2 chips, we currently disable 243 * the initiator role to allow multi-scsi-id target mode 244 * configurations. We can only respond on the same SCSI 245 * ID as our initiator role if we allow initiator operation. 246 * At some point, we should add a configuration knob to 247 * allow both roles to be loaded. 248 */ 249 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 250 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 251 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 252 |AHC_TARGETMODE, 253 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 254 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 255 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 256 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 257 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 258 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 259} ahc_feature; 260 261/* 262 * Bugs in the silicon that we work around in software. 263 */ 264typedef enum { 265 AHC_BUGNONE = 0x00, 266 /* 267 * On all chips prior to the U2 product line, 268 * the WIDEODD S/G segment feature does not 269 * work during scsi->HostBus transfers. 270 */ 271 AHC_TMODE_WIDEODD_BUG = 0x01, 272 /* 273 * On the aic7890/91 Rev 0 chips, the autoflush 274 * feature does not work. A manual flush of 275 * the DMA FIFO is required. 276 */ 277 AHC_AUTOFLUSH_BUG = 0x02, 278 /* 279 * On many chips, cacheline streaming does not work. 280 */ 281 AHC_CACHETHEN_BUG = 0x04, 282 /* 283 * On the aic7896/97 chips, cacheline 284 * streaming must be enabled. 285 */ 286 AHC_CACHETHEN_DIS_BUG = 0x08, 287 /* 288 * PCI 2.1 Retry failure on non-empty data fifo. 289 */ 290 AHC_PCI_2_1_RETRY_BUG = 0x10, 291 /* 292 * Controller does not handle cacheline residuals 293 * properly on S/G segments if PCI MWI instructions 294 * are allowed. 295 */ 296 AHC_PCI_MWI_BUG = 0x20, 297 /* 298 * An SCB upload using the SCB channel's 299 * auto array entry copy feature may 300 * corrupt data. This appears to only 301 * occur on 66MHz systems. 302 */ 303 AHC_SCBCHAN_UPLOAD_BUG = 0x40 304} ahc_bug; 305 306/* 307 * Configuration specific settings. 308 * The driver determines these settings by probing the 309 * chip/controller's configuration. 310 */ 311typedef enum { 312 AHC_FNONE = 0x000, 313 AHC_PRIMARY_CHANNEL = 0x003,/* 314 * The channel that should 315 * be probed first. 316 */ 317 AHC_USEDEFAULTS = 0x004,/* 318 * For cards without an seeprom 319 * or a BIOS to initialize the chip's 320 * SRAM, we use the default target 321 * settings. 322 */ 323 AHC_SEQUENCER_DEBUG = 0x008, 324 AHC_SHARED_SRAM = 0x010, 325 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 326 AHC_RESET_BUS_A = 0x040, 327 AHC_RESET_BUS_B = 0x080, 328 AHC_EXTENDED_TRANS_A = 0x100, 329 AHC_EXTENDED_TRANS_B = 0x200, 330 AHC_TERM_ENB_A = 0x400, 331 AHC_TERM_ENB_B = 0x800, 332 AHC_INITIATORROLE = 0x1000,/* 333 * Allow initiator operations on 334 * this controller. 335 */ 336 AHC_TARGETROLE = 0x2000,/* 337 * Allow target operations on this 338 * controller. 339 */ 340 AHC_NEWEEPROM_FMT = 0x4000, 341 AHC_RESOURCE_SHORTAGE = 0x8000, 342 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 343 AHC_INT50_SPEEDFLEX = 0x20000,/* 344 * Internal 50pin connector 345 * sits behind an aic3860 346 */ 347 AHC_SCB_BTT = 0x40000,/* 348 * The busy targets table is 349 * stored in SCB space rather 350 * than SRAM. 351 */ 352 AHC_BIOS_ENABLED = 0x80000, 353 AHC_ALL_INTERRUPTS = 0x100000, 354 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 355 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 356 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 357 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 358 AHC_SCB_CONFIG_USED = 0x4000000 /* No SEEPROM but SCB2 had info. */ 359} ahc_flag; 360 361/************************* Hardware SCB Definition ***************************/ 362 363/* 364 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 365 * consists of a "hardware SCB" mirroring the fields availible on the card 366 * and additional information the kernel stores for each transaction. 367 * 368 * To minimize space utilization, a portion of the hardware scb stores 369 * different data during different portions of a SCSI transaction. 370 * As initialized by the host driver for the initiator role, this area 371 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 372 * the cdb has been presented to the target, this area serves to store 373 * residual transfer information and the SCSI status byte. 374 * For the target role, the contents of this area do not change, but 375 * still serve a different purpose than for the initiator role. See 376 * struct target_data for details. 377 */ 378 379/* 380 * Status information embedded in the shared poriton of 381 * an SCB after passing the cdb to the target. The kernel 382 * driver will only read this data for transactions that 383 * complete abnormally (non-zero status byte). 384 */ 385struct status_pkt { 386 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 387 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 388 uint8_t scsi_status; /* Standard SCSI status byte */ 389}; 390 391/* 392 * Target mode version of the shared data SCB segment. 393 */ 394struct target_data { 395 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 396 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 397 uint8_t scsi_status; /* SCSI status to give to initiator */ 398 uint8_t target_phases; /* Bitmap of phases to execute */ 399 uint8_t data_phase; /* Data-In or Data-Out */ 400 uint8_t initiator_tag; /* Initiator's transaction tag */ 401}; 402 403struct hardware_scb { 404/*0*/ union { 405 /* 406 * If the cdb is 12 bytes or less, we embed it directly 407 * in the SCB. For longer cdbs, we embed the address 408 * of the cdb payload as seen by the chip and a DMA 409 * is used to pull it in. 410 */ 411 uint8_t cdb[12]; 412 uint32_t cdb_ptr; 413 struct status_pkt status; 414 struct target_data tdata; 415 } shared_data; 416/* 417 * A word about residuals. 418 * The scb is presented to the sequencer with the dataptr and datacnt 419 * fields initialized to the contents of the first S/G element to 420 * transfer. The sgptr field is initialized to the bus address for 421 * the S/G element that follows the first in the in core S/G array 422 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 423 * S/G entry for this transfer (single S/G element transfer with the 424 * first elements address and length preloaded in the dataptr/datacnt 425 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 426 * The SG_FULL_RESID flag ensures that the residual will be correctly 427 * noted even if no data transfers occur. Once the data phase is entered, 428 * the residual sgptr and datacnt are loaded from the sgptr and the 429 * datacnt fields. After each S/G element's dataptr and length are 430 * loaded into the hardware, the residual sgptr is advanced. After 431 * each S/G element is expired, its datacnt field is checked to see 432 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 433 * residual sg ptr and the transfer is considered complete. If the 434 * sequencer determines that there is a residual in the tranfer, it 435 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 436 * host memory. To sumarize: 437 * 438 * Sequencer: 439 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 440 * or residual_sgptr does not have SG_LIST_NULL set. 441 * 442 * o We are transfering the last segment if residual_datacnt has 443 * the SG_LAST_SEG flag set. 444 * 445 * Host: 446 * o A residual has occurred if a completed scb has the 447 * SG_RESID_VALID flag set. 448 * 449 * o residual_sgptr and sgptr refer to the "next" sg entry 450 * and so may point beyond the last valid sg entry for the 451 * transfer. 452 */ 453/*12*/ uint32_t dataptr; 454/*16*/ uint32_t datacnt; /* 455 * Byte 3 (numbered from 0) of 456 * the datacnt is really the 457 * 4th byte in that data address. 458 */ 459/*20*/ uint32_t sgptr; 460#define SG_PTR_MASK 0xFFFFFFF8 461/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 462/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 463/*26*/ uint8_t lun; 464/*27*/ uint8_t tag; /* 465 * Index into our kernel SCB array. 466 * Also used as the tag for tagged I/O 467 */ 468/*28*/ uint8_t cdb_len; 469/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 470/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 471/*31*/ uint8_t next; /* 472 * Used for threading SCBs in the 473 * "Waiting for Selection" and 474 * "Disconnected SCB" lists down 475 * in the sequencer. 476 */ 477/*32*/ uint8_t cdb32[32]; /* 478 * CDB storage for cdbs of size 479 * 13->32. We store them here 480 * because hardware scbs are 481 * allocated from DMA safe 482 * memory so we are guaranteed 483 * the controller can access 484 * this data. 485 */ 486}; 487 488/************************ Kernel SCB Definitions ******************************/ 489/* 490 * Some fields of the SCB are OS dependent. Here we collect the 491 * definitions for elements that all OS platforms need to include 492 * in there SCB definition. 493 */ 494 495/* 496 * Definition of a scatter/gather element as transfered to the controller. 497 * The aic7xxx chips only support a 24bit length. We use the top byte of 498 * the length to store additional address bits and a flag to indicate 499 * that a given segment terminates the transfer. This gives us an 500 * addressable range of 512GB on machines with 64bit PCI or with chips 501 * that can support dual address cycles on 32bit PCI busses. 502 */ 503struct ahc_dma_seg { 504 uint32_t addr; 505 uint32_t len; 506#define AHC_DMA_LAST_SEG 0x80000000 507#define AHC_SG_HIGH_ADDR_MASK 0x7F000000 508#define AHC_SG_LEN_MASK 0x00FFFFFF 509}; 510 511struct sg_map_node { 512 bus_dmamap_t sg_dmamap; 513 bus_addr_t sg_physaddr; 514 struct ahc_dma_seg* sg_vaddr; 515 SLIST_ENTRY(sg_map_node) links; 516}; 517 518/* 519 * The current state of this SCB. 520 */ 521typedef enum { 522 SCB_FREE = 0x0000, 523 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 524 * Another device was active 525 * during the first timeout for 526 * this SCB so we gave ourselves 527 * an additional timeout period 528 * in case it was hogging the 529 * bus. 530 */ 531 SCB_DEVICE_RESET = 0x0004, 532 SCB_SENSE = 0x0008, 533 SCB_CDB32_PTR = 0x0010, 534 SCB_RECOVERY_SCB = 0x0020, 535 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 536 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 537 SCB_ABORT = 0x0100, 538 SCB_UNTAGGEDQ = 0x0200, 539 SCB_ACTIVE = 0x0400, 540 SCB_TARGET_IMMEDIATE = 0x0800, 541 SCB_TRANSMISSION_ERROR = 0x1000,/* 542 * We detected a parity or CRC 543 * error that has effected the 544 * payload of the command. This 545 * flag is checked when normal 546 * status is returned to catch 547 * the case of a target not 548 * responding to our attempt 549 * to report the error. 550 */ 551 SCB_TARGET_SCB = 0x2000 552} scb_flag; 553 554struct scb { 555 struct hardware_scb *hscb; 556 union { 557 SLIST_ENTRY(scb) sle; 558 TAILQ_ENTRY(scb) tqe; 559 } links; 560 LIST_ENTRY(scb) pending_links; 561 ahc_io_ctx_t io_ctx; 562 struct ahc_softc *ahc_softc; 563 scb_flag flags; 564#ifndef __linux__ 565 bus_dmamap_t dmamap; 566#endif 567 struct scb_platform_data *platform_data; 568 struct sg_map_node *sg_map; 569 struct ahc_dma_seg *sg_list; 570 bus_addr_t sg_list_phys; 571 u_int sg_count;/* How full ahc_dma_seg is */ 572}; 573 574struct scb_data { 575 SLIST_HEAD(, scb) free_scbs; /* 576 * Pool of SCBs ready to be assigned 577 * commands to execute. 578 */ 579 struct scb *scbindex[256]; /* 580 * Mapping from tag to SCB. 581 * As tag identifiers are an 582 * 8bit value, we provide space 583 * for all possible tag values. 584 * Any lookups to entries at or 585 * above AHC_SCB_MAX_ALLOC will 586 * always fail. 587 */ 588 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 589 struct scb *scbarray; /* Array of kernel SCBs */ 590 struct scsi_sense_data *sense; /* Per SCB sense data */ 591 592 /* 593 * "Bus" addresses of our data structures. 594 */ 595 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 596 bus_dmamap_t hscb_dmamap; 597 bus_addr_t hscb_busaddr; 598 bus_dma_tag_t sense_dmat; 599 bus_dmamap_t sense_dmamap; 600 bus_addr_t sense_busaddr; 601 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 602 SLIST_HEAD(, sg_map_node) sg_maps; 603 uint8_t numscbs; 604 uint8_t maxhscbs; /* Number of SCBs on the card */ 605 uint8_t init_level; /* 606 * How far we've initialized 607 * this structure. 608 */ 609}; 610 611/************************ Target Mode Definitions *****************************/ 612 613/* 614 * Connection desciptor for select-in requests in target mode. 615 */ 616struct target_cmd { 617 uint8_t scsiid; /* Our ID and the initiator's ID */ 618 uint8_t identify; /* Identify message */ 619 uint8_t bytes[22]; /* 620 * Bytes contains any additional message 621 * bytes terminated by 0xFF. The remainder 622 * is the cdb to execute. 623 */ 624 uint8_t cmd_valid; /* 625 * When a command is complete, the firmware 626 * will set cmd_valid to all bits set. 627 * After the host has seen the command, 628 * the bits are cleared. This allows us 629 * to just peek at host memory to determine 630 * if more work is complete. cmd_valid is on 631 * an 8 byte boundary to simplify setting 632 * it on aic7880 hardware which only has 633 * limited direct access to the DMA FIFO. 634 */ 635 uint8_t pad[7]; 636}; 637 638/* 639 * Number of events we can buffer up if we run out 640 * of immediate notify ccbs. 641 */ 642#define AHC_TMODE_EVENT_BUFFER_SIZE 8 643struct ahc_tmode_event { 644 uint8_t initiator_id; 645 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 646#define EVENT_TYPE_BUS_RESET 0xFF 647 uint8_t event_arg; 648}; 649 650/* 651 * Per enabled lun target mode state. 652 * As this state is directly influenced by the host OS'es target mode 653 * environment, we let the OS module define it. Forward declare the 654 * structure here so we can store arrays of them, etc. in OS neutral 655 * data structures. 656 */ 657#ifdef AHC_TARGET_MODE 658struct ahc_tmode_lstate { 659 struct cam_path *path; 660 struct ccb_hdr_slist accept_tios; 661 struct ccb_hdr_slist immed_notifies; 662 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 663 uint8_t event_r_idx; 664 uint8_t event_w_idx; 665}; 666#else 667struct ahc_tmode_lstate; 668#endif 669 670/******************** Transfer Negotiation Datastructures *********************/ 671#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 672#define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 673#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 674#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 675 676#define AHC_WIDTH_UNKNOWN 0xFF 677#define AHC_PERIOD_UNKNOWN 0xFF 678#define AHC_OFFSET_UNKNOWN 0x0 679#define AHC_PPR_OPTS_UNKNOWN 0xFF 680 681/* 682 * Transfer Negotiation Information. 683 */ 684struct ahc_transinfo { 685 uint8_t protocol_version; /* SCSI Revision level */ 686 uint8_t transport_version; /* SPI Revision level */ 687 uint8_t width; /* Bus width */ 688 uint8_t period; /* Sync rate factor */ 689 uint8_t offset; /* Sync offset */ 690 uint8_t ppr_options; /* Parallel Protocol Request options */ 691}; 692 693/* 694 * Per-initiator current, goal and user transfer negotiation information. */ 695struct ahc_initiator_tinfo { 696 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 697 struct ahc_transinfo curr; 698 struct ahc_transinfo goal; 699 struct ahc_transinfo user; 700}; 701 702/* 703 * Per enabled target ID state. 704 * Pointers to lun target state as well as sync/wide negotiation information 705 * for each initiator<->target mapping. For the initiator role we pretend 706 * that we are the target and the targets are the initiators since the 707 * negotiation is the same regardless of role. 708 */ 709struct ahc_tmode_tstate { 710 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 711 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 712 713 /* 714 * Per initiator state bitmasks. 715 */ 716 uint16_t auto_negotiate;/* Auto Negotiation Required */ 717 uint16_t ultraenb; /* Using ultra sync rate */ 718 uint16_t discenable; /* Disconnection allowed */ 719 uint16_t tagenable; /* Tagged Queuing allowed */ 720}; 721 722/* 723 * Data structure for our table of allowed synchronous transfer rates. 724 */ 725struct ahc_syncrate { 726 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 727 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 728#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 729#define ST_SXFR 0x010 /* Rate Single Transition Only */ 730#define DT_SXFR 0x040 /* Rate Double Transition Only */ 731 uint8_t period; /* Period to send to SCSI target */ 732 char *rate; 733}; 734 735/* Safe and valid period for async negotiations. */ 736#define AHC_ASYNC_XFER_PERIOD 0x44 737#define AHC_ULTRA2_XFER_PERIOD 0x0a 738 739/* 740 * Indexes into our table of syncronous transfer rates. 741 */ 742#define AHC_SYNCRATE_DT 0 743#define AHC_SYNCRATE_ULTRA2 1 744#define AHC_SYNCRATE_ULTRA 3 745#define AHC_SYNCRATE_FAST 6 746 747/***************************** Lookup Tables **********************************/ 748/* 749 * Phase -> name and message out response 750 * to parity errors in each phase table. 751 */ 752struct ahc_phase_table_entry { 753 uint8_t phase; 754 uint8_t mesg_out; /* Message response to parity errors */ 755 char *phasemsg; 756}; 757 758/************************** Serial EEPROM Format ******************************/ 759 760struct seeprom_config { 761/* 762 * Per SCSI ID Configuration Flags 763 */ 764 uint16_t device_flags[16]; /* words 0-15 */ 765#define CFXFER 0x0007 /* synchronous transfer rate */ 766#define CFSYNCH 0x0008 /* enable synchronous transfer */ 767#define CFDISC 0x0010 /* enable disconnection */ 768#define CFWIDEB 0x0020 /* wide bus device */ 769#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 770#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 771#define CFSTART 0x0100 /* send start unit SCSI command */ 772#define CFINCBIOS 0x0200 /* include in BIOS scan */ 773#define CFRNFOUND 0x0400 /* report even if not found */ 774#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 775#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 776#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 777 778/* 779 * BIOS Control Bits 780 */ 781 uint16_t bios_control; /* word 16 */ 782#define CFSUPREM 0x0001 /* support all removeable drives */ 783#define CFSUPREMB 0x0002 /* support removeable boot drives */ 784#define CFBIOSEN 0x0004 /* BIOS enabled */ 785#define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 786#define CFSM2DRV 0x0010 /* support more than two drives */ 787#define CFSTPWLEVEL 0x0010 /* Termination level control */ 788#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 789#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 790#define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 791#define CFEXTEND 0x0080 /* extended translation enabled */ 792#define CFSCAMEN 0x0100 /* SCAM enable */ 793#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 794#define CFMSG_VERBOSE 0x0000 795#define CFMSG_SILENT 0x0200 796#define CFMSG_DIAG 0x0400 797#define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 798/* UNUSED 0xff00 */ 799 800/* 801 * Host Adapter Control Bits 802 */ 803 uint16_t adapter_control; /* word 17 */ 804#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 805#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 806#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 807#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 808#define CFSTERM 0x0004 /* SCSI low byte termination */ 809#define CFWSTERM 0x0008 /* SCSI high byte termination */ 810#define CFSPARITY 0x0010 /* SCSI parity */ 811#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 812#define CFMULTILUN 0x0020 813#define CFRESETB 0x0040 /* reset SCSI bus at boot */ 814#define CFCLUSTERENB 0x0080 /* Cluster Enable */ 815#define CFBOOTCHAN 0x0300 /* probe this channel first */ 816#define CFBOOTCHANSHIFT 8 817#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 818#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 819#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 820#define CFENABLEDV 0x4000 /* Perform Domain Validation*/ 821 822/* 823 * Bus Release Time, Host Adapter ID 824 */ 825 uint16_t brtime_id; /* word 18 */ 826#define CFSCSIID 0x000f /* host adapter SCSI ID */ 827/* UNUSED 0x00f0 */ 828#define CFBRTIME 0xff00 /* bus release time */ 829 830/* 831 * Maximum targets 832 */ 833 uint16_t max_targets; /* word 19 */ 834#define CFMAXTARG 0x00ff /* maximum targets */ 835#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 836#define CFBOOTID 0xf000 /* Target to boot from */ 837 uint16_t res_1[10]; /* words 20-29 */ 838 uint16_t signature; /* Signature == 0x250 */ 839#define CFSIGNATURE 0x250 840#define CFSIGNATURE2 0x300 841 uint16_t checksum; /* word 31 */ 842}; 843 844/**************************** Message Buffer *********************************/ 845typedef enum { 846 MSG_TYPE_NONE = 0x00, 847 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 848 MSG_TYPE_INITIATOR_MSGIN = 0x02, 849 MSG_TYPE_TARGET_MSGOUT = 0x03, 850 MSG_TYPE_TARGET_MSGIN = 0x04 851} ahc_msg_type; 852 853typedef enum { 854 MSGLOOP_IN_PROG, 855 MSGLOOP_MSGCOMPLETE, 856 MSGLOOP_TERMINATED 857} msg_loop_stat; 858 859/*********************** Software Configuration Structure *********************/ 860TAILQ_HEAD(scb_tailq, scb); 861 862struct ahc_suspend_channel_state { 863 uint8_t scsiseq; 864 uint8_t sxfrctl0; 865 uint8_t sxfrctl1; 866 uint8_t simode0; 867 uint8_t simode1; 868 uint8_t seltimer; 869 uint8_t seqctl; 870}; 871 872struct ahc_suspend_state { 873 struct ahc_suspend_channel_state channel[2]; 874 uint8_t optionmode; 875 uint8_t dscommand0; 876 uint8_t dspcistatus; 877 /* hsmailbox */ 878 uint8_t crccontrol1; 879 uint8_t scbbaddr; 880 /* Host and sequencer SCB counts */ 881 uint8_t dff_thrsh; 882 uint8_t *scratch_ram; 883 uint8_t *btt; 884}; 885 886typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 887typedef void ahc_callback_t (void *); 888 889struct ahc_softc { 890 bus_space_tag_t tag; 891 bus_space_handle_t bsh; 892#ifndef __linux__ 893 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 894#endif 895 struct scb_data *scb_data; 896 897 struct scb *next_queued_scb; 898 899 /* 900 * SCBs that have been sent to the controller 901 */ 902 LIST_HEAD(, scb) pending_scbs; 903 904 /* 905 * Counting lock for deferring the release of additional 906 * untagged transactions from the untagged_queues. When 907 * the lock is decremented to 0, all queues in the 908 * untagged_queues array are run. 909 */ 910 u_int untagged_queue_lock; 911 912 /* 913 * Per-target queue of untagged-transactions. The 914 * transaction at the head of the queue is the 915 * currently pending untagged transaction for the 916 * target. The driver only allows a single untagged 917 * transaction per target. 918 */ 919 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 920 921 /* 922 * Platform specific data. 923 */ 924 struct ahc_platform_data *platform_data; 925 926 /* 927 * Platform specific device information. 928 */ 929 ahc_dev_softc_t dev_softc; 930 931 /* 932 * Bus specific device information. 933 */ 934 ahc_bus_intr_t bus_intr; 935 936 /* 937 * Target mode related state kept on a per enabled lun basis. 938 * Targets that are not enabled will have null entries. 939 * As an initiator, we keep one target entry for our initiator 940 * ID to store our sync/wide transfer settings. 941 */ 942 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 943 944 /* 945 * The black hole device responsible for handling requests for 946 * disabled luns on enabled targets. 947 */ 948 struct ahc_tmode_lstate *black_hole; 949 950 /* 951 * Device instance currently on the bus awaiting a continue TIO 952 * for a command that was not given the disconnect priveledge. 953 */ 954 struct ahc_tmode_lstate *pending_device; 955 956 /* 957 * Card characteristics 958 */ 959 ahc_chip chip; 960 ahc_feature features; 961 ahc_bug bugs; 962 ahc_flag flags; 963 struct seeprom_config *seep_config; 964 965 /* Values to store in the SEQCTL register for pause and unpause */ 966 uint8_t unpause; 967 uint8_t pause; 968 969 /* Command Queues */ 970 uint8_t qoutfifonext; 971 uint8_t qinfifonext; 972 uint8_t *qoutfifo; 973 uint8_t *qinfifo; 974 975 /* Critical Section Data */ 976 struct cs *critical_sections; 977 u_int num_critical_sections; 978 979 /* Links for chaining softcs */ 980 TAILQ_ENTRY(ahc_softc) links; 981 982 /* Channel Names ('A', 'B', etc.) */ 983 char channel; 984 char channel_b; 985 986 /* Initiator Bus ID */ 987 uint8_t our_id; 988 uint8_t our_id_b; 989 990 /* 991 * PCI error detection. 992 */ 993 int unsolicited_ints; 994 995 /* 996 * Target incoming command FIFO. 997 */ 998 struct target_cmd *targetcmds; 999 uint8_t tqinfifonext; 1000 1001 /* 1002 * Incoming and outgoing message handling. 1003 */ 1004 uint8_t send_msg_perror; 1005 ahc_msg_type msg_type; 1006 uint8_t msgout_buf[12];/* Message we are sending */ 1007 uint8_t msgin_buf[12];/* Message we are receiving */ 1008 u_int msgout_len; /* Length of message to send */ 1009 u_int msgout_index; /* Current index in msgout */ 1010 u_int msgin_index; /* Current index in msgin */ 1011 1012 /* 1013 * Mapping information for data structures shared 1014 * between the sequencer and kernel. 1015 */ 1016 bus_dma_tag_t parent_dmat; 1017 bus_dma_tag_t shared_data_dmat; 1018 bus_dmamap_t shared_data_dmamap; 1019 bus_addr_t shared_data_busaddr; 1020 1021 /* 1022 * Bus address of the one byte buffer used to 1023 * work-around a DMA bug for chips <= aic7880 1024 * in target mode. 1025 */ 1026 bus_addr_t dma_bug_buf; 1027 1028 /* Information saved through suspend/resume cycles */ 1029 struct ahc_suspend_state suspend_state; 1030 1031 /* Number of enabled target mode device on this card */ 1032 u_int enabled_luns; 1033 1034 /* Initialization level of this data structure */ 1035 u_int init_level; 1036 1037 /* PCI cacheline size. */ 1038 u_int pci_cachesize; 1039 1040 u_int stack_size; 1041 uint16_t *saved_stack; 1042 1043 /* Per-Unit descriptive information */ 1044 const char *description; 1045 char *name; 1046 int unit; 1047 1048 /* Selection Timer settings */ 1049 int seltime; 1050 int seltime_b; 1051 1052 uint16_t user_discenable;/* Disconnection allowed */ 1053 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1054}; 1055 1056TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1057extern struct ahc_softc_tailq ahc_tailq; 1058 1059/************************ Active Device Information ***************************/ 1060typedef enum { 1061 ROLE_UNKNOWN, 1062 ROLE_INITIATOR, 1063 ROLE_TARGET 1064} role_t; 1065 1066struct ahc_devinfo { 1067 int our_scsiid; 1068 int target_offset; 1069 uint16_t target_mask; 1070 u_int target; 1071 u_int lun; 1072 char channel; 1073 role_t role; /* 1074 * Only guaranteed to be correct if not 1075 * in the busfree state. 1076 */ 1077}; 1078 1079/****************************** PCI Structures ********************************/ 1080typedef int (ahc_device_setup_t)(struct ahc_softc *); 1081 1082struct ahc_pci_identity { 1083 uint64_t full_id; 1084 uint64_t id_mask; 1085 char *name; 1086 ahc_device_setup_t *setup; 1087}; 1088extern struct ahc_pci_identity ahc_pci_ident_table []; 1089extern const u_int ahc_num_pci_devs; 1090 1091/***************************** VL/EISA Declarations ***************************/ 1092struct aic7770_identity { 1093 uint32_t full_id; 1094 uint32_t id_mask; 1095 char *name; 1096 ahc_device_setup_t *setup; 1097}; 1098extern struct aic7770_identity aic7770_ident_table []; 1099extern const int ahc_num_aic7770_devs; 1100 1101#define AHC_EISA_SLOT_OFFSET 0xc00 1102#define AHC_EISA_IOSIZE 0x100 1103 1104/*************************** Function Declarations ****************************/ 1105/******************************************************************************/ 1106u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1107void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1108void ahc_busy_tcl(struct ahc_softc *ahc, 1109 u_int tcl, u_int busyid); 1110 1111/***************************** PCI Front End *********************************/ 1112struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); 1113int ahc_pci_config(struct ahc_softc *, 1114 struct ahc_pci_identity *); 1115int ahc_pci_test_register_access(struct ahc_softc *); 1116 1117/*************************** EISA/VL Front End ********************************/ 1118struct aic7770_identity *aic7770_find_device(uint32_t); 1119int aic7770_config(struct ahc_softc *ahc, 1120 struct aic7770_identity *, 1121 u_int port); 1122 1123/************************** SCB and SCB queue management **********************/ 1124int ahc_probe_scbs(struct ahc_softc *); 1125void ahc_run_untagged_queues(struct ahc_softc *ahc); 1126void ahc_run_untagged_queue(struct ahc_softc *ahc, 1127 struct scb_tailq *queue); 1128void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1129 struct scb *scb); 1130int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1131 int target, char channel, int lun, 1132 u_int tag, role_t role); 1133 1134/****************************** Initialization ********************************/ 1135struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1136int ahc_softc_init(struct ahc_softc *); 1137void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1138int ahc_init(struct ahc_softc *ahc); 1139void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1140void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1141int ahc_suspend(struct ahc_softc *ahc); 1142int ahc_resume(struct ahc_softc *ahc); 1143void ahc_softc_insert(struct ahc_softc *); 1144struct ahc_softc *ahc_find_softc(struct ahc_softc *ahc); 1145void ahc_set_unit(struct ahc_softc *, int); 1146void ahc_set_name(struct ahc_softc *, char *); 1147void ahc_alloc_scbs(struct ahc_softc *ahc); 1148void ahc_free(struct ahc_softc *ahc); 1149int ahc_reset(struct ahc_softc *ahc); 1150void ahc_shutdown(void *arg); 1151 1152/*************************** Interrupt Services *******************************/ 1153void ahc_pci_intr(struct ahc_softc *ahc); 1154void ahc_clear_intstat(struct ahc_softc *ahc); 1155void ahc_run_qoutfifo(struct ahc_softc *ahc); 1156#ifdef AHC_TARGET_MODE 1157void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1158#endif 1159void ahc_handle_brkadrint(struct ahc_softc *ahc); 1160void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1161void ahc_handle_scsiint(struct ahc_softc *ahc, 1162 u_int intstat); 1163void ahc_clear_critical_section(struct ahc_softc *ahc); 1164 1165/***************************** Error Recovery *********************************/ 1166typedef enum { 1167 SEARCH_COMPLETE, 1168 SEARCH_COUNT, 1169 SEARCH_REMOVE 1170} ahc_search_action; 1171int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1172 char channel, int lun, u_int tag, 1173 role_t role, uint32_t status, 1174 ahc_search_action action); 1175int ahc_search_untagged_queues(struct ahc_softc *ahc, 1176 ahc_io_ctx_t ctx, 1177 int target, char channel, 1178 int lun, uint32_t status, 1179 ahc_search_action action); 1180int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1181 char channel, int lun, u_int tag, 1182 int stop_on_first, int remove, 1183 int save_state); 1184void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1185int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1186 int initiate_reset); 1187int ahc_abort_scbs(struct ahc_softc *ahc, int target, 1188 char channel, int lun, u_int tag, 1189 role_t role, uint32_t status); 1190void ahc_restart(struct ahc_softc *ahc); 1191void ahc_calc_residual(struct ahc_softc *ahc, 1192 struct scb *scb); 1193/*************************** Utility Functions ********************************/ 1194struct ahc_phase_table_entry* 1195 ahc_lookup_phase_entry(int phase); 1196void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1197 u_int our_id, u_int target, 1198 u_int lun, char channel, 1199 role_t role); 1200/************************** Transfer Negotiation ******************************/ 1201struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1202 u_int *ppr_options, u_int maxsync); 1203u_int ahc_find_period(struct ahc_softc *ahc, 1204 u_int scsirate, u_int maxsync); 1205void ahc_validate_offset(struct ahc_softc *ahc, 1206 struct ahc_initiator_tinfo *tinfo, 1207 struct ahc_syncrate *syncrate, 1208 u_int *offset, int wide, 1209 role_t role); 1210void ahc_validate_width(struct ahc_softc *ahc, 1211 struct ahc_initiator_tinfo *tinfo, 1212 u_int *bus_width, 1213 role_t role); 1214/* 1215 * Negotiation types. These are used to qualify if we should renegotiate 1216 * even if our goal and current transport parameters are identical. 1217 */ 1218typedef enum { 1219 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1220 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1221 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1222} ahc_neg_type; 1223int ahc_update_neg_request(struct ahc_softc*, 1224 struct ahc_devinfo*, 1225 struct ahc_tmode_tstate*, 1226 struct ahc_initiator_tinfo*, 1227 ahc_neg_type); 1228void ahc_set_width(struct ahc_softc *ahc, 1229 struct ahc_devinfo *devinfo, 1230 u_int width, u_int type, int paused); 1231void ahc_set_syncrate(struct ahc_softc *ahc, 1232 struct ahc_devinfo *devinfo, 1233 struct ahc_syncrate *syncrate, 1234 u_int period, u_int offset, 1235 u_int ppr_options, 1236 u_int type, int paused); 1237typedef enum { 1238 AHC_QUEUE_NONE, 1239 AHC_QUEUE_BASIC, 1240 AHC_QUEUE_TAGGED 1241} ahc_queue_alg; 1242 1243void ahc_set_tags(struct ahc_softc *ahc, 1244 struct ahc_devinfo *devinfo, 1245 ahc_queue_alg alg); 1246 1247/**************************** Target Mode *************************************/ 1248#ifdef AHC_TARGET_MODE 1249void ahc_send_lstate_events(struct ahc_softc *, 1250 struct ahc_tmode_lstate *); 1251void ahc_handle_en_lun(struct ahc_softc *ahc, 1252 struct cam_sim *sim, union ccb *ccb); 1253cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1254 struct cam_sim *sim, union ccb *ccb, 1255 struct ahc_tmode_tstate **tstate, 1256 struct ahc_tmode_lstate **lstate, 1257 int notfound_failure); 1258#ifndef AHC_TMODE_ENABLE 1259#define AHC_TMODE_ENABLE 0 1260#endif 1261#endif 1262/******************************* Debug ***************************************/ 1263#ifdef AHC_DEBUG 1264extern uint32_t ahc_debug; 1265#define AHC_SHOW_MISC 0x0001 1266#define AHC_SHOW_SENSE 0x0002 1267#define AHC_DUMP_SEEPROM 0x0004 1268#define AHC_SHOW_TERMCTL 0x0008 1269#define AHC_SHOW_MEMORY 0x0010 1270#define AHC_SHOW_MESSAGES 0x0020 1271#define AHC_SHOW_DV 0x0040 1272#define AHC_SHOW_SELTO 0x0080 1273#define AHC_SHOW_QFULL 0x0200 1274#define AHC_SHOW_QUEUE 0x0400 1275#define AHC_SHOW_TQIN 0x0800 1276#define AHC_DEBUG_SEQUENCER 0x1000 1277#endif 1278void ahc_print_scb(struct scb *scb); 1279void ahc_print_devinfo(struct ahc_softc *ahc, 1280 struct ahc_devinfo *dev); 1281void ahc_dump_card_state(struct ahc_softc *ahc); 1282int ahc_print_register(ahc_reg_parse_entry_t *table, 1283 u_int num_entries, 1284 const char *name, 1285 u_int address, 1286 u_int value, 1287 u_int *cur_column, 1288 u_int wrap_point); 1289/******************************* SEEPROM *************************************/ 1290int ahc_acquire_seeprom(struct ahc_softc *ahc, 1291 struct seeprom_descriptor *sd); 1292void ahc_release_seeprom(struct seeprom_descriptor *sd); 1293#endif /* _AIC7XXX_H_ */ 1294