1139749Simp/*- 297883Sgibbs * Product specific probe and attach routines for: 397883Sgibbs * aic7901 and aic7902 SCSI controllers 497883Sgibbs * 597883Sgibbs * Copyright (c) 1994-2001 Justin T. Gibbs. 6102686Sgibbs * Copyright (c) 2000-2002 Adaptec Inc. 797883Sgibbs * All rights reserved. 897883Sgibbs * 997883Sgibbs * Redistribution and use in source and binary forms, with or without 1097883Sgibbs * modification, are permitted provided that the following conditions 1197883Sgibbs * are met: 1297883Sgibbs * 1. Redistributions of source code must retain the above copyright 1397883Sgibbs * notice, this list of conditions, and the following disclaimer, 1497883Sgibbs * without modification. 1597883Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1697883Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1797883Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1897883Sgibbs * including a substantially similar Disclaimer requirement for further 1997883Sgibbs * binary redistribution. 2097883Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2197883Sgibbs * of any contributors may be used to endorse or promote products derived 2297883Sgibbs * from this software without specific prior written permission. 2397883Sgibbs * 2497883Sgibbs * Alternatively, this software may be distributed under the terms of the 2597883Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2697883Sgibbs * Software Foundation. 2797883Sgibbs * 2897883Sgibbs * NO WARRANTY 2997883Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3097883Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3197883Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3297883Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3397883Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3497883Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3597883Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3697883Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3797883Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3897883Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3997883Sgibbs * POSSIBILITY OF SUCH DAMAGES. 4097883Sgibbs * 41129134Sgibbs * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $ 4297883Sgibbs */ 4397883Sgibbs 4497883Sgibbs#ifdef __linux__ 4597883Sgibbs#include "aic79xx_osm.h" 4697883Sgibbs#include "aic79xx_inline.h" 4797883Sgibbs#else 48123579Sgibbs#include <sys/cdefs.h> 49123579Sgibbs__FBSDID("$FreeBSD$"); 5097883Sgibbs#include <dev/aic7xxx/aic79xx_osm.h> 5197883Sgibbs#include <dev/aic7xxx/aic79xx_inline.h> 5297883Sgibbs#endif 5397883Sgibbs 5497883Sgibbsstatic __inline uint64_t 5597883Sgibbsahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 5697883Sgibbs{ 5797883Sgibbs uint64_t id; 5897883Sgibbs 5997883Sgibbs id = subvendor 6097883Sgibbs | (subdevice << 16) 6197883Sgibbs | ((uint64_t)vendor << 32) 6297883Sgibbs | ((uint64_t)device << 48); 6397883Sgibbs 6497883Sgibbs return (id); 6597883Sgibbs} 6697883Sgibbs 6797883Sgibbs#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68125448Sgibbs#define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 6997883Sgibbs#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 7097883Sgibbs#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 71125448Sgibbs#define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 7297883Sgibbs 7397883Sgibbs#define ID_AIC7901 0x800F9005FFFF9005ull 74115330Sgibbs#define ID_AHA_29320A 0x8000900500609005ull 75115330Sgibbs#define ID_AHA_29320ALP 0x8017900500449005ull 76115330Sgibbs 77102686Sgibbs#define ID_AIC7901A 0x801E9005FFFF9005ull 78107440Sscottl#define ID_AHA_29320LP 0x8014900500449005ull 7997883Sgibbs 8097883Sgibbs#define ID_AIC7902 0x801F9005FFFF9005ull 81107440Sscottl#define ID_AIC7902_B 0x801D9005FFFF9005ull 8297883Sgibbs#define ID_AHA_39320 0x8010900500409005ull 83123579Sgibbs#define ID_AHA_29320 0x8012900500429005ull 84123579Sgibbs#define ID_AHA_29320B 0x8013900500439005ull 85115330Sgibbs#define ID_AHA_39320_B 0x8015900500409005ull 86129134Sgibbs#define ID_AHA_39320_B_DELL 0x8015900501681028ull 87111653Sgibbs#define ID_AHA_39320A 0x8016900500409005ull 8897883Sgibbs#define ID_AHA_39320D 0x8011900500419005ull 89107440Sscottl#define ID_AHA_39320D_B 0x801C900500419005ull 90107440Sscottl#define ID_AHA_39320D_HP 0x8011900500AC0E11ull 91107440Sscottl#define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 92198684Sbrueffer#define ID_AHA_39320LPE 0x8017900500459005ull 9397883Sgibbs#define ID_AIC7902_PCI_REV_A4 0x3 94102686Sgibbs#define ID_AIC7902_PCI_REV_B0 0x10 95107440Sscottl#define SUBID_HP 0x0E11 96284176Sachim#define DEVICE8081 0x8081 97284176Sachim#define DEVICE8088 0x8088 98284176Sachim#define DEVICE8089 0x8089 99284176Sachim#define ADAPTECVENDORID 0x9005 100284176Sachim#define SUBVENDOR9005 0x9005 10197883Sgibbs 102125448Sgibbs#define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 103125448Sgibbs 10497883Sgibbs#define DEVID_9005_TYPE(id) ((id) & 0xF) 10597883Sgibbs#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 10697883Sgibbs#define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 10797883Sgibbs#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 10897883Sgibbs 10997883Sgibbs#define DEVID_9005_MFUNC(id) ((id) & 0x10) 11097883Sgibbs 11197883Sgibbs#define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 11297883Sgibbs 11397883Sgibbs#define SUBID_9005_TYPE(id) ((id) & 0xF) 11497883Sgibbs#define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 11597883Sgibbs#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 11697883Sgibbs 11797883Sgibbs#define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 11897883Sgibbs 11997883Sgibbs#define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 12097883Sgibbs 12197883Sgibbs#define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 12297883Sgibbs#define SUBID_9005_SEEPTYPE_NONE 0x0 12397883Sgibbs#define SUBID_9005_SEEPTYPE_4K 0x1 12497883Sgibbs 125115330Sgibbsstatic ahd_device_setup_t ahd_aic7901_setup; 126107440Sscottlstatic ahd_device_setup_t ahd_aic7901A_setup; 12797883Sgibbsstatic ahd_device_setup_t ahd_aic7902_setup; 128116933Sgibbsstatic ahd_device_setup_t ahd_aic790X_setup; 12997883Sgibbs 13097883Sgibbsstruct ahd_pci_identity ahd_pci_ident_table [] = 13197883Sgibbs{ 132115330Sgibbs /* aic7901 based controllers */ 133115330Sgibbs { 134115330Sgibbs ID_AHA_29320A, 135115330Sgibbs ID_ALL_MASK, 136115330Sgibbs "Adaptec 29320A Ultra320 SCSI adapter", 137115330Sgibbs ahd_aic7901_setup 138115330Sgibbs }, 139115330Sgibbs { 140115330Sgibbs ID_AHA_29320ALP, 141115330Sgibbs ID_ALL_MASK, 142115330Sgibbs "Adaptec 29320ALP Ultra320 SCSI adapter", 143115330Sgibbs ahd_aic7901_setup 144115330Sgibbs }, 145107440Sscottl /* aic7901A based controllers */ 14697883Sgibbs { 147123579Sgibbs ID_AHA_29320LP, 148123579Sgibbs ID_ALL_MASK, 149123579Sgibbs "Adaptec 29320LP Ultra320 SCSI adapter", 150123579Sgibbs ahd_aic7901A_setup 151123579Sgibbs }, 152123579Sgibbs /* aic7902 based controllers */ 153123579Sgibbs { 154115330Sgibbs ID_AHA_29320, 155107440Sscottl ID_ALL_MASK, 156115330Sgibbs "Adaptec 29320 Ultra320 SCSI adapter", 157123579Sgibbs ahd_aic7902_setup 158107440Sscottl }, 159107440Sscottl { 160115330Sgibbs ID_AHA_29320B, 16197883Sgibbs ID_ALL_MASK, 162115330Sgibbs "Adaptec 29320B Ultra320 SCSI adapter", 163123579Sgibbs ahd_aic7902_setup 16497883Sgibbs }, 165115330Sgibbs { 16697883Sgibbs ID_AHA_39320, 16797883Sgibbs ID_ALL_MASK, 16897883Sgibbs "Adaptec 39320 Ultra320 SCSI adapter", 16997883Sgibbs ahd_aic7902_setup 17097883Sgibbs }, 17197883Sgibbs { 172115330Sgibbs ID_AHA_39320_B, 173115330Sgibbs ID_ALL_MASK, 174115330Sgibbs "Adaptec 39320 Ultra320 SCSI adapter", 175115330Sgibbs ahd_aic7902_setup 176115330Sgibbs }, 177115330Sgibbs { 178129134Sgibbs ID_AHA_39320_B_DELL, 179129134Sgibbs ID_ALL_MASK, 180129134Sgibbs "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 181129134Sgibbs ahd_aic7902_setup 182129134Sgibbs }, 183129134Sgibbs { 184111653Sgibbs ID_AHA_39320A, 185111653Sgibbs ID_ALL_MASK, 186111653Sgibbs "Adaptec 39320A Ultra320 SCSI adapter", 187111653Sgibbs ahd_aic7902_setup 188111653Sgibbs }, 189111653Sgibbs { 19097883Sgibbs ID_AHA_39320D, 19197883Sgibbs ID_ALL_MASK, 19297883Sgibbs "Adaptec 39320D Ultra320 SCSI adapter", 19397883Sgibbs ahd_aic7902_setup 19497883Sgibbs }, 19597883Sgibbs { 196107440Sscottl ID_AHA_39320D_HP, 19797883Sgibbs ID_ALL_MASK, 198107440Sscottl "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 19997883Sgibbs ahd_aic7902_setup 20097883Sgibbs }, 201102686Sgibbs { 202107440Sscottl ID_AHA_39320D_B, 203102686Sgibbs ID_ALL_MASK, 204107440Sscottl "Adaptec 39320D Ultra320 SCSI adapter", 205102686Sgibbs ahd_aic7902_setup 206102686Sgibbs }, 207102686Sgibbs { 208107440Sscottl ID_AHA_39320D_B_HP, 209102686Sgibbs ID_ALL_MASK, 210107440Sscottl "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 211102686Sgibbs ahd_aic7902_setup 212102686Sgibbs }, 213198684Sbrueffer { 214198684Sbrueffer ID_AHA_39320LPE, 215198684Sbrueffer ID_ALL_MASK, 216198684Sbrueffer "Adaptec 39320LPE Ultra320 SCSI adapter", 217198684Sbrueffer ahd_aic7902_setup 218198684Sbrueffer }, 21997883Sgibbs /* Generic chip probes for devices we don't know 'exactly' */ 22097883Sgibbs { 221125448Sgibbs ID_AIC7901 & ID_9005_GENERIC_MASK, 222129134Sgibbs ID_9005_GENERIC_MASK, 223115330Sgibbs "Adaptec AIC7901 Ultra320 SCSI adapter", 224115330Sgibbs ahd_aic7901_setup 225115330Sgibbs }, 226115330Sgibbs { 227107623Sscottl ID_AIC7901A & ID_DEV_VENDOR_MASK, 228107623Sscottl ID_DEV_VENDOR_MASK, 229107440Sscottl "Adaptec AIC7901A Ultra320 SCSI adapter", 230107440Sscottl ahd_aic7901A_setup 23197883Sgibbs }, 23297883Sgibbs { 23397883Sgibbs ID_AIC7902 & ID_9005_GENERIC_MASK, 23497883Sgibbs ID_9005_GENERIC_MASK, 235107440Sscottl "Adaptec AIC7902 Ultra320 SCSI adapter", 23697883Sgibbs ahd_aic7902_setup 23797883Sgibbs } 23897883Sgibbs}; 23997883Sgibbs 24097883Sgibbsconst u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 24197883Sgibbs 24297883Sgibbs#define DEVCONFIG 0x40 24397883Sgibbs#define PCIXINITPAT 0x0000E000ul 24497883Sgibbs#define PCIXINIT_PCI33_66 0x0000E000ul 24597883Sgibbs#define PCIXINIT_PCIX50_66 0x0000C000ul 24697883Sgibbs#define PCIXINIT_PCIX66_100 0x0000A000ul 24797883Sgibbs#define PCIXINIT_PCIX100_133 0x00008000ul 24897883Sgibbs#define PCI_BUS_MODES_INDEX(devconfig) \ 24997883Sgibbs (((devconfig) & PCIXINITPAT) >> 13) 25097883Sgibbsstatic const char *pci_bus_modes[] = 25197883Sgibbs{ 25297883Sgibbs "PCI bus mode unknown", 25397883Sgibbs "PCI bus mode unknown", 25497883Sgibbs "PCI bus mode unknown", 25597883Sgibbs "PCI bus mode unknown", 256202161Sgavin "PCI-X 101-133MHz", 257202161Sgavin "PCI-X 67-100MHz", 258202161Sgavin "PCI-X 50-66MHz", 259202161Sgavin "PCI 33 or 66MHz" 26097883Sgibbs}; 26197883Sgibbs 26297883Sgibbs#define TESTMODE 0x00000800ul 26397883Sgibbs#define IRDY_RST 0x00000200ul 26497883Sgibbs#define FRAME_RST 0x00000100ul 26597883Sgibbs#define PCI64BIT 0x00000080ul 26697883Sgibbs#define MRDCEN 0x00000040ul 26797883Sgibbs#define ENDIANSEL 0x00000020ul 26897883Sgibbs#define MIXQWENDIANEN 0x00000008ul 26997883Sgibbs#define DACEN 0x00000004ul 27097883Sgibbs#define STPWLEVEL 0x00000002ul 27197883Sgibbs#define QWENDIANSEL 0x00000001ul 27297883Sgibbs 27397883Sgibbs#define DEVCONFIG1 0x44 27497883Sgibbs#define PREQDIS 0x01 27597883Sgibbs 27697883Sgibbs#define CSIZE_LATTIME 0x0c 27797883Sgibbs#define CACHESIZE 0x000000fful 27897883Sgibbs#define LATTIME 0x0000ff00ul 27997883Sgibbs 28097883Sgibbsstatic int ahd_check_extport(struct ahd_softc *ahd); 28197883Sgibbsstatic void ahd_configure_termination(struct ahd_softc *ahd, 28297883Sgibbs u_int adapter_control); 28397883Sgibbsstatic void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 28497883Sgibbs 28597883Sgibbsstruct ahd_pci_identity * 286123579Sgibbsahd_find_pci_device(aic_dev_softc_t pci) 28797883Sgibbs{ 28897883Sgibbs uint64_t full_id; 28997883Sgibbs uint16_t device; 29097883Sgibbs uint16_t vendor; 29197883Sgibbs uint16_t subdevice; 29297883Sgibbs uint16_t subvendor; 29397883Sgibbs struct ahd_pci_identity *entry; 29497883Sgibbs u_int i; 29597883Sgibbs 296123579Sgibbs vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 297123579Sgibbs device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 298123579Sgibbs subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 299123579Sgibbs subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 300284176Sachim 301284176Sachim if ((vendor == ADAPTECVENDORID) && (subvendor == SUBVENDOR9005)) { 302284176Sachim if ((device == DEVICE8081) || (device == DEVICE8088) || 303284176Sachim (device == DEVICE8089)) { 304284176Sachim printf("Controller device ID conflict with PMC Adaptec HBA\n"); 305284176Sachim return (NULL); 306284176Sachim } 307284176Sachim } 308284176Sachim 30997883Sgibbs full_id = ahd_compose_id(device, 31097883Sgibbs vendor, 31197883Sgibbs subdevice, 31297883Sgibbs subvendor); 31397883Sgibbs 314125448Sgibbs /* 315125448Sgibbs * If we are configured to attach to HostRAID 316125448Sgibbs * controllers, mask out the IROC/HostRAID bit 317125448Sgibbs * in the 318125448Sgibbs */ 319125448Sgibbs if (ahd_attach_to_HostRAID_controllers) 320125448Sgibbs full_id &= ID_ALL_IROC_MASK; 321125448Sgibbs 32297883Sgibbs for (i = 0; i < ahd_num_pci_devs; i++) { 32397883Sgibbs entry = &ahd_pci_ident_table[i]; 32497883Sgibbs if (entry->full_id == (full_id & entry->id_mask)) { 32597883Sgibbs /* Honor exclusion entries. */ 32697883Sgibbs if (entry->name == NULL) 32797883Sgibbs return (NULL); 32897883Sgibbs return (entry); 32997883Sgibbs } 33097883Sgibbs } 33197883Sgibbs return (NULL); 33297883Sgibbs} 33397883Sgibbs 33497883Sgibbsint 33597883Sgibbsahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 33697883Sgibbs{ 33797883Sgibbs struct scb_data *shared_scb_data; 33897883Sgibbs u_int command; 33997883Sgibbs uint32_t devconfig; 340125448Sgibbs uint16_t device; 34197883Sgibbs uint16_t subvendor; 34297883Sgibbs int error; 34397883Sgibbs 34497883Sgibbs shared_scb_data = NULL; 345107440Sscottl ahd->description = entry->name; 346107440Sscottl /* 347125448Sgibbs * Record if this is a HostRAID board. 348125448Sgibbs */ 349125448Sgibbs device = aic_pci_read_config(ahd->dev_softc, 350125448Sgibbs PCIR_DEVICE, /*bytes*/2); 351125448Sgibbs if (DEVID_9005_HOSTRAID(device)) 352125448Sgibbs ahd->flags |= AHD_HOSTRAID_BOARD; 353125448Sgibbs 354125448Sgibbs /* 355107440Sscottl * Record if this is an HP board. 356107440Sscottl */ 357123579Sgibbs subvendor = aic_pci_read_config(ahd->dev_softc, 358107440Sscottl PCIR_SUBVEND_0, /*bytes*/2); 359107440Sscottl if (subvendor == SUBID_HP) 360107440Sscottl ahd->flags |= AHD_HP_BOARD; 361107440Sscottl 36297883Sgibbs error = entry->setup(ahd); 36397883Sgibbs if (error != 0) 36497883Sgibbs return (error); 365166109Sjhb 366166109Sjhb /* 367166109Sjhb * Find the PCI-X cap pointer. If we don't find it, 368166109Sjhb * pcix_ptr will be 0. 369166109Sjhb */ 370219902Sjhb pci_find_cap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr); 371123579Sgibbs devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 37297883Sgibbs if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 37397883Sgibbs ahd->chip |= AHD_PCI; 37497883Sgibbs /* Disable PCIX workarounds when running in PCI mode. */ 37597883Sgibbs ahd->bugs &= ~AHD_PCIX_BUG_MASK; 37697883Sgibbs } else { 37797883Sgibbs ahd->chip |= AHD_PCIX; 378166109Sjhb if (ahd->pcix_ptr == 0) 379166109Sjhb return (ENXIO); 38097883Sgibbs } 38197883Sgibbs ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 38297883Sgibbs 383123579Sgibbs aic_power_state_change(ahd, AIC_POWER_STATE_D0); 38497883Sgibbs 38597883Sgibbs error = ahd_pci_map_registers(ahd); 38697883Sgibbs if (error != 0) 38797883Sgibbs return (error); 38897883Sgibbs 38997883Sgibbs /* 39097883Sgibbs * If we need to support high memory, enable dual 39197883Sgibbs * address cycles. This bit must be set to enable 39297883Sgibbs * high address bit generation even if we are on a 39397883Sgibbs * 64bit bus (PCI64BIT set in devconfig). 39497883Sgibbs */ 39597883Sgibbs if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 39697883Sgibbs uint32_t devconfig; 39797883Sgibbs 39897883Sgibbs if (bootverbose) 39997883Sgibbs printf("%s: Enabling 39Bit Addressing\n", 40097883Sgibbs ahd_name(ahd)); 401123579Sgibbs devconfig = aic_pci_read_config(ahd->dev_softc, 40297883Sgibbs DEVCONFIG, /*bytes*/4); 40397883Sgibbs devconfig |= DACEN; 404123579Sgibbs aic_pci_write_config(ahd->dev_softc, DEVCONFIG, 40597883Sgibbs devconfig, /*bytes*/4); 40697883Sgibbs } 40797883Sgibbs 40897883Sgibbs /* Ensure busmastering is enabled */ 409123579Sgibbs command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 41097883Sgibbs command |= PCIM_CMD_BUSMASTEREN; 411123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 41297883Sgibbs 41397883Sgibbs error = ahd_softc_init(ahd); 41497883Sgibbs if (error != 0) 41597883Sgibbs return (error); 41697883Sgibbs 41797883Sgibbs ahd->bus_intr = ahd_pci_intr; 41897883Sgibbs 419115917Sgibbs error = ahd_reset(ahd, /*reinit*/FALSE); 42097883Sgibbs if (error != 0) 42197883Sgibbs return (ENXIO); 42297883Sgibbs 42397883Sgibbs ahd->pci_cachesize = 424123579Sgibbs aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 42597883Sgibbs /*bytes*/1) & CACHESIZE; 42697883Sgibbs ahd->pci_cachesize *= 4; 42797883Sgibbs 42897883Sgibbs ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 42997883Sgibbs /* See if we have a SEEPROM and perform auto-term */ 43097883Sgibbs error = ahd_check_extport(ahd); 43197883Sgibbs if (error != 0) 43297883Sgibbs return (error); 43397883Sgibbs 43497883Sgibbs /* Core initialization */ 43597883Sgibbs error = ahd_init(ahd); 43697883Sgibbs if (error != 0) 43797883Sgibbs return (error); 43897883Sgibbs 43997883Sgibbs /* 44097883Sgibbs * Allow interrupts now that we are completely setup. 44197883Sgibbs */ 44297883Sgibbs error = ahd_pci_map_int(ahd); 44397883Sgibbs if (error != 0) 44497883Sgibbs return (error); 44597883Sgibbs 446168807Sscottl ahd_lock(ahd); 44797883Sgibbs /* 44897883Sgibbs * Link this softc in with all other ahd instances. 44997883Sgibbs */ 45097883Sgibbs ahd_softc_insert(ahd); 451168807Sscottl ahd_unlock(ahd); 45297883Sgibbs return (0); 45397883Sgibbs} 45497883Sgibbs 45597883Sgibbs/* 456107440Sscottl * Perform some simple tests that should catch situations where 457107440Sscottl * our registers are invalidly mapped. 458107440Sscottl */ 459107440Sscottlint 460107440Sscottlahd_pci_test_register_access(struct ahd_softc *ahd) 461107440Sscottl{ 462115919Sgibbs uint32_t cmd; 463115919Sgibbs u_int targpcistat; 464115919Sgibbs u_int pci_status1; 465115919Sgibbs int error; 466115919Sgibbs uint8_t hcntrl; 467107440Sscottl 468107623Sscottl error = EIO; 469107623Sscottl 470109588Sgibbs /* 471109588Sgibbs * Enable PCI error interrupt status, but suppress NMIs 472109588Sgibbs * generated by SERR raised due to target aborts. 473109588Sgibbs */ 474123579Sgibbs cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 475123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 476109588Sgibbs cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 477107623Sscottl 478107440Sscottl /* 479107440Sscottl * First a simple test to see if any 480107440Sscottl * registers can be read. Reading 481107440Sscottl * HCNTRL has no side effects and has 482107440Sscottl * at least one bit that is guaranteed to 483107440Sscottl * be zero so it is a good register to 484107440Sscottl * use for this test. 485107440Sscottl */ 486109588Sgibbs hcntrl = ahd_inb(ahd, HCNTRL); 487109588Sgibbs if (hcntrl == 0xFF) 488107623Sscottl goto fail; 489107440Sscottl 490107440Sscottl /* 491107440Sscottl * Next create a situation where write combining 492107440Sscottl * or read prefetching could be initiated by the 493107440Sscottl * CPU or host bridge. Our device does not support 494300060Spfg * either, so look for data corruption and/or flagged 495120445Sscottl * PCI errors. First pause without causing another 496120445Sscottl * chip reset. 497107440Sscottl */ 498120445Sscottl hcntrl &= ~CHIPRST; 499109588Sgibbs ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 500109588Sgibbs while (ahd_is_paused(ahd) == 0) 501109588Sgibbs ; 502115919Sgibbs 503115919Sgibbs /* Clear any PCI errors that occurred before our driver attached. */ 504115919Sgibbs ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 505115919Sgibbs targpcistat = ahd_inb(ahd, TARGPCISTAT); 506115919Sgibbs ahd_outb(ahd, TARGPCISTAT, targpcistat); 507123579Sgibbs pci_status1 = aic_pci_read_config(ahd->dev_softc, 508115919Sgibbs PCIR_STATUS + 1, /*bytes*/1); 509123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 510115919Sgibbs pci_status1, /*bytes*/1); 511115919Sgibbs ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 512115919Sgibbs ahd_outb(ahd, CLRINT, CLRPCIINT); 513115919Sgibbs 514109588Sgibbs ahd_outb(ahd, SEQCTL0, PERRORDIS); 515107623Sscottl ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 516107623Sscottl if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 517107623Sscottl goto fail; 518107440Sscottl 519107623Sscottl if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 520107623Sscottl u_int targpcistat; 521107440Sscottl 522107623Sscottl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 523107623Sscottl targpcistat = ahd_inb(ahd, TARGPCISTAT); 524107623Sscottl if ((targpcistat & STA) != 0) 525107623Sscottl goto fail; 526107623Sscottl } 527107623Sscottl 528107623Sscottl error = 0; 529107623Sscottl 530107623Sscottlfail: 531107440Sscottl if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 532107440Sscottl 533107440Sscottl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 534107440Sscottl targpcistat = ahd_inb(ahd, TARGPCISTAT); 535107440Sscottl 536107440Sscottl /* Silently clear any latched errors. */ 537107440Sscottl ahd_outb(ahd, TARGPCISTAT, targpcistat); 538123579Sgibbs pci_status1 = aic_pci_read_config(ahd->dev_softc, 539107440Sscottl PCIR_STATUS + 1, /*bytes*/1); 540123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 541107440Sscottl pci_status1, /*bytes*/1); 542107623Sscottl ahd_outb(ahd, CLRINT, CLRPCIINT); 543107440Sscottl } 544109588Sgibbs ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 545123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 546107623Sscottl return (error); 547107440Sscottl} 548107440Sscottl 549107440Sscottl/* 55097883Sgibbs * Check the external port logic for a serial eeprom 55197883Sgibbs * and termination/cable detection contrls. 55297883Sgibbs */ 55397883Sgibbsstatic int 55497883Sgibbsahd_check_extport(struct ahd_softc *ahd) 55597883Sgibbs{ 556114623Sgibbs struct vpd_config vpd; 55797883Sgibbs struct seeprom_config *sc; 55897883Sgibbs u_int adapter_control; 55997883Sgibbs int have_seeprom; 56097883Sgibbs int error; 56197883Sgibbs 56297883Sgibbs sc = ahd->seep_config; 56397883Sgibbs have_seeprom = ahd_acquire_seeprom(ahd); 56497883Sgibbs if (have_seeprom) { 56597883Sgibbs u_int start_addr; 56697883Sgibbs 567114623Sgibbs /* 568114623Sgibbs * Fetch VPD for this function and parse it. 569114623Sgibbs */ 57097883Sgibbs if (bootverbose) 571114623Sgibbs printf("%s: Reading VPD from SEEPROM...", 572114623Sgibbs ahd_name(ahd)); 573114623Sgibbs 574114623Sgibbs /* Address is always in units of 16bit words */ 575114623Sgibbs start_addr = ((2 * sizeof(*sc)) 576114623Sgibbs + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 577114623Sgibbs 578114623Sgibbs error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 579114623Sgibbs start_addr, sizeof(vpd)/2, 580114623Sgibbs /*bytestream*/TRUE); 581114623Sgibbs if (error == 0) 582114623Sgibbs error = ahd_parse_vpddata(ahd, &vpd); 583114623Sgibbs if (bootverbose) 584114623Sgibbs printf("%s: VPD parsing %s\n", 585114623Sgibbs ahd_name(ahd), 586114623Sgibbs error == 0 ? "successful" : "failed"); 587114623Sgibbs 588114623Sgibbs if (bootverbose) 58997883Sgibbs printf("%s: Reading SEEPROM...", ahd_name(ahd)); 59097883Sgibbs 59197883Sgibbs /* Address is always in units of 16bit words */ 59297883Sgibbs start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 59397883Sgibbs 59497883Sgibbs error = ahd_read_seeprom(ahd, (uint16_t *)sc, 595114623Sgibbs start_addr, sizeof(*sc)/2, 596114623Sgibbs /*bytestream*/FALSE); 59797883Sgibbs 59897883Sgibbs if (error != 0) { 59997883Sgibbs printf("Unable to read SEEPROM\n"); 60097883Sgibbs have_seeprom = 0; 60197883Sgibbs } else { 60297883Sgibbs have_seeprom = ahd_verify_cksum(sc); 60397883Sgibbs 60497883Sgibbs if (bootverbose) { 60597883Sgibbs if (have_seeprom == 0) 60697883Sgibbs printf ("checksum error\n"); 60797883Sgibbs else 60897883Sgibbs printf ("done.\n"); 60997883Sgibbs } 61097883Sgibbs } 61197883Sgibbs ahd_release_seeprom(ahd); 61297883Sgibbs } 61397883Sgibbs 61497883Sgibbs if (!have_seeprom) { 61597883Sgibbs u_int nvram_scb; 61697883Sgibbs 61797883Sgibbs /* 61897883Sgibbs * Pull scratch ram settings and treat them as 61997883Sgibbs * if they are the contents of an seeprom if 62097883Sgibbs * the 'ADPT', 'BIOS', or 'ASPI' signature is found 62197883Sgibbs * in SCB 0xFF. We manually compose the data as 16bit 62297883Sgibbs * values to avoid endian issues. 62397883Sgibbs */ 62497883Sgibbs ahd_set_scbptr(ahd, 0xFF); 62597883Sgibbs nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 62697883Sgibbs if (nvram_scb != 0xFF 62797883Sgibbs && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 62897883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 62997883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 63097883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 63197883Sgibbs || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 63297883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 63397883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 63497883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 63597883Sgibbs || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 63697883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 63797883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 63897883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 63997883Sgibbs uint16_t *sc_data; 64097883Sgibbs int i; 64197883Sgibbs 64297883Sgibbs ahd_set_scbptr(ahd, nvram_scb); 64397883Sgibbs sc_data = (uint16_t *)sc; 64497883Sgibbs for (i = 0; i < 64; i += 2) 64597883Sgibbs *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 64697883Sgibbs have_seeprom = ahd_verify_cksum(sc); 64797883Sgibbs if (have_seeprom) 64897883Sgibbs ahd->flags |= AHD_SCB_CONFIG_USED; 64997883Sgibbs } 65097883Sgibbs } 65197883Sgibbs 652153072Sru#ifdef AHD_DEBUG 65397883Sgibbs if (have_seeprom != 0 65497883Sgibbs && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 655114623Sgibbs uint16_t *sc_data; 656114623Sgibbs int i; 65797883Sgibbs 65897883Sgibbs printf("%s: Seeprom Contents:", ahd_name(ahd)); 659114623Sgibbs sc_data = (uint16_t *)sc; 66097883Sgibbs for (i = 0; i < (sizeof(*sc)); i += 2) 661114623Sgibbs printf("\n\t0x%.4x", sc_data[i]); 66297883Sgibbs printf("\n"); 66397883Sgibbs } 66497883Sgibbs#endif 66597883Sgibbs 66697883Sgibbs if (!have_seeprom) { 66797883Sgibbs if (bootverbose) 66897883Sgibbs printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 66997883Sgibbs ahd->flags |= AHD_USEDEFAULTS; 67097883Sgibbs error = ahd_default_config(ahd); 67197883Sgibbs adapter_control = CFAUTOTERM|CFSEAUTOTERM; 67297883Sgibbs free(ahd->seep_config, M_DEVBUF); 67397883Sgibbs ahd->seep_config = NULL; 67497883Sgibbs } else { 67597883Sgibbs error = ahd_parse_cfgdata(ahd, sc); 67697883Sgibbs adapter_control = sc->adapter_control; 67797883Sgibbs } 67897883Sgibbs if (error != 0) 67997883Sgibbs return (error); 68097883Sgibbs 68197883Sgibbs ahd_configure_termination(ahd, adapter_control); 68297883Sgibbs 68397883Sgibbs return (0); 68497883Sgibbs} 68597883Sgibbs 68697883Sgibbsstatic void 68797883Sgibbsahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 68897883Sgibbs{ 68997883Sgibbs int error; 69097883Sgibbs u_int sxfrctl1; 69197883Sgibbs uint8_t termctl; 69297883Sgibbs uint32_t devconfig; 69397883Sgibbs 694123579Sgibbs devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 69597883Sgibbs devconfig &= ~STPWLEVEL; 696102686Sgibbs if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 69797883Sgibbs devconfig |= STPWLEVEL; 698102686Sgibbs if (bootverbose) 699102686Sgibbs printf("%s: STPWLEVEL is %s\n", 700102686Sgibbs ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 701123579Sgibbs aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 70297883Sgibbs 70397883Sgibbs /* Make sure current sensing is off. */ 70497883Sgibbs if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 70597883Sgibbs (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 70697883Sgibbs } 70797883Sgibbs 70897883Sgibbs /* 70997883Sgibbs * Read to sense. Write to set. 71097883Sgibbs */ 71197883Sgibbs error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 71297883Sgibbs if ((adapter_control & CFAUTOTERM) == 0) { 71397883Sgibbs if (bootverbose) 71497883Sgibbs printf("%s: Manual Primary Termination\n", 71597883Sgibbs ahd_name(ahd)); 71697883Sgibbs termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 71797883Sgibbs if ((adapter_control & CFSTERM) != 0) 71897883Sgibbs termctl |= FLX_TERMCTL_ENPRILOW; 71997883Sgibbs if ((adapter_control & CFWSTERM) != 0) 72097883Sgibbs termctl |= FLX_TERMCTL_ENPRIHIGH; 72197883Sgibbs } else if (error != 0) { 72297883Sgibbs printf("%s: Primary Auto-Term Sensing failed! " 72397883Sgibbs "Using Defaults.\n", ahd_name(ahd)); 72497883Sgibbs termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 72597883Sgibbs } 72697883Sgibbs 72797883Sgibbs if ((adapter_control & CFSEAUTOTERM) == 0) { 72897883Sgibbs if (bootverbose) 72997883Sgibbs printf("%s: Manual Secondary Termination\n", 73097883Sgibbs ahd_name(ahd)); 73197883Sgibbs termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 73297883Sgibbs if ((adapter_control & CFSELOWTERM) != 0) 73397883Sgibbs termctl |= FLX_TERMCTL_ENSECLOW; 73497883Sgibbs if ((adapter_control & CFSEHIGHTERM) != 0) 73597883Sgibbs termctl |= FLX_TERMCTL_ENSECHIGH; 73697883Sgibbs } else if (error != 0) { 73797883Sgibbs printf("%s: Secondary Auto-Term Sensing failed! " 73897883Sgibbs "Using Defaults.\n", ahd_name(ahd)); 73997883Sgibbs termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 74097883Sgibbs } 74197883Sgibbs 74297883Sgibbs /* 74397883Sgibbs * Now set the termination based on what we found. 74497883Sgibbs */ 74597883Sgibbs sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 746123579Sgibbs ahd->flags &= ~AHD_TERM_ENB_A; 74797883Sgibbs if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 74897883Sgibbs ahd->flags |= AHD_TERM_ENB_A; 74997883Sgibbs sxfrctl1 |= STPWEN; 75097883Sgibbs } 75197883Sgibbs /* Must set the latch once in order to be effective. */ 75297883Sgibbs ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 75397883Sgibbs ahd_outb(ahd, SXFRCTL1, sxfrctl1); 75497883Sgibbs 75597883Sgibbs error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 75697883Sgibbs if (error != 0) { 75797883Sgibbs printf("%s: Unable to set termination settings!\n", 75897883Sgibbs ahd_name(ahd)); 75997883Sgibbs } else if (bootverbose) { 76097883Sgibbs printf("%s: Primary High byte termination %sabled\n", 76197883Sgibbs ahd_name(ahd), 76297883Sgibbs (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 76397883Sgibbs 76497883Sgibbs printf("%s: Primary Low byte termination %sabled\n", 76597883Sgibbs ahd_name(ahd), 76697883Sgibbs (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 76797883Sgibbs 76897883Sgibbs printf("%s: Secondary High byte termination %sabled\n", 76997883Sgibbs ahd_name(ahd), 77097883Sgibbs (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 77197883Sgibbs 77297883Sgibbs printf("%s: Secondary Low byte termination %sabled\n", 77397883Sgibbs ahd_name(ahd), 77497883Sgibbs (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 77597883Sgibbs } 77697883Sgibbs return; 77797883Sgibbs} 77897883Sgibbs 77997883Sgibbs#define DPE 0x80 78097883Sgibbs#define SSE 0x40 78197883Sgibbs#define RMA 0x20 78297883Sgibbs#define RTA 0x10 78397883Sgibbs#define STA 0x08 78497883Sgibbs#define DPR 0x01 78597883Sgibbs 78697883Sgibbsstatic const char *split_status_source[] = 78797883Sgibbs{ 78897883Sgibbs "DFF0", 78997883Sgibbs "DFF1", 79097883Sgibbs "OVLY", 79197883Sgibbs "CMC", 79297883Sgibbs}; 79397883Sgibbs 79497883Sgibbsstatic const char *pci_status_source[] = 79597883Sgibbs{ 79697883Sgibbs "DFF0", 79797883Sgibbs "DFF1", 79897883Sgibbs "SG", 79997883Sgibbs "CMC", 80097883Sgibbs "OVLY", 80197883Sgibbs "NONE", 80297883Sgibbs "MSI", 80397883Sgibbs "TARG" 80497883Sgibbs}; 80597883Sgibbs 80697883Sgibbsstatic const char *split_status_strings[] = 80797883Sgibbs{ 808111653Sgibbs "%s: Received split response in %s.\n", 80997883Sgibbs "%s: Received split completion error message in %s\n", 81097883Sgibbs "%s: Receive overrun in %s\n", 81197883Sgibbs "%s: Count not complete in %s\n", 81297883Sgibbs "%s: Split completion data bucket in %s\n", 81397883Sgibbs "%s: Split completion address error in %s\n", 81497883Sgibbs "%s: Split completion byte count error in %s\n", 815111653Sgibbs "%s: Signaled Target-abort to early terminate a split in %s\n" 81697883Sgibbs}; 81797883Sgibbs 81897883Sgibbsstatic const char *pci_status_strings[] = 81997883Sgibbs{ 82097883Sgibbs "%s: Data Parity Error has been reported via PERR# in %s\n", 82197883Sgibbs "%s: Target initial wait state error in %s\n", 82297883Sgibbs "%s: Split completion read data parity error in %s\n", 82397883Sgibbs "%s: Split completion address attribute parity error in %s\n", 82497883Sgibbs "%s: Received a Target Abort in %s\n", 82597883Sgibbs "%s: Received a Master Abort in %s\n", 82697883Sgibbs "%s: Signal System Error Detected in %s\n", 82797883Sgibbs "%s: Address or Write Phase Parity Error Detected in %s.\n" 82897883Sgibbs}; 82997883Sgibbs 83097883Sgibbsvoid 83197883Sgibbsahd_pci_intr(struct ahd_softc *ahd) 83297883Sgibbs{ 83397883Sgibbs uint8_t pci_status[8]; 83497883Sgibbs ahd_mode_state saved_modes; 83597883Sgibbs u_int pci_status1; 83697883Sgibbs u_int intstat; 83797883Sgibbs u_int i; 83897883Sgibbs u_int reg; 83997883Sgibbs 84097883Sgibbs intstat = ahd_inb(ahd, INTSTAT); 84197883Sgibbs 84297883Sgibbs if ((intstat & SPLTINT) != 0) 84397883Sgibbs ahd_pci_split_intr(ahd, intstat); 84497883Sgibbs 84597883Sgibbs if ((intstat & PCIINT) == 0) 84697883Sgibbs return; 84797883Sgibbs 84897883Sgibbs printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 84997883Sgibbs saved_modes = ahd_save_modes(ahd); 85097883Sgibbs ahd_dump_card_state(ahd); 85197883Sgibbs ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 85297883Sgibbs for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 85397883Sgibbs 85497883Sgibbs if (i == 5) 85597883Sgibbs continue; 85697883Sgibbs pci_status[i] = ahd_inb(ahd, reg); 857111653Sgibbs /* Clear latched errors. So our interrupt deasserts. */ 85897883Sgibbs ahd_outb(ahd, reg, pci_status[i]); 85997883Sgibbs } 86097883Sgibbs 86197883Sgibbs for (i = 0; i < 8; i++) { 86297883Sgibbs u_int bit; 86397883Sgibbs 86497883Sgibbs if (i == 5) 86597883Sgibbs continue; 86697883Sgibbs 86797883Sgibbs for (bit = 0; bit < 8; bit++) { 86897883Sgibbs 86997883Sgibbs if ((pci_status[i] & (0x1 << bit)) != 0) { 87097883Sgibbs static const char *s; 87197883Sgibbs 87297883Sgibbs s = pci_status_strings[bit]; 87397883Sgibbs if (i == 7/*TARG*/ && bit == 3) 874107623Sscottl s = "%s: Signaled Target Abort\n"; 87597883Sgibbs printf(s, ahd_name(ahd), pci_status_source[i]); 87697883Sgibbs } 87797883Sgibbs } 87897883Sgibbs } 879123579Sgibbs pci_status1 = aic_pci_read_config(ahd->dev_softc, 88097883Sgibbs PCIR_STATUS + 1, /*bytes*/1); 881123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 88297883Sgibbs pci_status1, /*bytes*/1); 88397883Sgibbs ahd_restore_modes(ahd, saved_modes); 884107623Sscottl ahd_outb(ahd, CLRINT, CLRPCIINT); 88597883Sgibbs ahd_unpause(ahd); 88697883Sgibbs} 88797883Sgibbs 88897883Sgibbsstatic void 88997883Sgibbsahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 89097883Sgibbs{ 89197883Sgibbs uint8_t split_status[4]; 89297883Sgibbs uint8_t split_status1[4]; 89397883Sgibbs uint8_t sg_split_status[2]; 89497883Sgibbs uint8_t sg_split_status1[2]; 89597883Sgibbs ahd_mode_state saved_modes; 89697883Sgibbs u_int i; 897166109Sjhb uint32_t pcix_status; 89897883Sgibbs 89997883Sgibbs /* 90097883Sgibbs * Check for splits in all modes. Modes 0 and 1 90197883Sgibbs * additionally have SG engine splits to look at. 90297883Sgibbs */ 903166109Sjhb pcix_status = aic_pci_read_config(ahd->dev_softc, 904166109Sjhb ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4); 90597883Sgibbs printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 906166109Sjhb ahd_name(ahd), pcix_status >> 16); 90797883Sgibbs saved_modes = ahd_save_modes(ahd); 90897883Sgibbs for (i = 0; i < 4; i++) { 90997883Sgibbs ahd_set_modes(ahd, i, i); 91097883Sgibbs 91197883Sgibbs split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 91297883Sgibbs split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 913111653Sgibbs /* Clear latched errors. So our interrupt deasserts. */ 91497883Sgibbs ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 91597883Sgibbs ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 916114623Sgibbs if (i > 1) 91797883Sgibbs continue; 91897883Sgibbs sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 91997883Sgibbs sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 920111653Sgibbs /* Clear latched errors. So our interrupt deasserts. */ 92197883Sgibbs ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 92297883Sgibbs ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 92397883Sgibbs } 92497883Sgibbs 92597883Sgibbs for (i = 0; i < 4; i++) { 92697883Sgibbs u_int bit; 92797883Sgibbs 92897883Sgibbs for (bit = 0; bit < 8; bit++) { 92997883Sgibbs 93097883Sgibbs if ((split_status[i] & (0x1 << bit)) != 0) { 93197883Sgibbs static const char *s; 93297883Sgibbs 93397883Sgibbs s = split_status_strings[bit]; 93497883Sgibbs printf(s, ahd_name(ahd), 93597883Sgibbs split_status_source[i]); 93697883Sgibbs } 93797883Sgibbs 938114623Sgibbs if (i > 1) 93997883Sgibbs continue; 94097883Sgibbs 94197883Sgibbs if ((sg_split_status[i] & (0x1 << bit)) != 0) { 94297883Sgibbs static const char *s; 94397883Sgibbs 94497883Sgibbs s = split_status_strings[bit]; 94597883Sgibbs printf(s, ahd_name(ahd), "SG"); 94697883Sgibbs } 94797883Sgibbs } 94897883Sgibbs } 94997883Sgibbs /* 95097883Sgibbs * Clear PCI-X status bits. 95197883Sgibbs */ 952166109Sjhb aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS, 953166109Sjhb pcix_status, /*bytes*/4); 954107623Sscottl ahd_outb(ahd, CLRINT, CLRSPLTINT); 95597883Sgibbs ahd_restore_modes(ahd, saved_modes); 95697883Sgibbs} 95797883Sgibbs 95897883Sgibbsstatic int 959115330Sgibbsahd_aic7901_setup(struct ahd_softc *ahd) 960115330Sgibbs{ 961115330Sgibbs 962115330Sgibbs ahd->chip = AHD_AIC7901; 963116933Sgibbs ahd->features = AHD_AIC7901_FE; 964116933Sgibbs return (ahd_aic790X_setup(ahd)); 965115330Sgibbs} 966115330Sgibbs 967115330Sgibbsstatic int 968107440Sscottlahd_aic7901A_setup(struct ahd_softc *ahd) 96997883Sgibbs{ 970107440Sscottl 971107440Sscottl ahd->chip = AHD_AIC7901A; 972116933Sgibbs ahd->features = AHD_AIC7901A_FE; 973116933Sgibbs return (ahd_aic790X_setup(ahd)); 97497883Sgibbs} 97597883Sgibbs 97697883Sgibbsstatic int 97797883Sgibbsahd_aic7902_setup(struct ahd_softc *ahd) 97897883Sgibbs{ 979116933Sgibbs ahd->chip = AHD_AIC7902; 980116933Sgibbs ahd->features = AHD_AIC7902_FE; 981116933Sgibbs return (ahd_aic790X_setup(ahd)); 982116933Sgibbs} 983116933Sgibbs 984116933Sgibbsstatic int 985116933Sgibbsahd_aic790X_setup(struct ahd_softc *ahd) 986116933Sgibbs{ 987123579Sgibbs aic_dev_softc_t pci; 98897883Sgibbs u_int rev; 98997883Sgibbs 99097883Sgibbs pci = ahd->dev_softc; 991123579Sgibbs rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 992102686Sgibbs if (rev < ID_AIC7902_PCI_REV_A4) { 99397883Sgibbs printf("%s: Unable to attach to unsupported chip revision %d\n", 99497883Sgibbs ahd_name(ahd), rev); 995123579Sgibbs aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 99697883Sgibbs return (ENXIO); 99797883Sgibbs } 998123579Sgibbs ahd->channel = aic_get_pci_function(pci) + 'A'; 99997883Sgibbs if (rev < ID_AIC7902_PCI_REV_B0) { 100097883Sgibbs /* 100197883Sgibbs * Enable A series workarounds. 100297883Sgibbs */ 100397883Sgibbs ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 100497883Sgibbs | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 100597883Sgibbs | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 100697883Sgibbs | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 100797883Sgibbs | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1008111954Sgibbs | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1009111954Sgibbs | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1010111954Sgibbs | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1011111954Sgibbs | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1012114623Sgibbs | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1013114623Sgibbs | AHD_FAINT_LED_BUG; 101497883Sgibbs 1015107440Sscottl /* 1016300060Spfg * IO Cell parameter setup. 1017107440Sscottl */ 1018107440Sscottl AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1019102686Sgibbs 1020107440Sscottl if ((ahd->flags & AHD_HP_BOARD) == 0) 1021107440Sscottl AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1022107440Sscottl } else { 1023107440Sscottl u_int devconfig1; 1024102686Sgibbs 1025107440Sscottl ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1026134156Sgibbs | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1027141979Sgibbs ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1028107440Sscottl 1029107440Sscottl /* 1030116933Sgibbs * Some issues have been resolved in the 7901B. 1031116933Sgibbs */ 1032116933Sgibbs if ((ahd->features & AHD_MULTI_FUNC) != 0) 1033141979Sgibbs ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG 1034141979Sgibbs | AHD_BUSFREEREV_BUG; 1035116933Sgibbs 1036116933Sgibbs /* 1037300060Spfg * IO Cell parameter setup. 1038107440Sscottl */ 1039107440Sscottl AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1040107440Sscottl AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1041107440Sscottl AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1042107440Sscottl 1043107440Sscottl /* 1044107440Sscottl * Set the PREQDIS bit for H2B which disables some workaround 1045107440Sscottl * that doesn't work on regular PCI busses. 1046107440Sscottl * XXX - Find out exactly what this does from the hardware 1047107440Sscottl * folks! 1048107440Sscottl */ 1049123579Sgibbs devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1050123579Sgibbs aic_pci_write_config(pci, DEVCONFIG1, 1051107440Sscottl devconfig1|PREQDIS, /*bytes*/1); 1052123579Sgibbs devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1053107440Sscottl } 1054107440Sscottl 1055102686Sgibbs return (0); 1056102686Sgibbs} 1057