1139749Simp/*- 297883Sgibbs * Core definitions and data structures shareable across OS platforms. 397883Sgibbs * 4102680Sgibbs * Copyright (c) 1994-2002 Justin T. Gibbs. 5102680Sgibbs * Copyright (c) 2000-2002 Adaptec Inc. 697883Sgibbs * All rights reserved. 797883Sgibbs * 897883Sgibbs * Redistribution and use in source and binary forms, with or without 997883Sgibbs * modification, are permitted provided that the following conditions 1097883Sgibbs * are met: 1197883Sgibbs * 1. Redistributions of source code must retain the above copyright 1297883Sgibbs * notice, this list of conditions, and the following disclaimer, 1397883Sgibbs * without modification. 1497883Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1597883Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1697883Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1797883Sgibbs * including a substantially similar Disclaimer requirement for further 1897883Sgibbs * binary redistribution. 1997883Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2097883Sgibbs * of any contributors may be used to endorse or promote products derived 2197883Sgibbs * from this software without specific prior written permission. 2297883Sgibbs * 2397883Sgibbs * Alternatively, this software may be distributed under the terms of the 2497883Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2597883Sgibbs * Software Foundation. 2697883Sgibbs * 2797883Sgibbs * NO WARRANTY 2897883Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2997883Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3097883Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3197883Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3297883Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3397883Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3497883Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3597883Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3697883Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3797883Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3897883Sgibbs * POSSIBILITY OF SUCH DAMAGES. 3997883Sgibbs * 40129134Sgibbs * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#107 $ 4197883Sgibbs * 4297883Sgibbs * $FreeBSD$ 4397883Sgibbs */ 4497883Sgibbs 4597883Sgibbs#ifndef _AIC79XX_H_ 4697883Sgibbs#define _AIC79XX_H_ 4797883Sgibbs 4897883Sgibbs/* Register Definitions */ 4997883Sgibbs#include "aic79xx_reg.h" 5097883Sgibbs 5197883Sgibbs/************************* Forward Declarations *******************************/ 5297883Sgibbsstruct ahd_platform_data; 5397883Sgibbsstruct scb_platform_data; 5497883Sgibbs 5597883Sgibbs/****************************** Useful Macros *********************************/ 5697883Sgibbs#ifndef MAX 5797883Sgibbs#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 5897883Sgibbs#endif 5997883Sgibbs 6097883Sgibbs#ifndef MIN 6197883Sgibbs#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 6297883Sgibbs#endif 6397883Sgibbs 6497883Sgibbs#ifndef TRUE 6597883Sgibbs#define TRUE 1 6697883Sgibbs#endif 6797883Sgibbs#ifndef FALSE 6897883Sgibbs#define FALSE 0 6997883Sgibbs#endif 7097883Sgibbs 7197883Sgibbs#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 7297883Sgibbs 7397883Sgibbs#define ALL_CHANNELS '\0' 7497883Sgibbs#define ALL_TARGETS_MASK 0xFFFF 7597883Sgibbs#define INITIATOR_WILDCARD (~0) 7697883Sgibbs#define SCB_LIST_NULL 0xFF00 77123579Sgibbs#define SCB_LIST_NULL_LE (aic_htole16(SCB_LIST_NULL)) 78125448Sgibbs#define QOUTFIFO_ENTRY_VALID 0x80 7997883Sgibbs#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 8097883Sgibbs 8197883Sgibbs#define SCSIID_TARGET(ahd, scsiid) \ 8297883Sgibbs (((scsiid) & TID) >> TID_SHIFT) 8397883Sgibbs#define SCSIID_OUR_ID(scsiid) \ 8497883Sgibbs ((scsiid) & OID) 8597883Sgibbs#define SCSIID_CHANNEL(ahd, scsiid) ('A') 8697883Sgibbs#define SCB_IS_SCSIBUS_B(ahd, scb) (0) 8797883Sgibbs#define SCB_GET_OUR_ID(scb) \ 8897883Sgibbs SCSIID_OUR_ID((scb)->hscb->scsiid) 8997883Sgibbs#define SCB_GET_TARGET(ahd, scb) \ 9097883Sgibbs SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 9197883Sgibbs#define SCB_GET_CHANNEL(ahd, scb) \ 9297883Sgibbs SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 9397883Sgibbs#define SCB_GET_LUN(scb) \ 9497883Sgibbs ((scb)->hscb->lun) 9597883Sgibbs#define SCB_GET_TARGET_OFFSET(ahd, scb) \ 9697883Sgibbs SCB_GET_TARGET(ahd, scb) 9797883Sgibbs#define SCB_GET_TARGET_MASK(ahd, scb) \ 9897883Sgibbs (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 99109588Sgibbs#ifdef AHD_DEBUG 100109588Sgibbs#define SCB_IS_SILENT(scb) \ 101109588Sgibbs ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 102109588Sgibbs && (((scb)->flags & SCB_SILENT) != 0)) 103109588Sgibbs#else 104109588Sgibbs#define SCB_IS_SILENT(scb) \ 105109588Sgibbs (((scb)->flags & SCB_SILENT) != 0) 106109588Sgibbs#endif 10797883Sgibbs/* 10897883Sgibbs * TCLs have the following format: TTTTLLLLLLLL 10997883Sgibbs */ 11097883Sgibbs#define TCL_TARGET_OFFSET(tcl) \ 11197883Sgibbs ((((tcl) >> 4) & TID) >> 4) 11297883Sgibbs#define TCL_LUN(tcl) \ 113102680Sgibbs (tcl & (AHD_NUM_LUNS - 1)) 11497883Sgibbs#define BUILD_TCL(scsiid, lun) \ 11597883Sgibbs ((lun) | (((scsiid) & TID) << 4)) 11697883Sgibbs#define BUILD_TCL_RAW(target, channel, lun) \ 11797883Sgibbs ((lun) | ((target) << 8)) 11897883Sgibbs 11997883Sgibbs#define SCB_GET_TAG(scb) \ 120123579Sgibbs aic_le16toh(scb->hscb->tag) 12197883Sgibbs 12297883Sgibbs#ifndef AHD_TARGET_MODE 12397883Sgibbs#undef AHD_TMODE_ENABLE 12497883Sgibbs#define AHD_TMODE_ENABLE 0 12597883Sgibbs#endif 12697883Sgibbs 127102680Sgibbs#define AHD_BUILD_COL_IDX(target, lun) \ 128102680Sgibbs (((lun) << 4) | target) 129102680Sgibbs 130102680Sgibbs#define AHD_GET_SCB_COL_IDX(ahd, scb) \ 131102680Sgibbs ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 132102680Sgibbs 133102680Sgibbs#define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 134102680Sgibbsdo { \ 135102680Sgibbs (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 136102680Sgibbs (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 137102680Sgibbs} while (0) 138102680Sgibbs 139102680Sgibbs#define AHD_COPY_SCB_COL_IDX(dst, src) \ 140102680Sgibbsdo { \ 141102680Sgibbs dst->hscb->scsiid = src->hscb->scsiid; \ 142102680Sgibbs dst->hscb->lun = src->hscb->lun; \ 143102680Sgibbs} while (0) 144102680Sgibbs 145102680Sgibbs#define AHD_NEVER_COL_IDX 0xFFFF 146102680Sgibbs 14797883Sgibbs/**************************** Driver Constants ********************************/ 14897883Sgibbs/* 14997883Sgibbs * The maximum number of supported targets. 15097883Sgibbs */ 15197883Sgibbs#define AHD_NUM_TARGETS 16 15297883Sgibbs 15397883Sgibbs/* 15497883Sgibbs * The maximum number of supported luns. 15597883Sgibbs * The identify message only supports 64 luns in non-packetized transfers. 15697883Sgibbs * You can have 2^64 luns when information unit transfers are enabled, 15797883Sgibbs * but until we see a need to support that many, we support 256. 15897883Sgibbs */ 15997883Sgibbs#define AHD_NUM_LUNS_NONPKT 64 16097883Sgibbs#define AHD_NUM_LUNS 256 16197883Sgibbs 16297883Sgibbs/* 16397883Sgibbs * The maximum transfer per S/G segment. 16497883Sgibbs */ 16597883Sgibbs#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 16697883Sgibbs 16797883Sgibbs/* 16897883Sgibbs * The maximum amount of SCB storage in hardware on a controller. 16997883Sgibbs * This value represents an upper bound. Due to software design, 17097883Sgibbs * we may not be able to use this number. 17197883Sgibbs */ 17297883Sgibbs#define AHD_SCB_MAX 512 17397883Sgibbs 17497883Sgibbs/* 17597883Sgibbs * The maximum number of concurrent transactions supported per driver instance. 17697883Sgibbs * Sequencer Control Blocks (SCBs) store per-transaction information. 17797883Sgibbs */ 178102680Sgibbs#define AHD_MAX_QUEUE AHD_SCB_MAX 17997883Sgibbs 18097883Sgibbs/* 18197883Sgibbs * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 182114623Sgibbs * in size and accommodate as many transactions as can be queued concurrently. 18397883Sgibbs */ 184102680Sgibbs#define AHD_QIN_SIZE AHD_MAX_QUEUE 185102680Sgibbs#define AHD_QOUT_SIZE AHD_MAX_QUEUE 18697883Sgibbs 18797883Sgibbs#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 18897883Sgibbs/* 189102680Sgibbs * The maximum amount of SCB storage we allocate in host memory. 19097883Sgibbs */ 191102680Sgibbs#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 19297883Sgibbs 19397883Sgibbs/* 19497883Sgibbs * Ring Buffer of incoming target commands. 19597883Sgibbs * We allocate 256 to simplify the logic in the sequencer 19697883Sgibbs * by using the natural wrap point of an 8bit counter. 19797883Sgibbs */ 19897883Sgibbs#define AHD_TMODE_CMDS 256 19997883Sgibbs 20097883Sgibbs/* Reset line assertion time in us */ 201102680Sgibbs#define AHD_BUSRESET_DELAY 25 20297883Sgibbs 20397883Sgibbs/******************* Chip Characteristics/Operating Settings *****************/ 204125448Sgibbsextern uint32_t ahd_attach_to_HostRAID_controllers; 205125448Sgibbs 20697883Sgibbs/* 20797883Sgibbs * Chip Type 20897883Sgibbs * The chip order is from least sophisticated to most sophisticated. 20997883Sgibbs */ 21097883Sgibbstypedef enum { 21197883Sgibbs AHD_NONE = 0x0000, 21297883Sgibbs AHD_CHIPID_MASK = 0x00FF, 21397883Sgibbs AHD_AIC7901 = 0x0001, 21497883Sgibbs AHD_AIC7902 = 0x0002, 215102680Sgibbs AHD_AIC7901A = 0x0003, 21697883Sgibbs AHD_PCI = 0x0100, /* Bus type PCI */ 21797883Sgibbs AHD_PCIX = 0x0200, /* Bus type PCIX */ 21897883Sgibbs AHD_BUS_MASK = 0x0F00 21997883Sgibbs} ahd_chip; 22097883Sgibbs 22197883Sgibbs/* 22297883Sgibbs * Features available in each chip type. 22397883Sgibbs */ 22497883Sgibbstypedef enum { 225107441Sscottl AHD_FENONE = 0x00000, 226107441Sscottl AHD_WIDE = 0x00001,/* Wide Channel */ 227107441Sscottl AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 228107441Sscottl AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 229107441Sscottl AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 230107441Sscottl AHD_RTI = 0x04000,/* Retained Training Support */ 231107441Sscottl AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 232107441Sscottl AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 233123579Sgibbs AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */ 234107441Sscottl AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 235107441Sscottl AHD_AIC7901_FE = AHD_FENONE, 236116933Sgibbs AHD_AIC7901A_FE = AHD_FENONE, 237107441Sscottl AHD_AIC7902_FE = AHD_MULTI_FUNC 23897883Sgibbs} ahd_feature; 23997883Sgibbs 24097883Sgibbs/* 24197883Sgibbs * Bugs in the silicon that we work around in software. 24297883Sgibbs */ 24397883Sgibbstypedef enum { 24497883Sgibbs AHD_BUGNONE = 0x0000, 245107441Sscottl /* 246107441Sscottl * Rev A hardware fails to update LAST/CURR/NEXTSCB 247107441Sscottl * correctly in certain packetized selection cases. 248107441Sscottl */ 24997883Sgibbs AHD_SENT_SCB_UPDATE_BUG = 0x0001, 250107441Sscottl /* The wrong SCB is accessed to check the abort pending bit. */ 25197883Sgibbs AHD_ABORT_LQI_BUG = 0x0002, 252107441Sscottl /* Packetized bitbucket crosses packet boundaries. */ 25397883Sgibbs AHD_PKT_BITBUCKET_BUG = 0x0004, 254107441Sscottl /* The selection timer runs twice as long as its setting. */ 25597883Sgibbs AHD_LONG_SETIMO_BUG = 0x0008, 256107441Sscottl /* The Non-LQ CRC error status is delayed until phase change. */ 25797883Sgibbs AHD_NLQICRC_DELAYED_BUG = 0x0010, 258107441Sscottl /* The chip must be reset for all outgoing bus resets. */ 25997883Sgibbs AHD_SCSIRST_BUG = 0x0020, 260107441Sscottl /* Some PCIX fields must be saved and restored across chip reset. */ 261102680Sgibbs AHD_PCIX_CHIPRST_BUG = 0x0040, 262107441Sscottl /* MMAPIO is not functional in PCI-X mode. */ 263102680Sgibbs AHD_PCIX_MMAPIO_BUG = 0x0080, 264111954Sgibbs /* Reads to SCBRAM fail to reset the discard timer. */ 265111954Sgibbs AHD_PCIX_SCBRAM_RD_BUG = 0x0100, 26697883Sgibbs /* Bug workarounds that can be disabled on non-PCIX busses. */ 267102680Sgibbs AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 268111954Sgibbs | AHD_PCIX_MMAPIO_BUG 269111954Sgibbs | AHD_PCIX_SCBRAM_RD_BUG, 270107441Sscottl /* 271107441Sscottl * LQOSTOP0 status set even for forced selections with ATN 272107441Sscottl * to perform non-packetized message delivery. 273107441Sscottl */ 274111954Sgibbs AHD_LQO_ATNO_BUG = 0x0200, 275107441Sscottl /* FIFO auto-flush does not always trigger. */ 276111954Sgibbs AHD_AUTOFLUSH_BUG = 0x0400, 277107441Sscottl /* The CLRLQO registers are not self-clearing. */ 278111954Sgibbs AHD_CLRLQO_AUTOCLR_BUG = 0x0800, 279107441Sscottl /* The PACKETIZED status bit refers to the previous connection. */ 280111954Sgibbs AHD_PKTIZED_STATUS_BUG = 0x1000, 281107441Sscottl /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 282111954Sgibbs AHD_PKT_LUN_BUG = 0x2000, 283107441Sscottl /* 284107441Sscottl * Only the FIFO allocated to the non-packetized connection may 285107441Sscottl * be in use during a non-packetzied connection. 286107441Sscottl */ 287111954Sgibbs AHD_NONPACKFIFO_BUG = 0x4000, 288107441Sscottl /* 289107441Sscottl * Writing to a DFF SCBPTR register may fail if concurent with 290107441Sscottl * a hardware write to the other DFF SCBPTR register. This is 291107441Sscottl * not currently a concern in our sequencer since all chips with 292107441Sscottl * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 293107441Sscottl * occur in non-packetized connections. 294107441Sscottl */ 295111954Sgibbs AHD_MDFF_WSCBPTR_BUG = 0x8000, 296107441Sscottl /* SGHADDR updates are slow. */ 297111954Sgibbs AHD_REG_SLOW_SETTLE_BUG = 0x10000, 298107441Sscottl /* 299107441Sscottl * Changing the MODE_PTR coincident with an interrupt that 300107441Sscottl * switches to a different mode will cause the interrupt to 301107441Sscottl * be in the mode written outside of interrupt context. 302107441Sscottl */ 303111954Sgibbs AHD_SET_MODE_BUG = 0x20000, 304107441Sscottl /* Non-packetized busfree revision does not work. */ 305111954Sgibbs AHD_BUSFREEREV_BUG = 0x40000, 306107441Sscottl /* 307107441Sscottl * Paced transfers are indicated with a non-standard PPR 308107441Sscottl * option bit in the neg table, 160MHz is indicated by 309107441Sscottl * sync factor 0x7, and the offset if off by a factor of 2. 310107441Sscottl */ 311111954Sgibbs AHD_PACED_NEGTABLE_BUG = 0x80000, 312107441Sscottl /* LQOOVERRUN false positives. */ 313111954Sgibbs AHD_LQOOVERRUN_BUG = 0x100000, 314107441Sscottl /* 315107441Sscottl * Controller write to INTSTAT will lose to a host 316107441Sscottl * write to CLRINT. 317107441Sscottl */ 318111954Sgibbs AHD_INTCOLLISION_BUG = 0x200000, 319111653Sgibbs /* 320111653Sgibbs * The GEM318 violates the SCSI spec by not waiting 321111653Sgibbs * the mandated bus settle delay between phase changes 322111653Sgibbs * in some situations. Some aic79xx chip revs. are more 323111653Sgibbs * strict in this regard and will treat REQ assertions 324111653Sgibbs * that fall within the bus settle delay window as 325111653Sgibbs * glitches. This flag tells the firmware to tolerate 326111653Sgibbs * early REQ assertions. 327111653Sgibbs */ 328114623Sgibbs AHD_EARLY_REQ_BUG = 0x400000, 329114623Sgibbs /* 330114623Sgibbs * The LED does not stay on long enough in packetized modes. 331114623Sgibbs */ 332114623Sgibbs AHD_FAINT_LED_BUG = 0x800000 33397883Sgibbs} ahd_bug; 33497883Sgibbs 33597883Sgibbs/* 33697883Sgibbs * Configuration specific settings. 33797883Sgibbs * The driver determines these settings by probing the 33897883Sgibbs * chip/controller's configuration. 33997883Sgibbs */ 34097883Sgibbstypedef enum { 34197883Sgibbs AHD_FNONE = 0x00000, 342114623Sgibbs AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */ 34397883Sgibbs AHD_USEDEFAULTS = 0x00004,/* 34497883Sgibbs * For cards without an seeprom 34597883Sgibbs * or a BIOS to initialize the chip's 34697883Sgibbs * SRAM, we use the default target 34797883Sgibbs * settings. 34897883Sgibbs */ 34997883Sgibbs AHD_SEQUENCER_DEBUG = 0x00008, 35097883Sgibbs AHD_RESET_BUS_A = 0x00010, 35197883Sgibbs AHD_EXTENDED_TRANS_A = 0x00020, 35297883Sgibbs AHD_TERM_ENB_A = 0x00040, 35397883Sgibbs AHD_SPCHK_ENB_A = 0x00080, 35497883Sgibbs AHD_STPWLEVEL_A = 0x00100, 35597883Sgibbs AHD_INITIATORROLE = 0x00200,/* 35697883Sgibbs * Allow initiator operations on 35797883Sgibbs * this controller. 35897883Sgibbs */ 35997883Sgibbs AHD_TARGETROLE = 0x00400,/* 36097883Sgibbs * Allow target operations on this 36197883Sgibbs * controller. 36297883Sgibbs */ 36397883Sgibbs AHD_RESOURCE_SHORTAGE = 0x00800, 36497883Sgibbs AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 36597883Sgibbs AHD_INT50_SPEEDFLEX = 0x02000,/* 36697883Sgibbs * Internal 50pin connector 36797883Sgibbs * sits behind an aic3860 36897883Sgibbs */ 36997883Sgibbs AHD_BIOS_ENABLED = 0x04000, 37097883Sgibbs AHD_ALL_INTERRUPTS = 0x08000, 37197883Sgibbs AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 37297883Sgibbs AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 37397883Sgibbs AHD_CURRENT_SENSING = 0x40000, 37497883Sgibbs AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 375107441Sscottl AHD_HP_BOARD = 0x100000, 376109588Sgibbs AHD_RESET_POLL_ACTIVE = 0x200000, 377109588Sgibbs AHD_UPDATE_PEND_CMDS = 0x400000, 378116938Sgibbs AHD_RUNNING_QOUTFIFO = 0x800000, 379123579Sgibbs AHD_HAD_FIRST_SEL = 0x1000000, 380125448Sgibbs AHD_SHUTDOWN_RECOVERY = 0x2000000, /* Terminate recovery thread. */ 381125448Sgibbs AHD_HOSTRAID_BOARD = 0x4000000 38297883Sgibbs} ahd_flag; 38397883Sgibbs 38497883Sgibbs/************************* Hardware SCB Definition ***************************/ 38597883Sgibbs 38697883Sgibbs/* 38797883Sgibbs * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 388114623Sgibbs * consists of a "hardware SCB" mirroring the fields available on the card 38997883Sgibbs * and additional information the kernel stores for each transaction. 39097883Sgibbs * 39197883Sgibbs * To minimize space utilization, a portion of the hardware scb stores 39297883Sgibbs * different data during different portions of a SCSI transaction. 39397883Sgibbs * As initialized by the host driver for the initiator role, this area 39497883Sgibbs * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 39597883Sgibbs * the cdb has been presented to the target, this area serves to store 39697883Sgibbs * residual transfer information and the SCSI status byte. 39797883Sgibbs * For the target role, the contents of this area do not change, but 39897883Sgibbs * still serve a different purpose than for the initiator role. See 39997883Sgibbs * struct target_data for details. 40097883Sgibbs */ 40197883Sgibbs 40297883Sgibbs/* 40397883Sgibbs * Status information embedded in the shared poriton of 40497883Sgibbs * an SCB after passing the cdb to the target. The kernel 40597883Sgibbs * driver will only read this data for transactions that 40697883Sgibbs * complete abnormally. 40797883Sgibbs */ 40897883Sgibbsstruct initiator_status { 40997883Sgibbs uint32_t residual_datacnt; /* Residual in the current S/G seg */ 41097883Sgibbs uint32_t residual_sgptr; /* The next S/G for this transfer */ 41197883Sgibbs uint8_t scsi_status; /* Standard SCSI status byte */ 41297883Sgibbs}; 41397883Sgibbs 41497883Sgibbsstruct target_status { 41597883Sgibbs uint32_t residual_datacnt; /* Residual in the current S/G seg */ 41697883Sgibbs uint32_t residual_sgptr; /* The next S/G for this transfer */ 41797883Sgibbs uint8_t scsi_status; /* SCSI status to give to initiator */ 41897883Sgibbs uint8_t target_phases; /* Bitmap of phases to execute */ 41997883Sgibbs uint8_t data_phase; /* Data-In or Data-Out */ 42097883Sgibbs uint8_t initiator_tag; /* Initiator's transaction tag */ 42197883Sgibbs}; 42297883Sgibbs 42397883Sgibbs/* 42497883Sgibbs * Initiator mode SCB shared data area. 42597883Sgibbs * If the embedded CDB is 12 bytes or less, we embed 42697883Sgibbs * the sense buffer address in the SCB. This allows 427111653Sgibbs * us to retrieve sense information without interrupting 42897883Sgibbs * the host in packetized mode. 42997883Sgibbs */ 43097883Sgibbstypedef uint32_t sense_addr_t; 43197883Sgibbs#define MAX_CDB_LEN 16 43297883Sgibbs#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 43397883Sgibbsunion initiator_data { 434111653Sgibbs struct { 435111653Sgibbs uint64_t cdbptr; 436111653Sgibbs uint8_t cdblen; 437111653Sgibbs } cdb_from_host; 43897883Sgibbs uint8_t cdb[MAX_CDB_LEN]; 43997883Sgibbs struct { 44097883Sgibbs uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 44197883Sgibbs sense_addr_t sense_addr; 44297883Sgibbs } cdb_plus_saddr; 44397883Sgibbs}; 44497883Sgibbs 44597883Sgibbs/* 44697883Sgibbs * Target mode version of the shared data SCB segment. 44797883Sgibbs */ 44897883Sgibbsstruct target_data { 44997883Sgibbs uint32_t spare[2]; 45097883Sgibbs uint8_t scsi_status; /* SCSI status to give to initiator */ 45197883Sgibbs uint8_t target_phases; /* Bitmap of phases to execute */ 45297883Sgibbs uint8_t data_phase; /* Data-In or Data-Out */ 45397883Sgibbs uint8_t initiator_tag; /* Initiator's transaction tag */ 45497883Sgibbs}; 45597883Sgibbs 45697883Sgibbsstruct hardware_scb { 45797883Sgibbs/*0*/ union { 45897883Sgibbs union initiator_data idata; 45997883Sgibbs struct target_data tdata; 46097883Sgibbs struct initiator_status istatus; 46197883Sgibbs struct target_status tstatus; 46297883Sgibbs } shared_data; 46397883Sgibbs/* 46497883Sgibbs * A word about residuals. 46597883Sgibbs * The scb is presented to the sequencer with the dataptr and datacnt 46697883Sgibbs * fields initialized to the contents of the first S/G element to 46797883Sgibbs * transfer. The sgptr field is initialized to the bus address for 46897883Sgibbs * the S/G element that follows the first in the in core S/G array 46997883Sgibbs * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 47097883Sgibbs * S/G entry for this transfer (single S/G element transfer with the 47197883Sgibbs * first elements address and length preloaded in the dataptr/datacnt 47297883Sgibbs * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 47397883Sgibbs * The SG_FULL_RESID flag ensures that the residual will be correctly 47497883Sgibbs * noted even if no data transfers occur. Once the data phase is entered, 47597883Sgibbs * the residual sgptr and datacnt are loaded from the sgptr and the 47697883Sgibbs * datacnt fields. After each S/G element's dataptr and length are 47797883Sgibbs * loaded into the hardware, the residual sgptr is advanced. After 47897883Sgibbs * each S/G element is expired, its datacnt field is checked to see 47997883Sgibbs * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 48097883Sgibbs * residual sg ptr and the transfer is considered complete. If the 481300060Spfg * sequencer determines that there is a residual in the transfer, or 48297883Sgibbs * there is non-zero status, it will set the SG_STATUS_VALID flag in 48397883Sgibbs * sgptr and dma the scb back into host memory. To sumarize: 48497883Sgibbs * 48597883Sgibbs * Sequencer: 48697883Sgibbs * o A residual has occurred if SG_FULL_RESID is set in sgptr, 48797883Sgibbs * or residual_sgptr does not have SG_LIST_NULL set. 48897883Sgibbs * 489300060Spfg * o We are transferring the last segment if residual_datacnt has 49097883Sgibbs * the SG_LAST_SEG flag set. 49197883Sgibbs * 49297883Sgibbs * Host: 49397883Sgibbs * o A residual can only have occurred if a completed scb has the 49497883Sgibbs * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 49597883Sgibbs * the residual_datacnt, and the residual_sgptr field will tell 49697883Sgibbs * for sure. 49797883Sgibbs * 49897883Sgibbs * o residual_sgptr and sgptr refer to the "next" sg entry 49997883Sgibbs * and so may point beyond the last valid sg entry for the 50097883Sgibbs * transfer. 50197883Sgibbs */ 50297883Sgibbs#define SG_PTR_MASK 0xFFFFFFF8 503115407Sscottl/*16*/ uint16_t tag; /* Reused by Sequencer. */ 504115407Sscottl/*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 505115407Sscottl/*19*/ uint8_t scsiid; /* 50697883Sgibbs * Selection out Id 50797883Sgibbs * Our Id (bits 0-3) Their ID (bits 4-7) 50897883Sgibbs */ 509115407Sscottl/*20*/ uint8_t lun; 510115407Sscottl/*21*/ uint8_t task_attribute; 511115407Sscottl/*22*/ uint8_t cdb_len; 512115407Sscottl/*23*/ uint8_t task_management; 513115407Sscottl/*24*/ uint64_t dataptr; 514115407Sscottl/*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 515115407Sscottl/*36*/ uint32_t sgptr; 516115407Sscottl/*40*/ uint32_t hscb_busaddr; 517115407Sscottl/*44*/ uint32_t next_hscb_busaddr; 518114623Sgibbs/********** Long lun field only downloaded for full 8 byte lun support ********/ 519102680Sgibbs/*48*/ uint8_t pkt_long_lun[8]; 52097883Sgibbs/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 521102680Sgibbs/*56*/ uint8_t spare[8]; 52297883Sgibbs}; 52397883Sgibbs 52497883Sgibbs/************************ Kernel SCB Definitions ******************************/ 52597883Sgibbs/* 52697883Sgibbs * Some fields of the SCB are OS dependent. Here we collect the 52797883Sgibbs * definitions for elements that all OS platforms need to include 52897883Sgibbs * in there SCB definition. 52997883Sgibbs */ 53097883Sgibbs 53197883Sgibbs/* 532300060Spfg * Definition of a scatter/gather element as transferred to the controller. 53397883Sgibbs * The aic7xxx chips only support a 24bit length. We use the top byte of 53497883Sgibbs * the length to store additional address bits and a flag to indicate 53597883Sgibbs * that a given segment terminates the transfer. This gives us an 53697883Sgibbs * addressable range of 512GB on machines with 64bit PCI or with chips 53797883Sgibbs * that can support dual address cycles on 32bit PCI busses. 53897883Sgibbs */ 53997883Sgibbsstruct ahd_dma_seg { 54097883Sgibbs uint32_t addr; 54197883Sgibbs uint32_t len; 54297883Sgibbs#define AHD_DMA_LAST_SEG 0x80000000 54397883Sgibbs#define AHD_SG_HIGH_ADDR_MASK 0x7F000000 54497883Sgibbs#define AHD_SG_LEN_MASK 0x00FFFFFF 54597883Sgibbs}; 54697883Sgibbs 54797883Sgibbsstruct ahd_dma64_seg { 54897883Sgibbs uint64_t addr; 54997883Sgibbs uint32_t len; 55097883Sgibbs uint32_t pad; 55197883Sgibbs}; 55297883Sgibbs 55397883Sgibbsstruct map_node { 55497883Sgibbs bus_dmamap_t dmamap; 555123579Sgibbs bus_addr_t busaddr; 55697883Sgibbs uint8_t *vaddr; 55797883Sgibbs SLIST_ENTRY(map_node) links; 55897883Sgibbs}; 55997883Sgibbs 56097883Sgibbs/* 56197883Sgibbs * The current state of this SCB. 56297883Sgibbs */ 56397883Sgibbstypedef enum { 564102680Sgibbs SCB_FLAG_NONE = 0x00000, 565102680Sgibbs SCB_TRANSMISSION_ERROR = 0x00001,/* 566102680Sgibbs * We detected a parity or CRC 567102680Sgibbs * error that has effected the 568102680Sgibbs * payload of the command. This 569102680Sgibbs * flag is checked when normal 570102680Sgibbs * status is returned to catch 571102680Sgibbs * the case of a target not 572102680Sgibbs * responding to our attempt 573102680Sgibbs * to report the error. 574102680Sgibbs */ 575102680Sgibbs SCB_OTHERTCL_TIMEOUT = 0x00002,/* 576102680Sgibbs * Another device was active 577102680Sgibbs * during the first timeout for 578102680Sgibbs * this SCB so we gave ourselves 579102680Sgibbs * an additional timeout period 580102680Sgibbs * in case it was hogging the 581102680Sgibbs * bus. 582102680Sgibbs */ 583102680Sgibbs SCB_DEVICE_RESET = 0x00004, 584102680Sgibbs SCB_SENSE = 0x00008, 585102680Sgibbs SCB_CDB32_PTR = 0x00010, 586102680Sgibbs SCB_RECOVERY_SCB = 0x00020, 587102680Sgibbs SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 588102680Sgibbs SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 589102680Sgibbs SCB_ABORT = 0x00100, 590107441Sscottl SCB_ACTIVE = 0x00200, 591107441Sscottl SCB_TARGET_IMMEDIATE = 0x00400, 592107441Sscottl SCB_PACKETIZED = 0x00800, 593107441Sscottl SCB_EXPECT_PPR_BUSFREE = 0x01000, 594107441Sscottl SCB_PKT_SENSE = 0x02000, 595107441Sscottl SCB_CMDPHASE_ABORT = 0x04000, 596109588Sgibbs SCB_ON_COL_LIST = 0x08000, 597123579Sgibbs SCB_SILENT = 0x10000,/* 598109588Sgibbs * Be quiet about transmission type 599109588Sgibbs * errors. They are expected and we 600109588Sgibbs * don't want to upset the user. This 601109588Sgibbs * flag is typically used during DV. 602109588Sgibbs */ 603123579Sgibbs SCB_TIMEDOUT = 0x20000/* 604123579Sgibbs * SCB has timed out and is on the 605123579Sgibbs * timedout list. 606123579Sgibbs */ 60797883Sgibbs} scb_flag; 60897883Sgibbs 60997883Sgibbsstruct scb { 61097883Sgibbs struct hardware_scb *hscb; 61197883Sgibbs union { 61297883Sgibbs SLIST_ENTRY(scb) sle; 613102680Sgibbs LIST_ENTRY(scb) le; 61497883Sgibbs TAILQ_ENTRY(scb) tqe; 61597883Sgibbs } links; 616102680Sgibbs union { 617102680Sgibbs SLIST_ENTRY(scb) sle; 618102680Sgibbs LIST_ENTRY(scb) le; 619102680Sgibbs TAILQ_ENTRY(scb) tqe; 620102680Sgibbs } links2; 621102680Sgibbs#define pending_links links2.le 622102680Sgibbs#define collision_links links2.le 623123579Sgibbs LIST_ENTRY(scb) timedout_links; 624102680Sgibbs struct scb *col_scb; 625123579Sgibbs aic_io_ctx_t io_ctx; 62697883Sgibbs struct ahd_softc *ahd_softc; 62797883Sgibbs scb_flag flags; 62897883Sgibbs#ifndef __linux__ 62997883Sgibbs bus_dmamap_t dmamap; 63097883Sgibbs#endif 63197883Sgibbs struct scb_platform_data *platform_data; 63297883Sgibbs struct map_node *hscb_map; 63397883Sgibbs struct map_node *sg_map; 63497883Sgibbs struct map_node *sense_map; 63597883Sgibbs void *sg_list; 63697883Sgibbs uint8_t *sense_data; 63797883Sgibbs bus_addr_t sg_list_busaddr; 63897883Sgibbs bus_addr_t sense_busaddr; 63997883Sgibbs u_int sg_count;/* How full ahd_dma_seg is */ 640107441Sscottl#define AHD_MAX_LQ_CRC_ERRORS 5 641107441Sscottl u_int crc_retry_count; 642168807Sscottl aic_timer_t io_timer; 64397883Sgibbs}; 64497883Sgibbs 645102680SgibbsTAILQ_HEAD(scb_tailq, scb); 646102680SgibbsLIST_HEAD(scb_list, scb); 647102680Sgibbs 64897883Sgibbsstruct scb_data { 649102680Sgibbs /* 650102680Sgibbs * TAILQ of lists of free SCBs grouped by device 651102680Sgibbs * collision domains. 652102680Sgibbs */ 653102680Sgibbs struct scb_tailq free_scbs; 654102680Sgibbs 655102680Sgibbs /* 656102680Sgibbs * Per-device lists of SCBs whose tag ID would collide 657102680Sgibbs * with an already active tag on the device. 658102680Sgibbs */ 659102680Sgibbs struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 660102680Sgibbs 661102680Sgibbs /* 662102680Sgibbs * SCBs that will not collide with any active device. 663102680Sgibbs */ 664102680Sgibbs struct scb_list any_dev_free_scb_list; 665102680Sgibbs 666102680Sgibbs /* 667102680Sgibbs * Mapping from tag to SCB. 668102680Sgibbs */ 66997883Sgibbs struct scb *scbindex[AHD_SCB_MAX]; 670102680Sgibbs 671133911Sgibbs u_int recovery_scbs; /* Transactions currently in recovery */ 672133911Sgibbs 67397883Sgibbs /* 67497883Sgibbs * "Bus" addresses of our data structures. 67597883Sgibbs */ 67697883Sgibbs bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 67797883Sgibbs bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 67897883Sgibbs bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 679133911Sgibbs 68097883Sgibbs SLIST_HEAD(, map_node) hscb_maps; 68197883Sgibbs SLIST_HEAD(, map_node) sg_maps; 68297883Sgibbs SLIST_HEAD(, map_node) sense_maps; 68397883Sgibbs int scbs_left; /* unallocated scbs in head map_node */ 68497883Sgibbs int sgs_left; /* unallocated sgs in head map_node */ 68597883Sgibbs int sense_left; /* unallocated sense in head map_node */ 68697883Sgibbs uint16_t numscbs; 68797883Sgibbs uint16_t maxhscbs; /* Number of SCBs on the card */ 68897883Sgibbs uint8_t init_level; /* 68997883Sgibbs * How far we've initialized 69097883Sgibbs * this structure. 69197883Sgibbs */ 69297883Sgibbs}; 69397883Sgibbs 69497883Sgibbs/************************ Target Mode Definitions *****************************/ 69597883Sgibbs 69697883Sgibbs/* 69797883Sgibbs * Connection desciptor for select-in requests in target mode. 69897883Sgibbs */ 69997883Sgibbsstruct target_cmd { 70097883Sgibbs uint8_t scsiid; /* Our ID and the initiator's ID */ 70197883Sgibbs uint8_t identify; /* Identify message */ 70297883Sgibbs uint8_t bytes[22]; /* 70397883Sgibbs * Bytes contains any additional message 70497883Sgibbs * bytes terminated by 0xFF. The remainder 70597883Sgibbs * is the cdb to execute. 70697883Sgibbs */ 70797883Sgibbs uint8_t cmd_valid; /* 70897883Sgibbs * When a command is complete, the firmware 70997883Sgibbs * will set cmd_valid to all bits set. 71097883Sgibbs * After the host has seen the command, 71197883Sgibbs * the bits are cleared. This allows us 71297883Sgibbs * to just peek at host memory to determine 71397883Sgibbs * if more work is complete. cmd_valid is on 71497883Sgibbs * an 8 byte boundary to simplify setting 71597883Sgibbs * it on aic7880 hardware which only has 71697883Sgibbs * limited direct access to the DMA FIFO. 71797883Sgibbs */ 71897883Sgibbs uint8_t pad[7]; 71997883Sgibbs}; 72097883Sgibbs 72197883Sgibbs/* 72297883Sgibbs * Number of events we can buffer up if we run out 72397883Sgibbs * of immediate notify ccbs. 72497883Sgibbs */ 72597883Sgibbs#define AHD_TMODE_EVENT_BUFFER_SIZE 8 72697883Sgibbsstruct ahd_tmode_event { 72797883Sgibbs uint8_t initiator_id; 72897883Sgibbs uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 72997883Sgibbs#define EVENT_TYPE_BUS_RESET 0xFF 73097883Sgibbs uint8_t event_arg; 73197883Sgibbs}; 73297883Sgibbs 73397883Sgibbs/* 73497883Sgibbs * Per enabled lun target mode state. 73597883Sgibbs * As this state is directly influenced by the host OS'es target mode 73697883Sgibbs * environment, we let the OS module define it. Forward declare the 73797883Sgibbs * structure here so we can store arrays of them, etc. in OS neutral 73897883Sgibbs * data structures. 73997883Sgibbs */ 74097883Sgibbs#ifdef AHD_TARGET_MODE 74197883Sgibbsstruct ahd_tmode_lstate { 74297883Sgibbs struct cam_path *path; 74397883Sgibbs struct ccb_hdr_slist accept_tios; 74497883Sgibbs struct ccb_hdr_slist immed_notifies; 74597883Sgibbs struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 74697883Sgibbs uint8_t event_r_idx; 74797883Sgibbs uint8_t event_w_idx; 74897883Sgibbs}; 74997883Sgibbs#else 75097883Sgibbsstruct ahd_tmode_lstate; 75197883Sgibbs#endif 75297883Sgibbs 75397883Sgibbs/******************** Transfer Negotiation Datastructures *********************/ 75497883Sgibbs#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 75597883Sgibbs#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 75697883Sgibbs#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 75797883Sgibbs#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 75897883Sgibbs#define AHD_PERIOD_10MHz 0x19 75997883Sgibbs 760107441Sscottl#define AHD_WIDTH_UNKNOWN 0xFF 761107441Sscottl#define AHD_PERIOD_UNKNOWN 0xFF 762111653Sgibbs#define AHD_OFFSET_UNKNOWN 0xFF 763107441Sscottl#define AHD_PPR_OPTS_UNKNOWN 0xFF 764107441Sscottl 76597883Sgibbs/* 76697883Sgibbs * Transfer Negotiation Information. 76797883Sgibbs */ 76897883Sgibbsstruct ahd_transinfo { 76997883Sgibbs uint8_t protocol_version; /* SCSI Revision level */ 77097883Sgibbs uint8_t transport_version; /* SPI Revision level */ 77197883Sgibbs uint8_t width; /* Bus width */ 77297883Sgibbs uint8_t period; /* Sync rate factor */ 77397883Sgibbs uint8_t offset; /* Sync offset */ 77497883Sgibbs uint8_t ppr_options; /* Parallel Protocol Request options */ 77597883Sgibbs}; 77697883Sgibbs 77797883Sgibbs/* 77897883Sgibbs * Per-initiator current, goal and user transfer negotiation information. */ 77997883Sgibbsstruct ahd_initiator_tinfo { 78097883Sgibbs struct ahd_transinfo curr; 78197883Sgibbs struct ahd_transinfo goal; 78297883Sgibbs struct ahd_transinfo user; 78397883Sgibbs}; 78497883Sgibbs 78597883Sgibbs/* 78697883Sgibbs * Per enabled target ID state. 78797883Sgibbs * Pointers to lun target state as well as sync/wide negotiation information 78897883Sgibbs * for each initiator<->target mapping. For the initiator role we pretend 78997883Sgibbs * that we are the target and the targets are the initiators since the 79097883Sgibbs * negotiation is the same regardless of role. 79197883Sgibbs */ 79297883Sgibbsstruct ahd_tmode_tstate { 79397883Sgibbs struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 79497883Sgibbs struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 79597883Sgibbs 79697883Sgibbs /* 79797883Sgibbs * Per initiator state bitmasks. 79897883Sgibbs */ 79997883Sgibbs uint16_t auto_negotiate;/* Auto Negotiation Required */ 80097883Sgibbs uint16_t discenable; /* Disconnection allowed */ 80197883Sgibbs uint16_t tagenable; /* Tagged Queuing allowed */ 80297883Sgibbs}; 80397883Sgibbs 80497883Sgibbs/* 80597883Sgibbs * Points of interest along the negotiated transfer scale. 80697883Sgibbs */ 80797883Sgibbs#define AHD_SYNCRATE_160 0x8 80897883Sgibbs#define AHD_SYNCRATE_PACED 0x8 80997883Sgibbs#define AHD_SYNCRATE_DT 0x9 81097883Sgibbs#define AHD_SYNCRATE_ULTRA2 0xa 81197883Sgibbs#define AHD_SYNCRATE_ULTRA 0xc 81297883Sgibbs#define AHD_SYNCRATE_FAST 0x19 81397883Sgibbs#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 81497883Sgibbs#define AHD_SYNCRATE_SYNC 0x32 81597883Sgibbs#define AHD_SYNCRATE_MIN 0x60 81697883Sgibbs#define AHD_SYNCRATE_ASYNC 0xFF 817109588Sgibbs#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 81897883Sgibbs 819107441Sscottl/* Safe and valid period for async negotiations. */ 820107441Sscottl#define AHD_ASYNC_XFER_PERIOD 0x44 821107441Sscottl 82297883Sgibbs/* 82397883Sgibbs * In RevA, the synctable uses a 120MHz rate for the period 82497883Sgibbs * factor 8 and 160MHz for the period factor 7. The 120MHz 82597883Sgibbs * rate never made it into the official SCSI spec, so we must 82697883Sgibbs * compensate when setting the negotiation table for Rev A 82797883Sgibbs * parts. 82897883Sgibbs */ 82997883Sgibbs#define AHD_SYNCRATE_REVA_120 0x8 83097883Sgibbs#define AHD_SYNCRATE_REVA_160 0x7 83197883Sgibbs 83297883Sgibbs/***************************** Lookup Tables **********************************/ 83397883Sgibbs/* 83497883Sgibbs * Phase -> name and message out response 83597883Sgibbs * to parity errors in each phase table. 83697883Sgibbs */ 83797883Sgibbsstruct ahd_phase_table_entry { 83897883Sgibbs uint8_t phase; 83997883Sgibbs uint8_t mesg_out; /* Message response to parity errors */ 84097883Sgibbs char *phasemsg; 84197883Sgibbs}; 84297883Sgibbs 84397883Sgibbs/************************** Serial EEPROM Format ******************************/ 84497883Sgibbs 84597883Sgibbsstruct seeprom_config { 84697883Sgibbs/* 84797883Sgibbs * Per SCSI ID Configuration Flags 84897883Sgibbs */ 84997883Sgibbs uint16_t device_flags[16]; /* words 0-15 */ 85097883Sgibbs#define CFXFER 0x003F /* synchronous transfer rate */ 85197883Sgibbs#define CFXFER_ASYNC 0x3F 85297883Sgibbs#define CFQAS 0x0040 /* Negotiate QAS */ 85397883Sgibbs#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 85497883Sgibbs#define CFSTART 0x0100 /* send start unit SCSI command */ 85597883Sgibbs#define CFINCBIOS 0x0200 /* include in BIOS scan */ 85697883Sgibbs#define CFDISC 0x0400 /* enable disconnection */ 85797883Sgibbs#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 85897883Sgibbs#define CFWIDEB 0x1000 /* wide bus device */ 85997883Sgibbs#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 86097883Sgibbs 86197883Sgibbs/* 86297883Sgibbs * BIOS Control Bits 86397883Sgibbs */ 86497883Sgibbs uint16_t bios_control; /* word 16 */ 86597883Sgibbs#define CFSUPREM 0x0001 /* support all removeable drives */ 86697883Sgibbs#define CFSUPREMB 0x0002 /* support removeable boot drives */ 86797883Sgibbs#define CFBIOSSTATE 0x000C /* BIOS Action State */ 86897883Sgibbs#define CFBS_DISABLED 0x00 86997883Sgibbs#define CFBS_ENABLED 0x04 87097883Sgibbs#define CFBS_DISABLED_SCAN 0x08 87197883Sgibbs#define CFENABLEDV 0x0010 /* Perform Domain Validation */ 87297883Sgibbs#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 87397883Sgibbs#define CFSPARITY 0x0040 /* SCSI parity */ 87497883Sgibbs#define CFEXTEND 0x0080 /* extended translation enabled */ 87597883Sgibbs#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 87697883Sgibbs#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 87797883Sgibbs#define CFMSG_VERBOSE 0x0000 87897883Sgibbs#define CFMSG_SILENT 0x0200 87997883Sgibbs#define CFMSG_DIAG 0x0400 88097883Sgibbs#define CFRESETB 0x0800 /* reset SCSI bus at boot */ 88197883Sgibbs/* UNUSED 0xf000 */ 88297883Sgibbs 88397883Sgibbs/* 88497883Sgibbs * Host Adapter Control Bits 88597883Sgibbs */ 88697883Sgibbs uint16_t adapter_control; /* word 17 */ 88797883Sgibbs#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 88897883Sgibbs#define CFSTERM 0x0002 /* SCSI low byte termination */ 88997883Sgibbs#define CFWSTERM 0x0004 /* SCSI high byte termination */ 89097883Sgibbs#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 89197883Sgibbs#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 89297883Sgibbs#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 89397883Sgibbs#define CFSTPWLEVEL 0x0040 /* Termination level control */ 89497883Sgibbs#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 89597883Sgibbs#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 89697883Sgibbs#define CFCLUSTERENB 0x8000 /* Cluster Enable */ 89797883Sgibbs 89897883Sgibbs/* 89997883Sgibbs * Bus Release Time, Host Adapter ID 90097883Sgibbs */ 90197883Sgibbs uint16_t brtime_id; /* word 18 */ 90297883Sgibbs#define CFSCSIID 0x000f /* host adapter SCSI ID */ 90397883Sgibbs/* UNUSED 0x00f0 */ 90497883Sgibbs#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 90597883Sgibbs 90697883Sgibbs/* 90797883Sgibbs * Maximum targets 90897883Sgibbs */ 90997883Sgibbs uint16_t max_targets; /* word 19 */ 91097883Sgibbs#define CFMAXTARG 0x00ff /* maximum targets */ 91197883Sgibbs#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 91297883Sgibbs#define CFBOOTID 0xf000 /* Target to boot from */ 91397883Sgibbs uint16_t res_1[10]; /* words 20-29 */ 91497883Sgibbs uint16_t signature; /* BIOS Signature */ 91597883Sgibbs#define CFSIGNATURE 0x400 91697883Sgibbs uint16_t checksum; /* word 31 */ 91797883Sgibbs}; 91897883Sgibbs 919114623Sgibbs/* 920114623Sgibbs * Vital Product Data used during POST and by the BIOS. 921114623Sgibbs */ 922114623Sgibbsstruct vpd_config { 923114623Sgibbs uint8_t bios_flags; 924114623Sgibbs#define VPDMASTERBIOS 0x0001 925114623Sgibbs#define VPDBOOTHOST 0x0002 926114623Sgibbs uint8_t reserved_1[21]; 927114623Sgibbs uint8_t resource_type; 928114623Sgibbs uint8_t resource_len[2]; 929114623Sgibbs uint8_t resource_data[8]; 930114623Sgibbs uint8_t vpd_tag; 931114623Sgibbs uint16_t vpd_len; 932114623Sgibbs uint8_t vpd_keyword[2]; 933114623Sgibbs uint8_t length; 934114623Sgibbs uint8_t revision; 935114623Sgibbs uint8_t device_flags; 936114623Sgibbs uint8_t termnation_menus[2]; 937114623Sgibbs uint8_t fifo_threshold; 938114623Sgibbs uint8_t end_tag; 939114623Sgibbs uint8_t vpd_checksum; 940114623Sgibbs uint16_t default_target_flags; 941114623Sgibbs uint16_t default_bios_flags; 942114623Sgibbs uint16_t default_ctrl_flags; 943114623Sgibbs uint8_t default_irq; 944114623Sgibbs uint8_t pci_lattime; 945114623Sgibbs uint8_t max_target; 946114623Sgibbs uint8_t boot_lun; 947114623Sgibbs uint16_t signature; 948114623Sgibbs uint8_t reserved_2; 949114623Sgibbs uint8_t checksum; 950114623Sgibbs uint8_t reserved_3[4]; 951114623Sgibbs}; 952114623Sgibbs 95397883Sgibbs/****************************** Flexport Logic ********************************/ 95497883Sgibbs#define FLXADDR_TERMCTL 0x0 95597883Sgibbs#define FLX_TERMCTL_ENSECHIGH 0x8 95697883Sgibbs#define FLX_TERMCTL_ENSECLOW 0x4 95797883Sgibbs#define FLX_TERMCTL_ENPRIHIGH 0x2 95897883Sgibbs#define FLX_TERMCTL_ENPRILOW 0x1 95997883Sgibbs#define FLXADDR_ROMSTAT_CURSENSECTL 0x1 96097883Sgibbs#define FLX_ROMSTAT_SEECFG 0xF0 96197883Sgibbs#define FLX_ROMSTAT_EECFG 0x0F 96297883Sgibbs#define FLX_ROMSTAT_SEE_93C66 0x00 96397883Sgibbs#define FLX_ROMSTAT_SEE_NONE 0xF0 96497883Sgibbs#define FLX_ROMSTAT_EE_512x8 0x0 96597883Sgibbs#define FLX_ROMSTAT_EE_1MBx8 0x1 96697883Sgibbs#define FLX_ROMSTAT_EE_2MBx8 0x2 96797883Sgibbs#define FLX_ROMSTAT_EE_4MBx8 0x3 96897883Sgibbs#define FLX_ROMSTAT_EE_16MBx8 0x4 96997883Sgibbs#define CURSENSE_ENB 0x1 97097883Sgibbs#define FLXADDR_FLEXSTAT 0x2 97197883Sgibbs#define FLX_FSTAT_BUSY 0x1 97297883Sgibbs#define FLXADDR_CURRENT_STAT 0x4 97397883Sgibbs#define FLX_CSTAT_SEC_HIGH 0xC0 97497883Sgibbs#define FLX_CSTAT_SEC_LOW 0x30 97597883Sgibbs#define FLX_CSTAT_PRI_HIGH 0x0C 97697883Sgibbs#define FLX_CSTAT_PRI_LOW 0x03 97797883Sgibbs#define FLX_CSTAT_MASK 0x03 97897883Sgibbs#define FLX_CSTAT_SHIFT 2 97997883Sgibbs#define FLX_CSTAT_OKAY 0x0 98097883Sgibbs#define FLX_CSTAT_OVER 0x1 98197883Sgibbs#define FLX_CSTAT_UNDER 0x2 98297883Sgibbs#define FLX_CSTAT_INVALID 0x3 98397883Sgibbs 98497883Sgibbsint ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 985114623Sgibbs u_int start_addr, u_int count, int bstream); 98697883Sgibbs 98797883Sgibbsint ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 98897883Sgibbs u_int start_addr, u_int count); 98997883Sgibbsint ahd_wait_seeprom(struct ahd_softc *ahd); 990114623Sgibbsint ahd_verify_vpd_cksum(struct vpd_config *vpd); 99197883Sgibbsint ahd_verify_cksum(struct seeprom_config *sc); 99297883Sgibbsint ahd_acquire_seeprom(struct ahd_softc *ahd); 99397883Sgibbsvoid ahd_release_seeprom(struct ahd_softc *ahd); 99497883Sgibbs 99597883Sgibbs/**************************** Message Buffer *********************************/ 99697883Sgibbstypedef enum { 99797883Sgibbs MSG_FLAG_NONE = 0x00, 99897883Sgibbs MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 99997883Sgibbs MSG_FLAG_IU_REQ_CHANGED = 0x02, 100097883Sgibbs MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 1001107441Sscottl MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 1002107441Sscottl MSG_FLAG_PACKETIZED = 0x10 100397883Sgibbs} ahd_msg_flags; 100497883Sgibbs 100597883Sgibbstypedef enum { 100697883Sgibbs MSG_TYPE_NONE = 0x00, 100797883Sgibbs MSG_TYPE_INITIATOR_MSGOUT = 0x01, 100897883Sgibbs MSG_TYPE_INITIATOR_MSGIN = 0x02, 100997883Sgibbs MSG_TYPE_TARGET_MSGOUT = 0x03, 101097883Sgibbs MSG_TYPE_TARGET_MSGIN = 0x04 101197883Sgibbs} ahd_msg_type; 101297883Sgibbs 101397883Sgibbstypedef enum { 101497883Sgibbs MSGLOOP_IN_PROG, 101597883Sgibbs MSGLOOP_MSGCOMPLETE, 101697883Sgibbs MSGLOOP_TERMINATED 101797883Sgibbs} msg_loop_stat; 101897883Sgibbs 101997883Sgibbs/*********************** Software Configuration Structure *********************/ 102097883Sgibbsstruct ahd_suspend_channel_state { 102197883Sgibbs uint8_t scsiseq; 102297883Sgibbs uint8_t sxfrctl0; 102397883Sgibbs uint8_t sxfrctl1; 102497883Sgibbs uint8_t simode0; 102597883Sgibbs uint8_t simode1; 102697883Sgibbs uint8_t seltimer; 102797883Sgibbs uint8_t seqctl; 102897883Sgibbs}; 102997883Sgibbs 103097883Sgibbsstruct ahd_suspend_state { 103197883Sgibbs struct ahd_suspend_channel_state channel[2]; 103297883Sgibbs uint8_t optionmode; 103397883Sgibbs uint8_t dscommand0; 103497883Sgibbs uint8_t dspcistatus; 103597883Sgibbs /* hsmailbox */ 103697883Sgibbs uint8_t crccontrol1; 103797883Sgibbs uint8_t scbbaddr; 103897883Sgibbs /* Host and sequencer SCB counts */ 103997883Sgibbs uint8_t dff_thrsh; 104097883Sgibbs uint8_t *scratch_ram; 104197883Sgibbs uint8_t *btt; 104297883Sgibbs}; 104397883Sgibbs 104497883Sgibbstypedef void (*ahd_bus_intr_t)(struct ahd_softc *); 104597883Sgibbs 104697883Sgibbstypedef enum { 104797883Sgibbs AHD_MODE_DFF0, 104897883Sgibbs AHD_MODE_DFF1, 104997883Sgibbs AHD_MODE_CCHAN, 105097883Sgibbs AHD_MODE_SCSI, 105197883Sgibbs AHD_MODE_CFG, 105297883Sgibbs AHD_MODE_UNKNOWN 105397883Sgibbs} ahd_mode; 105497883Sgibbs 105597883Sgibbs#define AHD_MK_MSK(x) (0x01 << (x)) 105697883Sgibbs#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 105797883Sgibbs#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 105897883Sgibbs#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 105997883Sgibbs#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 106097883Sgibbs#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 106197883Sgibbs#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 106297883Sgibbs#define AHD_MODE_ANY_MSK (~0) 106397883Sgibbs 1064199260Sattiliotypedef enum { 1065199260Sattilio AHD_SYSCTL_ROOT, 1066199260Sattilio AHD_SYSCTL_SUMMARY, 1067199260Sattilio AHD_SYSCTL_DEBUG, 1068199260Sattilio AHD_SYSCTL_NUMBER 1069199260Sattilio} ahd_sysctl_types_t; 1070199260Sattilio 1071199260Sattiliotypedef enum { 1072199260Sattilio AHD_ERRORS_CORRECTABLE, 1073199260Sattilio AHD_ERRORS_UNCORRECTABLE, 1074199260Sattilio AHD_ERRORS_FATAL, 1075199260Sattilio AHD_ERRORS_NUMBER 1076199260Sattilio} ahd_sysctl_errors_t; 1077199260Sattilio 1078199260Sattilio#define AHD_CORRECTABLE_ERROR(sc) \ 1079199260Sattilio (((sc)->summerr[AHD_ERRORS_CORRECTABLE])++) 1080199260Sattilio#define AHD_UNCORRECTABLE_ERROR(sc) \ 1081199260Sattilio (((sc)->summerr[AHD_ERRORS_UNCORRECTABLE])++) 1082199260Sattilio#define AHD_FATAL_ERROR(sc) \ 1083199260Sattilio (((sc)->summerr[AHD_ERRORS_FATAL])++) 1084199260Sattilio 108597883Sgibbstypedef uint8_t ahd_mode_state; 108697883Sgibbs 108797883Sgibbstypedef void ahd_callback_t (void *); 108897883Sgibbs 1089125448Sgibbsstruct ahd_completion 1090125448Sgibbs{ 1091125448Sgibbs uint16_t tag; 1092125448Sgibbs uint8_t sg_status; 1093125448Sgibbs uint8_t valid_tag; 1094125448Sgibbs}; 1095125448Sgibbs 1096133911Sgibbs#define AIC_SCB_DATA(softc) (&(softc)->scb_data) 1097133911Sgibbs 109897883Sgibbsstruct ahd_softc { 109997883Sgibbs bus_space_tag_t tags[2]; 110097883Sgibbs bus_space_handle_t bshs[2]; 110197883Sgibbs#ifndef __linux__ 110297883Sgibbs bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 110397883Sgibbs#endif 110497883Sgibbs struct scb_data scb_data; 110597883Sgibbs 1106102680Sgibbs struct hardware_scb *next_queued_hscb; 1107123579Sgibbs struct map_node *next_queued_hscb_map; 110897883Sgibbs 110997883Sgibbs /* 111097883Sgibbs * SCBs that have been sent to the controller 111197883Sgibbs */ 111297883Sgibbs LIST_HEAD(, scb) pending_scbs; 111397883Sgibbs 111497883Sgibbs /* 1115123579Sgibbs * SCBs whose timeout routine has been called. 1116123579Sgibbs */ 1117123579Sgibbs LIST_HEAD(, scb) timedout_scbs; 1118123579Sgibbs 1119123579Sgibbs /* 112097883Sgibbs * Current register window mode information. 112197883Sgibbs */ 112297883Sgibbs ahd_mode dst_mode; 112397883Sgibbs ahd_mode src_mode; 112497883Sgibbs 112597883Sgibbs /* 112697883Sgibbs * Saved register window mode information 112797883Sgibbs * used for restore on next unpause. 112897883Sgibbs */ 112997883Sgibbs ahd_mode saved_dst_mode; 113097883Sgibbs ahd_mode saved_src_mode; 113197883Sgibbs 113297883Sgibbs /* 113397883Sgibbs * Platform specific data. 113497883Sgibbs */ 113597883Sgibbs struct ahd_platform_data *platform_data; 113697883Sgibbs 113797883Sgibbs /* 113897883Sgibbs * Platform specific device information. 113997883Sgibbs */ 1140123579Sgibbs aic_dev_softc_t dev_softc; 114197883Sgibbs 114297883Sgibbs /* 114397883Sgibbs * Bus specific device information. 114497883Sgibbs */ 114597883Sgibbs ahd_bus_intr_t bus_intr; 114697883Sgibbs 114797883Sgibbs /* 114897883Sgibbs * Target mode related state kept on a per enabled lun basis. 114997883Sgibbs * Targets that are not enabled will have null entries. 115097883Sgibbs * As an initiator, we keep one target entry for our initiator 115197883Sgibbs * ID to store our sync/wide transfer settings. 115297883Sgibbs */ 115397883Sgibbs struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 115497883Sgibbs 115597883Sgibbs /* 115697883Sgibbs * The black hole device responsible for handling requests for 115797883Sgibbs * disabled luns on enabled targets. 115897883Sgibbs */ 115997883Sgibbs struct ahd_tmode_lstate *black_hole; 116097883Sgibbs 116197883Sgibbs /* 116297883Sgibbs * Device instance currently on the bus awaiting a continue TIO 116397883Sgibbs * for a command that was not given the disconnect priveledge. 116497883Sgibbs */ 116597883Sgibbs struct ahd_tmode_lstate *pending_device; 116697883Sgibbs 116797883Sgibbs /* 116897883Sgibbs * Timer handles for timer driven callbacks. 116997883Sgibbs */ 1170123579Sgibbs aic_timer_t reset_timer; 1171123579Sgibbs aic_timer_t stat_timer; 117297883Sgibbs 117397883Sgibbs /* 1174109588Sgibbs * Statistics. 1175109588Sgibbs */ 1176137870Sgibbs#define AHD_STAT_UPDATE_MS 250 1177109588Sgibbs#define AHD_STAT_BUCKETS 4 1178109588Sgibbs u_int cmdcmplt_bucket; 1179109588Sgibbs uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1180109588Sgibbs uint32_t cmdcmplt_total; 1181109588Sgibbs 1182109588Sgibbs /* 1183199260Sattilio * Errors statistics and printouts. 1184199260Sattilio */ 1185199260Sattilio struct sysctl_ctx_list sysctl_ctx[AHD_SYSCTL_NUMBER]; 1186199260Sattilio struct sysctl_oid *sysctl_tree[AHD_SYSCTL_NUMBER]; 1187199260Sattilio u_int summerr[AHD_ERRORS_NUMBER]; 1188199260Sattilio 1189199260Sattilio /* 119097883Sgibbs * Card characteristics 119197883Sgibbs */ 119297883Sgibbs ahd_chip chip; 119397883Sgibbs ahd_feature features; 119497883Sgibbs ahd_bug bugs; 119597883Sgibbs ahd_flag flags; 119697883Sgibbs struct seeprom_config *seep_config; 119797883Sgibbs 119897883Sgibbs /* Command Queues */ 1199125448Sgibbs struct ahd_completion *qoutfifo; 120097883Sgibbs uint16_t qoutfifonext; 1201102680Sgibbs uint16_t qoutfifonext_valid_tag; 120297883Sgibbs uint16_t qinfifonext; 120397883Sgibbs uint16_t qinfifo[AHD_SCB_MAX]; 120497883Sgibbs 1205125448Sgibbs /* 1206125448Sgibbs * Our qfreeze count. The sequencer compares 1207125448Sgibbs * this value with its own counter to determine 1208125448Sgibbs * whether to allow selections to occur. 1209125448Sgibbs */ 1210125448Sgibbs uint16_t qfreeze_cnt; 1211125448Sgibbs 1212125448Sgibbs /* Values to store in the SEQCTL register for pause and unpause */ 1213125448Sgibbs uint8_t unpause; 1214125448Sgibbs uint8_t pause; 1215125448Sgibbs 121697883Sgibbs /* Critical Section Data */ 121797883Sgibbs struct cs *critical_sections; 121897883Sgibbs u_int num_critical_sections; 121997883Sgibbs 122097883Sgibbs /* Buffer for handling packetized bitbucket. */ 122197883Sgibbs uint8_t *overrun_buf; 122297883Sgibbs 122397883Sgibbs /* Links for chaining softcs */ 122497883Sgibbs TAILQ_ENTRY(ahd_softc) links; 122597883Sgibbs 122697883Sgibbs /* Channel Names ('A', 'B', etc.) */ 122797883Sgibbs char channel; 122897883Sgibbs 122997883Sgibbs /* Initiator Bus ID */ 123097883Sgibbs uint8_t our_id; 123197883Sgibbs 123297883Sgibbs /* 123397883Sgibbs * Target incoming command FIFO. 123497883Sgibbs */ 123597883Sgibbs struct target_cmd *targetcmds; 123697883Sgibbs uint8_t tqinfifonext; 123797883Sgibbs 123897883Sgibbs /* 1239109588Sgibbs * Cached verson of the hs_mailbox so we can avoid 1240109588Sgibbs * pausing the sequencer during mailbox updates. 1241109588Sgibbs */ 1242109588Sgibbs uint8_t hs_mailbox; 1243109588Sgibbs 1244109588Sgibbs /* 124597883Sgibbs * Incoming and outgoing message handling. 124697883Sgibbs */ 124797883Sgibbs uint8_t send_msg_perror; 124897883Sgibbs ahd_msg_flags msg_flags; 124997883Sgibbs ahd_msg_type msg_type; 125097883Sgibbs uint8_t msgout_buf[12];/* Message we are sending */ 125197883Sgibbs uint8_t msgin_buf[12];/* Message we are receiving */ 125297883Sgibbs u_int msgout_len; /* Length of message to send */ 125397883Sgibbs u_int msgout_index; /* Current index in msgout */ 125497883Sgibbs u_int msgin_index; /* Current index in msgin */ 125597883Sgibbs 125697883Sgibbs /* 125797883Sgibbs * Mapping information for data structures shared 125897883Sgibbs * between the sequencer and kernel. 125997883Sgibbs */ 126097883Sgibbs bus_dma_tag_t parent_dmat; 126197883Sgibbs bus_dma_tag_t shared_data_dmat; 1262123579Sgibbs struct map_node shared_data_map; 126397883Sgibbs 126497883Sgibbs /* Information saved through suspend/resume cycles */ 126597883Sgibbs struct ahd_suspend_state suspend_state; 126697883Sgibbs 126797883Sgibbs /* Number of enabled target mode device on this card */ 126897883Sgibbs u_int enabled_luns; 126997883Sgibbs 127097883Sgibbs /* Initialization level of this data structure */ 127197883Sgibbs u_int init_level; 127297883Sgibbs 127397883Sgibbs /* PCI cacheline size. */ 127497883Sgibbs u_int pci_cachesize; 127597883Sgibbs 1276166109Sjhb /* PCI-X capability offset. */ 1277166109Sjhb int pcix_ptr; 1278166109Sjhb 1279107441Sscottl /* IO Cell Parameters */ 1280107441Sscottl uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1281107441Sscottl 1282107441Sscottl u_int stack_size; 1283107441Sscottl uint16_t *saved_stack; 1284107441Sscottl 128597883Sgibbs /* Per-Unit descriptive information */ 128697883Sgibbs const char *description; 128797883Sgibbs const char *bus_description; 128897883Sgibbs char *name; 128997883Sgibbs int unit; 129097883Sgibbs 129197883Sgibbs /* Selection Timer settings */ 129297883Sgibbs int seltime; 129397883Sgibbs 1294109588Sgibbs /* 1295115329Sgibbs * Interrupt coalescing settings. 1296109588Sgibbs */ 1297115329Sgibbs#define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/ 1298115329Sgibbs#define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10 1299115329Sgibbs#define AHD_INT_COALESCING_MAXCMDS_MAX 127 1300115329Sgibbs#define AHD_INT_COALESCING_MINCMDS_DEFAULT 5 1301115329Sgibbs#define AHD_INT_COALESCING_MINCMDS_MAX 127 1302115329Sgibbs#define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000 1303115329Sgibbs#define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000 1304115329Sgibbs u_int int_coalescing_timer; 1305115329Sgibbs u_int int_coalescing_maxcmds; 1306115329Sgibbs u_int int_coalescing_mincmds; 1307115329Sgibbs u_int int_coalescing_threshold; 1308115329Sgibbs u_int int_coalescing_stop_threshold; 1309109588Sgibbs 131097883Sgibbs uint16_t user_discenable;/* Disconnection allowed */ 131197883Sgibbs uint16_t user_tagenable;/* Tagged Queuing allowed */ 131297883Sgibbs}; 131397883Sgibbs 131497883SgibbsTAILQ_HEAD(ahd_softc_tailq, ahd_softc); 131597883Sgibbsextern struct ahd_softc_tailq ahd_tailq; 131697883Sgibbs 1317107441Sscottl/*************************** IO Cell Configuration ****************************/ 1318107441Sscottl#define AHD_PRECOMP_SLEW_INDEX \ 1319107441Sscottl (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1320107441Sscottl 1321107441Sscottl#define AHD_AMPLITUDE_INDEX \ 1322107441Sscottl (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1323107441Sscottl 1324107441Sscottl#define AHD_SET_SLEWRATE(ahd, new_slew) \ 1325107441Sscottldo { \ 1326107441Sscottl (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1327107441Sscottl (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1328107441Sscottl (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1329107441Sscottl} while (0) 1330107441Sscottl 1331107441Sscottl#define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1332107441Sscottldo { \ 1333107441Sscottl (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1334107441Sscottl (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1335107441Sscottl (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1336107441Sscottl} while (0) 1337107441Sscottl 1338107441Sscottl#define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1339107441Sscottldo { \ 1340107441Sscottl (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1341107441Sscottl (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1342107441Sscottl (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1343107441Sscottl} while (0) 1344107441Sscottl 134597883Sgibbs/************************ Active Device Information ***************************/ 134697883Sgibbstypedef enum { 134797883Sgibbs ROLE_UNKNOWN, 134897883Sgibbs ROLE_INITIATOR, 134997883Sgibbs ROLE_TARGET 135097883Sgibbs} role_t; 135197883Sgibbs 135297883Sgibbsstruct ahd_devinfo { 135397883Sgibbs int our_scsiid; 135497883Sgibbs int target_offset; 135597883Sgibbs uint16_t target_mask; 135697883Sgibbs u_int target; 135797883Sgibbs u_int lun; 135897883Sgibbs char channel; 135997883Sgibbs role_t role; /* 136097883Sgibbs * Only guaranteed to be correct if not 136197883Sgibbs * in the busfree state. 136297883Sgibbs */ 136397883Sgibbs}; 136497883Sgibbs 136597883Sgibbs/****************************** PCI Structures ********************************/ 1366119690Sjhb#define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/ 1367119690Sjhb#define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */ 1368119690Sjhb#define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */ 136997883Sgibbs 137097883Sgibbstypedef int (ahd_device_setup_t)(struct ahd_softc *); 137197883Sgibbs 137297883Sgibbsstruct ahd_pci_identity { 137397883Sgibbs uint64_t full_id; 137497883Sgibbs uint64_t id_mask; 137597883Sgibbs char *name; 137697883Sgibbs ahd_device_setup_t *setup; 137797883Sgibbs}; 137897883Sgibbsextern struct ahd_pci_identity ahd_pci_ident_table []; 137997883Sgibbsextern const u_int ahd_num_pci_devs; 138097883Sgibbs 138197883Sgibbs/*************************** Function Declarations ****************************/ 138297883Sgibbs/******************************************************************************/ 1383109588Sgibbsvoid ahd_reset_cmds_pending(struct ahd_softc *ahd); 138497883Sgibbsu_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 138597883Sgibbsvoid ahd_busy_tcl(struct ahd_softc *ahd, 138697883Sgibbs u_int tcl, u_int busyid); 138797883Sgibbsstatic __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 138897883Sgibbsstatic __inline void 138997883Sgibbsahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 139097883Sgibbs{ 139197883Sgibbs ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 139297883Sgibbs} 139397883Sgibbs 139497883Sgibbs/***************************** PCI Front End *********************************/ 1395123579Sgibbsstruct ahd_pci_identity *ahd_find_pci_device(aic_dev_softc_t); 1396107441Sscottlint ahd_pci_config(struct ahd_softc *, 1397107441Sscottl struct ahd_pci_identity *); 1398107441Sscottlint ahd_pci_test_register_access(struct ahd_softc *); 139997883Sgibbs 140097883Sgibbs/************************** SCB and SCB queue management **********************/ 140197883Sgibbsint ahd_probe_scbs(struct ahd_softc *); 140297883Sgibbsvoid ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 140397883Sgibbs struct scb *scb); 140497883Sgibbsint ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 140597883Sgibbs int target, char channel, int lun, 140697883Sgibbs u_int tag, role_t role); 140797883Sgibbs 140897883Sgibbs/****************************** Initialization ********************************/ 140997883Sgibbsstruct ahd_softc *ahd_alloc(void *platform_arg, char *name); 141097883Sgibbsint ahd_softc_init(struct ahd_softc *); 141197883Sgibbsvoid ahd_controller_info(struct ahd_softc *ahd, char *buf); 141297883Sgibbsint ahd_init(struct ahd_softc *ahd); 141397883Sgibbsint ahd_default_config(struct ahd_softc *ahd); 1414114623Sgibbsint ahd_parse_vpddata(struct ahd_softc *ahd, 1415114623Sgibbs struct vpd_config *vpd); 141697883Sgibbsint ahd_parse_cfgdata(struct ahd_softc *ahd, 141797883Sgibbs struct seeprom_config *sc); 141897883Sgibbsvoid ahd_intr_enable(struct ahd_softc *ahd, int enable); 1419115329Sgibbsvoid ahd_update_coalescing_values(struct ahd_softc *ahd, 1420109588Sgibbs u_int timer, 1421109588Sgibbs u_int maxcmds, 1422109588Sgibbs u_int mincmds); 1423115329Sgibbsvoid ahd_enable_coalescing(struct ahd_softc *ahd, 1424109588Sgibbs int enable); 142597883Sgibbsvoid ahd_pause_and_flushwork(struct ahd_softc *ahd); 142697883Sgibbsint ahd_suspend(struct ahd_softc *ahd); 142797883Sgibbsint ahd_resume(struct ahd_softc *ahd); 142897883Sgibbsvoid ahd_softc_insert(struct ahd_softc *); 142997883Sgibbsvoid ahd_set_unit(struct ahd_softc *, int); 143097883Sgibbsvoid ahd_set_name(struct ahd_softc *, char *); 1431102680Sgibbsstruct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1432102680Sgibbsvoid ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1433168873Sscottlint ahd_alloc_scbs(struct ahd_softc *ahd); 143497883Sgibbsvoid ahd_free(struct ahd_softc *ahd); 1435115917Sgibbsint ahd_reset(struct ahd_softc *ahd, int reinit); 143697883Sgibbsvoid ahd_shutdown(void *arg); 1437115917Sgibbsint ahd_write_flexport(struct ahd_softc *ahd, 1438115917Sgibbs u_int addr, u_int value); 1439115917Sgibbsint ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1440115917Sgibbs uint8_t *value); 1441115917Sgibbsint ahd_wait_flexport(struct ahd_softc *ahd); 144297883Sgibbs 144397883Sgibbs/*************************** Interrupt Services *******************************/ 144497883Sgibbsvoid ahd_pci_intr(struct ahd_softc *ahd); 144597883Sgibbsvoid ahd_clear_intstat(struct ahd_softc *ahd); 1446109588Sgibbsvoid ahd_flush_qoutfifo(struct ahd_softc *ahd); 144797883Sgibbsvoid ahd_run_qoutfifo(struct ahd_softc *ahd); 144897883Sgibbs#ifdef AHD_TARGET_MODE 144997883Sgibbsvoid ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 145097883Sgibbs#endif 145197883Sgibbsvoid ahd_handle_hwerrint(struct ahd_softc *ahd); 145297883Sgibbsvoid ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 145397883Sgibbsvoid ahd_handle_scsiint(struct ahd_softc *ahd, 145497883Sgibbs u_int intstat); 145597883Sgibbsvoid ahd_clear_critical_section(struct ahd_softc *ahd); 145697883Sgibbs 145797883Sgibbs/***************************** Error Recovery *********************************/ 145897883Sgibbstypedef enum { 145997883Sgibbs SEARCH_COMPLETE, 146097883Sgibbs SEARCH_COUNT, 146197883Sgibbs SEARCH_REMOVE, 146297883Sgibbs SEARCH_PRINT 146397883Sgibbs} ahd_search_action; 1464133122Sgibbsvoid ahd_done_with_status(struct ahd_softc *ahd, 1465133122Sgibbs struct scb *scb, uint32_t status); 146697883Sgibbsint ahd_search_qinfifo(struct ahd_softc *ahd, int target, 146797883Sgibbs char channel, int lun, u_int tag, 146897883Sgibbs role_t role, uint32_t status, 146997883Sgibbs ahd_search_action action); 147097883Sgibbsint ahd_search_disc_list(struct ahd_softc *ahd, int target, 147197883Sgibbs char channel, int lun, u_int tag, 147297883Sgibbs int stop_on_first, int remove, 147397883Sgibbs int save_state); 147497883Sgibbsvoid ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 147597883Sgibbsint ahd_reset_channel(struct ahd_softc *ahd, char channel, 147697883Sgibbs int initiate_reset); 147797883Sgibbsint ahd_abort_scbs(struct ahd_softc *ahd, int target, 147897883Sgibbs char channel, int lun, u_int tag, 147997883Sgibbs role_t role, uint32_t status); 148097883Sgibbsvoid ahd_restart(struct ahd_softc *ahd); 148197883Sgibbsvoid ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 148297883Sgibbsvoid ahd_handle_scb_status(struct ahd_softc *ahd, 148397883Sgibbs struct scb *scb); 148497883Sgibbsvoid ahd_handle_scsi_status(struct ahd_softc *ahd, 148597883Sgibbs struct scb *scb); 148697883Sgibbsvoid ahd_calc_residual(struct ahd_softc *ahd, 148797883Sgibbs struct scb *scb); 1488123579Sgibbsvoid ahd_timeout(struct scb *scb); 1489123579Sgibbsvoid ahd_recover_commands(struct ahd_softc *ahd); 149097883Sgibbs/*************************** Utility Functions ********************************/ 149197883Sgibbsstruct ahd_phase_table_entry* 149297883Sgibbs ahd_lookup_phase_entry(int phase); 149397883Sgibbsvoid ahd_compile_devinfo(struct ahd_devinfo *devinfo, 149497883Sgibbs u_int our_id, u_int target, 149597883Sgibbs u_int lun, char channel, 149697883Sgibbs role_t role); 149797883Sgibbs/************************** Transfer Negotiation ******************************/ 149897883Sgibbsvoid ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 149997883Sgibbs u_int *ppr_options, u_int maxsync); 150097883Sgibbsvoid ahd_validate_offset(struct ahd_softc *ahd, 150197883Sgibbs struct ahd_initiator_tinfo *tinfo, 150297883Sgibbs u_int period, u_int *offset, 150397883Sgibbs int wide, role_t role); 150497883Sgibbsvoid ahd_validate_width(struct ahd_softc *ahd, 150597883Sgibbs struct ahd_initiator_tinfo *tinfo, 150697883Sgibbs u_int *bus_width, 150797883Sgibbs role_t role); 1508107441Sscottl/* 1509107441Sscottl * Negotiation types. These are used to qualify if we should renegotiate 1510107441Sscottl * even if our goal and current transport parameters are identical. 1511107441Sscottl */ 1512107441Sscottltypedef enum { 1513107441Sscottl AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1514107441Sscottl AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1515107441Sscottl AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1516107441Sscottl} ahd_neg_type; 151797883Sgibbsint ahd_update_neg_request(struct ahd_softc*, 151897883Sgibbs struct ahd_devinfo*, 151997883Sgibbs struct ahd_tmode_tstate*, 152097883Sgibbs struct ahd_initiator_tinfo*, 1521107441Sscottl ahd_neg_type); 152297883Sgibbsvoid ahd_set_width(struct ahd_softc *ahd, 152397883Sgibbs struct ahd_devinfo *devinfo, 152497883Sgibbs u_int width, u_int type, int paused); 152597883Sgibbsvoid ahd_set_syncrate(struct ahd_softc *ahd, 152697883Sgibbs struct ahd_devinfo *devinfo, 152797883Sgibbs u_int period, u_int offset, 152897883Sgibbs u_int ppr_options, 152997883Sgibbs u_int type, int paused); 153097883Sgibbstypedef enum { 153197883Sgibbs AHD_QUEUE_NONE, 153297883Sgibbs AHD_QUEUE_BASIC, 153397883Sgibbs AHD_QUEUE_TAGGED 153497883Sgibbs} ahd_queue_alg; 153597883Sgibbs 153697883Sgibbsvoid ahd_set_tags(struct ahd_softc *ahd, 153797883Sgibbs struct ahd_devinfo *devinfo, 153897883Sgibbs ahd_queue_alg alg); 153997883Sgibbs 154097883Sgibbs/**************************** Target Mode *************************************/ 154197883Sgibbs#ifdef AHD_TARGET_MODE 154297883Sgibbsvoid ahd_send_lstate_events(struct ahd_softc *, 154397883Sgibbs struct ahd_tmode_lstate *); 154497883Sgibbsvoid ahd_handle_en_lun(struct ahd_softc *ahd, 154597883Sgibbs struct cam_sim *sim, union ccb *ccb); 154697883Sgibbscam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 154797883Sgibbs struct cam_sim *sim, union ccb *ccb, 154897883Sgibbs struct ahd_tmode_tstate **tstate, 154997883Sgibbs struct ahd_tmode_lstate **lstate, 155097883Sgibbs int notfound_failure); 155197883Sgibbs#ifndef AHD_TMODE_ENABLE 155297883Sgibbs#define AHD_TMODE_ENABLE 0 155397883Sgibbs#endif 155497883Sgibbs#endif 155597883Sgibbs/******************************* Debug ***************************************/ 155697883Sgibbs#ifdef AHD_DEBUG 155797883Sgibbsextern uint32_t ahd_debug; 1558107441Sscottl#define AHD_SHOW_MISC 0x00001 1559107441Sscottl#define AHD_SHOW_SENSE 0x00002 1560107441Sscottl#define AHD_SHOW_RECOVERY 0x00004 1561107441Sscottl#define AHD_DUMP_SEEPROM 0x00008 1562107441Sscottl#define AHD_SHOW_TERMCTL 0x00010 1563107441Sscottl#define AHD_SHOW_MEMORY 0x00020 1564107441Sscottl#define AHD_SHOW_MESSAGES 0x00040 1565107441Sscottl#define AHD_SHOW_MODEPTR 0x00080 1566107441Sscottl#define AHD_SHOW_SELTO 0x00100 1567107441Sscottl#define AHD_SHOW_FIFOS 0x00200 1568107441Sscottl#define AHD_SHOW_QFULL 0x00400 1569107441Sscottl#define AHD_SHOW_DV 0x00800 1570107441Sscottl#define AHD_SHOW_MASKED_ERRORS 0x01000 1571107441Sscottl#define AHD_SHOW_QUEUE 0x02000 1572107441Sscottl#define AHD_SHOW_TQIN 0x04000 1573107441Sscottl#define AHD_SHOW_SG 0x08000 1574115329Sgibbs#define AHD_SHOW_INT_COALESCING 0x10000 1575109588Sgibbs#define AHD_DEBUG_SEQUENCER 0x20000 157697883Sgibbs#endif 157797883Sgibbsvoid ahd_print_scb(struct scb *scb); 1578107441Sscottlvoid ahd_print_devinfo(struct ahd_softc *ahd, 1579107441Sscottl struct ahd_devinfo *devinfo); 158097883Sgibbsvoid ahd_dump_sglist(struct scb *scb); 158197883Sgibbsvoid ahd_dump_all_cards_state(void); 158297883Sgibbsvoid ahd_dump_card_state(struct ahd_softc *ahd); 1583102680Sgibbsint ahd_print_register(ahd_reg_parse_entry_t *table, 1584102680Sgibbs u_int num_entries, 1585102680Sgibbs const char *name, 1586102680Sgibbs u_int address, 1587102680Sgibbs u_int value, 1588102680Sgibbs u_int *cur_column, 1589102680Sgibbs u_int wrap_point); 159097883Sgibbsvoid ahd_dump_scbs(struct ahd_softc *ahd); 159197883Sgibbs#endif /* _AIC79XX_H_ */ 1592