ahd_pci.c revision 119690
1/* 2 * FreeBSD, PCI product support functions 3 * 4 * Copyright (c) 1995-2001 Justin T. Gibbs 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: ahd_pci.c,v 1.8 2003/05/03 23:27:57 gibbs Exp $ 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/aic7xxx/ahd_pci.c 119690 2003-09-02 17:30:40Z jhb $"); 36 37#include <dev/aic7xxx/aic79xx_osm.h> 38 39#define AHD_PCI_IOADDR0 PCIR_BAR(0) /* Primary I/O BAR */ 40#define AHD_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */ 41#define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Secondary I/O BAR */ 42 43static int ahd_pci_probe(device_t dev); 44static int ahd_pci_attach(device_t dev); 45 46static device_method_t ahd_pci_device_methods[] = { 47 /* Device interface */ 48 DEVMETHOD(device_probe, ahd_pci_probe), 49 DEVMETHOD(device_attach, ahd_pci_attach), 50 DEVMETHOD(device_detach, ahd_detach), 51 { 0, 0 } 52}; 53 54static driver_t ahd_pci_driver = { 55 "ahd", 56 ahd_pci_device_methods, 57 sizeof(struct ahd_softc) 58}; 59 60static devclass_t ahd_devclass; 61 62DRIVER_MODULE(ahd, pci, ahd_pci_driver, ahd_devclass, 0, 0); 63DRIVER_MODULE(ahd, cardbus, ahd_pci_driver, ahd_devclass, 0, 0); 64MODULE_DEPEND(ahd_pci, ahd, 1, 1, 1); 65MODULE_VERSION(ahd_pci, 1); 66 67static int 68ahd_pci_probe(device_t dev) 69{ 70 struct ahd_pci_identity *entry; 71 72 entry = ahd_find_pci_device(dev); 73 if (entry != NULL) { 74 device_set_desc(dev, entry->name); 75 return (0); 76 } 77 return (ENXIO); 78} 79 80static int 81ahd_pci_attach(device_t dev) 82{ 83 struct ahd_pci_identity *entry; 84 struct ahd_softc *ahd; 85 char *name; 86 int error; 87 88 entry = ahd_find_pci_device(dev); 89 if (entry == NULL) 90 return (ENXIO); 91 92 /* 93 * Allocate a softc for this card and 94 * set it up for attachment by our 95 * common detect routine. 96 */ 97 name = malloc(strlen(device_get_nameunit(dev)) + 1, M_DEVBUF, M_NOWAIT); 98 if (name == NULL) 99 return (ENOMEM); 100 strcpy(name, device_get_nameunit(dev)); 101 ahd = ahd_alloc(dev, name); 102 if (ahd == NULL) 103 return (ENOMEM); 104 105 ahd_set_unit(ahd, device_get_unit(dev)); 106 107 /* 108 * Should we bother disabling 39Bit addressing 109 * based on installed memory? 110 */ 111 if (sizeof(bus_addr_t) > 4) 112 ahd->flags |= AHD_39BIT_ADDRESSING; 113 114 /* Allocate a dmatag for our SCB DMA maps */ 115 /* XXX Should be a child of the PCI bus dma tag */ 116 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 117 /*boundary*/0, 118 (ahd->flags & AHD_39BIT_ADDRESSING) 119 ? 0x7FFFFFFFFF 120 : BUS_SPACE_MAXADDR_32BIT, 121 /*highaddr*/BUS_SPACE_MAXADDR, 122 /*filter*/NULL, /*filterarg*/NULL, 123 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 124 /*nsegments*/AHD_NSEG, 125 /*maxsegsz*/AHD_MAXTRANSFER_SIZE, 126 /*flags*/0, 127 /*lockfunc*/busdma_lock_mutex, 128 /*lockarg*/&Giant, 129 &ahd->parent_dmat); 130 131 if (error != 0) { 132 printf("ahd_pci_attach: Could not allocate DMA tag " 133 "- error %d\n", error); 134 ahd_free(ahd); 135 return (ENOMEM); 136 } 137 ahd->dev_softc = dev; 138 error = ahd_pci_config(ahd, entry); 139 if (error != 0) { 140 ahd_free(ahd); 141 return (error); 142 } 143 144 ahd_attach(ahd); 145 return (0); 146} 147 148int 149ahd_pci_map_registers(struct ahd_softc *ahd) 150{ 151 struct resource *regs; 152 struct resource *regs2; 153 u_int command; 154 int regs_type; 155 int regs_id; 156 int regs_id2; 157 int allow_memio; 158 159 command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1); 160 regs = NULL; 161 regs2 = NULL; 162 regs_type = 0; 163 regs_id = 0; 164 165 /* Retrieve the per-device 'allow_memio' hint */ 166 if (resource_int_value(device_get_name(ahd->dev_softc), 167 device_get_unit(ahd->dev_softc), 168 "allow_memio", &allow_memio) != 0) { 169 if (bootverbose) 170 device_printf(ahd->dev_softc, 171 "Defaulting to MEMIO on\n"); 172 } 173 174 if ((command & PCIM_CMD_MEMEN) != 0 175 && (ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0 176 && allow_memio != 0) { 177 178 regs_type = SYS_RES_MEMORY; 179 regs_id = AHD_PCI_MEMADDR; 180 regs = bus_alloc_resource(ahd->dev_softc, regs_type, 181 ®s_id, 0, ~0, 1, RF_ACTIVE); 182 if (regs != NULL) { 183 int error; 184 185 ahd->tags[0] = rman_get_bustag(regs); 186 ahd->bshs[0] = rman_get_bushandle(regs); 187 ahd->tags[1] = ahd->tags[0]; 188 error = bus_space_subregion(ahd->tags[0], ahd->bshs[0], 189 /*offset*/0x100, 190 /*size*/0x100, 191 &ahd->bshs[1]); 192 /* 193 * Do a quick test to see if memory mapped 194 * I/O is functioning correctly. 195 */ 196 if (error != 0 197 || ahd_pci_test_register_access(ahd) != 0) { 198 device_printf(ahd->dev_softc, 199 "PCI Device %d:%d:%d failed memory " 200 "mapped test. Using PIO.\n", 201 ahd_get_pci_bus(ahd->dev_softc), 202 ahd_get_pci_slot(ahd->dev_softc), 203 ahd_get_pci_function(ahd->dev_softc)); 204 bus_release_resource(ahd->dev_softc, regs_type, 205 regs_id, regs); 206 regs = NULL; 207 } else { 208 command &= ~PCIM_CMD_PORTEN; 209 ahd_pci_write_config(ahd->dev_softc, 210 PCIR_COMMAND, 211 command, /*bytes*/1); 212 } 213 } 214 } 215 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) { 216 regs_type = SYS_RES_IOPORT; 217 regs_id = AHD_PCI_IOADDR0; 218 regs = bus_alloc_resource(ahd->dev_softc, regs_type, 219 ®s_id, 0, ~0, 1, RF_ACTIVE); 220 if (regs == NULL) { 221 device_printf(ahd->dev_softc, 222 "can't allocate register resources\n"); 223 return (ENOMEM); 224 } 225 ahd->tags[0] = rman_get_bustag(regs); 226 ahd->bshs[0] = rman_get_bushandle(regs); 227 228 /* And now the second BAR */ 229 regs_id2 = AHD_PCI_IOADDR1; 230 regs2 = bus_alloc_resource(ahd->dev_softc, regs_type, 231 ®s_id2, 0, ~0, 1, RF_ACTIVE); 232 if (regs2 == NULL) { 233 device_printf(ahd->dev_softc, 234 "can't allocate register resources\n"); 235 return (ENOMEM); 236 } 237 ahd->tags[1] = rman_get_bustag(regs2); 238 ahd->bshs[1] = rman_get_bushandle(regs2); 239 command &= ~PCIM_CMD_MEMEN; 240 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 241 command, /*bytes*/1); 242 ahd->platform_data->regs_res_type[1] = regs_type; 243 ahd->platform_data->regs_res_id[1] = regs_id2; 244 ahd->platform_data->regs[1] = regs2; 245 } 246 ahd->platform_data->regs_res_type[0] = regs_type; 247 ahd->platform_data->regs_res_id[0] = regs_id; 248 ahd->platform_data->regs[0] = regs; 249 return (0); 250} 251 252int 253ahd_pci_map_int(struct ahd_softc *ahd) 254{ 255 int zero; 256 257 zero = 0; 258 ahd->platform_data->irq = 259 bus_alloc_resource(ahd->dev_softc, SYS_RES_IRQ, &zero, 260 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 261 if (ahd->platform_data->irq == NULL) 262 return (ENOMEM); 263 ahd->platform_data->irq_res_type = SYS_RES_IRQ; 264 return (ahd_map_int(ahd)); 265} 266 267void 268ahd_power_state_change(struct ahd_softc *ahd, ahd_power_state new_state) 269{ 270 uint32_t cap; 271 u_int cap_offset; 272 273 /* 274 * Traverse the capability list looking for 275 * the power management capability. 276 */ 277 cap = 0; 278 cap_offset = ahd_pci_read_config(ahd->dev_softc, 279 PCIR_CAP_PTR, /*bytes*/1); 280 while (cap_offset != 0) { 281 282 cap = ahd_pci_read_config(ahd->dev_softc, 283 cap_offset, /*bytes*/4); 284 if ((cap & 0xFF) == 1 285 && ((cap >> 16) & 0x3) > 0) { 286 uint32_t pm_control; 287 288 pm_control = ahd_pci_read_config(ahd->dev_softc, 289 cap_offset + 4, 290 /*bytes*/2); 291 pm_control &= ~0x3; 292 pm_control |= new_state; 293 ahd_pci_write_config(ahd->dev_softc, 294 cap_offset + 4, 295 pm_control, /*bytes*/2); 296 break; 297 } 298 cap_offset = (cap >> 8) & 0xFF; 299 } 300} 301